1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 8) 28 29 #define MES_API_VERSION 0x14 30 31 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API 32 * to ease the debugging and parsing of ring buffer. 33 */ 34 enum {API_FRAME_SIZE_IN_DWORDS = 64}; 35 36 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in, 37 * this creates another queue 38 */ 39 enum {API_NUMBER_OF_COMMAND_MAX = 32}; 40 41 enum MES_API_TYPE { 42 MES_API_TYPE_SCHEDULER = 1, 43 MES_API_TYPE_MAX 44 }; 45 46 enum MES_SCH_API_OPCODE { 47 MES_SCH_API_SET_HW_RSRC = 0, 48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 49 MES_SCH_API_ADD_QUEUE = 2, 50 MES_SCH_API_REMOVE_QUEUE = 3, 51 MES_SCH_API_PERFORM_YIELD = 4, 52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */ 53 MES_SCH_API_SUSPEND = 6, 54 MES_SCH_API_RESUME = 7, 55 MES_SCH_API_RESET = 8, 56 MES_SCH_API_SET_LOG_BUFFER = 9, 57 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 59 MES_SCH_API_SET_DEBUG_VMID = 13, 60 MES_SCH_API_MISC = 14, 61 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 62 MES_SCH_API_AMD_LOG = 16, 63 MES_SCH_API_SET_SE_MODE = 17, 64 MES_SCH_API_SET_GANG_SUBMIT = 18, 65 MES_SCH_API_SET_HW_RSRC_1 = 19, 66 67 MES_SCH_API_MAX = 0xFF 68 }; 69 70 union MES_API_HEADER { 71 struct { 72 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 73 uint32_t opcode : 8; 74 uint32_t dwsize : 8; /* including header */ 75 uint32_t reserved : 12; 76 }; 77 78 uint32_t u32All; 79 }; 80 81 enum MES_AMD_PRIORITY_LEVEL { 82 AMD_PRIORITY_LEVEL_LOW = 0, 83 AMD_PRIORITY_LEVEL_NORMAL = 1, 84 AMD_PRIORITY_LEVEL_MEDIUM = 2, 85 AMD_PRIORITY_LEVEL_HIGH = 3, 86 AMD_PRIORITY_LEVEL_REALTIME = 4, 87 88 AMD_PRIORITY_NUM_LEVELS 89 }; 90 91 enum MES_QUEUE_TYPE { 92 MES_QUEUE_TYPE_GFX, 93 MES_QUEUE_TYPE_COMPUTE, 94 MES_QUEUE_TYPE_SDMA, 95 96 MES_QUEUE_TYPE_MAX, 97 }; 98 99 struct MES_API_STATUS { 100 uint64_t api_completion_fence_addr; 101 uint64_t api_completion_fence_value; 102 }; 103 104 105 enum { MAX_COMPUTE_PIPES = 8 }; 106 enum { MAX_GFX_PIPES = 2 }; 107 enum { MAX_SDMA_PIPES = 2 }; 108 109 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 110 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 111 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 112 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 113 114 115 enum { MAX_QUEUES_IN_A_GANG = 8 }; 116 117 enum VM_HUB_TYPE { 118 VM_HUB_TYPE_GC = 0, 119 VM_HUB_TYPE_MM = 1, 120 121 VM_HUB_TYPE_MAX, 122 }; 123 124 enum { VMID_INVALID = 0xffff }; 125 126 enum { MAX_VMID_GCHUB = 16 }; 127 enum { MAX_VMID_MMHUB = 16 }; 128 129 enum SET_DEBUG_VMID_OPERATIONS { 130 DEBUG_VMID_OP_PROGRAM = 0, 131 DEBUG_VMID_OP_ALLOCATE = 1, 132 DEBUG_VMID_OP_RELEASE = 2, 133 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1) 134 }; 135 136 enum MES_MS_LOG_CONTEXT_STATE { 137 MES_LOG_CONTEXT_STATE_IDLE = 0, 138 MES_LOG_CONTEXT_STATE_RUNNING = 1, 139 MES_LOG_CONTEXT_STATE_READY = 2, 140 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 141 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 142 }; 143 144 enum MES_MS_LOG_OPERATION { 145 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 146 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 147 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 148 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 149 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 150 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 151 }; 152 153 struct MES_LOG_CONTEXT_STATE_CHANGE { 154 uint64_t h_context; 155 enum MES_MS_LOG_CONTEXT_STATE new_context_state; 156 }; 157 158 struct MES_LOG_QUEUE_NEW_WORK { 159 uint64_t h_queue; 160 uint64_t reserved; 161 }; 162 163 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 164 uint64_t h_queue; 165 uint64_t h_sync_object; 166 }; 167 168 struct MES_LOG_QUEUE_NO_MORE_WORK { 169 uint64_t h_queue; 170 uint64_t reserved; 171 }; 172 173 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 174 uint64_t h_queue; 175 uint64_t h_sync_object; 176 }; 177 178 struct MES_LOG_ENTRY_HEADER { 179 uint32_t first_free_entry_index; 180 uint32_t wraparound_count; 181 uint64_t number_of_entries; 182 uint64_t reserved[2]; 183 }; 184 185 struct MES_LOG_ENTRY_DATA { 186 uint64_t gpu_time_stamp; 187 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 188 uint32_t reserved_operation_type_bits; 189 union { 190 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 191 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 192 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 193 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 194 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 195 uint64_t all[2]; 196 }; 197 }; 198 199 struct MES_LOG_BUFFER { 200 struct MES_LOG_ENTRY_HEADER header; 201 struct MES_LOG_ENTRY_DATA entries[]; 202 }; 203 204 enum MES_SWIP_TO_HWIP_DEF { 205 MES_MAX_HWIP_SEGMENT = 8, 206 }; 207 208 union MESAPI_SET_HW_RESOURCES { 209 struct { 210 union MES_API_HEADER header; 211 uint32_t vmid_mask_mmhub; 212 uint32_t vmid_mask_gfxhub; 213 uint32_t gds_size; 214 uint32_t paging_vmid; 215 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 216 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 217 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 218 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 219 uint64_t g_sch_ctx_gpu_mc_ptr; 220 uint64_t query_status_fence_gpu_mc_ptr; 221 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 222 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 223 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 224 struct MES_API_STATUS api_status; 225 union { 226 struct { 227 uint32_t disable_reset : 1; 228 uint32_t use_different_vmid_compute : 1; 229 uint32_t disable_mes_log : 1; 230 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 231 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 232 uint32_t second_gfx_pipe_enabled : 1; 233 uint32_t enable_level_process_quantum_check : 1; 234 uint32_t legacy_sch_mode : 1; 235 uint32_t disable_add_queue_wptr_mc_addr : 1; 236 uint32_t enable_mes_event_int_logging : 1; 237 uint32_t enable_reg_active_poll : 1; 238 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 239 uint32_t send_write_data : 1; 240 uint32_t os_tdr_timeout_override : 1; 241 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 242 uint32_t reserved : 17; 243 }; 244 uint32_t uint32_all; 245 }; 246 uint32_t oversubscription_timer; 247 uint64_t doorbell_info; 248 uint64_t event_intr_history_gpu_mc_ptr; 249 uint64_t timestamp; 250 uint32_t os_tdr_timeout_in_sec; 251 }; 252 253 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 254 }; 255 256 union MESAPI_SET_HW_RESOURCES_1 { 257 struct { 258 union MES_API_HEADER header; 259 struct MES_API_STATUS api_status; 260 uint64_t timestamp; 261 union { 262 struct { 263 uint32_t enable_mes_debug_ctx : 1; 264 uint32_t reserved : 31; 265 }; 266 uint32_t uint32_all; 267 }; 268 uint64_t mes_debug_ctx_mc_addr; 269 uint32_t mes_debug_ctx_size; 270 /* unit is 100ms */ 271 uint32_t mes_kiq_unmap_timeout; 272 }; 273 274 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 275 }; 276 277 union MESAPI__ADD_QUEUE { 278 struct { 279 union MES_API_HEADER header; 280 uint32_t process_id; 281 uint64_t page_table_base_addr; 282 uint64_t process_va_start; 283 uint64_t process_va_end; 284 uint64_t process_quantum; 285 uint64_t process_context_addr; 286 uint64_t gang_quantum; 287 uint64_t gang_context_addr; 288 uint32_t inprocess_gang_priority; 289 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 290 uint32_t doorbell_offset; 291 uint64_t mqd_addr; 292 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */ 293 uint64_t wptr_addr; 294 uint64_t h_context; 295 uint64_t h_queue; 296 enum MES_QUEUE_TYPE queue_type; 297 uint32_t gds_base; 298 union { 299 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */ 300 uint32_t gds_size; 301 uint32_t kfd_queue_size; 302 }; 303 uint32_t gws_base; 304 uint32_t gws_size; 305 uint32_t oa_mask; 306 uint64_t trap_handler_addr; 307 uint32_t vm_context_cntl; 308 309 struct { 310 uint32_t paging : 1; 311 uint32_t debug_vmid : 4; 312 uint32_t program_gds : 1; 313 uint32_t is_gang_suspended : 1; 314 uint32_t is_tmz_queue : 1; 315 uint32_t map_kiq_utility_queue : 1; 316 uint32_t is_kfd_process : 1; 317 uint32_t trap_en : 1; 318 uint32_t is_aql_queue : 1; 319 uint32_t skip_process_ctx_clear : 1; 320 uint32_t map_legacy_kq : 1; 321 uint32_t exclusively_scheduled : 1; 322 uint32_t is_long_running : 1; 323 uint32_t is_dwm_queue : 1; 324 uint32_t reserved : 15; 325 }; 326 struct MES_API_STATUS api_status; 327 uint64_t tma_addr; 328 uint32_t sch_id; 329 uint64_t timestamp; 330 uint32_t process_context_array_index; 331 uint32_t gang_context_array_index; 332 uint32_t pipe_id; //used for mapping legacy kernel queue 333 uint32_t queue_id; 334 uint32_t alignment_mode_setting; 335 }; 336 337 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 338 }; 339 340 union MESAPI__REMOVE_QUEUE { 341 struct { 342 union MES_API_HEADER header; 343 uint32_t doorbell_offset; 344 uint64_t gang_context_addr; 345 346 struct { 347 uint32_t reserved01 : 1; 348 uint32_t unmap_kiq_utility_queue : 1; 349 uint32_t preempt_legacy_gfx_queue : 1; 350 uint32_t unmap_legacy_queue : 1; 351 uint32_t reserved : 28; 352 }; 353 struct MES_API_STATUS api_status; 354 355 uint32_t pipe_id; 356 uint32_t queue_id; 357 358 uint64_t tf_addr; 359 uint32_t tf_data; 360 361 enum MES_QUEUE_TYPE queue_type; 362 uint64_t timestamp; 363 uint32_t gang_context_array_index; 364 }; 365 366 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 367 }; 368 369 union MESAPI__SET_SCHEDULING_CONFIG { 370 struct { 371 union MES_API_HEADER header; 372 /* Grace period when preempting another priority band for this priority band. 373 * The value for idle priority band is ignored, as it never preempts other bands. 374 */ 375 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 376 377 /* Default quantum for scheduling across processes within a priority band. */ 378 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 379 380 /* Default grace period for processes that preempt each other within a priority band.*/ 381 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 382 383 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level. 384 * Valid values are between 0 and 50, with the default being 10. 385 */ 386 uint32_t normal_yield_percent; 387 388 struct MES_API_STATUS api_status; 389 uint64_t timestamp; 390 }; 391 392 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 393 }; 394 395 union MESAPI__PERFORM_YIELD { 396 struct { 397 union MES_API_HEADER header; 398 uint32_t dummy; 399 struct MES_API_STATUS api_status; 400 uint64_t timestamp; 401 }; 402 403 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 404 }; 405 406 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 407 struct { 408 union MES_API_HEADER header; 409 uint32_t inprocess_gang_priority; 410 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 411 uint64_t gang_quantum; 412 uint64_t gang_context_addr; 413 struct MES_API_STATUS api_status; 414 uint32_t doorbell_offset; 415 uint64_t timestamp; 416 uint32_t gang_context_array_index; 417 struct { 418 uint32_t queue_quantum_scale : 2; 419 uint32_t queue_quantum_duration : 8; 420 uint32_t apply_quantum_all_processes : 1; 421 uint32_t reserved : 21; 422 }; 423 }; 424 425 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 426 }; 427 428 union MESAPI__SUSPEND { 429 struct { 430 union MES_API_HEADER header; 431 /* false - suspend all gangs; true - specific gang */ 432 struct { 433 uint32_t suspend_all_gangs : 1; 434 uint32_t reserved : 31; 435 }; 436 /* gang_context_addr is valid only if suspend_all = false */ 437 438 uint64_t gang_context_addr; 439 440 uint64_t suspend_fence_addr; 441 uint32_t suspend_fence_value; 442 443 struct MES_API_STATUS api_status; 444 445 union { 446 uint32_t return_value; // to be removed 447 uint32_t sch_id; //keep the old return_value temporarily for compatibility 448 }; 449 uint32_t doorbell_offset; 450 uint64_t timestamp; 451 enum MES_QUEUE_TYPE legacy_uq_type; 452 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level; 453 uint32_t gang_context_array_index; 454 }; 455 456 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 457 }; 458 459 union MESAPI__RESUME { 460 struct { 461 union MES_API_HEADER header; 462 /* false - resume all gangs; true - specified gang */ 463 struct { 464 uint32_t resume_all_gangs : 1; 465 uint32_t reserved : 31; 466 }; 467 /* valid only if resume_all_gangs = false */ 468 uint64_t gang_context_addr; 469 470 struct MES_API_STATUS api_status; 471 uint32_t doorbell_offset; 472 uint64_t timestamp; 473 uint32_t gang_context_array_index; 474 }; 475 476 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 477 }; 478 479 union MESAPI__RESET { 480 struct { 481 union MES_API_HEADER header; 482 483 struct { 484 /* Only reset the queue given by doorbell_offset (not entire gang) */ 485 uint32_t reset_queue_only : 1; 486 /* Hang detection first then reset any queues that are hung */ 487 uint32_t hang_detect_then_reset : 1; 488 /* Only do hang detection (no reset) */ 489 uint32_t hang_detect_only : 1; 490 /* Reset HP and LP kernel queues not managed by MES */ 491 uint32_t reset_legacy_gfx : 1; 492 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */ 493 uint32_t use_connected_queue_index : 1; 494 /* For gfx pipe 1 */ 495 uint32_t use_connected_queue_index_p1 : 1; 496 uint32_t reserved : 26; 497 }; 498 499 uint64_t gang_context_addr; 500 501 /* valid only if reset_queue_only = true */ 502 uint32_t doorbell_offset; 503 504 /* valid only if hang_detect_then_reset = true */ 505 uint64_t doorbell_offset_addr; 506 enum MES_QUEUE_TYPE queue_type; 507 508 /* valid only if reset_legacy_gfx = true */ 509 uint32_t pipe_id_lp; 510 uint32_t queue_id_lp; 511 uint32_t vmid_id_lp; 512 uint64_t mqd_mc_addr_lp; 513 uint32_t doorbell_offset_lp; 514 uint64_t wptr_addr_lp; 515 516 uint32_t pipe_id_hp; 517 uint32_t queue_id_hp; 518 uint32_t vmid_id_hp; 519 uint64_t mqd_mc_addr_hp; 520 uint32_t doorbell_offset_hp; 521 uint64_t wptr_addr_hp; 522 523 struct MES_API_STATUS api_status; 524 uint32_t active_vmids; 525 uint64_t timestamp; 526 527 uint32_t gang_context_array_index; 528 529 uint32_t connected_queue_index; 530 uint32_t connected_queue_index_p1; 531 }; 532 533 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 534 }; 535 536 union MESAPI__SET_LOGGING_BUFFER { 537 struct { 538 union MES_API_HEADER header; 539 /* There are separate log buffers for each queue type */ 540 enum MES_QUEUE_TYPE log_type; 541 /* Log buffer GPU Address */ 542 uint64_t logging_buffer_addr; 543 /* number of entries in the log buffer */ 544 uint32_t number_of_entries; 545 /* Entry index at which CPU interrupt needs to be signalled */ 546 uint32_t interrupt_entry; 547 548 struct MES_API_STATUS api_status; 549 uint64_t timestamp; 550 uint32_t vmid; 551 }; 552 553 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 554 }; 555 556 enum MES_API_QUERY_MES_OPCODE { 557 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE, 558 MES_API_QUERY_MES__CHECK_HEALTHY, 559 MES_API_QUERY_MES__MAX, 560 }; 561 562 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 }; 563 564 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE { 565 uint64_t proc_ctx_array_size_addr; 566 uint64_t gang_ctx_array_size_addr; 567 }; 568 569 struct MES_API_QUERY_MES__HEALTHY_CHECK { 570 uint64_t healthy_addr; 571 }; 572 573 union MESAPI__QUERY_MES_STATUS { 574 struct { 575 union MES_API_HEADER header; 576 enum MES_API_QUERY_MES_OPCODE subopcode; 577 struct MES_API_STATUS api_status; 578 uint64_t timestamp; 579 union { 580 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size; 581 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check; 582 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS]; 583 }; 584 }; 585 586 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 587 }; 588 589 union MESAPI__SET_DEBUG_VMID { 590 struct { 591 union MES_API_HEADER header; 592 struct MES_API_STATUS api_status; 593 union { 594 struct { 595 uint32_t use_gds : 1; 596 uint32_t operation : 2; 597 uint32_t reserved : 29; 598 } flags; 599 uint32_t u32All; 600 }; 601 uint32_t reserved; 602 uint32_t debug_vmid; 603 uint64_t process_context_addr; 604 uint64_t page_table_base_addr; 605 uint64_t process_va_start; 606 uint64_t process_va_end; 607 uint32_t gds_base; 608 uint32_t gds_size; 609 uint32_t gws_base; 610 uint32_t gws_size; 611 uint32_t oa_mask; 612 613 uint64_t output_addr; // output addr of the acquired vmid value 614 615 uint64_t timestamp; 616 617 uint32_t process_vm_cntl; 618 enum MES_QUEUE_TYPE queue_type; 619 620 uint32_t process_context_array_index; 621 622 uint32_t alignment_mode_setting; 623 }; 624 625 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 626 }; 627 628 enum MESAPI_MISC_OPCODE { 629 MESAPI_MISC__WRITE_REG, 630 MESAPI_MISC__INV_GART, 631 MESAPI_MISC__QUERY_STATUS, 632 MESAPI_MISC__READ_REG, 633 MESAPI_MISC__WAIT_REG_MEM, 634 MESAPI_MISC__SET_SHADER_DEBUGGER, 635 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 636 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 637 638 MESAPI_MISC__MAX, 639 }; 640 641 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; 642 643 struct WRITE_REG { 644 uint32_t reg_offset; 645 uint32_t reg_value; 646 }; 647 648 struct READ_REG { 649 uint32_t reg_offset; 650 uint64_t buffer_addr; 651 union { 652 struct { 653 uint32_t read64Bits : 1; 654 uint32_t reserved : 31; 655 } bits; 656 uint32_t all; 657 } option; 658 }; 659 660 struct INV_GART { 661 uint64_t inv_range_va_start; 662 uint64_t inv_range_size; 663 }; 664 665 struct QUERY_STATUS { 666 uint32_t context_id; 667 }; 668 669 enum WRM_OPERATION { 670 WRM_OPERATION__WAIT_REG_MEM, 671 WRM_OPERATION__WR_WAIT_WR_REG, 672 673 WRM_OPERATION__MAX, 674 }; 675 676 struct WAIT_REG_MEM { 677 enum WRM_OPERATION op; 678 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */ 679 uint32_t reference; 680 uint32_t mask; 681 uint32_t reg_offset1; 682 uint32_t reg_offset2; 683 }; 684 685 struct SET_SHADER_DEBUGGER { 686 uint64_t process_context_addr; 687 union { 688 struct { 689 uint32_t single_memop : 1; // SQ_DEBUG.single_memop 690 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op 691 uint32_t reserved : 30; 692 }; 693 uint32_t u32all; 694 } flags; 695 uint32_t spi_gdbg_per_vmid_cntl; 696 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL 697 uint32_t trap_en; 698 }; 699 700 struct SET_GANG_SUBMIT { 701 uint64_t gang_context_addr; 702 uint64_t slave_gang_context_addr; 703 uint32_t gang_context_array_index; 704 uint32_t slave_gang_context_array_index; 705 }; 706 707 union MESAPI__MISC { 708 struct { 709 union MES_API_HEADER header; 710 enum MESAPI_MISC_OPCODE opcode; 711 struct MES_API_STATUS api_status; 712 union { 713 struct WRITE_REG write_reg; 714 struct INV_GART inv_gart; 715 struct QUERY_STATUS query_status; 716 struct READ_REG read_reg; 717 struct WAIT_REG_MEM wait_reg_mem; 718 struct SET_SHADER_DEBUGGER set_shader_debugger; 719 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 720 721 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 722 }; 723 uint64_t timestamp; 724 uint32_t doorbell_offset; 725 uint32_t os_fence; 726 }; 727 728 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 729 }; 730 731 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 732 struct { 733 union MES_API_HEADER header; 734 uint64_t page_table_base_addr; 735 uint64_t process_context_addr; 736 struct MES_API_STATUS api_status; 737 uint64_t timestamp; 738 uint32_t process_context_array_index; 739 }; 740 741 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 742 }; 743 744 union MESAPI_AMD_LOG { 745 struct { 746 union MES_API_HEADER header; 747 uint64_t p_buffer_memory; 748 uint64_t p_buffer_size_used; 749 struct MES_API_STATUS api_status; 750 uint64_t timestamp; 751 }; 752 753 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 754 }; 755 756 enum MES_SE_MODE { 757 MES_SE_MODE_INVALID = 0, 758 MES_SE_MODE_SINGLE_SE = 1, 759 MES_SE_MODE_DUAL_SE = 2, 760 MES_SE_MODE_LOWER_POWER = 3, 761 }; 762 763 union MESAPI__SET_SE_MODE { 764 struct { 765 union MES_API_HEADER header; 766 /* the new SE mode to apply*/ 767 enum MES_SE_MODE new_se_mode; 768 /* the fence to make sure the ItCpgCtxtSync packet is completed */ 769 uint64_t cpg_ctxt_sync_fence_addr; 770 uint32_t cpg_ctxt_sync_fence_value; 771 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */ 772 union { 773 struct { 774 uint32_t log_seq_time : 1; 775 uint32_t reserved : 31; 776 }; 777 uint32_t uint32_all; 778 }; 779 struct MES_API_STATUS api_status; 780 }; 781 782 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 783 }; 784 785 union MESAPI__SET_GANG_SUBMIT { 786 struct { 787 union MES_API_HEADER header; 788 struct MES_API_STATUS api_status; 789 struct SET_GANG_SUBMIT set_gang_submit; 790 }; 791 792 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 793 }; 794 795 #pragma pack(pop) 796 797 #endif 798