1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_ind_reg - Indirect register spaces 33 */ 34 enum cgs_ind_reg { 35 CGS_IND_REG__MMIO, 36 CGS_IND_REG__PCIE, 37 CGS_IND_REG__SMC, 38 CGS_IND_REG__UVD_CTX, 39 CGS_IND_REG__DIDT, 40 CGS_IND_REG_GC_CAC, 41 CGS_IND_REG_SE_CAC, 42 CGS_IND_REG__AUDIO_ENDPT 43 }; 44 45 /** 46 * enum cgs_engine - Engines that can be statically power-gated 47 */ 48 enum cgs_engine { 49 CGS_ENGINE__UVD, 50 CGS_ENGINE__VCE, 51 CGS_ENGINE__VP8, 52 CGS_ENGINE__ACP_DMA, 53 CGS_ENGINE__ACP_DSP0, 54 CGS_ENGINE__ACP_DSP1, 55 CGS_ENGINE__ISP, 56 /* ... */ 57 }; 58 59 /* 60 * enum cgs_ucode_id - Firmware types for different IPs 61 */ 62 enum cgs_ucode_id { 63 CGS_UCODE_ID_SMU = 0, 64 CGS_UCODE_ID_SMU_SK, 65 CGS_UCODE_ID_SDMA0, 66 CGS_UCODE_ID_SDMA1, 67 CGS_UCODE_ID_CP_CE, 68 CGS_UCODE_ID_CP_PFP, 69 CGS_UCODE_ID_CP_ME, 70 CGS_UCODE_ID_CP_MEC, 71 CGS_UCODE_ID_CP_MEC_JT1, 72 CGS_UCODE_ID_CP_MEC_JT2, 73 CGS_UCODE_ID_GMCON_RENG, 74 CGS_UCODE_ID_RLC_G, 75 CGS_UCODE_ID_STORAGE, 76 CGS_UCODE_ID_MAXIMUM, 77 }; 78 79 /* 80 * enum cgs_resource_type - GPU resource type 81 */ 82 enum cgs_resource_type { 83 CGS_RESOURCE_TYPE_MMIO = 0, 84 CGS_RESOURCE_TYPE_FB, 85 CGS_RESOURCE_TYPE_IO, 86 CGS_RESOURCE_TYPE_DOORBELL, 87 CGS_RESOURCE_TYPE_ROM, 88 }; 89 90 /** 91 * struct cgs_firmware_info - Firmware information 92 */ 93 struct cgs_firmware_info { 94 uint16_t version; 95 uint16_t fw_version; 96 uint16_t feature_version; 97 uint32_t image_size; 98 uint64_t mc_addr; 99 100 /* only for smc firmware */ 101 uint32_t ucode_start_address; 102 103 void *kptr; 104 bool is_kicker; 105 }; 106 107 struct cgs_mode_info { 108 uint32_t refresh_rate; 109 uint32_t ref_clock; 110 uint32_t vblank_time_us; 111 }; 112 113 struct cgs_display_info { 114 uint32_t display_count; 115 uint32_t active_display_mask; 116 struct cgs_mode_info *mode_info; 117 }; 118 119 typedef unsigned long cgs_handle_t; 120 121 /** 122 * cgs_read_register() - Read an MMIO register 123 * @cgs_device: opaque device handle 124 * @offset: register offset 125 * 126 * Return: register value 127 */ 128 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 129 130 /** 131 * cgs_write_register() - Write an MMIO register 132 * @cgs_device: opaque device handle 133 * @offset: register offset 134 * @value: register value 135 */ 136 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 137 uint32_t value); 138 139 /** 140 * cgs_read_ind_register() - Read an indirect register 141 * @cgs_device: opaque device handle 142 * @offset: register offset 143 * 144 * Return: register value 145 */ 146 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 147 unsigned index); 148 149 /** 150 * cgs_write_ind_register() - Write an indirect register 151 * @cgs_device: opaque device handle 152 * @offset: register offset 153 * @value: register value 154 */ 155 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 156 unsigned index, uint32_t value); 157 158 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 159 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK 160 161 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ 162 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ 163 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) 164 165 #define CGS_REG_GET_FIELD(value, reg, field) \ 166 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) 167 168 #define CGS_WREG32_FIELD(device, reg, field, val) \ 169 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) 170 171 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ 172 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) 173 174 /** 175 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 176 * @cgs_device: opaque device handle 177 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 178 * @size: size of the region 179 * @offset: offset from the start of the region 180 * @resource_base: base address (not including offset) returned 181 * 182 * Return: 0 on success, -errno otherwise 183 */ 184 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 185 enum cgs_resource_type resource_type, 186 uint64_t size, 187 uint64_t offset, 188 uint64_t *resource_base); 189 190 /** 191 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 192 * @cgs_device: opaque device handle 193 * @table: data table index 194 * @size: size of the table (output, may be NULL) 195 * @frev: table format revision (output, may be NULL) 196 * @crev: table content revision (output, may be NULL) 197 * 198 * Return: Pointer to start of the table, or NULL on failure 199 */ 200 typedef const void *(*cgs_atom_get_data_table_t)( 201 struct cgs_device *cgs_device, unsigned table, 202 uint16_t *size, uint8_t *frev, uint8_t *crev); 203 204 /** 205 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 206 * @cgs_device: opaque device handle 207 * @table: data table index 208 * @frev: table format revision (output, may be NULL) 209 * @crev: table content revision (output, may be NULL) 210 * 211 * Return: 0 on success, -errno otherwise 212 */ 213 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 214 uint8_t *frev, uint8_t *crev); 215 216 /** 217 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 218 * @cgs_device: opaque device handle 219 * @table: command table index 220 * @args: arguments 221 * 222 * Return: 0 on success, -errno otherwise 223 */ 224 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 225 unsigned table, void *args); 226 227 /** 228 * cgs_get_firmware_info - Get the firmware information from core driver 229 * @cgs_device: opaque device handle 230 * @type: the firmware type 231 * @info: returend firmware information 232 * 233 * Return: 0 on success, -errno otherwise 234 */ 235 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 236 enum cgs_ucode_id type, 237 struct cgs_firmware_info *info); 238 239 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 240 enum cgs_ucode_id type); 241 242 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 243 enum amd_ip_block_type block_type, 244 enum amd_powergating_state state); 245 246 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 247 enum amd_ip_block_type block_type, 248 enum amd_clockgating_state state); 249 250 typedef int(*cgs_get_active_displays_info)( 251 struct cgs_device *cgs_device, 252 struct cgs_display_info *info); 253 254 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 255 256 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 257 258 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); 259 260 typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock); 261 262 struct cgs_ops { 263 /* MMIO access */ 264 cgs_read_register_t read_register; 265 cgs_write_register_t write_register; 266 cgs_read_ind_register_t read_ind_register; 267 cgs_write_ind_register_t write_ind_register; 268 /* PCI resources */ 269 cgs_get_pci_resource_t get_pci_resource; 270 /* ATOM BIOS */ 271 cgs_atom_get_data_table_t atom_get_data_table; 272 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 273 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 274 /* Firmware Info */ 275 cgs_get_firmware_info get_firmware_info; 276 cgs_rel_firmware rel_firmware; 277 /* cg pg interface*/ 278 cgs_set_powergating_state set_powergating_state; 279 cgs_set_clockgating_state set_clockgating_state; 280 /* display manager */ 281 cgs_get_active_displays_info get_active_displays_info; 282 /* notify dpm enabled */ 283 cgs_notify_dpm_enabled notify_dpm_enabled; 284 cgs_is_virtualization_enabled_t is_virtualization_enabled; 285 cgs_enter_safe_mode enter_safe_mode; 286 cgs_lock_grbm_idx lock_grbm_idx; 287 }; 288 289 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 290 291 struct cgs_device 292 { 293 const struct cgs_ops *ops; 294 const struct cgs_os_ops *os_ops; 295 /* to be embedded at the start of driver private structure */ 296 }; 297 298 /* Convenience macros that make CGS indirect function calls look like 299 * normal function calls */ 300 #define CGS_CALL(func,dev,...) \ 301 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 302 #define CGS_OS_CALL(func,dev,...) \ 303 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 304 305 #define cgs_read_register(dev,offset) \ 306 CGS_CALL(read_register,dev,offset) 307 #define cgs_write_register(dev,offset,value) \ 308 CGS_CALL(write_register,dev,offset,value) 309 #define cgs_read_ind_register(dev,space,index) \ 310 CGS_CALL(read_ind_register,dev,space,index) 311 #define cgs_write_ind_register(dev,space,index,value) \ 312 CGS_CALL(write_ind_register,dev,space,index,value) 313 314 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 315 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 316 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 317 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 318 #define cgs_atom_exec_cmd_table(dev,table,args) \ 319 CGS_CALL(atom_exec_cmd_table,dev,table,args) 320 321 #define cgs_get_firmware_info(dev, type, info) \ 322 CGS_CALL(get_firmware_info, dev, type, info) 323 #define cgs_rel_firmware(dev, type) \ 324 CGS_CALL(rel_firmware, dev, type) 325 #define cgs_set_powergating_state(dev, block_type, state) \ 326 CGS_CALL(set_powergating_state, dev, block_type, state) 327 #define cgs_set_clockgating_state(dev, block_type, state) \ 328 CGS_CALL(set_clockgating_state, dev, block_type, state) 329 #define cgs_notify_dpm_enabled(dev, enabled) \ 330 CGS_CALL(notify_dpm_enabled, dev, enabled) 331 332 #define cgs_get_active_displays_info(dev, info) \ 333 CGS_CALL(get_active_displays_info, dev, info) 334 335 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 336 resource_base) \ 337 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 338 resource_base) 339 340 #define cgs_is_virtualization_enabled(cgs_device) \ 341 CGS_CALL(is_virtualization_enabled, cgs_device) 342 343 #define cgs_enter_safe_mode(cgs_device, en) \ 344 CGS_CALL(enter_safe_mode, cgs_device, en) 345 346 #define cgs_lock_grbm_idx(cgs_device, lock) \ 347 CGS_CALL(lock_grbm_idx, cgs_device, lock) 348 349 350 #endif /* _CGS_COMMON_H */ 351