1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 28 29 #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ 30 31 /* 32 * Chip flags 33 */ 34 enum amd_chip_flags { 35 AMD_ASIC_MASK = 0x0000ffffUL, 36 AMD_FLAGS_MASK = 0xffff0000UL, 37 AMD_IS_MOBILITY = 0x00010000UL, 38 AMD_IS_APU = 0x00020000UL, 39 AMD_IS_PX = 0x00040000UL, 40 AMD_EXP_HW_SUPPORT = 0x00080000UL, 41 }; 42 43 enum amd_apu_flags { 44 AMD_APU_IS_RAVEN = 0x00000001UL, 45 AMD_APU_IS_RAVEN2 = 0x00000002UL, 46 AMD_APU_IS_PICASSO = 0x00000004UL, 47 AMD_APU_IS_RENOIR = 0x00000008UL, 48 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL, 49 AMD_APU_IS_VANGOGH = 0x00000020UL, 50 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL, 51 }; 52 53 /** 54 * DOC: IP Blocks 55 * 56 * GPUs are composed of IP (intellectual property) blocks. These 57 * IP blocks provide various functionalities: display, graphics, 58 * video decode, etc. The IP blocks that comprise a particular GPU 59 * are listed in the GPU's respective SoC file. amdgpu_device.c 60 * acquires the list of IP blocks for the GPU in use on initialization. 61 * It can then operate on this list to perform standard driver operations 62 * such as: init, fini, suspend, resume, etc. 63 * 64 * 65 * IP block implementations are named using the following convention: 66 * <functionality>_v<version> (E.g.: gfx_v6_0). 67 */ 68 69 /** 70 * enum amd_ip_block_type - Used to classify IP blocks by functionality. 71 * 72 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family 73 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller 74 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler 75 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller 76 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor 77 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine 78 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine 79 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine 80 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder 81 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine 82 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor 83 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next 84 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler 85 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine 86 * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types 87 */ 88 enum amd_ip_block_type { 89 AMD_IP_BLOCK_TYPE_COMMON, 90 AMD_IP_BLOCK_TYPE_GMC, 91 AMD_IP_BLOCK_TYPE_IH, 92 AMD_IP_BLOCK_TYPE_SMC, 93 AMD_IP_BLOCK_TYPE_PSP, 94 AMD_IP_BLOCK_TYPE_DCE, 95 AMD_IP_BLOCK_TYPE_GFX, 96 AMD_IP_BLOCK_TYPE_SDMA, 97 AMD_IP_BLOCK_TYPE_UVD, 98 AMD_IP_BLOCK_TYPE_VCE, 99 AMD_IP_BLOCK_TYPE_ACP, 100 AMD_IP_BLOCK_TYPE_VCN, 101 AMD_IP_BLOCK_TYPE_MES, 102 AMD_IP_BLOCK_TYPE_JPEG, 103 AMD_IP_BLOCK_TYPE_VPE, 104 AMD_IP_BLOCK_TYPE_NUM, 105 }; 106 107 enum amd_clockgating_state { 108 AMD_CG_STATE_GATE = 0, 109 AMD_CG_STATE_UNGATE, 110 }; 111 112 113 enum amd_powergating_state { 114 AMD_PG_STATE_GATE = 0, 115 AMD_PG_STATE_UNGATE, 116 }; 117 118 119 /* CG flags */ 120 #define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0) 121 #define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1) 122 #define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2) 123 #define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3) 124 #define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4) 125 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5) 126 #define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6) 127 #define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7) 128 #define AMD_CG_SUPPORT_MC_LS (1ULL << 8) 129 #define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9) 130 #define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10) 131 #define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11) 132 #define AMD_CG_SUPPORT_BIF_LS (1ULL << 12) 133 #define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13) 134 #define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14) 135 #define AMD_CG_SUPPORT_HDP_LS (1ULL << 15) 136 #define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16) 137 #define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17) 138 #define AMD_CG_SUPPORT_DRM_LS (1ULL << 18) 139 #define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19) 140 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20) 141 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21) 142 #define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22) 143 #define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23) 144 #define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24) 145 #define AMD_CG_SUPPORT_HDP_DS (1ULL << 25) 146 #define AMD_CG_SUPPORT_HDP_SD (1ULL << 26) 147 #define AMD_CG_SUPPORT_IH_CG (1ULL << 27) 148 #define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28) 149 #define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29) 150 #define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30) 151 #define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31) 152 #define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32) 153 #define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33) 154 /* PG flags */ 155 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 156 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 157 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 158 #define AMD_PG_SUPPORT_UVD (1 << 3) 159 #define AMD_PG_SUPPORT_VCE (1 << 4) 160 #define AMD_PG_SUPPORT_CP (1 << 5) 161 #define AMD_PG_SUPPORT_GDS (1 << 6) 162 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 163 #define AMD_PG_SUPPORT_SDMA (1 << 8) 164 #define AMD_PG_SUPPORT_ACP (1 << 9) 165 #define AMD_PG_SUPPORT_SAMU (1 << 10) 166 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 167 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 168 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 169 #define AMD_PG_SUPPORT_VCN (1 << 14) 170 #define AMD_PG_SUPPORT_VCN_DPG (1 << 15) 171 #define AMD_PG_SUPPORT_ATHUB (1 << 16) 172 #define AMD_PG_SUPPORT_JPEG (1 << 17) 173 #define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18) 174 175 /** 176 * enum PP_FEATURE_MASK - Used to mask power play features. 177 * 178 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock. 179 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock. 180 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes. 181 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep. 182 * @PP_POWER_CONTAINMENT_MASK: Power containment. 183 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake. 184 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control. 185 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support. 186 * @PP_ULV_MASK: Ultra low voltage. 187 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating. 188 * @PP_CLOCK_STRETCH_MASK: Clock stretching. 189 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control. 190 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock. 191 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock. 192 * @PP_OVERDRIVE_MASK: Over- and under-clocking support. 193 * @PP_GFXOFF_MASK: Dynamic graphics engine power control. 194 * @PP_ACG_MASK: Adaptive clock generator. 195 * @PP_STUTTER_MODE: Stutter mode. 196 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. 197 * @PP_GFX_DCS_MASK: GFX Async DCS. 198 * 199 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to 200 * the kernel's command line parameters. This is usually done through a system's 201 * boot loader (E.g. GRUB). If manually loading the driver, pass 202 * ppfeaturemask=<mask> as a modprobe parameter. 203 */ 204 enum PP_FEATURE_MASK { 205 PP_SCLK_DPM_MASK = 0x1, 206 PP_MCLK_DPM_MASK = 0x2, 207 PP_PCIE_DPM_MASK = 0x4, 208 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 209 PP_POWER_CONTAINMENT_MASK = 0x10, 210 PP_UVD_HANDSHAKE_MASK = 0x20, 211 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 212 PP_VBI_TIME_SUPPORT_MASK = 0x80, 213 PP_ULV_MASK = 0x100, 214 PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 215 PP_CLOCK_STRETCH_MASK = 0x400, 216 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 217 PP_SOCCLK_DPM_MASK = 0x1000, 218 PP_DCEFCLK_DPM_MASK = 0x2000, 219 PP_OVERDRIVE_MASK = 0x4000, 220 PP_GFXOFF_MASK = 0x8000, 221 PP_ACG_MASK = 0x10000, 222 PP_STUTTER_MODE = 0x20000, 223 PP_AVFS_MASK = 0x40000, 224 PP_GFX_DCS_MASK = 0x80000, 225 }; 226 227 enum amd_harvest_ip_mask { 228 AMD_HARVEST_IP_VCN_MASK = 0x1, 229 AMD_HARVEST_IP_JPEG_MASK = 0x2, 230 AMD_HARVEST_IP_DMU_MASK = 0x4, 231 }; 232 233 enum DC_FEATURE_MASK { 234 //Default value can be found at "uint amdgpu_dc_feature_mask" 235 DC_FBC_MASK = (1 << 0), //0x1, disabled by default 236 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default 237 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default 238 DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1 239 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default 240 DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default 241 DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default 242 DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default 243 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default 244 DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4 245 }; 246 247 enum DC_DEBUG_MASK { 248 DC_DISABLE_PIPE_SPLIT = 0x1, 249 DC_DISABLE_STUTTER = 0x2, 250 DC_DISABLE_DSC = 0x4, 251 DC_DISABLE_CLOCK_GATING = 0x8, 252 DC_DISABLE_PSR = 0x10, 253 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, 254 DC_DISABLE_MPO = 0x40, 255 DC_DISABLE_REPLAY = 0x50, 256 DC_ENABLE_DPIA_TRACE = 0x80, 257 }; 258 259 enum amd_dpm_forced_level; 260 261 /** 262 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 263 * @name: Name of IP block 264 * @early_init: sets up early driver state (pre sw_init), 265 * does not configure hw - Optional 266 * @late_init: sets up late driver/hw state (post hw_init) - Optional 267 * @sw_init: sets up driver state, does not configure hw 268 * @sw_fini: tears down driver state, does not configure hw 269 * @early_fini: tears down stuff before dev detached from driver 270 * @hw_init: sets up the hw state 271 * @hw_fini: tears down the hw state 272 * @late_fini: final cleanup 273 * @suspend: handles IP specific hw/sw changes for suspend 274 * @resume: handles IP specific hw/sw changes for resume 275 * @is_idle: returns current IP block idle status 276 * @wait_for_idle: poll for idle 277 * @check_soft_reset: check soft reset the IP block 278 * @pre_soft_reset: pre soft reset the IP block 279 * @soft_reset: soft reset the IP block 280 * @post_soft_reset: post soft reset the IP block 281 * @set_clockgating_state: enable/disable cg for the IP block 282 * @set_powergating_state: enable/disable pg for the IP block 283 * @get_clockgating_state: get current clockgating status 284 * 285 * These hooks provide an interface for controlling the operational state 286 * of IP blocks. After acquiring a list of IP blocks for the GPU in use, 287 * the driver can make chip-wide state changes by walking this list and 288 * making calls to hooks from each IP block. This list is ordered to ensure 289 * that the driver initializes the IP blocks in a safe sequence. 290 */ 291 struct amd_ip_funcs { 292 char *name; 293 int (*early_init)(void *handle); 294 int (*late_init)(void *handle); 295 int (*sw_init)(void *handle); 296 int (*sw_fini)(void *handle); 297 int (*early_fini)(void *handle); 298 int (*hw_init)(void *handle); 299 int (*hw_fini)(void *handle); 300 void (*late_fini)(void *handle); 301 int (*suspend)(void *handle); 302 int (*resume)(void *handle); 303 bool (*is_idle)(void *handle); 304 int (*wait_for_idle)(void *handle); 305 bool (*check_soft_reset)(void *handle); 306 int (*pre_soft_reset)(void *handle); 307 int (*soft_reset)(void *handle); 308 int (*post_soft_reset)(void *handle); 309 int (*set_clockgating_state)(void *handle, 310 enum amd_clockgating_state state); 311 int (*set_powergating_state)(void *handle, 312 enum amd_powergating_state state); 313 void (*get_clockgating_state)(void *handle, u64 *flags); 314 }; 315 316 317 #endif /* __AMD_SHARED_H__ */ 318