1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #include "dml2_internal_types.h" 7 #include "dml_top.h" 8 #include "dml2_core_dcn4_calcs.h" 9 #include "dml2_internal_shared_types.h" 10 #include "dml21_utils.h" 11 #include "dml21_translation_helper.h" 12 #include "dml2_dc_resource_mgmt.h" 13 14 static bool dml21_allocate_memory(struct dml2_context **dml_ctx) 15 { 16 *dml_ctx = kzalloc(sizeof(struct dml2_context), GFP_KERNEL); 17 if (!(*dml_ctx)) 18 return false; 19 20 (*dml_ctx)->v21.dml_init.dml2_instance = kzalloc(sizeof(struct dml2_instance), GFP_KERNEL); 21 if (!((*dml_ctx)->v21.dml_init.dml2_instance)) 22 return false; 23 24 (*dml_ctx)->v21.mode_support.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 25 (*dml_ctx)->v21.mode_programming.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 26 27 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; 28 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; 29 30 (*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL); 31 if (!((*dml_ctx)->v21.mode_programming.programming)) 32 return false; 33 34 return true; 35 } 36 37 static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) 38 { 39 bool disable_fams2; 40 struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options; 41 42 /* ODM options */ 43 pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm; 44 pmo_options->disable_dyn_odm_for_multi_stream = true; 45 pmo_options->disable_dyn_odm_for_stream_with_svp = true; 46 47 /* UCLK P-State options */ 48 if (in_dc->debug.dml21_force_pstate_method) { 49 dml_ctx->config.pmo.force_pstate_method_enable = true; 50 for (int i = 0; i < MAX_PIPES; i++) 51 dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; 52 } else { 53 dml_ctx->config.pmo.force_pstate_method_enable = false; 54 } 55 56 pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1); 57 58 /* NOTE: DRR and SubVP Require FAMS2 */ 59 disable_fams2 = !in_dc->debug.fams2_config.bits.enable; 60 pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) || 61 in_dc->debug.force_disable_subvp || 62 disable_fams2; 63 pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) || 64 disable_fams2; 65 pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) || 66 disable_fams2; 67 pmo_options->disable_fams2 = disable_fams2; 68 69 pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE || 70 in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY; 71 pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE; 72 } 73 74 static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 75 { 76 switch (in_dc->ctx->dce_version) { 77 case DCN_VERSION_4_01: 78 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp; 79 break; 80 default: 81 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid; 82 } 83 84 (*dml_ctx)->architecture = dml2_architecture_21; 85 86 /* Store configuration options */ 87 (*dml_ctx)->config = *config; 88 89 /*Initialize SOCBB and DCNIP params */ 90 dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 91 dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 92 dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc); 93 94 /* apply debug overrides */ 95 dml21_apply_debug_options(in_dc, *dml_ctx, config); 96 97 /*Initialize DML21 instance */ 98 dml2_initialize_instance(&(*dml_ctx)->v21.dml_init); 99 } 100 101 bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 102 { 103 /* Allocate memory for initializing DML21 instance */ 104 if (!dml21_allocate_memory(dml_ctx)) 105 return false; 106 107 dml21_init(in_dc, dml_ctx, config); 108 109 return true; 110 } 111 112 void dml21_destroy(struct dml2_context *dml2) 113 { 114 kfree(dml2->v21.dml_init.dml2_instance); 115 kfree(dml2->v21.mode_programming.programming); 116 } 117 118 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, 119 struct dml2_context *in_ctx, unsigned int pipe_cnt) 120 { 121 unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; 122 struct dml2_per_plane_programming *pln_prog = NULL; 123 struct dml2_per_stream_programming *stream_prog = NULL; 124 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 125 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 126 int num_pipes; 127 unsigned int dml_phantom_prog_idx; 128 129 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 130 131 /* copy global DCHUBBUB arbiter registers */ 132 memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); 133 134 /* legacy only */ 135 context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; 136 137 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 138 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 139 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 140 141 /* phantom's start after main planes */ 142 dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; 143 144 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { 145 pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 146 147 if (!pln_prog->plane_descriptor) 148 continue; 149 150 stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; 151 num_dpps_required = pln_prog->num_dpps_required; 152 153 if (num_dpps_required == 0) { 154 continue; 155 } 156 num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 157 158 if (num_pipes <= 0) 159 continue; 160 161 /* program each pipe */ 162 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 163 dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); 164 165 if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { 166 dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); 167 } 168 } 169 170 /* copy per plane mcache allocation */ 171 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); 172 if (pln_prog->phantom_plane.valid) { 173 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], 174 &pln_prog->phantom_plane.mcache_allocation, 175 sizeof(struct dml2_mcache_surface_allocation)); 176 177 dml_phantom_prog_idx++; 178 } 179 } 180 181 /* assign global clocks */ 182 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 183 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 184 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { 185 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = 186 in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; 187 } else { 188 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; 189 } 190 191 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { 192 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 193 in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; 194 } else { 195 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; 196 } 197 198 /* get global mall allocation */ 199 if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { 200 context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); 201 } else { 202 context->bw_ctx.bw.dcn.clk.num_ways = 0; 203 } 204 } 205 206 static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 207 { 208 bool result = false; 209 struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; 210 211 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 212 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 213 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); 214 215 if (!context) 216 return true; 217 218 if (context->stream_count == 0) { 219 dml21_build_fams2_programming(in_dc, context, dml_ctx); 220 return true; 221 } 222 223 /* scrub phantom's from current dc_state */ 224 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 225 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 226 227 /* Populate stream, plane mappings and other fields in display config. */ 228 result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 229 if (!result) 230 return false; 231 232 result = dml2_build_mode_programming(mode_programming); 233 if (!result) 234 return false; 235 236 /* Check and map HW resources */ 237 if (result && !dml_ctx->config.skip_hw_state_mapping) { 238 dml21_map_hw_resources(dml_ctx); 239 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); 240 /* if subvp phantoms are present, expand them into dc context */ 241 dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); 242 } 243 244 /* Copy DML CLK, WM and REG outputs to bandwidth context */ 245 if (result && !dml_ctx->config.skip_hw_state_mapping) { 246 dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); 247 dml21_copy_clocks_to_dc_state(dml_ctx, context); 248 dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); 249 dml21_build_fams2_programming(in_dc, context, dml_ctx); 250 } 251 252 return true; 253 } 254 255 static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 256 { 257 bool is_supported = false; 258 struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; 259 struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; 260 261 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 262 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 263 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); 264 265 if (!context || context->stream_count == 0) 266 return true; 267 268 /* Scrub phantom's from current dc_state */ 269 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 270 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 271 272 mode_support->dml2_instance = dml_init->dml2_instance; 273 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 274 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; 275 is_supported = dml2_check_mode_supported(mode_support); 276 if (!is_supported) 277 return false; 278 279 return true; 280 } 281 282 bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate) 283 { 284 bool out = false; 285 286 /* Use dml_validate_only for fast_validate path */ 287 if (fast_validate) { 288 out = dml21_check_mode_support(in_dc, context, dml_ctx); 289 } else 290 out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); 291 return out; 292 } 293 294 void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 295 { 296 unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; 297 int num_pipes; 298 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 299 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 300 301 struct dml2_per_plane_programming *pln_prog = NULL; 302 struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; 303 struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; 304 305 if (context->stream_count == 0) { 306 return; 307 } 308 309 memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); 310 l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; 311 312 /* phantom's start after main planes */ 313 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; 314 315 /* Build mcache programming parameters per plane per pipe */ 316 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 317 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 318 319 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; 320 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 321 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 322 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; 323 mcache_config->num_pipes = pln_prog->num_dpps_required; 324 l->build_mcache_programming_params.num_configurations++; 325 326 if (pln_prog->num_dpps_required == 0) { 327 continue; 328 } 329 330 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 331 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || 332 dc_main_pipes[0]->plane_state == NULL) 333 continue; 334 335 /* get config for each pipe */ 336 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 337 ASSERT(dc_main_pipes[dc_pipe_index]); 338 dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 339 } 340 341 /* get config for each phantom pipe */ 342 if (pln_prog->phantom_plane.valid && 343 dc_phantom_pipes[0] && 344 dc_main_pipes[0]->stream && 345 dc_phantom_pipes[0]->plane_state) { 346 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; 347 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 348 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 349 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; 350 mcache_config->num_pipes = pln_prog->num_dpps_required; 351 l->build_mcache_programming_params.num_configurations++; 352 353 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 354 ASSERT(dc_phantom_pipes[dc_pipe_index]); 355 dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 356 } 357 358 /* increment phantom index */ 359 dml_phantom_prog_idx++; 360 } 361 } 362 363 /* Call to generate mcache programming per plane per pipe for the given display configuration */ 364 dml2_build_mcache_programming(&l->build_mcache_programming_params); 365 366 /* get per plane per pipe mcache programming */ 367 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 368 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 369 370 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 371 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || 372 dc_main_pipes[0]->plane_state == NULL) 373 continue; 374 375 /* get config for each pipe */ 376 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 377 ASSERT(dc_main_pipes[dc_pipe_index]); 378 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { 379 memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, 380 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], 381 sizeof(struct dml2_hubp_pipe_mcache_regs)); 382 } 383 } 384 385 /* get config for each phantom pipe */ 386 if (pln_prog->phantom_plane.valid && 387 dc_phantom_pipes[0] && 388 dc_main_pipes[0]->stream && 389 dc_phantom_pipes[0]->plane_state) { 390 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 391 ASSERT(dc_phantom_pipes[dc_pipe_index]); 392 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { 393 memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, 394 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], 395 sizeof(struct dml2_hubp_pipe_mcache_regs)); 396 } 397 } 398 /* increment phantom index */ 399 dml_phantom_prog_idx++; 400 } 401 } 402 } 403 404 void dml21_copy(struct dml2_context *dst_dml_ctx, 405 struct dml2_context *src_dml_ctx) 406 { 407 /* Preserve references to internals */ 408 struct dml2_instance *dst_dml2_instance = dst_dml_ctx->v21.dml_init.dml2_instance; 409 struct dml2_display_cfg_programming *dst_dml2_programming = dst_dml_ctx->v21.mode_programming.programming; 410 411 /* Copy context */ 412 memcpy(dst_dml_ctx, src_dml_ctx, sizeof(struct dml2_context)); 413 414 /* Copy Internals */ 415 memcpy(dst_dml2_instance, src_dml_ctx->v21.dml_init.dml2_instance, sizeof(struct dml2_instance)); 416 memcpy(dst_dml2_programming, src_dml_ctx->v21.mode_programming.programming, sizeof(struct dml2_display_cfg_programming)); 417 418 /* Restore references to internals */ 419 dst_dml_ctx->v21.dml_init.dml2_instance = dst_dml2_instance; 420 421 dst_dml_ctx->v21.mode_support.dml2_instance = dst_dml2_instance; 422 dst_dml_ctx->v21.mode_programming.dml2_instance = dst_dml2_instance; 423 424 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; 425 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; 426 427 dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming; 428 429 /* need to initialize copied instance for internal references to be correct */ 430 dml2_initialize_instance(&dst_dml_ctx->v21.dml_init); 431 } 432 433 bool dml21_create_copy(struct dml2_context **dst_dml_ctx, 434 struct dml2_context *src_dml_ctx) 435 { 436 /* Allocate memory for initializing DML21 instance */ 437 if (!dml21_allocate_memory(dst_dml_ctx)) 438 return false; 439 440 dml21_copy(*dst_dml_ctx, src_dml_ctx); 441 442 return true; 443 } 444 445 void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 446 { 447 dml21_init(in_dc, dml_ctx, config); 448 } 449 450