1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #include "dml2_internal_types.h" 7 #include "dml_top.h" 8 #include "dml2_core_dcn4_calcs.h" 9 #include "dml2_internal_shared_types.h" 10 #include "dml21_utils.h" 11 #include "dml21_translation_helper.h" 12 #include "dml2_dc_resource_mgmt.h" 13 14 static bool dml21_allocate_memory(struct dml2_context **dml_ctx) 15 { 16 *dml_ctx = kzalloc(sizeof(struct dml2_context), GFP_KERNEL); 17 if (!(*dml_ctx)) 18 return false; 19 20 (*dml_ctx)->v21.dml_init.dml2_instance = kzalloc(sizeof(struct dml2_instance), GFP_KERNEL); 21 if (!((*dml_ctx)->v21.dml_init.dml2_instance)) 22 return false; 23 24 (*dml_ctx)->v21.mode_support.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 25 (*dml_ctx)->v21.mode_programming.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 26 27 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; 28 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; 29 30 (*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL); 31 if (!((*dml_ctx)->v21.mode_programming.programming)) 32 return false; 33 34 return true; 35 } 36 37 static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) 38 { 39 bool disable_fams2; 40 struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options; 41 42 /* ODM options */ 43 pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm; 44 pmo_options->disable_dyn_odm_for_multi_stream = true; 45 pmo_options->disable_dyn_odm_for_stream_with_svp = true; 46 47 /* UCLK P-State options */ 48 if (in_dc->debug.dml21_force_pstate_method) { 49 dml_ctx->config.pmo.force_pstate_method_enable = true; 50 for (int i = 0; i < MAX_PIPES; i++) 51 dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; 52 } else { 53 dml_ctx->config.pmo.force_pstate_method_enable = false; 54 } 55 56 pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1); 57 58 /* NOTE: DRR and SubVP Require FAMS2 */ 59 disable_fams2 = !in_dc->debug.fams2_config.bits.enable; 60 pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) || 61 in_dc->debug.force_disable_subvp || 62 disable_fams2; 63 pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) || 64 disable_fams2; 65 pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) || 66 disable_fams2; 67 pmo_options->disable_fams2 = disable_fams2; 68 69 pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE || 70 in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY; 71 pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE; 72 } 73 74 static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 75 { 76 switch (in_dc->ctx->dce_version) { 77 case DCN_VERSION_4_01: 78 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp; 79 break; 80 default: 81 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid; 82 } 83 84 (*dml_ctx)->architecture = dml2_architecture_21; 85 86 /* Store configuration options */ 87 (*dml_ctx)->config = *config; 88 89 /*Initialize SOCBB and DCNIP params */ 90 dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 91 dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 92 dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc); 93 94 /* apply debug overrides */ 95 dml21_apply_debug_options(in_dc, *dml_ctx, config); 96 97 /*Initialize DML21 instance */ 98 dml2_initialize_instance(&(*dml_ctx)->v21.dml_init); 99 } 100 101 bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 102 { 103 /* Allocate memory for initializing DML21 instance */ 104 if (!dml21_allocate_memory(dml_ctx)) 105 return false; 106 107 dml21_init(in_dc, dml_ctx, config); 108 109 return true; 110 } 111 112 void dml21_destroy(struct dml2_context *dml2) 113 { 114 kfree(dml2->v21.dml_init.dml2_instance); 115 kfree(dml2->v21.mode_programming.programming); 116 } 117 118 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, 119 struct dml2_context *in_ctx, unsigned int pipe_cnt) 120 { 121 unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; 122 struct dml2_per_plane_programming *pln_prog = NULL; 123 struct dml2_per_stream_programming *stream_prog = NULL; 124 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 125 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 126 int num_pipes; 127 128 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 129 130 /* copy global DCHUBBUB arbiter registers */ 131 memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); 132 133 /* legacy only */ 134 context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; 135 136 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 137 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 138 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 139 140 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { 141 pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 142 143 if (!pln_prog->plane_descriptor) 144 continue; 145 146 stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; 147 num_dpps_required = pln_prog->num_dpps_required; 148 149 if (num_dpps_required == 0) { 150 continue; 151 } 152 num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 153 154 if (num_pipes <= 0) 155 continue; 156 157 /* program each pipe */ 158 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 159 dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); 160 161 if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { 162 dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); 163 } 164 } 165 } 166 167 /* assign global clocks */ 168 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 169 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 170 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { 171 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = 172 in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; 173 } else { 174 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; 175 } 176 177 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { 178 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 179 in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; 180 } else { 181 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; 182 } 183 184 /* get global mall allocation */ 185 if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { 186 context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); 187 } else { 188 context->bw_ctx.bw.dcn.clk.num_ways = 0; 189 } 190 } 191 192 static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 193 { 194 bool result = false; 195 struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; 196 197 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 198 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 199 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); 200 201 if (!context) 202 return true; 203 204 if (context->stream_count == 0) { 205 dml21_build_fams2_programming(in_dc, context, dml_ctx); 206 return true; 207 } 208 209 /* scrub phantom's from current dc_state */ 210 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 211 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 212 213 /* Populate stream, plane mappings and other fields in display config. */ 214 result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 215 if (!result) 216 return false; 217 218 result = dml2_build_mode_programming(mode_programming); 219 if (!result) 220 return false; 221 222 /* Check and map HW resources */ 223 if (result && !dml_ctx->config.skip_hw_state_mapping) { 224 dml21_map_hw_resources(dml_ctx); 225 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); 226 /* if subvp phantoms are present, expand them into dc context */ 227 dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); 228 } 229 230 /* Copy DML CLK, WM and REG outputs to bandwidth context */ 231 if (result && !dml_ctx->config.skip_hw_state_mapping) { 232 dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); 233 dml21_copy_clocks_to_dc_state(dml_ctx, context); 234 dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); 235 dml21_build_fams2_programming(in_dc, context, dml_ctx); 236 } 237 238 return true; 239 } 240 241 static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 242 { 243 bool is_supported = false; 244 struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; 245 struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; 246 247 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 248 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 249 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); 250 251 if (!context || context->stream_count == 0) 252 return true; 253 254 /* Scrub phantom's from current dc_state */ 255 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 256 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 257 258 mode_support->dml2_instance = dml_init->dml2_instance; 259 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 260 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; 261 is_supported = dml2_check_mode_supported(mode_support); 262 if (!is_supported) 263 return false; 264 265 return true; 266 } 267 268 bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate) 269 { 270 bool out = false; 271 272 /* Use dml_validate_only for fast_validate path */ 273 if (fast_validate) { 274 out = dml21_check_mode_support(in_dc, context, dml_ctx); 275 } else 276 out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); 277 return out; 278 } 279 280 void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 281 { 282 unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; 283 int num_pipes; 284 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 285 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 286 287 struct dml2_per_plane_programming *pln_prog = NULL; 288 struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; 289 struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; 290 291 if (context->stream_count == 0) { 292 return; 293 } 294 295 memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); 296 l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; 297 298 /* phantom's start after main planes */ 299 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; 300 301 /* Build mcache programming parameters per plane per pipe */ 302 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 303 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 304 305 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; 306 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 307 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 308 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; 309 mcache_config->num_pipes = pln_prog->num_dpps_required; 310 l->build_mcache_programming_params.num_configurations++; 311 312 if (pln_prog->num_dpps_required == 0) { 313 continue; 314 } 315 316 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 317 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || 318 dc_main_pipes[0]->plane_state == NULL) 319 continue; 320 321 /* get config for each pipe */ 322 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 323 ASSERT(dc_main_pipes[dc_pipe_index]); 324 dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 325 } 326 327 /* get config for each phantom pipe */ 328 if (pln_prog->phantom_plane.valid && 329 dc_phantom_pipes[0] && 330 dc_main_pipes[0]->stream && 331 dc_phantom_pipes[0]->plane_state) { 332 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; 333 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 334 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 335 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; 336 mcache_config->num_pipes = pln_prog->num_dpps_required; 337 l->build_mcache_programming_params.num_configurations++; 338 339 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 340 ASSERT(dc_phantom_pipes[dc_pipe_index]); 341 dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 342 } 343 344 /* increment phantom index */ 345 dml_phantom_prog_idx++; 346 } 347 } 348 349 /* Call to generate mcache programming per plane per pipe for the given display configuration */ 350 dml2_build_mcache_programming(&l->build_mcache_programming_params); 351 352 /* get per plane per pipe mcache programming */ 353 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 354 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 355 356 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 357 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || 358 dc_main_pipes[0]->plane_state == NULL) 359 continue; 360 361 /* get config for each pipe */ 362 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 363 ASSERT(dc_main_pipes[dc_pipe_index]); 364 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { 365 memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, 366 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], 367 sizeof(struct dml2_hubp_pipe_mcache_regs)); 368 } 369 } 370 371 /* get config for each phantom pipe */ 372 if (pln_prog->phantom_plane.valid && 373 dc_phantom_pipes[0] && 374 dc_main_pipes[0]->stream && 375 dc_phantom_pipes[0]->plane_state) { 376 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 377 ASSERT(dc_phantom_pipes[dc_pipe_index]); 378 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { 379 memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, 380 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], 381 sizeof(struct dml2_hubp_pipe_mcache_regs)); 382 } 383 } 384 /* increment phantom index */ 385 dml_phantom_prog_idx++; 386 } 387 } 388 } 389 390 void dml21_copy(struct dml2_context *dst_dml_ctx, 391 struct dml2_context *src_dml_ctx) 392 { 393 /* Preserve references to internals */ 394 struct dml2_instance *dst_dml2_instance = dst_dml_ctx->v21.dml_init.dml2_instance; 395 struct dml2_display_cfg_programming *dst_dml2_programming = dst_dml_ctx->v21.mode_programming.programming; 396 397 /* Copy context */ 398 memcpy(dst_dml_ctx, src_dml_ctx, sizeof(struct dml2_context)); 399 400 /* Copy Internals */ 401 memcpy(dst_dml2_instance, src_dml_ctx->v21.dml_init.dml2_instance, sizeof(struct dml2_instance)); 402 memcpy(dst_dml2_programming, src_dml_ctx->v21.mode_programming.programming, sizeof(struct dml2_display_cfg_programming)); 403 404 /* Restore references to internals */ 405 dst_dml_ctx->v21.dml_init.dml2_instance = dst_dml2_instance; 406 407 dst_dml_ctx->v21.mode_support.dml2_instance = dst_dml2_instance; 408 dst_dml_ctx->v21.mode_programming.dml2_instance = dst_dml2_instance; 409 410 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; 411 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; 412 413 dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming; 414 415 /* need to initialize copied instance for internal references to be correct */ 416 dml2_initialize_instance(&dst_dml_ctx->v21.dml_init); 417 } 418 419 bool dml21_create_copy(struct dml2_context **dst_dml_ctx, 420 struct dml2_context *src_dml_ctx) 421 { 422 /* Allocate memory for initializing DML21 instance */ 423 if (!dml21_allocate_memory(dst_dml_ctx)) 424 return false; 425 426 dml21_copy(*dst_dml_ctx, src_dml_ctx); 427 428 return true; 429 } 430 431 void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 432 { 433 dml21_init(in_dc, dml_ctx, config); 434 } 435 436