1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #include "dml2_internal_shared_types.h" 7 #include "dml21_translation_helper.h" 8 #include "dml2_internal_types.h" 9 #include "dml21_utils.h" 10 #include "dml2_dc_resource_mgmt.h" 11 12 #include "dml2_core_dcn4_calcs.h" 13 14 15 int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id) 16 { 17 int i; 18 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 19 if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id) 20 return i; 21 } 22 23 return -1; 24 } 25 26 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) 27 { 28 int i; 29 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 30 if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) 31 return i; 32 } 33 34 return -1; 35 } 36 37 bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id) 38 { 39 int i, j; 40 41 if (!plane_id) 42 return false; 43 44 for (i = 0; i < state->stream_count; i++) { 45 for (j = 0; j < state->stream_status[i].plane_count; j++) { 46 if (state->stream_status[i].plane_states[j] == plane) { 47 *plane_id = (i << 16) | j; 48 return true; 49 } 50 } 51 } 52 53 return false; 54 } 55 56 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id) 57 { 58 return 0xffff & plane_id; 59 } 60 61 void find_valid_pipe_idx_for_stream_index(const struct dml2_context *dml_ctx, unsigned int *dml_pipe_idx, unsigned int stream_index) 62 { 63 unsigned int i = 0; 64 65 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 66 if (dml_ctx->v21.mode_programming.programming->plane_programming[i].plane_descriptor->stream_index == stream_index) { 67 *dml_pipe_idx = i; 68 return; 69 } 70 } 71 } 72 73 void find_pipe_regs_idx(const struct dml2_context *dml_ctx, 74 struct pipe_ctx *pipe, unsigned int *pipe_regs_idx) 75 { 76 struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe); 77 78 *pipe_regs_idx = dml_ctx->config.callbacks.get_odm_slice_index(opp_head); 79 80 if (pipe->plane_state) 81 *pipe_regs_idx += dml_ctx->config.callbacks.get_mpc_slice_index(pipe); 82 } 83 84 /* places pipe references into pipes arrays and returns number of pipes */ 85 int dml21_find_dc_pipes_for_plane(const struct dc *in_dc, 86 struct dc_state *context, 87 struct dml2_context *dml_ctx, 88 struct pipe_ctx **dc_main_pipes, 89 struct pipe_ctx **dc_phantom_pipes, 90 int dml_plane_idx) 91 { 92 unsigned int dml_stream_index; 93 unsigned int main_stream_id; 94 unsigned int dc_plane_index; 95 struct dc_stream_state *dc_main_stream; 96 struct dc_stream_status *dc_main_stream_status; 97 struct dc_plane_state *dc_main_plane; 98 struct dc_stream_state *dc_phantom_stream; 99 struct dc_stream_status *dc_phantom_stream_status; 100 struct dc_plane_state *dc_phantom_plane; 101 int num_pipes = 0; 102 103 dml_stream_index = dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_idx].plane_descriptor->stream_index; 104 main_stream_id = dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]; 105 106 dc_main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, main_stream_id); 107 dc_main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_main_stream); 108 109 /* find main plane based on id */ 110 dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_idx]); 111 dc_main_plane = dc_main_stream_status->plane_states[dc_plane_index]; 112 113 if (dc_main_plane) { 114 num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc_main_pipes); 115 } else { 116 /* stream was configured with dummy plane, so get pipes from opp head */ 117 struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream); 118 num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes); 119 } 120 121 /* if phantom exists, find associated pipes */ 122 dc_phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream); 123 if (dc_phantom_stream && num_pipes > 0) { 124 dc_phantom_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream); 125 126 /* phantom plane will have same index as main */ 127 dc_phantom_plane = dc_phantom_stream_status->plane_states[dc_plane_index]; 128 129 dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_pipes); 130 } 131 132 return num_pipes; 133 } 134 135 136 void dml21_update_pipe_ctx_dchub_regs(struct dml2_display_rq_regs *rq_regs, 137 struct dml2_display_dlg_regs *disp_dlg_regs, 138 struct dml2_display_ttu_regs *disp_ttu_regs, 139 struct pipe_ctx *out) 140 { 141 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); 142 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; 143 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; 144 //out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size; 145 //out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size; 146 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; 147 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; 148 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; 149 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; 150 151 out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size; 152 out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size; 153 //out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size; 154 //out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size; 155 out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size; 156 out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size; 157 out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height; 158 out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear; 159 160 out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode; 161 out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode; 162 //out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode; 163 out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode; 164 out->rq_regs.plane1_base_address = rq_regs->plane1_base_address; 165 out->unbounded_req = rq_regs->unbounded_request_enabled; 166 167 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); 168 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; 169 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; 170 out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; 171 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; 172 out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler; 173 out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler; 174 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; 175 out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank; 176 out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank; 177 out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip; 178 out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip; 179 out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq; 180 out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch; 181 out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c; 182 out->dlg_regs.refcyc_per_tdlut_group = disp_dlg_regs->refcyc_per_tdlut_group; 183 out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l; 184 out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c; 185 //out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; 186 //out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c; 187 out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l; 188 out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c; 189 //out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l; 190 //out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c; 191 out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l; 192 out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c; 193 out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l; 194 out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c; 195 //out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l; 196 //out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c; 197 //out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l; 198 //out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c; 199 out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l; 200 out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c; 201 out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l; 202 out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c; 203 out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank; 204 out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip; 205 out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank; 206 out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip; 207 out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0; 208 out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0; 209 //out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1; 210 //out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1; 211 out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0; 212 out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit; 213 out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata; 214 out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta; 215 216 memset(&out->ttu_regs, 0, sizeof(out->ttu_regs)); 217 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; 218 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm; 219 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; 220 out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip; 221 out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l; 222 out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c; 223 out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0; 224 //out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1; 225 out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l; 226 out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c; 227 out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0; 228 //out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1; 229 out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l; 230 out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c; 231 out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0; 232 //out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1; 233 out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l; 234 out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c; 235 out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0; 236 //out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1; 237 } 238 239 void dml21_populate_mall_allocation_size(struct dc_state *context, 240 struct dml2_context *in_ctx, 241 struct dml2_per_plane_programming *pln_prog, 242 struct pipe_ctx *dc_pipe) 243 { 244 245 /* Reuse MALL Allocation Sizes logic from dcn32_fpu.c */ 246 /* Count from active, top pipes per plane only. Only add mall_ss_size_bytes for each unique plane. */ 247 if (dc_pipe->stream && dc_pipe->plane_state && 248 (dc_pipe->top_pipe == NULL || 249 dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) && 250 dc_pipe->prev_odm_pipe == NULL) { 251 /* SS: all active surfaces stored in MALL */ 252 if (in_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, dc_pipe) != SUBVP_PHANTOM) { 253 dc_pipe->surface_size_in_mall_bytes = pln_prog->surface_size_mall_bytes; 254 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; 255 } else { 256 /* SUBVP: phantom surfaces only stored in MALL */ 257 dc_pipe->surface_size_in_mall_bytes = pln_prog->svp_size_mall_bytes; 258 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; 259 } 260 } 261 } 262 263 bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx) 264 { 265 /* If this assert is hit then we have a link encoder dynamic management issue */ 266 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); 267 return (pipe_ctx->stream_res.hpo_dp_stream_enc && 268 pipe_ctx->link_res.hpo_dp_link_enc && 269 dc_is_dp_signal(pipe_ctx->stream->signal)); 270 } 271 272 void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, 273 struct dml2_per_stream_programming *stream_prog) 274 { 275 unsigned int pipe_reg_index = 0; 276 277 dml21_populate_pipe_ctx_dlg_params(dml_ctx, context, pipe_ctx, stream_prog); 278 find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index); 279 280 if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) { 281 memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set)); 282 pipe_ctx->unbounded_req = false; 283 284 /* legacy only, should be removed later */ 285 dml21_update_pipe_ctx_dchub_regs(&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->rq_regs, 286 &pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->dlg_regs, 287 &pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx); 288 289 pipe_ctx->det_buffer_size_kb = 0; 290 } else { 291 memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set)); 292 pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled; 293 294 /* legacy only, should be removed later */ 295 dml21_update_pipe_ctx_dchub_regs(&pln_prog->pipe_regs[pipe_reg_index]->rq_regs, 296 &pln_prog->pipe_regs[pipe_reg_index]->dlg_regs, 297 &pln_prog->pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx); 298 299 pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64; 300 } 301 302 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4.dppclk_khz; 303 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) 304 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; 305 306 dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx); 307 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[pipe_ctx->pipe_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); 308 } 309 310 static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml_ctx, 311 const struct dc *dc, 312 struct dc_state *context, 313 struct dc_stream_state *main_stream, 314 struct dml2_per_stream_programming *stream_programming) 315 { 316 struct dc_stream_state *phantom_stream; 317 struct dml2_stream_parameters *phantom_stream_descriptor = &stream_programming->phantom_stream.descriptor; 318 319 phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream); 320 321 /* copy details of phantom stream from main */ 322 memcpy(&phantom_stream->timing, &main_stream->timing, sizeof(phantom_stream->timing)); 323 memcpy(&phantom_stream->src, &main_stream->src, sizeof(phantom_stream->src)); 324 memcpy(&phantom_stream->dst, &main_stream->dst, sizeof(phantom_stream->dst)); 325 326 /* modify timing for phantom */ 327 phantom_stream->timing.v_front_porch = phantom_stream_descriptor->timing.v_front_porch; 328 phantom_stream->timing.v_addressable = phantom_stream_descriptor->timing.v_active; 329 phantom_stream->timing.v_total = phantom_stream_descriptor->timing.v_total; 330 phantom_stream->timing.flags.DSC = 0; // phantom always has DSC disabled 331 332 phantom_stream->dst.y = 0; 333 phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active; 334 335 phantom_stream->src.y = 0; 336 phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height; 337 338 phantom_stream->use_dynamic_meta = false; 339 340 dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream); 341 342 return phantom_stream; 343 } 344 345 static struct dc_plane_state *dml21_add_phantom_plane(struct dml2_context *dml_ctx, 346 const struct dc *dc, 347 struct dc_state *context, 348 struct dc_stream_state *phantom_stream, 349 struct dc_plane_state *main_plane, 350 struct dml2_per_plane_programming *plane_programming) 351 { 352 struct dc_plane_state *phantom_plane; 353 354 phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane); 355 356 phantom_plane->format = main_plane->format; 357 phantom_plane->rotation = main_plane->rotation; 358 phantom_plane->visible = main_plane->visible; 359 360 memcpy(&phantom_plane->address, &main_plane->address, sizeof(phantom_plane->address)); 361 memcpy(&phantom_plane->scaling_quality, &main_plane->scaling_quality, 362 sizeof(phantom_plane->scaling_quality)); 363 memcpy(&phantom_plane->src_rect, &main_plane->src_rect, sizeof(phantom_plane->src_rect)); 364 memcpy(&phantom_plane->dst_rect, &main_plane->dst_rect, sizeof(phantom_plane->dst_rect)); 365 memcpy(&phantom_plane->clip_rect, &main_plane->clip_rect, sizeof(phantom_plane->clip_rect)); 366 memcpy(&phantom_plane->plane_size, &main_plane->plane_size, 367 sizeof(phantom_plane->plane_size)); 368 memcpy(&phantom_plane->tiling_info, &main_plane->tiling_info, 369 sizeof(phantom_plane->tiling_info)); 370 memcpy(&phantom_plane->dcc, &main_plane->dcc, sizeof(phantom_plane->dcc)); 371 372 phantom_plane->format = main_plane->format; 373 phantom_plane->rotation = main_plane->rotation; 374 phantom_plane->visible = main_plane->visible; 375 376 /* Shadow pipe has small viewport. */ 377 phantom_plane->clip_rect.y = 0; 378 phantom_plane->clip_rect.height = phantom_stream->src.height; 379 380 dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context); 381 382 return phantom_plane; 383 } 384 385 void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx) 386 { 387 unsigned int dml_stream_index, dml_plane_index, dc_plane_index; 388 struct dc_stream_state *main_stream; 389 struct dc_stream_status *main_stream_status; 390 struct dc_stream_state *phantom_stream; 391 struct dc_plane_state *main_plane; 392 bool phantoms_added = false; 393 394 /* create phantom streams and planes and add to context */ 395 for (dml_stream_index = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_config.num_streams; dml_stream_index++) { 396 /* iterate through DML streams looking for phantoms */ 397 if (dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index].phantom_stream.enabled) { 398 /* find associated dc stream */ 399 main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, 400 dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]); 401 402 main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, main_stream); 403 404 if (main_stream_status->plane_count == 0) 405 continue; 406 407 /* create phantom stream for subvp enabled stream */ 408 phantom_stream = dml21_add_phantom_stream(dml_ctx, 409 dc, 410 context, 411 main_stream, 412 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index]); 413 414 /* iterate through DML planes associated with this stream */ 415 for (dml_plane_index = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_plane_index++) { 416 if (dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index].plane_descriptor->stream_index == dml_stream_index) { 417 /* find associated dc plane */ 418 dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_index]); 419 main_plane = main_stream_status->plane_states[dc_plane_index]; 420 421 /* create phantom planes for subvp enabled plane */ 422 dml21_add_phantom_plane(dml_ctx, 423 dc, 424 context, 425 phantom_stream, 426 main_plane, 427 &dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index]); 428 429 phantoms_added = true; 430 } 431 } 432 } 433 } 434 435 if (phantoms_added) 436 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); 437 } 438 439 void dml21_build_fams2_programming(const struct dc *dc, 440 struct dc_state *context, 441 struct dml2_context *dml_ctx) 442 { 443 int i, j, k; 444 445 /* reset fams2 data */ 446 context->bw_ctx.bw.dcn.fams2_stream_count = 0; 447 memset(&context->bw_ctx.bw.dcn.fams2_stream_params, 0, sizeof(struct dmub_fams2_stream_static_state) * DML2_MAX_PLANES); 448 449 if (!dml_ctx->v21.mode_programming.programming->fams2_required) 450 return; 451 452 for (i = 0; i < context->stream_count; i++) { 453 int dml_stream_idx; 454 struct dc_stream_state *phantom_stream; 455 struct dc_stream_status *phantom_status; 456 457 struct dmub_fams2_stream_static_state *static_state = &context->bw_ctx.bw.dcn.fams2_stream_params[context->bw_ctx.bw.dcn.fams2_stream_count]; 458 459 struct dc_stream_state *stream = context->streams[i]; 460 461 if (context->stream_status[i].plane_count == 0 || 462 dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { 463 /* can ignore blanked or phantom streams */ 464 continue; 465 } 466 467 dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); 468 if (dml_stream_idx < 0) { 469 ASSERT(dml_stream_idx >= 0); 470 continue; 471 } 472 473 /* copy static state from PMO */ 474 memcpy(static_state, 475 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_params, 476 sizeof(struct dmub_fams2_stream_static_state)); 477 478 /* get information from context */ 479 static_state->num_planes = context->stream_status[i].plane_count; 480 static_state->otg_inst = context->stream_status[i].primary_otg_inst; 481 482 /* populate pipe masks for planes */ 483 for (j = 0; j < context->stream_status[i].plane_count; j++) { 484 for (k = 0; k < dc->res_pool->pipe_count; k++) { 485 if (context->res_ctx.pipe_ctx[k].stream && 486 context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id && 487 context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { 488 static_state->pipe_mask |= (1 << k); 489 static_state->plane_pipe_masks[j] |= (1 << k); 490 } 491 } 492 } 493 494 /* get per method programming */ 495 switch (static_state->type) { 496 case FAMS2_STREAM_TYPE_VBLANK: 497 case FAMS2_STREAM_TYPE_VACTIVE: 498 case FAMS2_STREAM_TYPE_DRR: 499 break; 500 case FAMS2_STREAM_TYPE_SUBVP: 501 phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); 502 phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); 503 504 /* phantom status should always be present */ 505 ASSERT(phantom_status); 506 static_state->sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; 507 508 /* populate pipe masks for phantom planes */ 509 for (j = 0; j < phantom_status->plane_count; j++) { 510 for (k = 0; k < dc->res_pool->pipe_count; k++) { 511 if (context->res_ctx.pipe_ctx[k].stream && 512 context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id && 513 context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) { 514 static_state->sub_state.subvp.phantom_pipe_mask |= (1 << k); 515 static_state->sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k); 516 } 517 } 518 } 519 break; 520 default: 521 ASSERT(false); 522 break; 523 } 524 525 context->bw_ctx.bw.dcn.fams2_stream_count++; 526 } 527 528 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_stream_count > 0; 529 } 530 531 bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format) 532 { 533 return source_format >= dml2_420_8 && source_format <= dml2_rgbe_alpha; 534 } 535