1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_features.h" 27 #include "display_mode_enums.h" 28 29 #ifndef __DISPLAY_MODE_STRUCTS_H__ 30 #define __DISPLAY_MODE_STRUCTS_H__ 31 32 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 33 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 34 typedef struct _vcs_dpi_ip_params_st ip_params_st; 35 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 36 typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 37 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 38 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 39 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 40 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 41 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 42 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 43 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 44 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 45 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 46 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 47 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 48 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 49 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 50 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 51 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 52 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 53 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 54 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 55 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 56 57 typedef struct { 58 double UrgentWatermark; 59 double WritebackUrgentWatermark; 60 double DRAMClockChangeWatermark; 61 double FCLKChangeWatermark; 62 double WritebackDRAMClockChangeWatermark; 63 double WritebackFCLKChangeWatermark; 64 double StutterExitWatermark; 65 double StutterEnterPlusExitWatermark; 66 double Z8StutterExitWatermark; 67 double Z8StutterEnterPlusExitWatermark; 68 double USRRetrainingWatermark; 69 } Watermarks; 70 71 typedef struct { 72 double UrgentLatency; 73 double ExtraLatency; 74 double WritebackLatency; 75 double DRAMClockChangeLatency; 76 double FCLKChangeLatency; 77 double SRExitTime; 78 double SREnterPlusExitTime; 79 double SRExitZ8Time; 80 double SREnterPlusExitZ8Time; 81 double USRRetrainingLatencyPlusSMNLatency; 82 } Latencies; 83 84 typedef struct { 85 double Dppclk; 86 double Dispclk; 87 double PixelClock; 88 double DCFClkDeepSleep; 89 unsigned int DPPPerSurface; 90 bool ScalerEnabled; 91 enum dm_rotation_angle SourceRotation; 92 unsigned int ViewportHeight; 93 unsigned int ViewportHeightChroma; 94 unsigned int BlockWidth256BytesY; 95 unsigned int BlockHeight256BytesY; 96 unsigned int BlockWidth256BytesC; 97 unsigned int BlockHeight256BytesC; 98 unsigned int BlockWidthY; 99 unsigned int BlockHeightY; 100 unsigned int BlockWidthC; 101 unsigned int BlockHeightC; 102 unsigned int InterlaceEnable; 103 unsigned int NumberOfCursors; 104 unsigned int VBlank; 105 unsigned int HTotal; 106 unsigned int HActive; 107 bool DCCEnable; 108 enum odm_combine_mode ODMMode; 109 enum source_format_class SourcePixelFormat; 110 enum dm_swizzle_mode SurfaceTiling; 111 unsigned int BytePerPixelY; 112 unsigned int BytePerPixelC; 113 bool ProgressiveToInterlaceUnitInOPP; 114 double VRatio; 115 double VRatioChroma; 116 unsigned int VTaps; 117 unsigned int VTapsChroma; 118 unsigned int PitchY; 119 unsigned int DCCMetaPitchY; 120 unsigned int PitchC; 121 unsigned int DCCMetaPitchC; 122 bool ViewportStationary; 123 unsigned int ViewportXStart; 124 unsigned int ViewportYStart; 125 unsigned int ViewportXStartC; 126 unsigned int ViewportYStartC; 127 bool FORCE_ONE_ROW_FOR_FRAME; 128 unsigned int SwathHeightY; 129 unsigned int SwathHeightC; 130 } DmlPipe; 131 132 typedef struct { 133 double UrgentLatency; 134 double ExtraLatency; 135 double WritebackLatency; 136 double DRAMClockChangeLatency; 137 double FCLKChangeLatency; 138 double SRExitTime; 139 double SREnterPlusExitTime; 140 double SRExitZ8Time; 141 double SREnterPlusExitZ8Time; 142 double USRRetrainingLatency; 143 double SMNLatency; 144 } SOCParametersList; 145 146 struct _vcs_dpi_voltage_scaling_st { 147 int state; 148 double dscclk_mhz; 149 double dcfclk_mhz; 150 double socclk_mhz; 151 double phyclk_d18_mhz; 152 double phyclk_d32_mhz; 153 double dram_speed_mts; 154 double fabricclk_mhz; 155 double dispclk_mhz; 156 double dram_bw_per_chan_gbps; 157 double phyclk_mhz; 158 double dppclk_mhz; 159 double dtbclk_mhz; 160 }; 161 162 struct _vcs_dpi_soc_bounding_box_st { 163 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 164 /* 165 * This is a temporary stash for updating @clock_limits with the PMFW 166 * clock table. Do not use outside of *update_bw_boudning_box functions. 167 */ 168 struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES]; 169 unsigned int num_states; 170 double sr_exit_time_us; 171 double sr_enter_plus_exit_time_us; 172 double sr_exit_z8_time_us; 173 double sr_enter_plus_exit_z8_time_us; 174 double urgent_latency_us; 175 double urgent_latency_pixel_data_only_us; 176 double urgent_latency_pixel_mixed_with_vm_data_us; 177 double urgent_latency_vm_data_only_us; 178 double usr_retraining_latency_us; 179 double smn_latency_us; 180 double fclk_change_latency_us; 181 double mall_allocated_for_dcn_mbytes; 182 double pct_ideal_fabric_bw_after_urgent; 183 double pct_ideal_dram_bw_after_urgent_strobe; 184 double max_avg_fabric_bw_use_normal_percent; 185 double max_avg_dram_bw_use_normal_strobe_percent; 186 enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final; 187 bool dram_clock_change_requirement_final; 188 double writeback_latency_us; 189 double ideal_dram_bw_after_urgent_percent; 190 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 191 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 192 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 193 double pct_ideal_sdp_bw_after_urgent; 194 double max_avg_sdp_bw_use_normal_percent; 195 double max_avg_dram_bw_use_normal_percent; 196 unsigned int max_request_size_bytes; 197 double downspread_percent; 198 double dram_page_open_time_ns; 199 double dram_rw_turnaround_time_ns; 200 double dram_return_buffer_per_channel_bytes; 201 double dram_channel_width_bytes; 202 double fabric_datapath_to_dcn_data_return_bytes; 203 double dcn_downspread_percent; 204 double dispclk_dppclk_vco_speed_mhz; 205 double dfs_vco_period_ps; 206 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 207 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 208 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 209 unsigned int round_trip_ping_latency_dcfclk_cycles; 210 unsigned int urgent_out_of_order_return_per_channel_bytes; 211 unsigned int channel_interleave_bytes; 212 unsigned int num_banks; 213 unsigned int num_chans; 214 unsigned int vmm_page_size_bytes; 215 unsigned int hostvm_min_page_size_bytes; 216 unsigned int gpuvm_min_page_size_bytes; 217 double dram_clock_change_latency_us; 218 double dummy_pstate_latency_us; 219 double writeback_dram_clock_change_latency_us; 220 unsigned int return_bus_width_bytes; 221 unsigned int voltage_override; 222 double xfc_bus_transport_time_us; 223 double xfc_xbuf_latency_tolerance_us; 224 int use_urgent_burst_bw; 225 double min_dcfclk; 226 bool do_urgent_latency_adjustment; 227 double urgent_latency_adjustment_fabric_clock_component_us; 228 double urgent_latency_adjustment_fabric_clock_reference_mhz; 229 bool disable_dram_clock_change_vactive_support; 230 bool allow_dram_clock_one_display_vactive; 231 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank; 232 }; 233 234 struct _vcs_dpi_ip_params_st { 235 bool use_min_dcfclk; 236 bool clamp_min_dcfclk; 237 bool gpuvm_enable; 238 bool hostvm_enable; 239 bool dsc422_native_support; 240 unsigned int gpuvm_max_page_table_levels; 241 unsigned int hostvm_max_page_table_levels; 242 unsigned int hostvm_cached_page_table_levels; 243 unsigned int pte_group_size_bytes; 244 unsigned int max_inter_dcn_tile_repeaters; 245 unsigned int num_dsc; 246 unsigned int odm_capable; 247 unsigned int rob_buffer_size_kbytes; 248 unsigned int det_buffer_size_kbytes; 249 unsigned int min_comp_buffer_size_kbytes; 250 unsigned int dpte_buffer_size_in_pte_reqs_luma; 251 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 252 unsigned int pde_proc_buffer_size_64k_reqs; 253 unsigned int dpp_output_buffer_pixels; 254 unsigned int opp_output_buffer_lines; 255 unsigned int pixel_chunk_size_kbytes; 256 unsigned int alpha_pixel_chunk_size_kbytes; 257 unsigned int min_pixel_chunk_size_bytes; 258 unsigned int dcc_meta_buffer_size_bytes; 259 unsigned char pte_enable; 260 unsigned int pte_chunk_size_kbytes; 261 unsigned int meta_chunk_size_kbytes; 262 unsigned int min_meta_chunk_size_bytes; 263 unsigned int writeback_chunk_size_kbytes; 264 unsigned int line_buffer_size_bits; 265 unsigned int max_line_buffer_lines; 266 unsigned int writeback_luma_buffer_size_kbytes; 267 unsigned int writeback_chroma_buffer_size_kbytes; 268 unsigned int writeback_chroma_line_buffer_width_pixels; 269 270 unsigned int writeback_interface_buffer_size_kbytes; 271 unsigned int writeback_line_buffer_buffer_size; 272 273 unsigned int writeback_10bpc420_supported; 274 double writeback_max_hscl_ratio; 275 double writeback_max_vscl_ratio; 276 double writeback_min_hscl_ratio; 277 double writeback_min_vscl_ratio; 278 unsigned int maximum_dsc_bits_per_component; 279 unsigned int maximum_pixels_per_line_per_dsc_unit; 280 unsigned int writeback_max_hscl_taps; 281 unsigned int writeback_max_vscl_taps; 282 unsigned int writeback_line_buffer_luma_buffer_size; 283 unsigned int writeback_line_buffer_chroma_buffer_size; 284 285 unsigned int max_page_table_levels; 286 unsigned int max_num_dpp; 287 unsigned int max_num_otg; 288 unsigned int cursor_chunk_size; 289 unsigned int cursor_buffer_size; 290 unsigned int max_num_wb; 291 unsigned int max_dchub_pscl_bw_pix_per_clk; 292 unsigned int max_pscl_lb_bw_pix_per_clk; 293 unsigned int max_lb_vscl_bw_pix_per_clk; 294 unsigned int max_vscl_hscl_bw_pix_per_clk; 295 double max_hscl_ratio; 296 double max_vscl_ratio; 297 unsigned int hscl_mults; 298 unsigned int vscl_mults; 299 unsigned int max_hscl_taps; 300 unsigned int max_vscl_taps; 301 unsigned int xfc_supported; 302 unsigned int ptoi_supported; 303 unsigned int gfx7_compat_tiling_supported; 304 305 bool odm_combine_4to1_supported; 306 bool dynamic_metadata_vm_enabled; 307 unsigned int max_num_hdmi_frl_outputs; 308 309 unsigned int xfc_fill_constant_bytes; 310 double dispclk_ramp_margin_percent; 311 double xfc_fill_bw_overhead_percent; 312 double underscan_factor; 313 unsigned int min_vblank_lines; 314 unsigned int dppclk_delay_subtotal; 315 unsigned int dispclk_delay_subtotal; 316 double dcfclk_cstate_latency; 317 unsigned int dppclk_delay_scl; 318 unsigned int dppclk_delay_scl_lb_only; 319 unsigned int dppclk_delay_cnvc_formatter; 320 unsigned int dppclk_delay_cnvc_cursor; 321 unsigned int is_line_buffer_bpp_fixed; 322 unsigned int line_buffer_fixed_bpp; 323 unsigned int dcc_supported; 324 unsigned int config_return_buffer_size_in_kbytes; 325 unsigned int compressed_buffer_segment_size_in_kbytes; 326 unsigned int meta_fifo_size_in_kentries; 327 unsigned int zero_size_buffer_entries; 328 unsigned int compbuf_reserved_space_64b; 329 unsigned int compbuf_reserved_space_zs; 330 331 unsigned int IsLineBufferBppFixed; 332 unsigned int LineBufferFixedBpp; 333 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 334 unsigned int bug_forcing_LC_req_same_size_fixed; 335 unsigned int number_of_cursors; 336 unsigned int max_num_dp2p0_outputs; 337 unsigned int max_num_dp2p0_streams; 338 unsigned int VBlankNomDefaultUS; 339 }; 340 341 struct _vcs_dpi_display_xfc_params_st { 342 double xfc_tslv_vready_offset_us; 343 double xfc_tslv_vupdate_width_us; 344 double xfc_tslv_vupdate_offset_us; 345 int xfc_slv_chunk_size_bytes; 346 }; 347 348 struct _vcs_dpi_display_pipe_source_params_st { 349 int source_format; 350 double dcc_fraction_of_zs_req_luma; 351 double dcc_fraction_of_zs_req_chroma; 352 unsigned char dcc; 353 unsigned int dcc_rate; 354 unsigned int dcc_rate_chroma; 355 unsigned char dcc_use_global; 356 unsigned char vm; 357 bool unbounded_req_mode; 358 bool gpuvm; // gpuvm enabled 359 bool hostvm; // hostvm enabled 360 bool gpuvm_levels_force_en; 361 unsigned int gpuvm_levels_force; 362 bool hostvm_levels_force_en; 363 unsigned int hostvm_levels_force; 364 int source_scan; 365 int source_rotation; // new in dml32 366 unsigned int det_size_override; // use to populate DETSizeOverride in vba struct 367 int sw_mode; 368 int macro_tile_size; 369 unsigned int surface_width_y; 370 unsigned int surface_height_y; 371 unsigned int surface_width_c; 372 unsigned int surface_height_c; 373 unsigned int viewport_width; 374 unsigned int viewport_height; 375 unsigned int viewport_y_y; 376 unsigned int viewport_y_c; 377 unsigned int viewport_width_c; 378 unsigned int viewport_height_c; 379 unsigned int viewport_width_max; 380 unsigned int viewport_height_max; 381 unsigned int viewport_x_y; 382 unsigned int viewport_x_c; 383 bool viewport_stationary; 384 unsigned int dcc_rate_luma; 385 unsigned int gpuvm_min_page_size_kbytes; 386 unsigned int use_mall_for_pstate_change; 387 unsigned int use_mall_for_static_screen; 388 bool force_one_row_for_frame; 389 bool pte_buffer_mode; 390 unsigned int data_pitch; 391 unsigned int data_pitch_c; 392 unsigned int meta_pitch; 393 unsigned int meta_pitch_c; 394 unsigned int cur0_src_width; 395 int cur0_bpp; 396 unsigned int cur1_src_width; 397 int cur1_bpp; 398 int num_cursors; 399 unsigned char is_hsplit; 400 unsigned char dynamic_metadata_enable; 401 unsigned int dynamic_metadata_lines_before_active; 402 unsigned int dynamic_metadata_xmit_bytes; 403 unsigned int hsplit_grp; 404 unsigned char xfc_enable; 405 unsigned char xfc_slave; 406 unsigned char immediate_flip; 407 struct _vcs_dpi_display_xfc_params_st xfc_params; 408 //for vstartuplines calculation freesync 409 unsigned char v_total_min; 410 unsigned char v_total_max; 411 }; 412 struct writeback_st { 413 int wb_src_height; 414 int wb_src_width; 415 int wb_dst_width; 416 int wb_dst_height; 417 int wb_pixel_format; 418 int wb_htaps_luma; 419 int wb_vtaps_luma; 420 int wb_htaps_chroma; 421 int wb_vtaps_chroma; 422 unsigned int wb_htaps; 423 unsigned int wb_vtaps; 424 double wb_hratio; 425 double wb_vratio; 426 }; 427 428 struct display_audio_params_st { 429 unsigned int audio_sample_rate_khz; 430 int audio_sample_layout; 431 }; 432 433 struct _vcs_dpi_display_output_params_st { 434 int dp_lanes; 435 double output_bpp; 436 unsigned int dsc_input_bpc; 437 int dsc_enable; 438 int wb_enable; 439 int num_active_wb; 440 int output_type; 441 int is_virtual; 442 int output_format; 443 int dsc_slices; 444 int max_audio_sample_rate; 445 struct writeback_st wb; 446 struct display_audio_params_st audio; 447 unsigned int output_bpc; 448 int dp_rate; 449 unsigned int dp_multistream_id; 450 bool dp_multistream_en; 451 }; 452 453 struct _vcs_dpi_scaler_ratio_depth_st { 454 double hscl_ratio; 455 double vscl_ratio; 456 double hscl_ratio_c; 457 double vscl_ratio_c; 458 double vinit; 459 double vinit_c; 460 double vinit_bot; 461 double vinit_bot_c; 462 int lb_depth; 463 int scl_enable; 464 }; 465 466 struct _vcs_dpi_scaler_taps_st { 467 unsigned int htaps; 468 unsigned int vtaps; 469 unsigned int htaps_c; 470 unsigned int vtaps_c; 471 }; 472 473 struct _vcs_dpi_display_pipe_dest_params_st { 474 unsigned int recout_width; 475 unsigned int recout_height; 476 unsigned int full_recout_width; 477 unsigned int full_recout_height; 478 unsigned int hblank_start; 479 unsigned int hblank_end; 480 unsigned int vblank_start; 481 unsigned int vblank_end; 482 unsigned int htotal; 483 unsigned int vtotal; 484 unsigned int vfront_porch; 485 unsigned int vactive; 486 unsigned int hactive; 487 unsigned int vstartup_start; 488 unsigned int vupdate_offset; 489 unsigned int vupdate_width; 490 unsigned int vready_offset; 491 unsigned char interlaced; 492 double pixel_rate_mhz; 493 unsigned char synchronized_vblank_all_planes; 494 unsigned char otg_inst; 495 unsigned int odm_combine; 496 unsigned char use_maximum_vstartup; 497 unsigned int vtotal_max; 498 unsigned int vtotal_min; 499 unsigned int refresh_rate; 500 bool synchronize_timings; 501 unsigned int odm_combine_policy; 502 bool drr_display; 503 }; 504 505 struct _vcs_dpi_display_pipe_params_st { 506 display_pipe_source_params_st src; 507 display_pipe_dest_params_st dest; 508 scaler_ratio_depth_st scale_ratio_depth; 509 scaler_taps_st scale_taps; 510 }; 511 512 struct _vcs_dpi_display_clocks_and_cfg_st { 513 int voltage; 514 double dppclk_mhz; 515 double refclk_mhz; 516 double dispclk_mhz; 517 double dcfclk_mhz; 518 double socclk_mhz; 519 }; 520 521 struct _vcs_dpi_display_e2e_pipe_params_st { 522 display_pipe_params_st pipe; 523 display_output_params_st dout; 524 display_clocks_and_cfg_st clks_cfg; 525 }; 526 527 struct _vcs_dpi_display_data_rq_misc_params_st { 528 unsigned int full_swath_bytes; 529 unsigned int stored_swath_bytes; 530 unsigned int blk256_height; 531 unsigned int blk256_width; 532 unsigned int req_height; 533 unsigned int req_width; 534 }; 535 536 struct _vcs_dpi_display_data_rq_sizing_params_st { 537 unsigned int chunk_bytes; 538 unsigned int min_chunk_bytes; 539 unsigned int meta_chunk_bytes; 540 unsigned int min_meta_chunk_bytes; 541 unsigned int mpte_group_bytes; 542 unsigned int dpte_group_bytes; 543 }; 544 545 struct _vcs_dpi_display_data_rq_dlg_params_st { 546 unsigned int swath_width_ub; 547 unsigned int swath_height; 548 unsigned int req_per_swath_ub; 549 unsigned int meta_pte_bytes_per_frame_ub; 550 unsigned int dpte_req_per_row_ub; 551 unsigned int dpte_groups_per_row_ub; 552 unsigned int dpte_row_height; 553 unsigned int dpte_bytes_per_row_ub; 554 unsigned int meta_chunks_per_row_ub; 555 unsigned int meta_req_per_row_ub; 556 unsigned int meta_row_height; 557 unsigned int meta_bytes_per_row_ub; 558 }; 559 560 struct _vcs_dpi_display_rq_dlg_params_st { 561 display_data_rq_dlg_params_st rq_l; 562 display_data_rq_dlg_params_st rq_c; 563 }; 564 565 struct _vcs_dpi_display_rq_sizing_params_st { 566 display_data_rq_sizing_params_st rq_l; 567 display_data_rq_sizing_params_st rq_c; 568 }; 569 570 struct _vcs_dpi_display_rq_misc_params_st { 571 display_data_rq_misc_params_st rq_l; 572 display_data_rq_misc_params_st rq_c; 573 }; 574 575 struct _vcs_dpi_display_rq_params_st { 576 unsigned char yuv420; 577 unsigned char yuv420_10bpc; 578 unsigned char rgbe_alpha; 579 display_rq_misc_params_st misc; 580 display_rq_sizing_params_st sizing; 581 display_rq_dlg_params_st dlg; 582 }; 583 584 struct _vcs_dpi_display_dlg_regs_st { 585 unsigned int refcyc_h_blank_end; 586 unsigned int dlg_vblank_end; 587 unsigned int min_dst_y_next_start; 588 unsigned int optimized_min_dst_y_next_start; 589 unsigned int optimized_min_dst_y_next_start_us; 590 unsigned int refcyc_per_htotal; 591 unsigned int refcyc_x_after_scaler; 592 unsigned int dst_y_after_scaler; 593 unsigned int dst_y_prefetch; 594 unsigned int dst_y_per_vm_vblank; 595 unsigned int dst_y_per_row_vblank; 596 unsigned int dst_y_per_vm_flip; 597 unsigned int dst_y_per_row_flip; 598 unsigned int ref_freq_to_pix_freq; 599 unsigned int vratio_prefetch; 600 unsigned int vratio_prefetch_c; 601 unsigned int refcyc_per_pte_group_vblank_l; 602 unsigned int refcyc_per_pte_group_vblank_c; 603 unsigned int refcyc_per_meta_chunk_vblank_l; 604 unsigned int refcyc_per_meta_chunk_vblank_c; 605 unsigned int refcyc_per_pte_group_flip_l; 606 unsigned int refcyc_per_pte_group_flip_c; 607 unsigned int refcyc_per_meta_chunk_flip_l; 608 unsigned int refcyc_per_meta_chunk_flip_c; 609 unsigned int dst_y_per_pte_row_nom_l; 610 unsigned int dst_y_per_pte_row_nom_c; 611 unsigned int refcyc_per_pte_group_nom_l; 612 unsigned int refcyc_per_pte_group_nom_c; 613 unsigned int dst_y_per_meta_row_nom_l; 614 unsigned int dst_y_per_meta_row_nom_c; 615 unsigned int refcyc_per_meta_chunk_nom_l; 616 unsigned int refcyc_per_meta_chunk_nom_c; 617 unsigned int refcyc_per_line_delivery_pre_l; 618 unsigned int refcyc_per_line_delivery_pre_c; 619 unsigned int refcyc_per_line_delivery_l; 620 unsigned int refcyc_per_line_delivery_c; 621 unsigned int chunk_hdl_adjust_cur0; 622 unsigned int chunk_hdl_adjust_cur1; 623 unsigned int vready_after_vcount0; 624 unsigned int dst_y_offset_cur0; 625 unsigned int dst_y_offset_cur1; 626 unsigned int xfc_reg_transfer_delay; 627 unsigned int xfc_reg_precharge_delay; 628 unsigned int xfc_reg_remote_surface_flip_latency; 629 unsigned int xfc_reg_prefetch_margin; 630 unsigned int dst_y_delta_drq_limit; 631 unsigned int refcyc_per_vm_group_vblank; 632 unsigned int refcyc_per_vm_group_flip; 633 unsigned int refcyc_per_vm_req_vblank; 634 unsigned int refcyc_per_vm_req_flip; 635 unsigned int refcyc_per_vm_dmdata; 636 unsigned int dmdata_dl_delta; 637 }; 638 639 struct _vcs_dpi_display_ttu_regs_st { 640 unsigned int qos_level_low_wm; 641 unsigned int qos_level_high_wm; 642 unsigned int min_ttu_vblank; 643 unsigned int qos_level_flip; 644 unsigned int refcyc_per_req_delivery_l; 645 unsigned int refcyc_per_req_delivery_c; 646 unsigned int refcyc_per_req_delivery_cur0; 647 unsigned int refcyc_per_req_delivery_cur1; 648 unsigned int refcyc_per_req_delivery_pre_l; 649 unsigned int refcyc_per_req_delivery_pre_c; 650 unsigned int refcyc_per_req_delivery_pre_cur0; 651 unsigned int refcyc_per_req_delivery_pre_cur1; 652 unsigned int qos_level_fixed_l; 653 unsigned int qos_level_fixed_c; 654 unsigned int qos_level_fixed_cur0; 655 unsigned int qos_level_fixed_cur1; 656 unsigned int qos_ramp_disable_l; 657 unsigned int qos_ramp_disable_c; 658 unsigned int qos_ramp_disable_cur0; 659 unsigned int qos_ramp_disable_cur1; 660 }; 661 662 struct _vcs_dpi_display_data_rq_regs_st { 663 unsigned int chunk_size; 664 unsigned int min_chunk_size; 665 unsigned int meta_chunk_size; 666 unsigned int min_meta_chunk_size; 667 unsigned int dpte_group_size; 668 unsigned int mpte_group_size; 669 unsigned int swath_height; 670 unsigned int pte_row_height_linear; 671 }; 672 673 struct _vcs_dpi_display_rq_regs_st { 674 display_data_rq_regs_st rq_regs_l; 675 display_data_rq_regs_st rq_regs_c; 676 unsigned int drq_expansion_mode; 677 unsigned int prq_expansion_mode; 678 unsigned int mrq_expansion_mode; 679 unsigned int crq_expansion_mode; 680 unsigned int plane1_base_address; 681 unsigned int aperture_low_addr; // bits [47:18] 682 unsigned int aperture_high_addr; // bits [47:18] 683 }; 684 685 struct _vcs_dpi_display_dlg_sys_params_st { 686 double t_mclk_wm_us; 687 double t_urg_wm_us; 688 double t_sr_wm_us; 689 double t_extra_us; 690 double mem_trip_us; 691 double deepsleep_dcfclk_mhz; 692 double total_flip_bw; 693 unsigned int total_flip_bytes; 694 }; 695 696 struct _vcs_dpi_display_arb_params_st { 697 int max_req_outstanding; 698 int min_req_outstanding; 699 int sat_level_us; 700 int hvm_min_req_outstand_commit_threshold; 701 int hvm_max_qos_commit_threshold; 702 int compbuf_reserved_space_kbytes; 703 }; 704 705 #endif /*__DISPLAY_MODE_STRUCTS_H__*/ 706