1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "reg_helper.h" 30 31 #include "core_types.h" 32 #include "link_encoder.h" 33 #include "dce_link_encoder.h" 34 #include "stream_encoder.h" 35 #include "i2caux_interface.h" 36 #include "dc_bios_types.h" 37 38 #include "gpio_service_interface.h" 39 40 #include "dce/dce_11_0_d.h" 41 #include "dce/dce_11_0_sh_mask.h" 42 #include "dce/dce_11_0_enum.h" 43 44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 46 #endif 47 48 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 49 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 50 #endif 51 52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 54 #endif 55 56 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 57 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 58 #endif 59 60 #define CTX \ 61 enc110->base.ctx 62 #define DC_LOGGER \ 63 enc110->base.ctx->logger 64 65 #define REG(reg)\ 66 (enc110->link_regs->reg) 67 68 #define AUX_REG(reg)\ 69 (enc110->aux_regs->reg) 70 71 #define HPD_REG(reg)\ 72 (enc110->hpd_regs->reg) 73 74 #define DEFAULT_AUX_MAX_DATA_SIZE 16 75 #define AUX_MAX_DEFER_WRITE_RETRY 20 76 /* 77 * @brief 78 * Trigger Source Select 79 * ASIC-dependent, actual values for register programming 80 */ 81 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 86 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 87 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 88 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 89 90 enum { 91 DP_MST_UPDATE_MAX_RETRY = 50 92 }; 93 94 #define DIG_REG(reg)\ 95 (reg + enc110->offsets.dig) 96 97 #define DP_REG(reg)\ 98 (reg + enc110->offsets.dp) 99 100 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 101 .validate_output_with_stream = 102 dce110_link_encoder_validate_output_with_stream, 103 .hw_init = dce110_link_encoder_hw_init, 104 .setup = dce110_link_encoder_setup, 105 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 106 .enable_dp_output = dce110_link_encoder_enable_dp_output, 107 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 108 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 109 .disable_output = dce110_link_encoder_disable_output, 110 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 111 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 112 .update_mst_stream_allocation_table = 113 dce110_link_encoder_update_mst_stream_allocation_table, 114 .psr_program_dp_dphy_fast_training = 115 dce110_psr_program_dp_dphy_fast_training, 116 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 117 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 118 .enable_hpd = dce110_link_encoder_enable_hpd, 119 .disable_hpd = dce110_link_encoder_disable_hpd, 120 .is_dig_enabled = dce110_is_dig_enabled, 121 .destroy = dce110_link_encoder_destroy, 122 .get_max_link_cap = dce110_link_encoder_get_max_link_cap 123 }; 124 125 static enum bp_result link_transmitter_control( 126 struct dce110_link_encoder *enc110, 127 struct bp_transmitter_control *cntl) 128 { 129 enum bp_result result; 130 struct dc_bios *bp = enc110->base.ctx->dc_bios; 131 132 result = bp->funcs->transmitter_control(bp, cntl); 133 134 return result; 135 } 136 137 static void enable_phy_bypass_mode( 138 struct dce110_link_encoder *enc110, 139 bool enable) 140 { 141 /* This register resides in DP back end block; 142 * transmitter is used for the offset */ 143 144 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 145 146 } 147 148 static void disable_prbs_symbols( 149 struct dce110_link_encoder *enc110, 150 bool disable) 151 { 152 /* This register resides in DP back end block; 153 * transmitter is used for the offset */ 154 155 REG_UPDATE_4(DP_DPHY_CNTL, 156 DPHY_ATEST_SEL_LANE0, disable, 157 DPHY_ATEST_SEL_LANE1, disable, 158 DPHY_ATEST_SEL_LANE2, disable, 159 DPHY_ATEST_SEL_LANE3, disable); 160 } 161 162 static void disable_prbs_mode( 163 struct dce110_link_encoder *enc110) 164 { 165 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 166 } 167 168 static void program_pattern_symbols( 169 struct dce110_link_encoder *enc110, 170 uint16_t pattern_symbols[8]) 171 { 172 /* This register resides in DP back end block; 173 * transmitter is used for the offset */ 174 175 REG_SET_3(DP_DPHY_SYM0, 0, 176 DPHY_SYM1, pattern_symbols[0], 177 DPHY_SYM2, pattern_symbols[1], 178 DPHY_SYM3, pattern_symbols[2]); 179 180 /* This register resides in DP back end block; 181 * transmitter is used for the offset */ 182 183 REG_SET_3(DP_DPHY_SYM1, 0, 184 DPHY_SYM4, pattern_symbols[3], 185 DPHY_SYM5, pattern_symbols[4], 186 DPHY_SYM6, pattern_symbols[5]); 187 188 /* This register resides in DP back end block; 189 * transmitter is used for the offset */ 190 191 REG_SET_2(DP_DPHY_SYM2, 0, 192 DPHY_SYM7, pattern_symbols[6], 193 DPHY_SYM8, pattern_symbols[7]); 194 } 195 196 static void set_dp_phy_pattern_d102( 197 struct dce110_link_encoder *enc110) 198 { 199 /* Disable PHY Bypass mode to setup the test pattern */ 200 enable_phy_bypass_mode(enc110, false); 201 202 /* For 10-bit PRBS or debug symbols 203 * please use the following sequence: */ 204 205 /* Enable debug symbols on the lanes */ 206 207 disable_prbs_symbols(enc110, true); 208 209 /* Disable PRBS mode */ 210 disable_prbs_mode(enc110); 211 212 /* Program debug symbols to be output */ 213 { 214 uint16_t pattern_symbols[8] = { 215 0x2AA, 0x2AA, 0x2AA, 0x2AA, 216 0x2AA, 0x2AA, 0x2AA, 0x2AA 217 }; 218 219 program_pattern_symbols(enc110, pattern_symbols); 220 } 221 222 /* Enable phy bypass mode to enable the test pattern */ 223 224 enable_phy_bypass_mode(enc110, true); 225 } 226 227 static void set_link_training_complete( 228 struct dce110_link_encoder *enc110, 229 bool complete) 230 { 231 /* This register resides in DP back end block; 232 * transmitter is used for the offset */ 233 234 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 235 236 } 237 238 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 239 struct link_encoder *enc, 240 uint32_t index) 241 { 242 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 243 /* Write Training Pattern */ 244 245 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 246 247 /* Set HW Register Training Complete to false */ 248 249 set_link_training_complete(enc110, false); 250 251 /* Disable PHY Bypass mode to output Training Pattern */ 252 253 enable_phy_bypass_mode(enc110, false); 254 255 /* Disable PRBS mode */ 256 disable_prbs_mode(enc110); 257 } 258 259 static void setup_panel_mode( 260 struct dce110_link_encoder *enc110, 261 enum dp_panel_mode panel_mode) 262 { 263 uint32_t value; 264 struct dc_context *ctx = enc110->base.ctx; 265 266 /* if psp set panel mode, dal should be program it */ 267 if (ctx->dc->caps.psp_setup_panel_mode) 268 return; 269 270 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 271 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 272 273 switch (panel_mode) { 274 case DP_PANEL_MODE_EDP: 275 value = 0x1; 276 break; 277 case DP_PANEL_MODE_SPECIAL: 278 value = 0x11; 279 break; 280 default: 281 value = 0x0; 282 break; 283 } 284 285 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 286 } 287 288 static void set_dp_phy_pattern_symbol_error( 289 struct dce110_link_encoder *enc110) 290 { 291 /* Disable PHY Bypass mode to setup the test pattern */ 292 enable_phy_bypass_mode(enc110, false); 293 294 /* program correct panel mode*/ 295 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 296 297 /* A PRBS23 pattern is used for most DP electrical measurements. */ 298 299 /* Enable PRBS symbols on the lanes */ 300 disable_prbs_symbols(enc110, false); 301 302 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 303 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 304 DPHY_PRBS_SEL, 1, 305 DPHY_PRBS_EN, 1); 306 307 /* Enable phy bypass mode to enable the test pattern */ 308 enable_phy_bypass_mode(enc110, true); 309 } 310 311 static void set_dp_phy_pattern_prbs7( 312 struct dce110_link_encoder *enc110) 313 { 314 /* Disable PHY Bypass mode to setup the test pattern */ 315 enable_phy_bypass_mode(enc110, false); 316 317 /* A PRBS7 pattern is used for most DP electrical measurements. */ 318 319 /* Enable PRBS symbols on the lanes */ 320 disable_prbs_symbols(enc110, false); 321 322 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 323 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 324 DPHY_PRBS_SEL, 0, 325 DPHY_PRBS_EN, 1); 326 327 /* Enable phy bypass mode to enable the test pattern */ 328 enable_phy_bypass_mode(enc110, true); 329 } 330 331 static void set_dp_phy_pattern_80bit_custom( 332 struct dce110_link_encoder *enc110, 333 const uint8_t *pattern) 334 { 335 /* Disable PHY Bypass mode to setup the test pattern */ 336 enable_phy_bypass_mode(enc110, false); 337 338 /* Enable debug symbols on the lanes */ 339 340 disable_prbs_symbols(enc110, true); 341 342 /* Enable PHY bypass mode to enable the test pattern */ 343 /* TODO is it really needed ? */ 344 345 enable_phy_bypass_mode(enc110, true); 346 347 /* Program 80 bit custom pattern */ 348 { 349 uint16_t pattern_symbols[8]; 350 351 pattern_symbols[0] = 352 ((pattern[1] & 0x03) << 8) | pattern[0]; 353 pattern_symbols[1] = 354 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 355 pattern_symbols[2] = 356 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 357 pattern_symbols[3] = 358 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 359 pattern_symbols[4] = 360 ((pattern[6] & 0x03) << 8) | pattern[5]; 361 pattern_symbols[5] = 362 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 363 pattern_symbols[6] = 364 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 365 pattern_symbols[7] = 366 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 367 368 program_pattern_symbols(enc110, pattern_symbols); 369 } 370 371 /* Enable phy bypass mode to enable the test pattern */ 372 373 enable_phy_bypass_mode(enc110, true); 374 } 375 376 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 377 struct dce110_link_encoder *enc110, 378 unsigned int cp2520_pattern) 379 { 380 381 /* previously there is a register DP_HBR2_EYE_PATTERN 382 * that is enabled to get the pattern. 383 * But it does not work with the latest spec change, 384 * so we are programming the following registers manually. 385 * 386 * The following settings have been confirmed 387 * by Nick Chorney and Sandra Liu */ 388 389 /* Disable PHY Bypass mode to setup the test pattern */ 390 391 enable_phy_bypass_mode(enc110, false); 392 393 /* Setup DIG encoder in DP SST mode */ 394 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 395 396 /* ensure normal panel mode. */ 397 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 398 399 /* no vbid after BS (SR) 400 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 401 * 11000260 / 11000104 / 110000FC */ 402 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 403 DP_IDLE_BS_INTERVAL, 0xFC, 404 DP_VBID_DISABLE, 1, 405 DP_VID_ENHANCED_FRAME_MODE, 1); 406 407 /* swap every BS with SR */ 408 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 409 410 /* select cp2520 patterns */ 411 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 412 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 413 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 414 else 415 /* pre-DCE11 can only generate CP2520 pattern 2 */ 416 ASSERT(cp2520_pattern == 2); 417 418 /* set link training complete */ 419 set_link_training_complete(enc110, true); 420 421 /* disable video stream */ 422 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 423 424 /* Disable PHY Bypass mode to setup the test pattern */ 425 enable_phy_bypass_mode(enc110, false); 426 } 427 428 #if defined(CONFIG_DRM_AMD_DC_SI) 429 static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2( 430 struct dce110_link_encoder *enc110, 431 unsigned int cp2520_pattern) 432 { 433 434 /* previously there is a register DP_HBR2_EYE_PATTERN 435 * that is enabled to get the pattern. 436 * But it does not work with the latest spec change, 437 * so we are programming the following registers manually. 438 * 439 * The following settings have been confirmed 440 * by Nick Chorney and Sandra Liu */ 441 442 /* Disable PHY Bypass mode to setup the test pattern */ 443 444 enable_phy_bypass_mode(enc110, false); 445 446 /* Setup DIG encoder in DP SST mode */ 447 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 448 449 /* ensure normal panel mode. */ 450 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 451 452 /* no vbid after BS (SR) 453 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 454 * 11000260 / 11000104 / 110000FC */ 455 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 456 DP_IDLE_BS_INTERVAL, 0xFC, 457 DP_VBID_DISABLE, 1, 458 DP_VID_ENHANCED_FRAME_MODE, 1); 459 460 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */ 461 462 /* select cp2520 patterns */ 463 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 464 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 465 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 466 else 467 /* pre-DCE11 can only generate CP2520 pattern 2 */ 468 ASSERT(cp2520_pattern == 2); 469 470 /* set link training complete */ 471 set_link_training_complete(enc110, true); 472 473 /* disable video stream */ 474 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 475 476 /* Disable PHY Bypass mode to setup the test pattern */ 477 enable_phy_bypass_mode(enc110, false); 478 } 479 #endif 480 481 static void set_dp_phy_pattern_passthrough_mode( 482 struct dce110_link_encoder *enc110, 483 enum dp_panel_mode panel_mode) 484 { 485 /* program correct panel mode */ 486 setup_panel_mode(enc110, panel_mode); 487 488 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 489 * in case we were doing HBR2 compliance pattern before 490 */ 491 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 492 DP_IDLE_BS_INTERVAL, 0x2000, 493 DP_VBID_DISABLE, 0, 494 DP_VID_ENHANCED_FRAME_MODE, 1); 495 496 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 497 498 /* set link training complete */ 499 set_link_training_complete(enc110, true); 500 501 /* Disable PHY Bypass mode to setup the test pattern */ 502 enable_phy_bypass_mode(enc110, false); 503 504 /* Disable PRBS mode */ 505 disable_prbs_mode(enc110); 506 } 507 508 #if defined(CONFIG_DRM_AMD_DC_SI) 509 static void dce60_set_dp_phy_pattern_passthrough_mode( 510 struct dce110_link_encoder *enc110, 511 enum dp_panel_mode panel_mode) 512 { 513 /* program correct panel mode */ 514 setup_panel_mode(enc110, panel_mode); 515 516 /* restore LINK_FRAMING_CNTL 517 * in case we were doing HBR2 compliance pattern before 518 */ 519 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 520 DP_IDLE_BS_INTERVAL, 0x2000, 521 DP_VBID_DISABLE, 0, 522 DP_VID_ENHANCED_FRAME_MODE, 1); 523 524 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */ 525 526 /* set link training complete */ 527 set_link_training_complete(enc110, true); 528 529 /* Disable PHY Bypass mode to setup the test pattern */ 530 enable_phy_bypass_mode(enc110, false); 531 532 /* Disable PRBS mode */ 533 disable_prbs_mode(enc110); 534 } 535 #endif 536 537 /* return value is bit-vector */ 538 static uint8_t get_frontend_source( 539 enum engine_id engine) 540 { 541 switch (engine) { 542 case ENGINE_ID_DIGA: 543 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 544 case ENGINE_ID_DIGB: 545 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 546 case ENGINE_ID_DIGC: 547 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 548 case ENGINE_ID_DIGD: 549 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 550 case ENGINE_ID_DIGE: 551 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 552 case ENGINE_ID_DIGF: 553 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 554 case ENGINE_ID_DIGG: 555 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 556 default: 557 ASSERT_CRITICAL(false); 558 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 559 } 560 } 561 562 static void configure_encoder( 563 struct dce110_link_encoder *enc110, 564 const struct dc_link_settings *link_settings) 565 { 566 /* set number of lanes */ 567 568 REG_SET(DP_CONFIG, 0, 569 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 570 571 /* setup scrambler */ 572 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 573 } 574 575 #if defined(CONFIG_DRM_AMD_DC_SI) 576 static void dce60_configure_encoder( 577 struct dce110_link_encoder *enc110, 578 const struct dc_link_settings *link_settings) 579 { 580 /* set number of lanes */ 581 582 REG_SET(DP_CONFIG, 0, 583 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 584 585 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */ 586 } 587 #endif 588 589 static void aux_initialize( 590 struct dce110_link_encoder *enc110) 591 { 592 struct dc_context *ctx = enc110->base.ctx; 593 enum hpd_source_id hpd_source = enc110->base.hpd_source; 594 uint32_t addr = AUX_REG(AUX_CONTROL); 595 uint32_t value = dm_read_reg(ctx, addr); 596 597 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 598 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 599 dm_write_reg(ctx, addr, value); 600 601 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 602 value = dm_read_reg(ctx, addr); 603 604 /* 1/4 window (the maximum allowed) */ 605 set_reg_field_value(value, 1, 606 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 607 dm_write_reg(ctx, addr, value); 608 609 } 610 611 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 612 bool exit_link_training_required) 613 { 614 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 615 616 if (exit_link_training_required) 617 REG_UPDATE(DP_DPHY_FAST_TRAINING, 618 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 619 else { 620 REG_UPDATE(DP_DPHY_FAST_TRAINING, 621 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 622 /*In DCE 11, we are able to pre-program a Force SR register 623 * to be able to trigger SR symbol after 5 idle patterns 624 * transmitted. Upon PSR Exit, DMCU can trigger 625 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 626 * DPHY_LOAD_BS_COUNT_START and the internal counter 627 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 628 * replaced by SR symbol once. 629 */ 630 631 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 632 } 633 } 634 635 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 636 unsigned int sdp_transmit_line_num_deadline) 637 { 638 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 639 640 REG_UPDATE_2(DP_SEC_CNTL1, 641 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 642 DP_SEC_GSP0_PRIORITY, 1); 643 } 644 645 bool dce110_is_dig_enabled(struct link_encoder *enc) 646 { 647 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 648 uint32_t value; 649 650 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 651 return value; 652 } 653 654 static void link_encoder_disable(struct dce110_link_encoder *enc110) 655 { 656 /* reset training pattern */ 657 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 658 DPHY_TRAINING_PATTERN_SEL, 0); 659 660 /* reset training complete */ 661 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 662 663 /* reset panel mode */ 664 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 665 } 666 667 static void hpd_initialize( 668 struct dce110_link_encoder *enc110) 669 { 670 /* Associate HPD with DIG_BE */ 671 enum hpd_source_id hpd_source = enc110->base.hpd_source; 672 673 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 674 } 675 676 bool dce110_link_encoder_validate_dvi_output( 677 const struct dce110_link_encoder *enc110, 678 enum signal_type connector_signal, 679 enum signal_type signal, 680 const struct dc_crtc_timing *crtc_timing) 681 { 682 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 683 684 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 685 max_pixel_clock *= 2; 686 687 /* This handles the case of HDMI downgrade to DVI we don't want to 688 * we don't want to cap the pixel clock if the DDI is not DVI. 689 */ 690 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 691 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 692 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 693 694 /* DVI only support RGB pixel encoding */ 695 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 696 return false; 697 698 /*connect DVI via adpater's HDMI connector*/ 699 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 700 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 701 signal != SIGNAL_TYPE_HDMI_TYPE_A && 702 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 703 return false; 704 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 705 return false; 706 707 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 708 return false; 709 710 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 711 switch (crtc_timing->display_color_depth) { 712 case COLOR_DEPTH_666: 713 case COLOR_DEPTH_888: 714 break; 715 case COLOR_DEPTH_101010: 716 case COLOR_DEPTH_161616: 717 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 718 return false; 719 break; 720 default: 721 return false; 722 } 723 724 return true; 725 } 726 727 static bool dce110_link_encoder_validate_hdmi_output( 728 const struct dce110_link_encoder *enc110, 729 const struct dc_crtc_timing *crtc_timing, 730 int adjusted_pix_clk_khz) 731 { 732 enum dc_color_depth max_deep_color = 733 enc110->base.features.max_hdmi_deep_color; 734 735 if (max_deep_color < crtc_timing->display_color_depth) 736 return false; 737 738 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 739 return false; 740 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 741 return false; 742 743 if ((adjusted_pix_clk_khz == 0) || 744 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 745 return false; 746 747 /* DCE11 HW does not support 420 */ 748 if (!enc110->base.features.hdmi_ycbcr420_supported && 749 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 750 return false; 751 752 if (!enc110->base.features.flags.bits.HDMI_6GB_EN && 753 adjusted_pix_clk_khz >= 300000) 754 return false; 755 if (enc110->base.ctx->dc->debug.hdmi20_disable && 756 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 757 return false; 758 return true; 759 } 760 761 bool dce110_link_encoder_validate_dp_output( 762 const struct dce110_link_encoder *enc110, 763 const struct dc_crtc_timing *crtc_timing) 764 { 765 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 766 return false; 767 768 return true; 769 } 770 771 void dce110_link_encoder_construct( 772 struct dce110_link_encoder *enc110, 773 const struct encoder_init_data *init_data, 774 const struct encoder_feature_support *enc_features, 775 const struct dce110_link_enc_registers *link_regs, 776 const struct dce110_link_enc_aux_registers *aux_regs, 777 const struct dce110_link_enc_hpd_registers *hpd_regs) 778 { 779 struct bp_encoder_cap_info bp_cap_info = {0}; 780 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 781 enum bp_result result = BP_RESULT_OK; 782 783 enc110->base.funcs = &dce110_lnk_enc_funcs; 784 enc110->base.ctx = init_data->ctx; 785 enc110->base.id = init_data->encoder; 786 787 enc110->base.hpd_source = init_data->hpd_source; 788 enc110->base.connector = init_data->connector; 789 790 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 791 792 enc110->base.features = *enc_features; 793 794 enc110->base.transmitter = init_data->transmitter; 795 796 /* set the flag to indicate whether driver poll the I2C data pin 797 * while doing the DP sink detect 798 */ 799 800 /* if (dal_adapter_service_is_feature_supported(as, 801 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 802 enc110->base.features.flags.bits. 803 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 804 805 enc110->base.output_signals = 806 SIGNAL_TYPE_DVI_SINGLE_LINK | 807 SIGNAL_TYPE_DVI_DUAL_LINK | 808 SIGNAL_TYPE_LVDS | 809 SIGNAL_TYPE_DISPLAY_PORT | 810 SIGNAL_TYPE_DISPLAY_PORT_MST | 811 SIGNAL_TYPE_EDP | 812 SIGNAL_TYPE_HDMI_TYPE_A; 813 814 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 815 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 816 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 817 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 818 * Prefer DIG assignment is decided by board design. 819 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 820 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 821 * By this, adding DIGG should not hurt DCE 8.0. 822 * This will let DCE 8.1 share DCE 8.0 as much as possible 823 */ 824 825 enc110->link_regs = link_regs; 826 enc110->aux_regs = aux_regs; 827 enc110->hpd_regs = hpd_regs; 828 829 switch (enc110->base.transmitter) { 830 case TRANSMITTER_UNIPHY_A: 831 enc110->base.preferred_engine = ENGINE_ID_DIGA; 832 break; 833 case TRANSMITTER_UNIPHY_B: 834 enc110->base.preferred_engine = ENGINE_ID_DIGB; 835 break; 836 case TRANSMITTER_UNIPHY_C: 837 enc110->base.preferred_engine = ENGINE_ID_DIGC; 838 break; 839 case TRANSMITTER_UNIPHY_D: 840 enc110->base.preferred_engine = ENGINE_ID_DIGD; 841 break; 842 case TRANSMITTER_UNIPHY_E: 843 enc110->base.preferred_engine = ENGINE_ID_DIGE; 844 break; 845 case TRANSMITTER_UNIPHY_F: 846 enc110->base.preferred_engine = ENGINE_ID_DIGF; 847 break; 848 case TRANSMITTER_UNIPHY_G: 849 enc110->base.preferred_engine = ENGINE_ID_DIGG; 850 break; 851 default: 852 ASSERT_CRITICAL(false); 853 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 854 } 855 856 /* default to one to mirror Windows behavior */ 857 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 858 859 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 860 enc110->base.id, &bp_cap_info); 861 862 /* Override features with DCE-specific values */ 863 if (BP_RESULT_OK == result) { 864 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 865 bp_cap_info.DP_HBR2_EN; 866 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 867 bp_cap_info.DP_HBR3_EN; 868 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 869 } else { 870 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 871 __func__, 872 result); 873 } 874 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 875 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 876 } 877 } 878 879 bool dce110_link_encoder_validate_output_with_stream( 880 struct link_encoder *enc, 881 const struct dc_stream_state *stream) 882 { 883 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 884 bool is_valid; 885 886 switch (stream->signal) { 887 case SIGNAL_TYPE_DVI_SINGLE_LINK: 888 case SIGNAL_TYPE_DVI_DUAL_LINK: 889 is_valid = dce110_link_encoder_validate_dvi_output( 890 enc110, 891 stream->link->connector_signal, 892 stream->signal, 893 &stream->timing); 894 break; 895 case SIGNAL_TYPE_HDMI_TYPE_A: 896 is_valid = dce110_link_encoder_validate_hdmi_output( 897 enc110, 898 &stream->timing, 899 stream->phy_pix_clk); 900 break; 901 case SIGNAL_TYPE_DISPLAY_PORT: 902 case SIGNAL_TYPE_DISPLAY_PORT_MST: 903 is_valid = dce110_link_encoder_validate_dp_output( 904 enc110, &stream->timing); 905 break; 906 case SIGNAL_TYPE_EDP: 907 case SIGNAL_TYPE_LVDS: 908 is_valid = 909 (stream->timing. 910 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; 911 break; 912 case SIGNAL_TYPE_VIRTUAL: 913 is_valid = true; 914 break; 915 default: 916 is_valid = false; 917 break; 918 } 919 920 return is_valid; 921 } 922 923 void dce110_link_encoder_hw_init( 924 struct link_encoder *enc) 925 { 926 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 927 struct bp_transmitter_control cntl = { 0 }; 928 enum bp_result result; 929 930 cntl.action = TRANSMITTER_CONTROL_INIT; 931 cntl.engine_id = ENGINE_ID_UNKNOWN; 932 cntl.transmitter = enc110->base.transmitter; 933 cntl.connector_obj_id = enc110->base.connector; 934 cntl.lanes_number = LANE_COUNT_FOUR; 935 cntl.coherent = false; 936 cntl.hpd_sel = enc110->base.hpd_source; 937 938 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 939 cntl.signal = SIGNAL_TYPE_EDP; 940 941 result = link_transmitter_control(enc110, &cntl); 942 943 if (result != BP_RESULT_OK) { 944 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 945 __func__); 946 BREAK_TO_DEBUGGER(); 947 return; 948 } 949 950 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 951 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 952 953 result = link_transmitter_control(enc110, &cntl); 954 955 ASSERT(result == BP_RESULT_OK); 956 957 } 958 aux_initialize(enc110); 959 960 /* reinitialize HPD. 961 * hpd_initialize() will pass DIG_FE id to HW context. 962 * All other routine within HW context will use fe_engine_offset 963 * as DIG_FE id even caller pass DIG_FE id. 964 * So this routine must be called first. */ 965 hpd_initialize(enc110); 966 } 967 968 void dce110_link_encoder_destroy(struct link_encoder **enc) 969 { 970 kfree(TO_DCE110_LINK_ENC(*enc)); 971 *enc = NULL; 972 } 973 974 void dce110_link_encoder_setup( 975 struct link_encoder *enc, 976 enum signal_type signal) 977 { 978 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 979 980 switch (signal) { 981 case SIGNAL_TYPE_EDP: 982 case SIGNAL_TYPE_DISPLAY_PORT: 983 /* DP SST */ 984 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 985 break; 986 case SIGNAL_TYPE_LVDS: 987 /* LVDS */ 988 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 989 break; 990 case SIGNAL_TYPE_DVI_SINGLE_LINK: 991 case SIGNAL_TYPE_DVI_DUAL_LINK: 992 /* TMDS-DVI */ 993 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 994 break; 995 case SIGNAL_TYPE_HDMI_TYPE_A: 996 /* TMDS-HDMI */ 997 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 998 break; 999 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1000 /* DP MST */ 1001 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1002 break; 1003 default: 1004 ASSERT_CRITICAL(false); 1005 /* invalid mode ! */ 1006 break; 1007 } 1008 1009 } 1010 1011 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1012 void dce110_link_encoder_enable_tmds_output( 1013 struct link_encoder *enc, 1014 enum clock_source_id clock_source, 1015 enum dc_color_depth color_depth, 1016 enum signal_type signal, 1017 uint32_t pixel_clock) 1018 { 1019 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1020 struct bp_transmitter_control cntl = { 0 }; 1021 enum bp_result result; 1022 1023 /* Enable the PHY */ 1024 cntl.connector_obj_id = enc110->base.connector; 1025 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1026 cntl.engine_id = enc->preferred_engine; 1027 cntl.transmitter = enc110->base.transmitter; 1028 cntl.pll_id = clock_source; 1029 cntl.signal = signal; 1030 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 1031 cntl.lanes_number = 8; 1032 else 1033 cntl.lanes_number = 4; 1034 1035 cntl.hpd_sel = enc110->base.hpd_source; 1036 1037 cntl.pixel_clock = pixel_clock; 1038 cntl.color_depth = color_depth; 1039 1040 result = link_transmitter_control(enc110, &cntl); 1041 1042 if (result != BP_RESULT_OK) { 1043 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1044 __func__); 1045 BREAK_TO_DEBUGGER(); 1046 } 1047 } 1048 1049 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1050 void dce110_link_encoder_enable_lvds_output( 1051 struct link_encoder *enc, 1052 enum clock_source_id clock_source, 1053 uint32_t pixel_clock) 1054 { 1055 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1056 struct bp_transmitter_control cntl = { 0 }; 1057 enum bp_result result; 1058 1059 /* Enable the PHY */ 1060 cntl.connector_obj_id = enc110->base.connector; 1061 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1062 cntl.engine_id = enc->preferred_engine; 1063 cntl.transmitter = enc110->base.transmitter; 1064 cntl.pll_id = clock_source; 1065 cntl.signal = SIGNAL_TYPE_LVDS; 1066 cntl.lanes_number = 4; 1067 1068 cntl.hpd_sel = enc110->base.hpd_source; 1069 1070 cntl.pixel_clock = pixel_clock; 1071 1072 result = link_transmitter_control(enc110, &cntl); 1073 1074 if (result != BP_RESULT_OK) { 1075 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1076 __func__); 1077 BREAK_TO_DEBUGGER(); 1078 } 1079 } 1080 1081 /* enables DP PHY output */ 1082 void dce110_link_encoder_enable_dp_output( 1083 struct link_encoder *enc, 1084 const struct dc_link_settings *link_settings, 1085 enum clock_source_id clock_source) 1086 { 1087 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1088 struct bp_transmitter_control cntl = { 0 }; 1089 enum bp_result result; 1090 1091 /* Enable the PHY */ 1092 1093 /* number_of_lanes is used for pixel clock adjust, 1094 * but it's not passed to asic_control. 1095 * We need to set number of lanes manually. 1096 */ 1097 configure_encoder(enc110, link_settings); 1098 cntl.connector_obj_id = enc110->base.connector; 1099 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1100 cntl.engine_id = enc->preferred_engine; 1101 cntl.transmitter = enc110->base.transmitter; 1102 cntl.pll_id = clock_source; 1103 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1104 cntl.lanes_number = link_settings->lane_count; 1105 cntl.hpd_sel = enc110->base.hpd_source; 1106 cntl.pixel_clock = link_settings->link_rate 1107 * LINK_RATE_REF_FREQ_IN_KHZ; 1108 /* TODO: check if undefined works */ 1109 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1110 1111 result = link_transmitter_control(enc110, &cntl); 1112 1113 if (result != BP_RESULT_OK) { 1114 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1115 __func__); 1116 BREAK_TO_DEBUGGER(); 1117 } 1118 } 1119 1120 /* enables DP PHY output in MST mode */ 1121 void dce110_link_encoder_enable_dp_mst_output( 1122 struct link_encoder *enc, 1123 const struct dc_link_settings *link_settings, 1124 enum clock_source_id clock_source) 1125 { 1126 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1127 struct bp_transmitter_control cntl = { 0 }; 1128 enum bp_result result; 1129 1130 /* Enable the PHY */ 1131 1132 /* number_of_lanes is used for pixel clock adjust, 1133 * but it's not passed to asic_control. 1134 * We need to set number of lanes manually. 1135 */ 1136 configure_encoder(enc110, link_settings); 1137 1138 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1139 cntl.engine_id = ENGINE_ID_UNKNOWN; 1140 cntl.transmitter = enc110->base.transmitter; 1141 cntl.pll_id = clock_source; 1142 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1143 cntl.lanes_number = link_settings->lane_count; 1144 cntl.hpd_sel = enc110->base.hpd_source; 1145 cntl.pixel_clock = link_settings->link_rate 1146 * LINK_RATE_REF_FREQ_IN_KHZ; 1147 /* TODO: check if undefined works */ 1148 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1149 1150 result = link_transmitter_control(enc110, &cntl); 1151 1152 if (result != BP_RESULT_OK) { 1153 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1154 __func__); 1155 BREAK_TO_DEBUGGER(); 1156 } 1157 } 1158 1159 #if defined(CONFIG_DRM_AMD_DC_SI) 1160 /* enables DP PHY output */ 1161 void dce60_link_encoder_enable_dp_output( 1162 struct link_encoder *enc, 1163 const struct dc_link_settings *link_settings, 1164 enum clock_source_id clock_source) 1165 { 1166 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1167 struct bp_transmitter_control cntl = { 0 }; 1168 enum bp_result result; 1169 1170 /* Enable the PHY */ 1171 1172 /* number_of_lanes is used for pixel clock adjust, 1173 * but it's not passed to asic_control. 1174 * We need to set number of lanes manually. 1175 */ 1176 dce60_configure_encoder(enc110, link_settings); 1177 cntl.connector_obj_id = enc110->base.connector; 1178 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1179 cntl.engine_id = enc->preferred_engine; 1180 cntl.transmitter = enc110->base.transmitter; 1181 cntl.pll_id = clock_source; 1182 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1183 cntl.lanes_number = link_settings->lane_count; 1184 cntl.hpd_sel = enc110->base.hpd_source; 1185 cntl.pixel_clock = link_settings->link_rate 1186 * LINK_RATE_REF_FREQ_IN_KHZ; 1187 /* TODO: check if undefined works */ 1188 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1189 1190 result = link_transmitter_control(enc110, &cntl); 1191 1192 if (result != BP_RESULT_OK) { 1193 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1194 __func__); 1195 BREAK_TO_DEBUGGER(); 1196 } 1197 } 1198 1199 /* enables DP PHY output in MST mode */ 1200 void dce60_link_encoder_enable_dp_mst_output( 1201 struct link_encoder *enc, 1202 const struct dc_link_settings *link_settings, 1203 enum clock_source_id clock_source) 1204 { 1205 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1206 struct bp_transmitter_control cntl = { 0 }; 1207 enum bp_result result; 1208 1209 /* Enable the PHY */ 1210 1211 /* number_of_lanes is used for pixel clock adjust, 1212 * but it's not passed to asic_control. 1213 * We need to set number of lanes manually. 1214 */ 1215 dce60_configure_encoder(enc110, link_settings); 1216 1217 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1218 cntl.engine_id = ENGINE_ID_UNKNOWN; 1219 cntl.transmitter = enc110->base.transmitter; 1220 cntl.pll_id = clock_source; 1221 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1222 cntl.lanes_number = link_settings->lane_count; 1223 cntl.hpd_sel = enc110->base.hpd_source; 1224 cntl.pixel_clock = link_settings->link_rate 1225 * LINK_RATE_REF_FREQ_IN_KHZ; 1226 /* TODO: check if undefined works */ 1227 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1228 1229 result = link_transmitter_control(enc110, &cntl); 1230 1231 if (result != BP_RESULT_OK) { 1232 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1233 __func__); 1234 BREAK_TO_DEBUGGER(); 1235 } 1236 } 1237 #endif 1238 1239 /* 1240 * @brief 1241 * Disable transmitter and its encoder 1242 */ 1243 void dce110_link_encoder_disable_output( 1244 struct link_encoder *enc, 1245 enum signal_type signal) 1246 { 1247 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1248 struct bp_transmitter_control cntl = { 0 }; 1249 enum bp_result result; 1250 1251 if (!dce110_is_dig_enabled(enc)) { 1252 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1253 return; 1254 } 1255 /* Power-down RX and disable GPU PHY should be paired. 1256 * Disabling PHY without powering down RX may cause 1257 * symbol lock loss, on which we will get DP Sink interrupt. */ 1258 1259 /* There is a case for the DP active dongles 1260 * where we want to disable the PHY but keep RX powered, 1261 * for those we need to ignore DP Sink interrupt 1262 * by checking lane count that has been set 1263 * on the last do_enable_output(). */ 1264 1265 /* disable transmitter */ 1266 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1267 cntl.transmitter = enc110->base.transmitter; 1268 cntl.hpd_sel = enc110->base.hpd_source; 1269 cntl.signal = signal; 1270 cntl.connector_obj_id = enc110->base.connector; 1271 1272 result = link_transmitter_control(enc110, &cntl); 1273 1274 if (result != BP_RESULT_OK) { 1275 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1276 __func__); 1277 BREAK_TO_DEBUGGER(); 1278 return; 1279 } 1280 1281 /* disable encoder */ 1282 if (dc_is_dp_signal(signal)) 1283 link_encoder_disable(enc110); 1284 } 1285 1286 void dce110_link_encoder_dp_set_lane_settings( 1287 struct link_encoder *enc, 1288 const struct link_training_settings *link_settings) 1289 { 1290 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1291 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1292 int32_t lane = 0; 1293 struct bp_transmitter_control cntl = { 0 }; 1294 1295 if (!link_settings) { 1296 BREAK_TO_DEBUGGER(); 1297 return; 1298 } 1299 1300 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1301 cntl.transmitter = enc110->base.transmitter; 1302 cntl.connector_obj_id = enc110->base.connector; 1303 cntl.lanes_number = link_settings->link_settings.lane_count; 1304 cntl.hpd_sel = enc110->base.hpd_source; 1305 cntl.pixel_clock = link_settings->link_settings.link_rate * 1306 LINK_RATE_REF_FREQ_IN_KHZ; 1307 1308 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1309 /* translate lane settings */ 1310 1311 training_lane_set.bits.VOLTAGE_SWING_SET = 1312 link_settings->lane_settings[lane].VOLTAGE_SWING; 1313 training_lane_set.bits.PRE_EMPHASIS_SET = 1314 link_settings->lane_settings[lane].PRE_EMPHASIS; 1315 1316 /* post cursor 2 setting only applies to HBR2 link rate */ 1317 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1318 /* this is passed to VBIOS 1319 * to program post cursor 2 level */ 1320 1321 training_lane_set.bits.POST_CURSOR2_SET = 1322 link_settings->lane_settings[lane].POST_CURSOR2; 1323 } 1324 1325 cntl.lane_select = lane; 1326 cntl.lane_settings = training_lane_set.raw; 1327 1328 /* call VBIOS table to set voltage swing and pre-emphasis */ 1329 link_transmitter_control(enc110, &cntl); 1330 } 1331 } 1332 1333 /* set DP PHY test and training patterns */ 1334 void dce110_link_encoder_dp_set_phy_pattern( 1335 struct link_encoder *enc, 1336 const struct encoder_set_dp_phy_pattern_param *param) 1337 { 1338 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1339 1340 switch (param->dp_phy_pattern) { 1341 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1342 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1343 break; 1344 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1345 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1346 break; 1347 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1348 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1349 break; 1350 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1351 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1352 break; 1353 case DP_TEST_PATTERN_D102: 1354 set_dp_phy_pattern_d102(enc110); 1355 break; 1356 case DP_TEST_PATTERN_SYMBOL_ERROR: 1357 set_dp_phy_pattern_symbol_error(enc110); 1358 break; 1359 case DP_TEST_PATTERN_PRBS7: 1360 set_dp_phy_pattern_prbs7(enc110); 1361 break; 1362 case DP_TEST_PATTERN_80BIT_CUSTOM: 1363 set_dp_phy_pattern_80bit_custom( 1364 enc110, param->custom_pattern); 1365 break; 1366 case DP_TEST_PATTERN_CP2520_1: 1367 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1368 break; 1369 case DP_TEST_PATTERN_CP2520_2: 1370 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1371 break; 1372 case DP_TEST_PATTERN_CP2520_3: 1373 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1374 break; 1375 case DP_TEST_PATTERN_VIDEO_MODE: { 1376 set_dp_phy_pattern_passthrough_mode( 1377 enc110, param->dp_panel_mode); 1378 break; 1379 } 1380 1381 default: 1382 /* invalid phy pattern */ 1383 ASSERT_CRITICAL(false); 1384 break; 1385 } 1386 } 1387 1388 #if defined(CONFIG_DRM_AMD_DC_SI) 1389 /* set DP PHY test and training patterns */ 1390 void dce60_link_encoder_dp_set_phy_pattern( 1391 struct link_encoder *enc, 1392 const struct encoder_set_dp_phy_pattern_param *param) 1393 { 1394 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1395 1396 switch (param->dp_phy_pattern) { 1397 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1398 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1399 break; 1400 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1401 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1402 break; 1403 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1404 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1405 break; 1406 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1407 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1408 break; 1409 case DP_TEST_PATTERN_D102: 1410 set_dp_phy_pattern_d102(enc110); 1411 break; 1412 case DP_TEST_PATTERN_SYMBOL_ERROR: 1413 set_dp_phy_pattern_symbol_error(enc110); 1414 break; 1415 case DP_TEST_PATTERN_PRBS7: 1416 set_dp_phy_pattern_prbs7(enc110); 1417 break; 1418 case DP_TEST_PATTERN_80BIT_CUSTOM: 1419 set_dp_phy_pattern_80bit_custom( 1420 enc110, param->custom_pattern); 1421 break; 1422 case DP_TEST_PATTERN_CP2520_1: 1423 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1424 break; 1425 case DP_TEST_PATTERN_CP2520_2: 1426 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1427 break; 1428 case DP_TEST_PATTERN_CP2520_3: 1429 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1430 break; 1431 case DP_TEST_PATTERN_VIDEO_MODE: { 1432 dce60_set_dp_phy_pattern_passthrough_mode( 1433 enc110, param->dp_panel_mode); 1434 break; 1435 } 1436 1437 default: 1438 /* invalid phy pattern */ 1439 ASSERT_CRITICAL(false); 1440 break; 1441 } 1442 } 1443 #endif 1444 1445 static void fill_stream_allocation_row_info( 1446 const struct link_mst_stream_allocation *stream_allocation, 1447 uint32_t *src, 1448 uint32_t *slots) 1449 { 1450 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1451 1452 if (stream_enc) { 1453 *src = stream_enc->id; 1454 *slots = stream_allocation->slot_count; 1455 } else { 1456 *src = 0; 1457 *slots = 0; 1458 } 1459 } 1460 1461 /* programs DP MST VC payload allocation */ 1462 void dce110_link_encoder_update_mst_stream_allocation_table( 1463 struct link_encoder *enc, 1464 const struct link_mst_stream_allocation_table *table) 1465 { 1466 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1467 uint32_t value0 = 0; 1468 uint32_t value1 = 0; 1469 uint32_t value2 = 0; 1470 uint32_t slots = 0; 1471 uint32_t src = 0; 1472 uint32_t retries = 0; 1473 1474 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1475 1476 /* --- Set MSE Stream Attribute - 1477 * Setup VC Payload Table on Tx Side, 1478 * Issue allocation change trigger 1479 * to commit payload on both tx and rx side */ 1480 1481 /* we should clean-up table each time */ 1482 1483 if (table->stream_count >= 1) { 1484 fill_stream_allocation_row_info( 1485 &table->stream_allocations[0], 1486 &src, 1487 &slots); 1488 } else { 1489 src = 0; 1490 slots = 0; 1491 } 1492 1493 REG_UPDATE_2(DP_MSE_SAT0, 1494 DP_MSE_SAT_SRC0, src, 1495 DP_MSE_SAT_SLOT_COUNT0, slots); 1496 1497 if (table->stream_count >= 2) { 1498 fill_stream_allocation_row_info( 1499 &table->stream_allocations[1], 1500 &src, 1501 &slots); 1502 } else { 1503 src = 0; 1504 slots = 0; 1505 } 1506 1507 REG_UPDATE_2(DP_MSE_SAT0, 1508 DP_MSE_SAT_SRC1, src, 1509 DP_MSE_SAT_SLOT_COUNT1, slots); 1510 1511 if (table->stream_count >= 3) { 1512 fill_stream_allocation_row_info( 1513 &table->stream_allocations[2], 1514 &src, 1515 &slots); 1516 } else { 1517 src = 0; 1518 slots = 0; 1519 } 1520 1521 REG_UPDATE_2(DP_MSE_SAT1, 1522 DP_MSE_SAT_SRC2, src, 1523 DP_MSE_SAT_SLOT_COUNT2, slots); 1524 1525 if (table->stream_count >= 4) { 1526 fill_stream_allocation_row_info( 1527 &table->stream_allocations[3], 1528 &src, 1529 &slots); 1530 } else { 1531 src = 0; 1532 slots = 0; 1533 } 1534 1535 REG_UPDATE_2(DP_MSE_SAT1, 1536 DP_MSE_SAT_SRC3, src, 1537 DP_MSE_SAT_SLOT_COUNT3, slots); 1538 1539 /* --- wait for transaction finish */ 1540 1541 /* send allocation change trigger (ACT) ? 1542 * this step first sends the ACT, 1543 * then double buffers the SAT into the hardware 1544 * making the new allocation active on the DP MST mode link */ 1545 1546 1547 /* DP_MSE_SAT_UPDATE: 1548 * 0 - No Action 1549 * 1 - Update SAT with trigger 1550 * 2 - Update SAT without trigger */ 1551 1552 REG_UPDATE(DP_MSE_SAT_UPDATE, 1553 DP_MSE_SAT_UPDATE, 1); 1554 1555 /* wait for update to complete 1556 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1557 * then wait for the transmission 1558 * of at least 16 MTP headers on immediate local link. 1559 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1560 * a value of 1 indicates that DP MST mode 1561 * is in the 16 MTP keepout region after a VC has been added. 1562 * MST stream bandwidth (VC rate) can be configured 1563 * after this bit is cleared */ 1564 1565 do { 1566 udelay(10); 1567 1568 value0 = REG_READ(DP_MSE_SAT_UPDATE); 1569 1570 REG_GET(DP_MSE_SAT_UPDATE, 1571 DP_MSE_SAT_UPDATE, &value1); 1572 1573 REG_GET(DP_MSE_SAT_UPDATE, 1574 DP_MSE_16_MTP_KEEPOUT, &value2); 1575 1576 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1577 if (!value1 && !value2) 1578 break; 1579 ++retries; 1580 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1581 } 1582 1583 void dce110_link_encoder_connect_dig_be_to_fe( 1584 struct link_encoder *enc, 1585 enum engine_id engine, 1586 bool connect) 1587 { 1588 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1589 uint32_t field; 1590 1591 if (engine != ENGINE_ID_UNKNOWN) { 1592 1593 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1594 1595 if (connect) 1596 field |= get_frontend_source(engine); 1597 else 1598 field &= ~get_frontend_source(engine); 1599 1600 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1601 } 1602 } 1603 1604 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1605 { 1606 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1607 struct dc_context *ctx = enc110->base.ctx; 1608 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1609 uint32_t hpd_enable = 0; 1610 uint32_t value = dm_read_reg(ctx, addr); 1611 1612 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1613 1614 if (hpd_enable == 0) 1615 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1616 } 1617 1618 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1619 { 1620 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1621 struct dc_context *ctx = enc110->base.ctx; 1622 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1623 uint32_t value = dm_read_reg(ctx, addr); 1624 1625 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1626 } 1627 1628 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 1629 struct dc_link_settings *link_settings) 1630 { 1631 /* Set Default link settings */ 1632 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 1633 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; 1634 1635 /* Higher link settings based on feature supported */ 1636 if (enc->features.flags.bits.IS_HBR2_CAPABLE) 1637 max_link_cap.link_rate = LINK_RATE_HIGH2; 1638 1639 if (enc->features.flags.bits.IS_HBR3_CAPABLE) 1640 max_link_cap.link_rate = LINK_RATE_HIGH3; 1641 1642 *link_settings = max_link_cap; 1643 } 1644 1645 #if defined(CONFIG_DRM_AMD_DC_SI) 1646 static const struct link_encoder_funcs dce60_lnk_enc_funcs = { 1647 .validate_output_with_stream = 1648 dce110_link_encoder_validate_output_with_stream, 1649 .hw_init = dce110_link_encoder_hw_init, 1650 .setup = dce110_link_encoder_setup, 1651 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 1652 .enable_dp_output = dce60_link_encoder_enable_dp_output, 1653 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, 1654 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 1655 .disable_output = dce110_link_encoder_disable_output, 1656 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 1657 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, 1658 .update_mst_stream_allocation_table = 1659 dce110_link_encoder_update_mst_stream_allocation_table, 1660 .psr_program_dp_dphy_fast_training = 1661 dce110_psr_program_dp_dphy_fast_training, 1662 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 1663 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 1664 .enable_hpd = dce110_link_encoder_enable_hpd, 1665 .disable_hpd = dce110_link_encoder_disable_hpd, 1666 .is_dig_enabled = dce110_is_dig_enabled, 1667 .destroy = dce110_link_encoder_destroy, 1668 .get_max_link_cap = dce110_link_encoder_get_max_link_cap 1669 }; 1670 1671 void dce60_link_encoder_construct( 1672 struct dce110_link_encoder *enc110, 1673 const struct encoder_init_data *init_data, 1674 const struct encoder_feature_support *enc_features, 1675 const struct dce110_link_enc_registers *link_regs, 1676 const struct dce110_link_enc_aux_registers *aux_regs, 1677 const struct dce110_link_enc_hpd_registers *hpd_regs) 1678 { 1679 struct bp_encoder_cap_info bp_cap_info = {0}; 1680 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 1681 enum bp_result result = BP_RESULT_OK; 1682 1683 enc110->base.funcs = &dce60_lnk_enc_funcs; 1684 enc110->base.ctx = init_data->ctx; 1685 enc110->base.id = init_data->encoder; 1686 1687 enc110->base.hpd_source = init_data->hpd_source; 1688 enc110->base.connector = init_data->connector; 1689 1690 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1691 1692 enc110->base.features = *enc_features; 1693 1694 enc110->base.transmitter = init_data->transmitter; 1695 1696 /* set the flag to indicate whether driver poll the I2C data pin 1697 * while doing the DP sink detect 1698 */ 1699 1700 /* if (dal_adapter_service_is_feature_supported(as, 1701 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 1702 enc110->base.features.flags.bits. 1703 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 1704 1705 enc110->base.output_signals = 1706 SIGNAL_TYPE_DVI_SINGLE_LINK | 1707 SIGNAL_TYPE_DVI_DUAL_LINK | 1708 SIGNAL_TYPE_LVDS | 1709 SIGNAL_TYPE_DISPLAY_PORT | 1710 SIGNAL_TYPE_DISPLAY_PORT_MST | 1711 SIGNAL_TYPE_EDP | 1712 SIGNAL_TYPE_HDMI_TYPE_A; 1713 1714 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 1715 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 1716 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 1717 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 1718 * Prefer DIG assignment is decided by board design. 1719 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 1720 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 1721 * By this, adding DIGG should not hurt DCE 8.0. 1722 * This will let DCE 8.1 share DCE 8.0 as much as possible 1723 */ 1724 1725 enc110->link_regs = link_regs; 1726 enc110->aux_regs = aux_regs; 1727 enc110->hpd_regs = hpd_regs; 1728 1729 switch (enc110->base.transmitter) { 1730 case TRANSMITTER_UNIPHY_A: 1731 enc110->base.preferred_engine = ENGINE_ID_DIGA; 1732 break; 1733 case TRANSMITTER_UNIPHY_B: 1734 enc110->base.preferred_engine = ENGINE_ID_DIGB; 1735 break; 1736 case TRANSMITTER_UNIPHY_C: 1737 enc110->base.preferred_engine = ENGINE_ID_DIGC; 1738 break; 1739 case TRANSMITTER_UNIPHY_D: 1740 enc110->base.preferred_engine = ENGINE_ID_DIGD; 1741 break; 1742 case TRANSMITTER_UNIPHY_E: 1743 enc110->base.preferred_engine = ENGINE_ID_DIGE; 1744 break; 1745 case TRANSMITTER_UNIPHY_F: 1746 enc110->base.preferred_engine = ENGINE_ID_DIGF; 1747 break; 1748 case TRANSMITTER_UNIPHY_G: 1749 enc110->base.preferred_engine = ENGINE_ID_DIGG; 1750 break; 1751 default: 1752 ASSERT_CRITICAL(false); 1753 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1754 } 1755 1756 /* default to one to mirror Windows behavior */ 1757 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 1758 1759 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 1760 enc110->base.id, &bp_cap_info); 1761 1762 /* Override features with DCE-specific values */ 1763 if (BP_RESULT_OK == result) { 1764 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 1765 bp_cap_info.DP_HBR2_EN; 1766 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 1767 bp_cap_info.DP_HBR3_EN; 1768 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 1769 } else { 1770 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 1771 __func__, 1772 result); 1773 } 1774 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 1775 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 1776 } 1777 } 1778 #endif 1779