1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 29 #include "dc_types.h" 30 #include "core_types.h" 31 32 #include "include/grph_object_id.h" 33 #include "include/logger_interface.h" 34 35 #include "dce_clock_source.h" 36 #include "clk_mgr.h" 37 38 #include "reg_helper.h" 39 40 #define REG(reg)\ 41 (clk_src->regs->reg) 42 43 #define CTX \ 44 clk_src->base.ctx 45 46 #define DC_LOGGER_INIT() 47 48 #undef FN 49 #define FN(reg_name, field_name) \ 50 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name 51 52 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 53 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 54 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 55 56 static const struct spread_spectrum_data *get_ss_data_entry( 57 struct dce110_clk_src *clk_src, 58 enum signal_type signal, 59 uint32_t pix_clk_khz) 60 { 61 62 uint32_t entrys_num; 63 uint32_t i; 64 struct spread_spectrum_data *ss_parm = NULL; 65 struct spread_spectrum_data *ret = NULL; 66 67 switch (signal) { 68 case SIGNAL_TYPE_DVI_SINGLE_LINK: 69 case SIGNAL_TYPE_DVI_DUAL_LINK: 70 ss_parm = clk_src->dvi_ss_params; 71 entrys_num = clk_src->dvi_ss_params_cnt; 72 break; 73 74 case SIGNAL_TYPE_HDMI_TYPE_A: 75 ss_parm = clk_src->hdmi_ss_params; 76 entrys_num = clk_src->hdmi_ss_params_cnt; 77 break; 78 79 case SIGNAL_TYPE_LVDS: 80 ss_parm = clk_src->lvds_ss_params; 81 entrys_num = clk_src->lvds_ss_params_cnt; 82 break; 83 84 case SIGNAL_TYPE_DISPLAY_PORT: 85 case SIGNAL_TYPE_DISPLAY_PORT_MST: 86 case SIGNAL_TYPE_EDP: 87 case SIGNAL_TYPE_VIRTUAL: 88 ss_parm = clk_src->dp_ss_params; 89 entrys_num = clk_src->dp_ss_params_cnt; 90 break; 91 92 default: 93 ss_parm = NULL; 94 entrys_num = 0; 95 break; 96 } 97 98 if (ss_parm == NULL) 99 return ret; 100 101 for (i = 0; i < entrys_num; ++i, ++ss_parm) { 102 if (ss_parm->freq_range_khz >= pix_clk_khz) { 103 ret = ss_parm; 104 break; 105 } 106 } 107 108 return ret; 109 } 110 111 /** 112 * Function: calculate_fb_and_fractional_fb_divider 113 * 114 * * DESCRIPTION: Calculates feedback and fractional feedback dividers values 115 * 116 *PARAMETERS: 117 * targetPixelClock Desired frequency in 100 Hz 118 * ref_divider Reference divider (already known) 119 * postDivider Post Divider (already known) 120 * feedback_divider_param Pointer where to store 121 * calculated feedback divider value 122 * fract_feedback_divider_param Pointer where to store 123 * calculated fract feedback divider value 124 * 125 *RETURNS: 126 * It fills the locations pointed by feedback_divider_param 127 * and fract_feedback_divider_param 128 * It returns - true if feedback divider not 0 129 * - false should never happen) 130 */ 131 static bool calculate_fb_and_fractional_fb_divider( 132 struct calc_pll_clock_source *calc_pll_cs, 133 uint32_t target_pix_clk_100hz, 134 uint32_t ref_divider, 135 uint32_t post_divider, 136 uint32_t *feedback_divider_param, 137 uint32_t *fract_feedback_divider_param) 138 { 139 uint64_t feedback_divider; 140 141 feedback_divider = 142 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 143 feedback_divider *= 10; 144 /* additional factor, since we divide by 10 afterwards */ 145 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); 146 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); 147 148 /*Round to the number of precision 149 * The following code replace the old code (ullfeedbackDivider + 5)/10 150 * for example if the difference between the number 151 * of fractional feedback decimal point and the fractional FB Divider precision 152 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ 153 154 feedback_divider += 5ULL * 155 calc_pll_cs->fract_fb_divider_precision_factor; 156 feedback_divider = 157 div_u64(feedback_divider, 158 calc_pll_cs->fract_fb_divider_precision_factor * 10); 159 feedback_divider *= (uint64_t) 160 (calc_pll_cs->fract_fb_divider_precision_factor); 161 162 *feedback_divider_param = 163 div_u64_rem( 164 feedback_divider, 165 calc_pll_cs->fract_fb_divider_factor, 166 fract_feedback_divider_param); 167 168 if (*feedback_divider_param != 0) 169 return true; 170 return false; 171 } 172 173 /** 174 *calc_fb_divider_checking_tolerance 175 * 176 *DESCRIPTION: Calculates Feedback and Fractional Feedback divider values 177 * for passed Reference and Post divider, checking for tolerance. 178 *PARAMETERS: 179 * pll_settings Pointer to structure 180 * ref_divider Reference divider (already known) 181 * postDivider Post Divider (already known) 182 * tolerance Tolerance for Calculated Pixel Clock to be within 183 * 184 *RETURNS: 185 * It fills the PLLSettings structure with PLL Dividers values 186 * if calculated values are within required tolerance 187 * It returns - true if error is within tolerance 188 * - false if error is not within tolerance 189 */ 190 static bool calc_fb_divider_checking_tolerance( 191 struct calc_pll_clock_source *calc_pll_cs, 192 struct pll_settings *pll_settings, 193 uint32_t ref_divider, 194 uint32_t post_divider, 195 uint32_t tolerance) 196 { 197 uint32_t feedback_divider; 198 uint32_t fract_feedback_divider; 199 uint32_t actual_calculated_clock_100hz; 200 uint32_t abs_err; 201 uint64_t actual_calc_clk_100hz; 202 203 calculate_fb_and_fractional_fb_divider( 204 calc_pll_cs, 205 pll_settings->adjusted_pix_clk_100hz, 206 ref_divider, 207 post_divider, 208 &feedback_divider, 209 &fract_feedback_divider); 210 211 /*Actual calculated value*/ 212 actual_calc_clk_100hz = (uint64_t)feedback_divider * 213 calc_pll_cs->fract_fb_divider_factor + 214 fract_feedback_divider; 215 actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10; 216 actual_calc_clk_100hz = 217 div_u64(actual_calc_clk_100hz, 218 ref_divider * post_divider * 219 calc_pll_cs->fract_fb_divider_factor); 220 221 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); 222 223 abs_err = (actual_calculated_clock_100hz > 224 pll_settings->adjusted_pix_clk_100hz) 225 ? actual_calculated_clock_100hz - 226 pll_settings->adjusted_pix_clk_100hz 227 : pll_settings->adjusted_pix_clk_100hz - 228 actual_calculated_clock_100hz; 229 230 if (abs_err <= tolerance) { 231 /*found good values*/ 232 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; 233 pll_settings->reference_divider = ref_divider; 234 pll_settings->feedback_divider = feedback_divider; 235 pll_settings->fract_feedback_divider = fract_feedback_divider; 236 pll_settings->pix_clk_post_divider = post_divider; 237 pll_settings->calculated_pix_clk_100hz = 238 actual_calculated_clock_100hz; 239 pll_settings->vco_freq = 240 actual_calculated_clock_100hz * post_divider / 10; 241 return true; 242 } 243 return false; 244 } 245 246 static bool calc_pll_dividers_in_range( 247 struct calc_pll_clock_source *calc_pll_cs, 248 struct pll_settings *pll_settings, 249 uint32_t min_ref_divider, 250 uint32_t max_ref_divider, 251 uint32_t min_post_divider, 252 uint32_t max_post_divider, 253 uint32_t err_tolerance) 254 { 255 uint32_t ref_divider; 256 uint32_t post_divider; 257 uint32_t tolerance; 258 259 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% 260 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ 261 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / 262 100000; 263 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE) 264 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE; 265 266 for ( 267 post_divider = max_post_divider; 268 post_divider >= min_post_divider; 269 --post_divider) { 270 for ( 271 ref_divider = min_ref_divider; 272 ref_divider <= max_ref_divider; 273 ++ref_divider) { 274 if (calc_fb_divider_checking_tolerance( 275 calc_pll_cs, 276 pll_settings, 277 ref_divider, 278 post_divider, 279 tolerance)) { 280 return true; 281 } 282 } 283 } 284 285 return false; 286 } 287 288 static uint32_t calculate_pixel_clock_pll_dividers( 289 struct calc_pll_clock_source *calc_pll_cs, 290 struct pll_settings *pll_settings) 291 { 292 uint32_t err_tolerance; 293 uint32_t min_post_divider; 294 uint32_t max_post_divider; 295 uint32_t min_ref_divider; 296 uint32_t max_ref_divider; 297 298 if (pll_settings->adjusted_pix_clk_100hz == 0) { 299 DC_LOG_ERROR( 300 "%s Bad requested pixel clock", __func__); 301 return MAX_PLL_CALC_ERROR; 302 } 303 304 /* 1) Find Post divider ranges */ 305 if (pll_settings->pix_clk_post_divider) { 306 min_post_divider = pll_settings->pix_clk_post_divider; 307 max_post_divider = pll_settings->pix_clk_post_divider; 308 } else { 309 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; 310 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < 311 calc_pll_cs->min_vco_khz * 10) { 312 min_post_divider = calc_pll_cs->min_vco_khz * 10 / 313 pll_settings->adjusted_pix_clk_100hz; 314 if ((min_post_divider * 315 pll_settings->adjusted_pix_clk_100hz) < 316 calc_pll_cs->min_vco_khz * 10) 317 min_post_divider++; 318 } 319 320 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; 321 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz 322 > calc_pll_cs->max_vco_khz * 10) 323 max_post_divider = calc_pll_cs->max_vco_khz * 10 / 324 pll_settings->adjusted_pix_clk_100hz; 325 } 326 327 /* 2) Find Reference divider ranges 328 * When SS is enabled, or for Display Port even without SS, 329 * pll_settings->referenceDivider is not zero. 330 * So calculate PPLL FB and fractional FB divider 331 * using the passed reference divider*/ 332 333 if (pll_settings->reference_divider) { 334 min_ref_divider = pll_settings->reference_divider; 335 max_ref_divider = pll_settings->reference_divider; 336 } else { 337 min_ref_divider = ((calc_pll_cs->ref_freq_khz 338 / calc_pll_cs->max_pll_input_freq_khz) 339 > calc_pll_cs->min_pll_ref_divider) 340 ? calc_pll_cs->ref_freq_khz 341 / calc_pll_cs->max_pll_input_freq_khz 342 : calc_pll_cs->min_pll_ref_divider; 343 344 max_ref_divider = ((calc_pll_cs->ref_freq_khz 345 / calc_pll_cs->min_pll_input_freq_khz) 346 < calc_pll_cs->max_pll_ref_divider) 347 ? calc_pll_cs->ref_freq_khz / 348 calc_pll_cs->min_pll_input_freq_khz 349 : calc_pll_cs->max_pll_ref_divider; 350 } 351 352 /* If some parameters are invalid we could have scenario when "min">"max" 353 * which produced endless loop later. 354 * We should investigate why we get the wrong parameters. 355 * But to follow the similar logic when "adjustedPixelClock" is set to be 0 356 * it is better to return here than cause system hang/watchdog timeout later. 357 * ## SVS Wed 15 Jul 2009 */ 358 359 if (min_post_divider > max_post_divider) { 360 DC_LOG_ERROR( 361 "%s Post divider range is invalid", __func__); 362 return MAX_PLL_CALC_ERROR; 363 } 364 365 if (min_ref_divider > max_ref_divider) { 366 DC_LOG_ERROR( 367 "%s Reference divider range is invalid", __func__); 368 return MAX_PLL_CALC_ERROR; 369 } 370 371 /* 3) Try to find PLL dividers given ranges 372 * starting with minimal error tolerance. 373 * Increase error tolerance until PLL dividers found*/ 374 err_tolerance = MAX_PLL_CALC_ERROR; 375 376 while (!calc_pll_dividers_in_range( 377 calc_pll_cs, 378 pll_settings, 379 min_ref_divider, 380 max_ref_divider, 381 min_post_divider, 382 max_post_divider, 383 err_tolerance)) 384 err_tolerance += (err_tolerance > 10) 385 ? (err_tolerance / 10) 386 : 1; 387 388 return err_tolerance; 389 } 390 391 static bool pll_adjust_pix_clk( 392 struct dce110_clk_src *clk_src, 393 struct pixel_clk_params *pix_clk_params, 394 struct pll_settings *pll_settings) 395 { 396 uint32_t actual_pix_clk_100hz = 0; 397 uint32_t requested_clk_100hz = 0; 398 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 399 0 }; 400 enum bp_result bp_result; 401 switch (pix_clk_params->signal_type) { 402 case SIGNAL_TYPE_HDMI_TYPE_A: { 403 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 404 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 405 switch (pix_clk_params->color_depth) { 406 case COLOR_DEPTH_101010: 407 requested_clk_100hz = (requested_clk_100hz * 5) >> 2; 408 break; /* x1.25*/ 409 case COLOR_DEPTH_121212: 410 requested_clk_100hz = (requested_clk_100hz * 6) >> 2; 411 break; /* x1.5*/ 412 case COLOR_DEPTH_161616: 413 requested_clk_100hz = requested_clk_100hz * 2; 414 break; /* x2.0*/ 415 default: 416 break; 417 } 418 } 419 actual_pix_clk_100hz = requested_clk_100hz; 420 } 421 break; 422 423 case SIGNAL_TYPE_DISPLAY_PORT: 424 case SIGNAL_TYPE_DISPLAY_PORT_MST: 425 case SIGNAL_TYPE_EDP: 426 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; 427 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 428 break; 429 430 default: 431 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 432 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 433 break; 434 } 435 436 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; 437 bp_adjust_pixel_clock_params. 438 encoder_object_id = pix_clk_params->encoder_object_id; 439 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; 440 bp_adjust_pixel_clock_params. 441 ss_enable = pix_clk_params->flags.ENABLE_SS; 442 bp_result = clk_src->bios->funcs->adjust_pixel_clock( 443 clk_src->bios, &bp_adjust_pixel_clock_params); 444 if (bp_result == BP_RESULT_OK) { 445 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; 446 pll_settings->adjusted_pix_clk_100hz = 447 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; 448 pll_settings->reference_divider = 449 bp_adjust_pixel_clock_params.reference_divider; 450 pll_settings->pix_clk_post_divider = 451 bp_adjust_pixel_clock_params.pixel_clock_post_divider; 452 453 return true; 454 } 455 456 return false; 457 } 458 459 /** 460 * Calculate PLL Dividers for given Clock Value. 461 * First will call VBIOS Adjust Exec table to check if requested Pixel clock 462 * will be Adjusted based on usage. 463 * Then it will calculate PLL Dividers for this Adjusted clock using preferred 464 * method (Maximum VCO frequency). 465 * 466 * \return 467 * Calculation error in units of 0.01% 468 */ 469 470 static uint32_t dce110_get_pix_clk_dividers_helper ( 471 struct dce110_clk_src *clk_src, 472 struct pll_settings *pll_settings, 473 struct pixel_clk_params *pix_clk_params) 474 { 475 uint32_t field = 0; 476 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 477 DC_LOGGER_INIT(); 478 /* Check if reference clock is external (not pcie/xtalin) 479 * HW Dce80 spec: 480 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB 481 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ 482 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); 483 pll_settings->use_external_clk = (field > 1); 484 485 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always 486 * (we do not care any more from SI for some older DP Sink which 487 * does not report SS support, no known issues) */ 488 if ((pix_clk_params->flags.ENABLE_SS) || 489 (dc_is_dp_signal(pix_clk_params->signal_type))) { 490 491 const struct spread_spectrum_data *ss_data = get_ss_data_entry( 492 clk_src, 493 pix_clk_params->signal_type, 494 pll_settings->adjusted_pix_clk_100hz / 10); 495 496 if (NULL != ss_data) 497 pll_settings->ss_percentage = ss_data->percentage; 498 } 499 500 /* Check VBIOS AdjustPixelClock Exec table */ 501 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { 502 /* Should never happen, ASSERT and fill up values to be able 503 * to continue. */ 504 DC_LOG_ERROR( 505 "%s: Failed to adjust pixel clock!!", __func__); 506 pll_settings->actual_pix_clk_100hz = 507 pix_clk_params->requested_pix_clk_100hz; 508 pll_settings->adjusted_pix_clk_100hz = 509 pix_clk_params->requested_pix_clk_100hz; 510 511 if (dc_is_dp_signal(pix_clk_params->signal_type)) 512 pll_settings->adjusted_pix_clk_100hz = 1000000; 513 } 514 515 /* Calculate Dividers */ 516 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) 517 /*Calculate Dividers by HDMI object, no SS case or SS case */ 518 pll_calc_error = 519 calculate_pixel_clock_pll_dividers( 520 &clk_src->calc_pll_hdmi, 521 pll_settings); 522 else 523 /*Calculate Dividers by default object, no SS case or SS case */ 524 pll_calc_error = 525 calculate_pixel_clock_pll_dividers( 526 &clk_src->calc_pll, 527 pll_settings); 528 529 return pll_calc_error; 530 } 531 532 static void dce112_get_pix_clk_dividers_helper ( 533 struct dce110_clk_src *clk_src, 534 struct pll_settings *pll_settings, 535 struct pixel_clk_params *pix_clk_params) 536 { 537 uint32_t actual_pixel_clock_100hz; 538 539 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; 540 /* Calculate Dividers */ 541 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 542 switch (pix_clk_params->color_depth) { 543 case COLOR_DEPTH_101010: 544 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; 545 break; 546 case COLOR_DEPTH_121212: 547 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; 548 break; 549 case COLOR_DEPTH_161616: 550 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; 551 break; 552 default: 553 break; 554 } 555 } 556 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; 557 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; 558 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 559 } 560 561 static uint32_t dce110_get_pix_clk_dividers( 562 struct clock_source *cs, 563 struct pixel_clk_params *pix_clk_params, 564 struct pll_settings *pll_settings) 565 { 566 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 567 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 568 DC_LOGGER_INIT(); 569 570 if (pix_clk_params == NULL || pll_settings == NULL 571 || pix_clk_params->requested_pix_clk_100hz == 0) { 572 DC_LOG_ERROR( 573 "%s: Invalid parameters!!\n", __func__); 574 return pll_calc_error; 575 } 576 577 memset(pll_settings, 0, sizeof(*pll_settings)); 578 579 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 580 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 581 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 582 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 583 pll_settings->actual_pix_clk_100hz = 584 pix_clk_params->requested_pix_clk_100hz; 585 return 0; 586 } 587 588 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, 589 pll_settings, pix_clk_params); 590 591 return pll_calc_error; 592 } 593 594 static uint32_t dce112_get_pix_clk_dividers( 595 struct clock_source *cs, 596 struct pixel_clk_params *pix_clk_params, 597 struct pll_settings *pll_settings) 598 { 599 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 600 DC_LOGGER_INIT(); 601 602 if (pix_clk_params == NULL || pll_settings == NULL 603 || pix_clk_params->requested_pix_clk_100hz == 0) { 604 DC_LOG_ERROR( 605 "%s: Invalid parameters!!\n", __func__); 606 return -1; 607 } 608 609 memset(pll_settings, 0, sizeof(*pll_settings)); 610 611 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 612 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 613 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 614 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 615 pll_settings->actual_pix_clk_100hz = 616 pix_clk_params->requested_pix_clk_100hz; 617 return -1; 618 } 619 620 dce112_get_pix_clk_dividers_helper(clk_src, 621 pll_settings, pix_clk_params); 622 623 return 0; 624 } 625 626 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) 627 { 628 enum bp_result result; 629 struct bp_spread_spectrum_parameters bp_ss_params = {0}; 630 631 bp_ss_params.pll_id = clk_src->base.id; 632 633 /*Call ASICControl to process ATOMBIOS Exec table*/ 634 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( 635 clk_src->bios, 636 &bp_ss_params, 637 false); 638 639 return result == BP_RESULT_OK; 640 } 641 642 static bool calculate_ss( 643 const struct pll_settings *pll_settings, 644 const struct spread_spectrum_data *ss_data, 645 struct delta_sigma_data *ds_data) 646 { 647 struct fixed31_32 fb_div; 648 struct fixed31_32 ss_amount; 649 struct fixed31_32 ss_nslip_amount; 650 struct fixed31_32 ss_ds_frac_amount; 651 struct fixed31_32 ss_step_size; 652 struct fixed31_32 modulation_time; 653 654 if (ds_data == NULL) 655 return false; 656 if (ss_data == NULL) 657 return false; 658 if (ss_data->percentage == 0) 659 return false; 660 if (pll_settings == NULL) 661 return false; 662 663 memset(ds_data, 0, sizeof(struct delta_sigma_data)); 664 665 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ 666 /* 6 decimal point support in fractional feedback divider */ 667 fb_div = dc_fixpt_from_fraction( 668 pll_settings->fract_feedback_divider, 1000000); 669 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 670 671 ds_data->ds_frac_amount = 0; 672 /*spreadSpectrumPercentage is in the unit of .01%, 673 * so have to divided by 100 * 100*/ 674 ss_amount = dc_fixpt_mul( 675 fb_div, dc_fixpt_from_fraction(ss_data->percentage, 676 100 * ss_data->percentage_divider)); 677 ds_data->feedback_amount = dc_fixpt_floor(ss_amount); 678 679 ss_nslip_amount = dc_fixpt_sub(ss_amount, 680 dc_fixpt_from_int(ds_data->feedback_amount)); 681 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); 682 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); 683 684 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, 685 dc_fixpt_from_int(ds_data->nfrac_amount)); 686 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); 687 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); 688 689 /* compute SS_STEP_SIZE_DSFRAC */ 690 modulation_time = dc_fixpt_from_fraction( 691 pll_settings->reference_freq * 1000, 692 pll_settings->reference_divider * ss_data->modulation_freq_hz); 693 694 if (ss_data->flags.CENTER_SPREAD) 695 modulation_time = dc_fixpt_div_int(modulation_time, 4); 696 else 697 modulation_time = dc_fixpt_div_int(modulation_time, 2); 698 699 ss_step_size = dc_fixpt_div(ss_amount, modulation_time); 700 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ 701 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); 702 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); 703 704 return true; 705 } 706 707 static bool enable_spread_spectrum( 708 struct dce110_clk_src *clk_src, 709 enum signal_type signal, struct pll_settings *pll_settings) 710 { 711 struct bp_spread_spectrum_parameters bp_params = {0}; 712 struct delta_sigma_data d_s_data; 713 const struct spread_spectrum_data *ss_data = NULL; 714 715 ss_data = get_ss_data_entry( 716 clk_src, 717 signal, 718 pll_settings->calculated_pix_clk_100hz / 10); 719 720 /* Pixel clock PLL has been programmed to generate desired pixel clock, 721 * now enable SS on pixel clock */ 722 /* TODO is it OK to return true not doing anything ??*/ 723 if (ss_data != NULL && pll_settings->ss_percentage != 0) { 724 if (calculate_ss(pll_settings, ss_data, &d_s_data)) { 725 bp_params.ds.feedback_amount = 726 d_s_data.feedback_amount; 727 bp_params.ds.nfrac_amount = 728 d_s_data.nfrac_amount; 729 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; 730 bp_params.ds_frac_amount = 731 d_s_data.ds_frac_amount; 732 bp_params.flags.DS_TYPE = 1; 733 bp_params.pll_id = clk_src->base.id; 734 bp_params.percentage = ss_data->percentage; 735 if (ss_data->flags.CENTER_SPREAD) 736 bp_params.flags.CENTER_SPREAD = 1; 737 if (ss_data->flags.EXTERNAL_SS) 738 bp_params.flags.EXTERNAL_SS = 1; 739 740 if (BP_RESULT_OK != 741 clk_src->bios->funcs-> 742 enable_spread_spectrum_on_ppll( 743 clk_src->bios, 744 &bp_params, 745 true)) 746 return false; 747 } else 748 return false; 749 } 750 return true; 751 } 752 753 static void dce110_program_pixel_clk_resync( 754 struct dce110_clk_src *clk_src, 755 enum signal_type signal_type, 756 enum dc_color_depth colordepth) 757 { 758 REG_UPDATE(RESYNC_CNTL, 759 DCCG_DEEP_COLOR_CNTL1, 0); 760 /* 761 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 762 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 763 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 764 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 765 */ 766 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) 767 return; 768 769 switch (colordepth) { 770 case COLOR_DEPTH_888: 771 REG_UPDATE(RESYNC_CNTL, 772 DCCG_DEEP_COLOR_CNTL1, 0); 773 break; 774 case COLOR_DEPTH_101010: 775 REG_UPDATE(RESYNC_CNTL, 776 DCCG_DEEP_COLOR_CNTL1, 1); 777 break; 778 case COLOR_DEPTH_121212: 779 REG_UPDATE(RESYNC_CNTL, 780 DCCG_DEEP_COLOR_CNTL1, 2); 781 break; 782 case COLOR_DEPTH_161616: 783 REG_UPDATE(RESYNC_CNTL, 784 DCCG_DEEP_COLOR_CNTL1, 3); 785 break; 786 default: 787 break; 788 } 789 } 790 791 static void dce112_program_pixel_clk_resync( 792 struct dce110_clk_src *clk_src, 793 enum signal_type signal_type, 794 enum dc_color_depth colordepth, 795 bool enable_ycbcr420) 796 { 797 uint32_t deep_color_cntl = 0; 798 uint32_t double_rate_enable = 0; 799 800 /* 801 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 802 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 803 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 804 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 805 */ 806 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 807 double_rate_enable = enable_ycbcr420 ? 1 : 0; 808 809 switch (colordepth) { 810 case COLOR_DEPTH_888: 811 deep_color_cntl = 0; 812 break; 813 case COLOR_DEPTH_101010: 814 deep_color_cntl = 1; 815 break; 816 case COLOR_DEPTH_121212: 817 deep_color_cntl = 2; 818 break; 819 case COLOR_DEPTH_161616: 820 deep_color_cntl = 3; 821 break; 822 default: 823 break; 824 } 825 } 826 827 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) 828 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, 829 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, 830 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); 831 else 832 REG_UPDATE(PIXCLK_RESYNC_CNTL, 833 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); 834 835 } 836 837 static bool dce110_program_pix_clk( 838 struct clock_source *clock_source, 839 struct pixel_clk_params *pix_clk_params, 840 struct pll_settings *pll_settings) 841 { 842 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 843 struct bp_pixel_clock_parameters bp_pc_params = {0}; 844 845 /* First disable SS 846 * ATOMBIOS will enable by default SS on PLL for DP, 847 * do not disable it here 848 */ 849 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 850 !dc_is_dp_signal(pix_clk_params->signal_type) && 851 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 852 disable_spread_spectrum(clk_src); 853 854 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 855 bp_pc_params.controller_id = pix_clk_params->controller_id; 856 bp_pc_params.pll_id = clock_source->id; 857 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 858 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 859 bp_pc_params.signal_type = pix_clk_params->signal_type; 860 861 bp_pc_params.reference_divider = pll_settings->reference_divider; 862 bp_pc_params.feedback_divider = pll_settings->feedback_divider; 863 bp_pc_params.fractional_feedback_divider = 864 pll_settings->fract_feedback_divider; 865 bp_pc_params.pixel_clock_post_divider = 866 pll_settings->pix_clk_post_divider; 867 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = 868 pll_settings->use_external_clk; 869 870 if (clk_src->bios->funcs->set_pixel_clock( 871 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 872 return false; 873 /* Enable SS 874 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), 875 * based on HW display PLL team, SS control settings should be programmed 876 * during PLL Reset, but they do not have effect 877 * until SS_EN is asserted.*/ 878 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL 879 && !dc_is_dp_signal(pix_clk_params->signal_type)) { 880 881 if (pix_clk_params->flags.ENABLE_SS) 882 if (!enable_spread_spectrum(clk_src, 883 pix_clk_params->signal_type, 884 pll_settings)) 885 return false; 886 887 /* Resync deep color DTO */ 888 dce110_program_pixel_clk_resync(clk_src, 889 pix_clk_params->signal_type, 890 pix_clk_params->color_depth); 891 } 892 893 return true; 894 } 895 896 static bool dce112_program_pix_clk( 897 struct clock_source *clock_source, 898 struct pixel_clk_params *pix_clk_params, 899 struct pll_settings *pll_settings) 900 { 901 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 902 struct bp_pixel_clock_parameters bp_pc_params = {0}; 903 904 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 905 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { 906 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 907 unsigned dp_dto_ref_100hz = 7000000; 908 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; 909 910 /* Set DTO values: phase = target clock, modulo = reference clock */ 911 REG_WRITE(PHASE[inst], clock_100hz); 912 REG_WRITE(MODULO[inst], dp_dto_ref_100hz); 913 914 /* Enable DTO */ 915 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 916 return true; 917 } 918 #endif 919 /* First disable SS 920 * ATOMBIOS will enable by default SS on PLL for DP, 921 * do not disable it here 922 */ 923 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 924 !dc_is_dp_signal(pix_clk_params->signal_type) && 925 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 926 disable_spread_spectrum(clk_src); 927 928 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 929 bp_pc_params.controller_id = pix_clk_params->controller_id; 930 bp_pc_params.pll_id = clock_source->id; 931 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 932 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 933 bp_pc_params.signal_type = pix_clk_params->signal_type; 934 935 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 936 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 937 pll_settings->use_external_clk; 938 bp_pc_params.flags.SET_XTALIN_REF_SRC = 939 !pll_settings->use_external_clk; 940 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 941 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 942 } 943 } 944 if (clk_src->bios->funcs->set_pixel_clock( 945 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 946 return false; 947 /* Resync deep color DTO */ 948 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 949 dce112_program_pixel_clk_resync(clk_src, 950 pix_clk_params->signal_type, 951 pix_clk_params->color_depth, 952 pix_clk_params->flags.SUPPORT_YCBCR420); 953 954 return true; 955 } 956 957 958 static bool dce110_clock_source_power_down( 959 struct clock_source *clk_src) 960 { 961 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); 962 enum bp_result bp_result; 963 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; 964 965 if (clk_src->dp_clk_src) 966 return true; 967 968 /* If Pixel Clock is 0 it means Power Down Pll*/ 969 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; 970 bp_pixel_clock_params.pll_id = clk_src->id; 971 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; 972 973 /*Call ASICControl to process ATOMBIOS Exec table*/ 974 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( 975 dce110_clk_src->bios, 976 &bp_pixel_clock_params); 977 978 return bp_result == BP_RESULT_OK; 979 } 980 981 static bool get_pixel_clk_frequency_100hz( 982 const struct clock_source *clock_source, 983 unsigned int inst, 984 unsigned int *pixel_clk_khz) 985 { 986 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 987 unsigned int clock_hz = 0; 988 989 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 990 clock_hz = REG_READ(PHASE[inst]); 991 992 /* NOTE: There is agreement with VBIOS here that MODULO is 993 * programmed equal to DPREFCLK, in which case PHASE will be 994 * equivalent to pixel clock. 995 */ 996 *pixel_clk_khz = clock_hz / 100; 997 return true; 998 } 999 1000 return false; 1001 } 1002 1003 /*****************************************/ 1004 /* Constructor */ 1005 /*****************************************/ 1006 1007 static const struct clock_source_funcs dce112_clk_src_funcs = { 1008 .cs_power_down = dce110_clock_source_power_down, 1009 .program_pix_clk = dce112_program_pix_clk, 1010 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1011 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1012 }; 1013 static const struct clock_source_funcs dce110_clk_src_funcs = { 1014 .cs_power_down = dce110_clock_source_power_down, 1015 .program_pix_clk = dce110_program_pix_clk, 1016 .get_pix_clk_dividers = dce110_get_pix_clk_dividers, 1017 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1018 }; 1019 1020 1021 static void get_ss_info_from_atombios( 1022 struct dce110_clk_src *clk_src, 1023 enum as_signal_type as_signal, 1024 struct spread_spectrum_data *spread_spectrum_data[], 1025 uint32_t *ss_entries_num) 1026 { 1027 enum bp_result bp_result = BP_RESULT_FAILURE; 1028 struct spread_spectrum_info *ss_info; 1029 struct spread_spectrum_data *ss_data; 1030 struct spread_spectrum_info *ss_info_cur; 1031 struct spread_spectrum_data *ss_data_cur; 1032 uint32_t i; 1033 DC_LOGGER_INIT(); 1034 if (ss_entries_num == NULL) { 1035 DC_LOG_SYNC( 1036 "Invalid entry !!!\n"); 1037 return; 1038 } 1039 if (spread_spectrum_data == NULL) { 1040 DC_LOG_SYNC( 1041 "Invalid array pointer!!!\n"); 1042 return; 1043 } 1044 1045 spread_spectrum_data[0] = NULL; 1046 *ss_entries_num = 0; 1047 1048 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( 1049 clk_src->bios, 1050 as_signal); 1051 1052 if (*ss_entries_num == 0) 1053 return; 1054 1055 ss_info = kcalloc(*ss_entries_num, 1056 sizeof(struct spread_spectrum_info), 1057 GFP_KERNEL); 1058 ss_info_cur = ss_info; 1059 if (ss_info == NULL) 1060 return; 1061 1062 ss_data = kcalloc(*ss_entries_num, 1063 sizeof(struct spread_spectrum_data), 1064 GFP_KERNEL); 1065 if (ss_data == NULL) 1066 goto out_free_info; 1067 1068 for (i = 0, ss_info_cur = ss_info; 1069 i < (*ss_entries_num); 1070 ++i, ++ss_info_cur) { 1071 1072 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( 1073 clk_src->bios, 1074 as_signal, 1075 i, 1076 ss_info_cur); 1077 1078 if (bp_result != BP_RESULT_OK) 1079 goto out_free_data; 1080 } 1081 1082 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; 1083 i < (*ss_entries_num); 1084 ++i, ++ss_info_cur, ++ss_data_cur) { 1085 1086 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) { 1087 DC_LOG_SYNC( 1088 "Invalid ATOMBIOS SS Table!!!\n"); 1089 goto out_free_data; 1090 } 1091 1092 /* for HDMI check SS percentage, 1093 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ 1094 if (as_signal == AS_SIGNAL_TYPE_HDMI 1095 && ss_info_cur->spread_spectrum_percentage > 6){ 1096 /* invalid input, do nothing */ 1097 DC_LOG_SYNC( 1098 "Invalid SS percentage "); 1099 DC_LOG_SYNC( 1100 "for HDMI in ATOMBIOS info Table!!!\n"); 1101 continue; 1102 } 1103 if (ss_info_cur->spread_percentage_divider == 1000) { 1104 /* Keep previous precision from ATOMBIOS for these 1105 * in case new precision set by ATOMBIOS for these 1106 * (otherwise all code in DCE specific classes 1107 * for all previous ASICs would need 1108 * to be updated for SS calculations, 1109 * Audio SS compensation and DP DTO SS compensation 1110 * which assumes fixed SS percentage Divider = 100)*/ 1111 ss_info_cur->spread_spectrum_percentage /= 10; 1112 ss_info_cur->spread_percentage_divider = 100; 1113 } 1114 1115 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; 1116 ss_data_cur->percentage = 1117 ss_info_cur->spread_spectrum_percentage; 1118 ss_data_cur->percentage_divider = 1119 ss_info_cur->spread_percentage_divider; 1120 ss_data_cur->modulation_freq_hz = 1121 ss_info_cur->spread_spectrum_range; 1122 1123 if (ss_info_cur->type.CENTER_MODE) 1124 ss_data_cur->flags.CENTER_SPREAD = 1; 1125 1126 if (ss_info_cur->type.EXTERNAL) 1127 ss_data_cur->flags.EXTERNAL_SS = 1; 1128 1129 } 1130 1131 *spread_spectrum_data = ss_data; 1132 kfree(ss_info); 1133 return; 1134 1135 out_free_data: 1136 kfree(ss_data); 1137 *ss_entries_num = 0; 1138 out_free_info: 1139 kfree(ss_info); 1140 } 1141 1142 static void ss_info_from_atombios_create( 1143 struct dce110_clk_src *clk_src) 1144 { 1145 get_ss_info_from_atombios( 1146 clk_src, 1147 AS_SIGNAL_TYPE_DISPLAY_PORT, 1148 &clk_src->dp_ss_params, 1149 &clk_src->dp_ss_params_cnt); 1150 get_ss_info_from_atombios( 1151 clk_src, 1152 AS_SIGNAL_TYPE_HDMI, 1153 &clk_src->hdmi_ss_params, 1154 &clk_src->hdmi_ss_params_cnt); 1155 get_ss_info_from_atombios( 1156 clk_src, 1157 AS_SIGNAL_TYPE_DVI, 1158 &clk_src->dvi_ss_params, 1159 &clk_src->dvi_ss_params_cnt); 1160 get_ss_info_from_atombios( 1161 clk_src, 1162 AS_SIGNAL_TYPE_LVDS, 1163 &clk_src->lvds_ss_params, 1164 &clk_src->lvds_ss_params_cnt); 1165 } 1166 1167 static bool calc_pll_max_vco_construct( 1168 struct calc_pll_clock_source *calc_pll_cs, 1169 struct calc_pll_clock_source_init_data *init_data) 1170 { 1171 uint32_t i; 1172 struct dc_firmware_info fw_info = { { 0 } }; 1173 if (calc_pll_cs == NULL || 1174 init_data == NULL || 1175 init_data->bp == NULL) 1176 return false; 1177 1178 if (init_data->bp->funcs->get_firmware_info( 1179 init_data->bp, 1180 &fw_info) != BP_RESULT_OK) 1181 return false; 1182 1183 calc_pll_cs->ctx = init_data->ctx; 1184 calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency; 1185 calc_pll_cs->min_vco_khz = 1186 fw_info.pll_info.min_output_pxl_clk_pll_frequency; 1187 calc_pll_cs->max_vco_khz = 1188 fw_info.pll_info.max_output_pxl_clk_pll_frequency; 1189 1190 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) 1191 calc_pll_cs->max_pll_input_freq_khz = 1192 init_data->max_override_input_pxl_clk_pll_freq_khz; 1193 else 1194 calc_pll_cs->max_pll_input_freq_khz = 1195 fw_info.pll_info.max_input_pxl_clk_pll_frequency; 1196 1197 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) 1198 calc_pll_cs->min_pll_input_freq_khz = 1199 init_data->min_override_input_pxl_clk_pll_freq_khz; 1200 else 1201 calc_pll_cs->min_pll_input_freq_khz = 1202 fw_info.pll_info.min_input_pxl_clk_pll_frequency; 1203 1204 calc_pll_cs->min_pix_clock_pll_post_divider = 1205 init_data->min_pix_clk_pll_post_divider; 1206 calc_pll_cs->max_pix_clock_pll_post_divider = 1207 init_data->max_pix_clk_pll_post_divider; 1208 calc_pll_cs->min_pll_ref_divider = 1209 init_data->min_pll_ref_divider; 1210 calc_pll_cs->max_pll_ref_divider = 1211 init_data->max_pll_ref_divider; 1212 1213 if (init_data->num_fract_fb_divider_decimal_point == 0 || 1214 init_data->num_fract_fb_divider_decimal_point_precision > 1215 init_data->num_fract_fb_divider_decimal_point) { 1216 DC_LOG_ERROR( 1217 "The dec point num or precision is incorrect!"); 1218 return false; 1219 } 1220 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { 1221 DC_LOG_ERROR( 1222 "Incorrect fract feedback divider precision num!"); 1223 return false; 1224 } 1225 1226 calc_pll_cs->fract_fb_divider_decimal_points_num = 1227 init_data->num_fract_fb_divider_decimal_point; 1228 calc_pll_cs->fract_fb_divider_precision = 1229 init_data->num_fract_fb_divider_decimal_point_precision; 1230 calc_pll_cs->fract_fb_divider_factor = 1; 1231 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) 1232 calc_pll_cs->fract_fb_divider_factor *= 10; 1233 1234 calc_pll_cs->fract_fb_divider_precision_factor = 1; 1235 for ( 1236 i = 0; 1237 i < (calc_pll_cs->fract_fb_divider_decimal_points_num - 1238 calc_pll_cs->fract_fb_divider_precision); 1239 ++i) 1240 calc_pll_cs->fract_fb_divider_precision_factor *= 10; 1241 1242 return true; 1243 } 1244 1245 bool dce110_clk_src_construct( 1246 struct dce110_clk_src *clk_src, 1247 struct dc_context *ctx, 1248 struct dc_bios *bios, 1249 enum clock_source_id id, 1250 const struct dce110_clk_src_regs *regs, 1251 const struct dce110_clk_src_shift *cs_shift, 1252 const struct dce110_clk_src_mask *cs_mask) 1253 { 1254 struct dc_firmware_info fw_info = { { 0 } }; 1255 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; 1256 struct calc_pll_clock_source_init_data calc_pll_cs_init_data; 1257 1258 clk_src->base.ctx = ctx; 1259 clk_src->bios = bios; 1260 clk_src->base.id = id; 1261 clk_src->base.funcs = &dce110_clk_src_funcs; 1262 1263 clk_src->regs = regs; 1264 clk_src->cs_shift = cs_shift; 1265 clk_src->cs_mask = cs_mask; 1266 1267 if (clk_src->bios->funcs->get_firmware_info( 1268 clk_src->bios, &fw_info) != BP_RESULT_OK) { 1269 ASSERT_CRITICAL(false); 1270 goto unexpected_failure; 1271 } 1272 1273 clk_src->ext_clk_khz = 1274 fw_info.external_clock_source_frequency_for_dp; 1275 1276 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ 1277 calc_pll_cs_init_data.bp = bios; 1278 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; 1279 calc_pll_cs_init_data.max_pix_clk_pll_post_divider = 1280 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1281 calc_pll_cs_init_data.min_pll_ref_divider = 1; 1282 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1283 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1284 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; 1285 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1286 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; 1287 /*numberOfFractFBDividerDecimalPoints*/ 1288 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = 1289 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1290 /*number of decimal point to round off for fractional feedback divider value*/ 1291 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = 1292 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1293 calc_pll_cs_init_data.ctx = ctx; 1294 1295 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ 1296 calc_pll_cs_init_data_hdmi.bp = bios; 1297 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; 1298 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = 1299 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1300 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; 1301 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1302 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1303 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; 1304 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1305 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; 1306 /*numberOfFractFBDividerDecimalPoints*/ 1307 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = 1308 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1309 /*number of decimal point to round off for fractional feedback divider value*/ 1310 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = 1311 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1312 calc_pll_cs_init_data_hdmi.ctx = ctx; 1313 1314 clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency; 1315 1316 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) 1317 return true; 1318 1319 /* PLL only from here on */ 1320 ss_info_from_atombios_create(clk_src); 1321 1322 if (!calc_pll_max_vco_construct( 1323 &clk_src->calc_pll, 1324 &calc_pll_cs_init_data)) { 1325 ASSERT_CRITICAL(false); 1326 goto unexpected_failure; 1327 } 1328 1329 1330 calc_pll_cs_init_data_hdmi. 1331 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; 1332 calc_pll_cs_init_data_hdmi. 1333 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; 1334 1335 1336 if (!calc_pll_max_vco_construct( 1337 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { 1338 ASSERT_CRITICAL(false); 1339 goto unexpected_failure; 1340 } 1341 1342 return true; 1343 1344 unexpected_failure: 1345 return false; 1346 } 1347 1348 bool dce112_clk_src_construct( 1349 struct dce110_clk_src *clk_src, 1350 struct dc_context *ctx, 1351 struct dc_bios *bios, 1352 enum clock_source_id id, 1353 const struct dce110_clk_src_regs *regs, 1354 const struct dce110_clk_src_shift *cs_shift, 1355 const struct dce110_clk_src_mask *cs_mask) 1356 { 1357 struct dc_firmware_info fw_info = { { 0 } }; 1358 1359 clk_src->base.ctx = ctx; 1360 clk_src->bios = bios; 1361 clk_src->base.id = id; 1362 clk_src->base.funcs = &dce112_clk_src_funcs; 1363 1364 clk_src->regs = regs; 1365 clk_src->cs_shift = cs_shift; 1366 clk_src->cs_mask = cs_mask; 1367 1368 if (clk_src->bios->funcs->get_firmware_info( 1369 clk_src->bios, &fw_info) != BP_RESULT_OK) { 1370 ASSERT_CRITICAL(false); 1371 return false; 1372 } 1373 1374 clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp; 1375 1376 return true; 1377 } 1378 1379