1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 31 #include "dc_types.h" 32 #include "core_types.h" 33 34 #include "include/grph_object_id.h" 35 #include "include/logger_interface.h" 36 37 #include "dce_clock_source.h" 38 #include "clk_mgr.h" 39 40 #include "reg_helper.h" 41 42 #define REG(reg)\ 43 (clk_src->regs->reg) 44 45 #define CTX \ 46 clk_src->base.ctx 47 48 #define DC_LOGGER_INIT() 49 50 #undef FN 51 #define FN(reg_name, field_name) \ 52 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name 53 54 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 55 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 56 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 57 58 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 59 60 static const struct spread_spectrum_data *get_ss_data_entry( 61 struct dce110_clk_src *clk_src, 62 enum signal_type signal, 63 uint32_t pix_clk_khz) 64 { 65 66 uint32_t entrys_num; 67 uint32_t i; 68 struct spread_spectrum_data *ss_parm = NULL; 69 struct spread_spectrum_data *ret = NULL; 70 71 switch (signal) { 72 case SIGNAL_TYPE_DVI_SINGLE_LINK: 73 case SIGNAL_TYPE_DVI_DUAL_LINK: 74 ss_parm = clk_src->dvi_ss_params; 75 entrys_num = clk_src->dvi_ss_params_cnt; 76 break; 77 78 case SIGNAL_TYPE_HDMI_TYPE_A: 79 ss_parm = clk_src->hdmi_ss_params; 80 entrys_num = clk_src->hdmi_ss_params_cnt; 81 break; 82 83 case SIGNAL_TYPE_LVDS: 84 ss_parm = clk_src->lvds_ss_params; 85 entrys_num = clk_src->lvds_ss_params_cnt; 86 break; 87 88 case SIGNAL_TYPE_DISPLAY_PORT: 89 case SIGNAL_TYPE_DISPLAY_PORT_MST: 90 case SIGNAL_TYPE_EDP: 91 case SIGNAL_TYPE_VIRTUAL: 92 ss_parm = clk_src->dp_ss_params; 93 entrys_num = clk_src->dp_ss_params_cnt; 94 break; 95 96 default: 97 ss_parm = NULL; 98 entrys_num = 0; 99 break; 100 } 101 102 if (ss_parm == NULL) 103 return ret; 104 105 for (i = 0; i < entrys_num; ++i, ++ss_parm) { 106 if (ss_parm->freq_range_khz >= pix_clk_khz) { 107 ret = ss_parm; 108 break; 109 } 110 } 111 112 return ret; 113 } 114 115 /** 116 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional 117 * feedback dividers values 118 * 119 * @calc_pll_cs: Pointer to clock source information 120 * @target_pix_clk_100hz: Desired frequency in 100 Hz 121 * @ref_divider: Reference divider (already known) 122 * @post_divider: Post Divider (already known) 123 * @feedback_divider_param: Pointer where to store 124 * calculated feedback divider value 125 * @fract_feedback_divider_param: Pointer where to store 126 * calculated fract feedback divider value 127 * 128 * return: 129 * It fills the locations pointed by feedback_divider_param 130 * and fract_feedback_divider_param 131 * It returns - true if feedback divider not 0 132 * - false should never happen) 133 */ 134 static bool calculate_fb_and_fractional_fb_divider( 135 struct calc_pll_clock_source *calc_pll_cs, 136 uint32_t target_pix_clk_100hz, 137 uint32_t ref_divider, 138 uint32_t post_divider, 139 uint32_t *feedback_divider_param, 140 uint32_t *fract_feedback_divider_param) 141 { 142 uint64_t feedback_divider; 143 144 feedback_divider = 145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 146 feedback_divider *= 10; 147 /* additional factor, since we divide by 10 afterwards */ 148 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); 149 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); 150 151 /*Round to the number of precision 152 * The following code replace the old code (ullfeedbackDivider + 5)/10 153 * for example if the difference between the number 154 * of fractional feedback decimal point and the fractional FB Divider precision 155 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ 156 157 feedback_divider += 5ULL * 158 calc_pll_cs->fract_fb_divider_precision_factor; 159 feedback_divider = 160 div_u64(feedback_divider, 161 calc_pll_cs->fract_fb_divider_precision_factor * 10); 162 feedback_divider *= (uint64_t) 163 (calc_pll_cs->fract_fb_divider_precision_factor); 164 165 *feedback_divider_param = 166 div_u64_rem( 167 feedback_divider, 168 calc_pll_cs->fract_fb_divider_factor, 169 fract_feedback_divider_param); 170 171 if (*feedback_divider_param != 0) 172 return true; 173 return false; 174 } 175 176 /** 177 * calc_fb_divider_checking_tolerance - Calculates Feedback and 178 * Fractional Feedback divider values 179 * for passed Reference and Post divider, 180 * checking for tolerance. 181 * @calc_pll_cs: Pointer to clock source information 182 * @pll_settings: Pointer to PLL settings 183 * @ref_divider: Reference divider (already known) 184 * @post_divider: Post Divider (already known) 185 * @tolerance: Tolerance for Calculated Pixel Clock to be within 186 * 187 * return: 188 * It fills the PLLSettings structure with PLL Dividers values 189 * if calculated values are within required tolerance 190 * It returns - true if error is within tolerance 191 * - false if error is not within tolerance 192 */ 193 static bool calc_fb_divider_checking_tolerance( 194 struct calc_pll_clock_source *calc_pll_cs, 195 struct pll_settings *pll_settings, 196 uint32_t ref_divider, 197 uint32_t post_divider, 198 uint32_t tolerance) 199 { 200 uint32_t feedback_divider; 201 uint32_t fract_feedback_divider; 202 uint32_t actual_calculated_clock_100hz; 203 uint32_t abs_err; 204 uint64_t actual_calc_clk_100hz; 205 206 calculate_fb_and_fractional_fb_divider( 207 calc_pll_cs, 208 pll_settings->adjusted_pix_clk_100hz, 209 ref_divider, 210 post_divider, 211 &feedback_divider, 212 &fract_feedback_divider); 213 214 /*Actual calculated value*/ 215 actual_calc_clk_100hz = (uint64_t)feedback_divider * 216 calc_pll_cs->fract_fb_divider_factor + 217 fract_feedback_divider; 218 actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10; 219 actual_calc_clk_100hz = 220 div_u64(actual_calc_clk_100hz, 221 ref_divider * post_divider * 222 calc_pll_cs->fract_fb_divider_factor); 223 224 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); 225 226 abs_err = (actual_calculated_clock_100hz > 227 pll_settings->adjusted_pix_clk_100hz) 228 ? actual_calculated_clock_100hz - 229 pll_settings->adjusted_pix_clk_100hz 230 : pll_settings->adjusted_pix_clk_100hz - 231 actual_calculated_clock_100hz; 232 233 if (abs_err <= tolerance) { 234 /*found good values*/ 235 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; 236 pll_settings->reference_divider = ref_divider; 237 pll_settings->feedback_divider = feedback_divider; 238 pll_settings->fract_feedback_divider = fract_feedback_divider; 239 pll_settings->pix_clk_post_divider = post_divider; 240 pll_settings->calculated_pix_clk_100hz = 241 actual_calculated_clock_100hz; 242 pll_settings->vco_freq = 243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); 244 return true; 245 } 246 return false; 247 } 248 249 static bool calc_pll_dividers_in_range( 250 struct calc_pll_clock_source *calc_pll_cs, 251 struct pll_settings *pll_settings, 252 uint32_t min_ref_divider, 253 uint32_t max_ref_divider, 254 uint32_t min_post_divider, 255 uint32_t max_post_divider, 256 uint32_t err_tolerance) 257 { 258 uint32_t ref_divider; 259 uint32_t post_divider; 260 uint32_t tolerance; 261 262 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% 263 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ 264 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / 265 100000; 266 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE) 267 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE; 268 269 for ( 270 post_divider = max_post_divider; 271 post_divider >= min_post_divider; 272 --post_divider) { 273 for ( 274 ref_divider = min_ref_divider; 275 ref_divider <= max_ref_divider; 276 ++ref_divider) { 277 if (calc_fb_divider_checking_tolerance( 278 calc_pll_cs, 279 pll_settings, 280 ref_divider, 281 post_divider, 282 tolerance)) { 283 return true; 284 } 285 } 286 } 287 288 return false; 289 } 290 291 static uint32_t calculate_pixel_clock_pll_dividers( 292 struct calc_pll_clock_source *calc_pll_cs, 293 struct pll_settings *pll_settings) 294 { 295 uint32_t err_tolerance; 296 uint32_t min_post_divider; 297 uint32_t max_post_divider; 298 uint32_t min_ref_divider; 299 uint32_t max_ref_divider; 300 301 if (pll_settings->adjusted_pix_clk_100hz == 0) { 302 DC_LOG_ERROR( 303 "%s Bad requested pixel clock", __func__); 304 return MAX_PLL_CALC_ERROR; 305 } 306 307 /* 1) Find Post divider ranges */ 308 if (pll_settings->pix_clk_post_divider) { 309 min_post_divider = pll_settings->pix_clk_post_divider; 310 max_post_divider = pll_settings->pix_clk_post_divider; 311 } else { 312 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; 313 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < 314 calc_pll_cs->min_vco_khz * 10) { 315 min_post_divider = calc_pll_cs->min_vco_khz * 10 / 316 pll_settings->adjusted_pix_clk_100hz; 317 if ((min_post_divider * 318 pll_settings->adjusted_pix_clk_100hz) < 319 calc_pll_cs->min_vco_khz * 10) 320 min_post_divider++; 321 } 322 323 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; 324 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz 325 > calc_pll_cs->max_vco_khz * 10) 326 max_post_divider = calc_pll_cs->max_vco_khz * 10 / 327 pll_settings->adjusted_pix_clk_100hz; 328 } 329 330 /* 2) Find Reference divider ranges 331 * When SS is enabled, or for Display Port even without SS, 332 * pll_settings->referenceDivider is not zero. 333 * So calculate PPLL FB and fractional FB divider 334 * using the passed reference divider*/ 335 336 if (pll_settings->reference_divider) { 337 min_ref_divider = pll_settings->reference_divider; 338 max_ref_divider = pll_settings->reference_divider; 339 } else { 340 min_ref_divider = ((calc_pll_cs->ref_freq_khz 341 / calc_pll_cs->max_pll_input_freq_khz) 342 > calc_pll_cs->min_pll_ref_divider) 343 ? calc_pll_cs->ref_freq_khz 344 / calc_pll_cs->max_pll_input_freq_khz 345 : calc_pll_cs->min_pll_ref_divider; 346 347 max_ref_divider = ((calc_pll_cs->ref_freq_khz 348 / calc_pll_cs->min_pll_input_freq_khz) 349 < calc_pll_cs->max_pll_ref_divider) 350 ? calc_pll_cs->ref_freq_khz / 351 calc_pll_cs->min_pll_input_freq_khz 352 : calc_pll_cs->max_pll_ref_divider; 353 } 354 355 /* If some parameters are invalid we could have scenario when "min">"max" 356 * which produced endless loop later. 357 * We should investigate why we get the wrong parameters. 358 * But to follow the similar logic when "adjustedPixelClock" is set to be 0 359 * it is better to return here than cause system hang/watchdog timeout later. 360 * ## SVS Wed 15 Jul 2009 */ 361 362 if (min_post_divider > max_post_divider) { 363 DC_LOG_ERROR( 364 "%s Post divider range is invalid", __func__); 365 return MAX_PLL_CALC_ERROR; 366 } 367 368 if (min_ref_divider > max_ref_divider) { 369 DC_LOG_ERROR( 370 "%s Reference divider range is invalid", __func__); 371 return MAX_PLL_CALC_ERROR; 372 } 373 374 /* 3) Try to find PLL dividers given ranges 375 * starting with minimal error tolerance. 376 * Increase error tolerance until PLL dividers found*/ 377 err_tolerance = MAX_PLL_CALC_ERROR; 378 379 while (!calc_pll_dividers_in_range( 380 calc_pll_cs, 381 pll_settings, 382 min_ref_divider, 383 max_ref_divider, 384 min_post_divider, 385 max_post_divider, 386 err_tolerance)) 387 err_tolerance += (err_tolerance > 10) 388 ? (err_tolerance / 10) 389 : 1; 390 391 return err_tolerance; 392 } 393 394 static bool pll_adjust_pix_clk( 395 struct dce110_clk_src *clk_src, 396 struct pixel_clk_params *pix_clk_params, 397 struct pll_settings *pll_settings) 398 { 399 uint32_t actual_pix_clk_100hz = 0; 400 uint32_t requested_clk_100hz = 0; 401 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 402 0 }; 403 enum bp_result bp_result; 404 switch (pix_clk_params->signal_type) { 405 case SIGNAL_TYPE_HDMI_TYPE_A: { 406 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 407 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 408 switch (pix_clk_params->color_depth) { 409 case COLOR_DEPTH_101010: 410 requested_clk_100hz = (requested_clk_100hz * 5) >> 2; 411 break; /* x1.25*/ 412 case COLOR_DEPTH_121212: 413 requested_clk_100hz = (requested_clk_100hz * 6) >> 2; 414 break; /* x1.5*/ 415 case COLOR_DEPTH_161616: 416 requested_clk_100hz = requested_clk_100hz * 2; 417 break; /* x2.0*/ 418 default: 419 break; 420 } 421 } 422 actual_pix_clk_100hz = requested_clk_100hz; 423 } 424 break; 425 426 case SIGNAL_TYPE_DISPLAY_PORT: 427 case SIGNAL_TYPE_DISPLAY_PORT_MST: 428 case SIGNAL_TYPE_EDP: 429 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; 430 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 431 break; 432 433 default: 434 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 435 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 436 break; 437 } 438 439 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; 440 bp_adjust_pixel_clock_params. 441 encoder_object_id = pix_clk_params->encoder_object_id; 442 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; 443 bp_adjust_pixel_clock_params. 444 ss_enable = pix_clk_params->flags.ENABLE_SS; 445 bp_result = clk_src->bios->funcs->adjust_pixel_clock( 446 clk_src->bios, &bp_adjust_pixel_clock_params); 447 if (bp_result == BP_RESULT_OK) { 448 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; 449 pll_settings->adjusted_pix_clk_100hz = 450 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; 451 pll_settings->reference_divider = 452 bp_adjust_pixel_clock_params.reference_divider; 453 pll_settings->pix_clk_post_divider = 454 bp_adjust_pixel_clock_params.pixel_clock_post_divider; 455 456 return true; 457 } 458 459 return false; 460 } 461 462 /* 463 * Calculate PLL Dividers for given Clock Value. 464 * First will call VBIOS Adjust Exec table to check if requested Pixel clock 465 * will be Adjusted based on usage. 466 * Then it will calculate PLL Dividers for this Adjusted clock using preferred 467 * method (Maximum VCO frequency). 468 * 469 * \return 470 * Calculation error in units of 0.01% 471 */ 472 473 static uint32_t dce110_get_pix_clk_dividers_helper ( 474 struct dce110_clk_src *clk_src, 475 struct pll_settings *pll_settings, 476 struct pixel_clk_params *pix_clk_params) 477 { 478 uint32_t field = 0; 479 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 480 DC_LOGGER_INIT(); 481 /* Check if reference clock is external (not pcie/xtalin) 482 * HW Dce80 spec: 483 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB 484 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ 485 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); 486 pll_settings->use_external_clk = (field > 1); 487 488 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always 489 * (we do not care any more from SI for some older DP Sink which 490 * does not report SS support, no known issues) */ 491 if ((pix_clk_params->flags.ENABLE_SS) || 492 (dc_is_dp_signal(pix_clk_params->signal_type))) { 493 494 const struct spread_spectrum_data *ss_data = get_ss_data_entry( 495 clk_src, 496 pix_clk_params->signal_type, 497 pll_settings->adjusted_pix_clk_100hz / 10); 498 499 if (NULL != ss_data) 500 pll_settings->ss_percentage = ss_data->percentage; 501 } 502 503 /* Check VBIOS AdjustPixelClock Exec table */ 504 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { 505 /* Should never happen, ASSERT and fill up values to be able 506 * to continue. */ 507 DC_LOG_ERROR( 508 "%s: Failed to adjust pixel clock!!", __func__); 509 pll_settings->actual_pix_clk_100hz = 510 pix_clk_params->requested_pix_clk_100hz; 511 pll_settings->adjusted_pix_clk_100hz = 512 pix_clk_params->requested_pix_clk_100hz; 513 514 if (dc_is_dp_signal(pix_clk_params->signal_type)) 515 pll_settings->adjusted_pix_clk_100hz = 1000000; 516 } 517 518 /* Calculate Dividers */ 519 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) 520 /*Calculate Dividers by HDMI object, no SS case or SS case */ 521 pll_calc_error = 522 calculate_pixel_clock_pll_dividers( 523 &clk_src->calc_pll_hdmi, 524 pll_settings); 525 else 526 /*Calculate Dividers by default object, no SS case or SS case */ 527 pll_calc_error = 528 calculate_pixel_clock_pll_dividers( 529 &clk_src->calc_pll, 530 pll_settings); 531 532 return pll_calc_error; 533 } 534 535 static void dce112_get_pix_clk_dividers_helper ( 536 struct dce110_clk_src *clk_src, 537 struct pll_settings *pll_settings, 538 struct pixel_clk_params *pix_clk_params) 539 { 540 uint32_t actual_pixel_clock_100hz; 541 542 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; 543 /* Calculate Dividers */ 544 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 545 switch (pix_clk_params->color_depth) { 546 case COLOR_DEPTH_101010: 547 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; 548 break; 549 case COLOR_DEPTH_121212: 550 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; 551 break; 552 case COLOR_DEPTH_161616: 553 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; 554 break; 555 default: 556 break; 557 } 558 } 559 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; 560 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; 561 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 562 } 563 564 static uint32_t dce110_get_pix_clk_dividers( 565 struct clock_source *cs, 566 struct pixel_clk_params *pix_clk_params, 567 struct pll_settings *pll_settings) 568 { 569 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 570 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 571 DC_LOGGER_INIT(); 572 573 if (pix_clk_params == NULL || pll_settings == NULL 574 || pix_clk_params->requested_pix_clk_100hz == 0) { 575 DC_LOG_ERROR( 576 "%s: Invalid parameters!!\n", __func__); 577 return pll_calc_error; 578 } 579 580 memset(pll_settings, 0, sizeof(*pll_settings)); 581 582 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 583 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 584 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 585 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 586 pll_settings->actual_pix_clk_100hz = 587 pix_clk_params->requested_pix_clk_100hz; 588 return 0; 589 } 590 591 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, 592 pll_settings, pix_clk_params); 593 594 return pll_calc_error; 595 } 596 597 static uint32_t dce112_get_pix_clk_dividers( 598 struct clock_source *cs, 599 struct pixel_clk_params *pix_clk_params, 600 struct pll_settings *pll_settings) 601 { 602 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 603 DC_LOGGER_INIT(); 604 605 if (pix_clk_params == NULL || pll_settings == NULL 606 || pix_clk_params->requested_pix_clk_100hz == 0) { 607 DC_LOG_ERROR( 608 "%s: Invalid parameters!!\n", __func__); 609 return -1; 610 } 611 612 memset(pll_settings, 0, sizeof(*pll_settings)); 613 614 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 615 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 616 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 617 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 618 pll_settings->actual_pix_clk_100hz = 619 pix_clk_params->requested_pix_clk_100hz; 620 return -1; 621 } 622 623 dce112_get_pix_clk_dividers_helper(clk_src, 624 pll_settings, pix_clk_params); 625 626 return 0; 627 } 628 629 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) 630 { 631 enum bp_result result; 632 struct bp_spread_spectrum_parameters bp_ss_params = {0}; 633 634 bp_ss_params.pll_id = clk_src->base.id; 635 636 /*Call ASICControl to process ATOMBIOS Exec table*/ 637 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( 638 clk_src->bios, 639 &bp_ss_params, 640 false); 641 642 return result == BP_RESULT_OK; 643 } 644 645 static bool calculate_ss( 646 const struct pll_settings *pll_settings, 647 const struct spread_spectrum_data *ss_data, 648 struct delta_sigma_data *ds_data) 649 { 650 struct fixed31_32 fb_div; 651 struct fixed31_32 ss_amount; 652 struct fixed31_32 ss_nslip_amount; 653 struct fixed31_32 ss_ds_frac_amount; 654 struct fixed31_32 ss_step_size; 655 struct fixed31_32 modulation_time; 656 657 if (ds_data == NULL) 658 return false; 659 if (ss_data == NULL) 660 return false; 661 if (ss_data->percentage == 0) 662 return false; 663 if (pll_settings == NULL) 664 return false; 665 666 memset(ds_data, 0, sizeof(struct delta_sigma_data)); 667 668 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ 669 /* 6 decimal point support in fractional feedback divider */ 670 fb_div = dc_fixpt_from_fraction( 671 pll_settings->fract_feedback_divider, 1000000); 672 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 673 674 ds_data->ds_frac_amount = 0; 675 /*spreadSpectrumPercentage is in the unit of .01%, 676 * so have to divided by 100 * 100*/ 677 ss_amount = dc_fixpt_mul( 678 fb_div, dc_fixpt_from_fraction(ss_data->percentage, 679 100 * ss_data->percentage_divider)); 680 ds_data->feedback_amount = dc_fixpt_floor(ss_amount); 681 682 ss_nslip_amount = dc_fixpt_sub(ss_amount, 683 dc_fixpt_from_int(ds_data->feedback_amount)); 684 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); 685 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); 686 687 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, 688 dc_fixpt_from_int(ds_data->nfrac_amount)); 689 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); 690 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); 691 692 /* compute SS_STEP_SIZE_DSFRAC */ 693 modulation_time = dc_fixpt_from_fraction( 694 pll_settings->reference_freq * 1000, 695 pll_settings->reference_divider * ss_data->modulation_freq_hz); 696 697 if (ss_data->flags.CENTER_SPREAD) 698 modulation_time = dc_fixpt_div_int(modulation_time, 4); 699 else 700 modulation_time = dc_fixpt_div_int(modulation_time, 2); 701 702 ss_step_size = dc_fixpt_div(ss_amount, modulation_time); 703 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ 704 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); 705 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); 706 707 return true; 708 } 709 710 static bool enable_spread_spectrum( 711 struct dce110_clk_src *clk_src, 712 enum signal_type signal, struct pll_settings *pll_settings) 713 { 714 struct bp_spread_spectrum_parameters bp_params = {0}; 715 struct delta_sigma_data d_s_data; 716 const struct spread_spectrum_data *ss_data = NULL; 717 718 ss_data = get_ss_data_entry( 719 clk_src, 720 signal, 721 pll_settings->calculated_pix_clk_100hz / 10); 722 723 /* Pixel clock PLL has been programmed to generate desired pixel clock, 724 * now enable SS on pixel clock */ 725 /* TODO is it OK to return true not doing anything ??*/ 726 if (ss_data != NULL && pll_settings->ss_percentage != 0) { 727 if (calculate_ss(pll_settings, ss_data, &d_s_data)) { 728 bp_params.ds.feedback_amount = 729 d_s_data.feedback_amount; 730 bp_params.ds.nfrac_amount = 731 d_s_data.nfrac_amount; 732 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; 733 bp_params.ds_frac_amount = 734 d_s_data.ds_frac_amount; 735 bp_params.flags.DS_TYPE = 1; 736 bp_params.pll_id = clk_src->base.id; 737 bp_params.percentage = ss_data->percentage; 738 if (ss_data->flags.CENTER_SPREAD) 739 bp_params.flags.CENTER_SPREAD = 1; 740 if (ss_data->flags.EXTERNAL_SS) 741 bp_params.flags.EXTERNAL_SS = 1; 742 743 if (BP_RESULT_OK != 744 clk_src->bios->funcs-> 745 enable_spread_spectrum_on_ppll( 746 clk_src->bios, 747 &bp_params, 748 true)) 749 return false; 750 } else 751 return false; 752 } 753 return true; 754 } 755 756 static void dce110_program_pixel_clk_resync( 757 struct dce110_clk_src *clk_src, 758 enum signal_type signal_type, 759 enum dc_color_depth colordepth) 760 { 761 REG_UPDATE(RESYNC_CNTL, 762 DCCG_DEEP_COLOR_CNTL1, 0); 763 /* 764 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 765 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 766 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 767 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 768 */ 769 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) 770 return; 771 772 switch (colordepth) { 773 case COLOR_DEPTH_888: 774 REG_UPDATE(RESYNC_CNTL, 775 DCCG_DEEP_COLOR_CNTL1, 0); 776 break; 777 case COLOR_DEPTH_101010: 778 REG_UPDATE(RESYNC_CNTL, 779 DCCG_DEEP_COLOR_CNTL1, 1); 780 break; 781 case COLOR_DEPTH_121212: 782 REG_UPDATE(RESYNC_CNTL, 783 DCCG_DEEP_COLOR_CNTL1, 2); 784 break; 785 case COLOR_DEPTH_161616: 786 REG_UPDATE(RESYNC_CNTL, 787 DCCG_DEEP_COLOR_CNTL1, 3); 788 break; 789 default: 790 break; 791 } 792 } 793 794 static void dce112_program_pixel_clk_resync( 795 struct dce110_clk_src *clk_src, 796 enum signal_type signal_type, 797 enum dc_color_depth colordepth, 798 bool enable_ycbcr420) 799 { 800 uint32_t deep_color_cntl = 0; 801 uint32_t double_rate_enable = 0; 802 803 /* 804 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 805 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 806 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 807 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 808 */ 809 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 810 double_rate_enable = enable_ycbcr420 ? 1 : 0; 811 812 switch (colordepth) { 813 case COLOR_DEPTH_888: 814 deep_color_cntl = 0; 815 break; 816 case COLOR_DEPTH_101010: 817 deep_color_cntl = 1; 818 break; 819 case COLOR_DEPTH_121212: 820 deep_color_cntl = 2; 821 break; 822 case COLOR_DEPTH_161616: 823 deep_color_cntl = 3; 824 break; 825 default: 826 break; 827 } 828 } 829 830 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) 831 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, 832 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, 833 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); 834 else 835 REG_UPDATE(PIXCLK_RESYNC_CNTL, 836 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); 837 838 } 839 840 static bool dce110_program_pix_clk( 841 struct clock_source *clock_source, 842 struct pixel_clk_params *pix_clk_params, 843 struct pll_settings *pll_settings) 844 { 845 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 846 struct bp_pixel_clock_parameters bp_pc_params = {0}; 847 848 /* First disable SS 849 * ATOMBIOS will enable by default SS on PLL for DP, 850 * do not disable it here 851 */ 852 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 853 !dc_is_dp_signal(pix_clk_params->signal_type) && 854 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 855 disable_spread_spectrum(clk_src); 856 857 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 858 bp_pc_params.controller_id = pix_clk_params->controller_id; 859 bp_pc_params.pll_id = clock_source->id; 860 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 861 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 862 bp_pc_params.signal_type = pix_clk_params->signal_type; 863 864 bp_pc_params.reference_divider = pll_settings->reference_divider; 865 bp_pc_params.feedback_divider = pll_settings->feedback_divider; 866 bp_pc_params.fractional_feedback_divider = 867 pll_settings->fract_feedback_divider; 868 bp_pc_params.pixel_clock_post_divider = 869 pll_settings->pix_clk_post_divider; 870 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = 871 pll_settings->use_external_clk; 872 873 switch (pix_clk_params->color_depth) { 874 case COLOR_DEPTH_101010: 875 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30; 876 break; 877 case COLOR_DEPTH_121212: 878 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36; 879 break; 880 case COLOR_DEPTH_161616: 881 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48; 882 break; 883 default: 884 break; 885 } 886 887 if (clk_src->bios->funcs->set_pixel_clock( 888 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 889 return false; 890 /* Enable SS 891 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), 892 * based on HW display PLL team, SS control settings should be programmed 893 * during PLL Reset, but they do not have effect 894 * until SS_EN is asserted.*/ 895 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL 896 && !dc_is_dp_signal(pix_clk_params->signal_type)) { 897 898 if (pix_clk_params->flags.ENABLE_SS) 899 if (!enable_spread_spectrum(clk_src, 900 pix_clk_params->signal_type, 901 pll_settings)) 902 return false; 903 904 /* Resync deep color DTO */ 905 dce110_program_pixel_clk_resync(clk_src, 906 pix_clk_params->signal_type, 907 pix_clk_params->color_depth); 908 } 909 910 return true; 911 } 912 913 static bool dce112_program_pix_clk( 914 struct clock_source *clock_source, 915 struct pixel_clk_params *pix_clk_params, 916 struct pll_settings *pll_settings) 917 { 918 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 919 struct bp_pixel_clock_parameters bp_pc_params = {0}; 920 921 #if defined(CONFIG_DRM_AMD_DC_DCN) 922 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { 923 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 924 unsigned dp_dto_ref_100hz = 7000000; 925 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; 926 927 /* Set DTO values: phase = target clock, modulo = reference clock */ 928 REG_WRITE(PHASE[inst], clock_100hz); 929 REG_WRITE(MODULO[inst], dp_dto_ref_100hz); 930 931 /* Enable DTO */ 932 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 933 return true; 934 } 935 #endif 936 /* First disable SS 937 * ATOMBIOS will enable by default SS on PLL for DP, 938 * do not disable it here 939 */ 940 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 941 !dc_is_dp_signal(pix_clk_params->signal_type) && 942 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 943 disable_spread_spectrum(clk_src); 944 945 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 946 bp_pc_params.controller_id = pix_clk_params->controller_id; 947 bp_pc_params.pll_id = clock_source->id; 948 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 949 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 950 bp_pc_params.signal_type = pix_clk_params->signal_type; 951 952 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 953 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 954 pll_settings->use_external_clk; 955 bp_pc_params.flags.SET_XTALIN_REF_SRC = 956 !pll_settings->use_external_clk; 957 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 958 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 959 } 960 } 961 if (clk_src->bios->funcs->set_pixel_clock( 962 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 963 return false; 964 /* Resync deep color DTO */ 965 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 966 dce112_program_pixel_clk_resync(clk_src, 967 pix_clk_params->signal_type, 968 pix_clk_params->color_depth, 969 pix_clk_params->flags.SUPPORT_YCBCR420); 970 971 return true; 972 } 973 974 #if defined(CONFIG_DRM_AMD_DC_DCN) 975 static bool dcn31_program_pix_clk( 976 struct clock_source *clock_source, 977 struct pixel_clk_params *pix_clk_params, 978 struct pll_settings *pll_settings) 979 { 980 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 981 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 982 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 983 const struct pixel_rate_range_table_entry *e = 984 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 985 struct bp_pixel_clock_parameters bp_pc_params = {0}; 986 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 987 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 988 if (dc_is_dp_signal(pix_clk_params->signal_type)) { 989 if (e) { 990 /* Set DTO values: phase = target clock, modulo = reference clock*/ 991 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 992 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 993 } else { 994 /* Set DTO values: phase = target clock, modulo = reference clock*/ 995 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 996 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 997 } 998 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 999 } else { 1000 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { 1001 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1002 unsigned dp_dto_ref_100hz = 7000000; 1003 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; 1004 1005 /* Set DTO values: phase = target clock, modulo = reference clock */ 1006 REG_WRITE(PHASE[inst], clock_100hz); 1007 REG_WRITE(MODULO[inst], dp_dto_ref_100hz); 1008 1009 /* Enable DTO */ 1010 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1011 return true; 1012 } 1013 1014 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1015 bp_pc_params.controller_id = pix_clk_params->controller_id; 1016 bp_pc_params.pll_id = clock_source->id; 1017 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 1018 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 1019 bp_pc_params.signal_type = pix_clk_params->signal_type; 1020 1021 // Make sure we send the correct color depth to DMUB for HDMI 1022 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1023 switch (pix_clk_params->color_depth) { 1024 case COLOR_DEPTH_888: 1025 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1026 break; 1027 case COLOR_DEPTH_101010: 1028 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30; 1029 break; 1030 case COLOR_DEPTH_121212: 1031 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36; 1032 break; 1033 case COLOR_DEPTH_161616: 1034 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48; 1035 break; 1036 default: 1037 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1038 break; 1039 } 1040 bp_pc_params.color_depth = bp_pc_colour_depth; 1041 } 1042 1043 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 1044 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 1045 pll_settings->use_external_clk; 1046 bp_pc_params.flags.SET_XTALIN_REF_SRC = 1047 !pll_settings->use_external_clk; 1048 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 1049 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 1050 } 1051 } 1052 if (clk_src->bios->funcs->set_pixel_clock( 1053 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 1054 return false; 1055 /* Resync deep color DTO */ 1056 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 1057 dce112_program_pixel_clk_resync(clk_src, 1058 pix_clk_params->signal_type, 1059 pix_clk_params->color_depth, 1060 pix_clk_params->flags.SUPPORT_YCBCR420); 1061 } 1062 1063 return true; 1064 } 1065 #endif 1066 1067 static bool dce110_clock_source_power_down( 1068 struct clock_source *clk_src) 1069 { 1070 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); 1071 enum bp_result bp_result; 1072 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; 1073 1074 if (clk_src->dp_clk_src) 1075 return true; 1076 1077 /* If Pixel Clock is 0 it means Power Down Pll*/ 1078 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; 1079 bp_pixel_clock_params.pll_id = clk_src->id; 1080 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; 1081 1082 /*Call ASICControl to process ATOMBIOS Exec table*/ 1083 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( 1084 dce110_clk_src->bios, 1085 &bp_pixel_clock_params); 1086 1087 return bp_result == BP_RESULT_OK; 1088 } 1089 1090 static bool get_pixel_clk_frequency_100hz( 1091 const struct clock_source *clock_source, 1092 unsigned int inst, 1093 unsigned int *pixel_clk_khz) 1094 { 1095 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1096 unsigned int clock_hz = 0; 1097 unsigned int modulo_hz = 0; 1098 1099 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 1100 clock_hz = REG_READ(PHASE[inst]); 1101 1102 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1103 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1104 /* NOTE: In case VBLANK syncronization is enabled, MODULO may 1105 * not be programmed equal to DPREFCLK 1106 */ 1107 modulo_hz = REG_READ(MODULO[inst]); 1108 *pixel_clk_khz = div_u64((uint64_t)clock_hz* 1109 clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, 1110 modulo_hz); 1111 } else { 1112 /* NOTE: There is agreement with VBIOS here that MODULO is 1113 * programmed equal to DPREFCLK, in which case PHASE will be 1114 * equivalent to pixel clock. 1115 */ 1116 *pixel_clk_khz = clock_hz / 100; 1117 } 1118 return true; 1119 } 1120 1121 return false; 1122 } 1123 1124 #if defined(CONFIG_DRM_AMD_DC_DCN) 1125 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 1126 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { 1127 // /1.001 rates 1128 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17 1129 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340 1130 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758 1131 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87 1132 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516 1133 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83 1134 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527 1135 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429 1136 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033 1137 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857 1138 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6 1139 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091 1140 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055 1141 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325 1142 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231 1143 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974 1144 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455 1145 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066 1146 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377 1147 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308 1148 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987 1149 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209 1150 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099 1151 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131 1152 1153 // *1.001 rates 1154 {27020, 27030, 27000, 1001, 1000}, //27Mhz 1155 {54050, 54060, 54000, 1001, 1000}, //54Mhz 1156 {108100, 108110, 108000, 1001, 1000},//108Mhz 1157 }; 1158 1159 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 1160 unsigned int pixel_rate_khz) 1161 { 1162 int i; 1163 1164 for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) { 1165 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; 1166 1167 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) { 1168 return e; 1169 } 1170 } 1171 1172 return NULL; 1173 } 1174 #endif 1175 1176 static bool dcn20_program_pix_clk( 1177 struct clock_source *clock_source, 1178 struct pixel_clk_params *pix_clk_params, 1179 struct pll_settings *pll_settings) 1180 { 1181 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1182 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1183 1184 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); 1185 1186 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1187 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1188 /* NOTE: In case VBLANK syncronization is enabled, 1189 * we need to set modulo to default DPREFCLK first 1190 * dce112_program_pix_clk does not set default DPREFCLK 1191 */ 1192 REG_WRITE(MODULO[inst], 1193 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); 1194 } 1195 return true; 1196 } 1197 1198 static bool dcn20_override_dp_pix_clk( 1199 struct clock_source *clock_source, 1200 unsigned int inst, 1201 unsigned int pixel_clk, 1202 unsigned int ref_clk) 1203 { 1204 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1205 1206 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0); 1207 REG_WRITE(PHASE[inst], pixel_clk); 1208 REG_WRITE(MODULO[inst], ref_clk); 1209 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1210 return true; 1211 } 1212 1213 static const struct clock_source_funcs dcn20_clk_src_funcs = { 1214 .cs_power_down = dce110_clock_source_power_down, 1215 .program_pix_clk = dcn20_program_pix_clk, 1216 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1217 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz, 1218 .override_dp_pix_clk = dcn20_override_dp_pix_clk 1219 }; 1220 1221 #if defined(CONFIG_DRM_AMD_DC_DCN) 1222 static bool dcn3_program_pix_clk( 1223 struct clock_source *clock_source, 1224 struct pixel_clk_params *pix_clk_params, 1225 struct pll_settings *pll_settings) 1226 { 1227 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1228 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1229 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1230 const struct pixel_rate_range_table_entry *e = 1231 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 1232 1233 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 1234 if (dc_is_dp_signal(pix_clk_params->signal_type)) { 1235 if (e) { 1236 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1237 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 1238 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 1239 } else { 1240 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1241 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 1242 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 1243 } 1244 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1245 } else 1246 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table 1247 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); 1248 1249 return true; 1250 } 1251 1252 static uint32_t dcn3_get_pix_clk_dividers( 1253 struct clock_source *cs, 1254 struct pixel_clk_params *pix_clk_params, 1255 struct pll_settings *pll_settings) 1256 { 1257 unsigned long long actual_pix_clk_100Hz = pix_clk_params->requested_pix_clk_100hz; 1258 struct dce110_clk_src *clk_src; 1259 1260 clk_src = TO_DCE110_CLK_SRC(cs); 1261 DC_LOGGER_INIT(); 1262 1263 if (pix_clk_params == NULL || pll_settings == NULL 1264 || pix_clk_params->requested_pix_clk_100hz == 0) { 1265 DC_LOG_ERROR( 1266 "%s: Invalid parameters!!\n", __func__); 1267 return -1; 1268 } 1269 1270 memset(pll_settings, 0, sizeof(*pll_settings)); 1271 /* Adjust for HDMI Type A deep color */ 1272 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1273 switch (pix_clk_params->color_depth) { 1274 case COLOR_DEPTH_101010: 1275 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2; 1276 break; 1277 case COLOR_DEPTH_121212: 1278 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2; 1279 break; 1280 case COLOR_DEPTH_161616: 1281 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2; 1282 break; 1283 default: 1284 break; 1285 } 1286 } 1287 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1288 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1289 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1290 1291 return 0; 1292 } 1293 1294 static const struct clock_source_funcs dcn3_clk_src_funcs = { 1295 .cs_power_down = dce110_clock_source_power_down, 1296 .program_pix_clk = dcn3_program_pix_clk, 1297 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1298 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1299 }; 1300 1301 static const struct clock_source_funcs dcn31_clk_src_funcs = { 1302 .cs_power_down = dce110_clock_source_power_down, 1303 .program_pix_clk = dcn31_program_pix_clk, 1304 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1305 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1306 }; 1307 #endif 1308 /*****************************************/ 1309 /* Constructor */ 1310 /*****************************************/ 1311 1312 static const struct clock_source_funcs dce112_clk_src_funcs = { 1313 .cs_power_down = dce110_clock_source_power_down, 1314 .program_pix_clk = dce112_program_pix_clk, 1315 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1316 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1317 }; 1318 static const struct clock_source_funcs dce110_clk_src_funcs = { 1319 .cs_power_down = dce110_clock_source_power_down, 1320 .program_pix_clk = dce110_program_pix_clk, 1321 .get_pix_clk_dividers = dce110_get_pix_clk_dividers, 1322 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1323 }; 1324 1325 1326 static void get_ss_info_from_atombios( 1327 struct dce110_clk_src *clk_src, 1328 enum as_signal_type as_signal, 1329 struct spread_spectrum_data *spread_spectrum_data[], 1330 uint32_t *ss_entries_num) 1331 { 1332 enum bp_result bp_result = BP_RESULT_FAILURE; 1333 struct spread_spectrum_info *ss_info; 1334 struct spread_spectrum_data *ss_data; 1335 struct spread_spectrum_info *ss_info_cur; 1336 struct spread_spectrum_data *ss_data_cur; 1337 uint32_t i; 1338 DC_LOGGER_INIT(); 1339 if (ss_entries_num == NULL) { 1340 DC_LOG_SYNC( 1341 "Invalid entry !!!\n"); 1342 return; 1343 } 1344 if (spread_spectrum_data == NULL) { 1345 DC_LOG_SYNC( 1346 "Invalid array pointer!!!\n"); 1347 return; 1348 } 1349 1350 spread_spectrum_data[0] = NULL; 1351 *ss_entries_num = 0; 1352 1353 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( 1354 clk_src->bios, 1355 as_signal); 1356 1357 if (*ss_entries_num == 0) 1358 return; 1359 1360 ss_info = kcalloc(*ss_entries_num, 1361 sizeof(struct spread_spectrum_info), 1362 GFP_KERNEL); 1363 ss_info_cur = ss_info; 1364 if (ss_info == NULL) 1365 return; 1366 1367 ss_data = kcalloc(*ss_entries_num, 1368 sizeof(struct spread_spectrum_data), 1369 GFP_KERNEL); 1370 if (ss_data == NULL) 1371 goto out_free_info; 1372 1373 for (i = 0, ss_info_cur = ss_info; 1374 i < (*ss_entries_num); 1375 ++i, ++ss_info_cur) { 1376 1377 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( 1378 clk_src->bios, 1379 as_signal, 1380 i, 1381 ss_info_cur); 1382 1383 if (bp_result != BP_RESULT_OK) 1384 goto out_free_data; 1385 } 1386 1387 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; 1388 i < (*ss_entries_num); 1389 ++i, ++ss_info_cur, ++ss_data_cur) { 1390 1391 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) { 1392 DC_LOG_SYNC( 1393 "Invalid ATOMBIOS SS Table!!!\n"); 1394 goto out_free_data; 1395 } 1396 1397 /* for HDMI check SS percentage, 1398 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ 1399 if (as_signal == AS_SIGNAL_TYPE_HDMI 1400 && ss_info_cur->spread_spectrum_percentage > 6){ 1401 /* invalid input, do nothing */ 1402 DC_LOG_SYNC( 1403 "Invalid SS percentage "); 1404 DC_LOG_SYNC( 1405 "for HDMI in ATOMBIOS info Table!!!\n"); 1406 continue; 1407 } 1408 if (ss_info_cur->spread_percentage_divider == 1000) { 1409 /* Keep previous precision from ATOMBIOS for these 1410 * in case new precision set by ATOMBIOS for these 1411 * (otherwise all code in DCE specific classes 1412 * for all previous ASICs would need 1413 * to be updated for SS calculations, 1414 * Audio SS compensation and DP DTO SS compensation 1415 * which assumes fixed SS percentage Divider = 100)*/ 1416 ss_info_cur->spread_spectrum_percentage /= 10; 1417 ss_info_cur->spread_percentage_divider = 100; 1418 } 1419 1420 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; 1421 ss_data_cur->percentage = 1422 ss_info_cur->spread_spectrum_percentage; 1423 ss_data_cur->percentage_divider = 1424 ss_info_cur->spread_percentage_divider; 1425 ss_data_cur->modulation_freq_hz = 1426 ss_info_cur->spread_spectrum_range; 1427 1428 if (ss_info_cur->type.CENTER_MODE) 1429 ss_data_cur->flags.CENTER_SPREAD = 1; 1430 1431 if (ss_info_cur->type.EXTERNAL) 1432 ss_data_cur->flags.EXTERNAL_SS = 1; 1433 1434 } 1435 1436 *spread_spectrum_data = ss_data; 1437 kfree(ss_info); 1438 return; 1439 1440 out_free_data: 1441 kfree(ss_data); 1442 *ss_entries_num = 0; 1443 out_free_info: 1444 kfree(ss_info); 1445 } 1446 1447 static void ss_info_from_atombios_create( 1448 struct dce110_clk_src *clk_src) 1449 { 1450 get_ss_info_from_atombios( 1451 clk_src, 1452 AS_SIGNAL_TYPE_DISPLAY_PORT, 1453 &clk_src->dp_ss_params, 1454 &clk_src->dp_ss_params_cnt); 1455 get_ss_info_from_atombios( 1456 clk_src, 1457 AS_SIGNAL_TYPE_HDMI, 1458 &clk_src->hdmi_ss_params, 1459 &clk_src->hdmi_ss_params_cnt); 1460 get_ss_info_from_atombios( 1461 clk_src, 1462 AS_SIGNAL_TYPE_DVI, 1463 &clk_src->dvi_ss_params, 1464 &clk_src->dvi_ss_params_cnt); 1465 get_ss_info_from_atombios( 1466 clk_src, 1467 AS_SIGNAL_TYPE_LVDS, 1468 &clk_src->lvds_ss_params, 1469 &clk_src->lvds_ss_params_cnt); 1470 } 1471 1472 static bool calc_pll_max_vco_construct( 1473 struct calc_pll_clock_source *calc_pll_cs, 1474 struct calc_pll_clock_source_init_data *init_data) 1475 { 1476 uint32_t i; 1477 struct dc_firmware_info *fw_info; 1478 if (calc_pll_cs == NULL || 1479 init_data == NULL || 1480 init_data->bp == NULL) 1481 return false; 1482 1483 if (!init_data->bp->fw_info_valid) 1484 return false; 1485 1486 fw_info = &init_data->bp->fw_info; 1487 calc_pll_cs->ctx = init_data->ctx; 1488 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; 1489 calc_pll_cs->min_vco_khz = 1490 fw_info->pll_info.min_output_pxl_clk_pll_frequency; 1491 calc_pll_cs->max_vco_khz = 1492 fw_info->pll_info.max_output_pxl_clk_pll_frequency; 1493 1494 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) 1495 calc_pll_cs->max_pll_input_freq_khz = 1496 init_data->max_override_input_pxl_clk_pll_freq_khz; 1497 else 1498 calc_pll_cs->max_pll_input_freq_khz = 1499 fw_info->pll_info.max_input_pxl_clk_pll_frequency; 1500 1501 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) 1502 calc_pll_cs->min_pll_input_freq_khz = 1503 init_data->min_override_input_pxl_clk_pll_freq_khz; 1504 else 1505 calc_pll_cs->min_pll_input_freq_khz = 1506 fw_info->pll_info.min_input_pxl_clk_pll_frequency; 1507 1508 calc_pll_cs->min_pix_clock_pll_post_divider = 1509 init_data->min_pix_clk_pll_post_divider; 1510 calc_pll_cs->max_pix_clock_pll_post_divider = 1511 init_data->max_pix_clk_pll_post_divider; 1512 calc_pll_cs->min_pll_ref_divider = 1513 init_data->min_pll_ref_divider; 1514 calc_pll_cs->max_pll_ref_divider = 1515 init_data->max_pll_ref_divider; 1516 1517 if (init_data->num_fract_fb_divider_decimal_point == 0 || 1518 init_data->num_fract_fb_divider_decimal_point_precision > 1519 init_data->num_fract_fb_divider_decimal_point) { 1520 DC_LOG_ERROR( 1521 "The dec point num or precision is incorrect!"); 1522 return false; 1523 } 1524 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { 1525 DC_LOG_ERROR( 1526 "Incorrect fract feedback divider precision num!"); 1527 return false; 1528 } 1529 1530 calc_pll_cs->fract_fb_divider_decimal_points_num = 1531 init_data->num_fract_fb_divider_decimal_point; 1532 calc_pll_cs->fract_fb_divider_precision = 1533 init_data->num_fract_fb_divider_decimal_point_precision; 1534 calc_pll_cs->fract_fb_divider_factor = 1; 1535 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) 1536 calc_pll_cs->fract_fb_divider_factor *= 10; 1537 1538 calc_pll_cs->fract_fb_divider_precision_factor = 1; 1539 for ( 1540 i = 0; 1541 i < (calc_pll_cs->fract_fb_divider_decimal_points_num - 1542 calc_pll_cs->fract_fb_divider_precision); 1543 ++i) 1544 calc_pll_cs->fract_fb_divider_precision_factor *= 10; 1545 1546 return true; 1547 } 1548 1549 bool dce110_clk_src_construct( 1550 struct dce110_clk_src *clk_src, 1551 struct dc_context *ctx, 1552 struct dc_bios *bios, 1553 enum clock_source_id id, 1554 const struct dce110_clk_src_regs *regs, 1555 const struct dce110_clk_src_shift *cs_shift, 1556 const struct dce110_clk_src_mask *cs_mask) 1557 { 1558 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; 1559 struct calc_pll_clock_source_init_data calc_pll_cs_init_data; 1560 1561 clk_src->base.ctx = ctx; 1562 clk_src->bios = bios; 1563 clk_src->base.id = id; 1564 clk_src->base.funcs = &dce110_clk_src_funcs; 1565 1566 clk_src->regs = regs; 1567 clk_src->cs_shift = cs_shift; 1568 clk_src->cs_mask = cs_mask; 1569 1570 if (!clk_src->bios->fw_info_valid) { 1571 ASSERT_CRITICAL(false); 1572 goto unexpected_failure; 1573 } 1574 1575 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1576 1577 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ 1578 calc_pll_cs_init_data.bp = bios; 1579 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; 1580 calc_pll_cs_init_data.max_pix_clk_pll_post_divider = 1581 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1582 calc_pll_cs_init_data.min_pll_ref_divider = 1; 1583 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1584 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1585 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; 1586 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1587 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; 1588 /*numberOfFractFBDividerDecimalPoints*/ 1589 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = 1590 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1591 /*number of decimal point to round off for fractional feedback divider value*/ 1592 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = 1593 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1594 calc_pll_cs_init_data.ctx = ctx; 1595 1596 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ 1597 calc_pll_cs_init_data_hdmi.bp = bios; 1598 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; 1599 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = 1600 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1601 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; 1602 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1603 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1604 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; 1605 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1606 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; 1607 /*numberOfFractFBDividerDecimalPoints*/ 1608 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = 1609 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1610 /*number of decimal point to round off for fractional feedback divider value*/ 1611 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = 1612 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1613 calc_pll_cs_init_data_hdmi.ctx = ctx; 1614 1615 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; 1616 1617 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) 1618 return true; 1619 1620 /* PLL only from here on */ 1621 ss_info_from_atombios_create(clk_src); 1622 1623 if (!calc_pll_max_vco_construct( 1624 &clk_src->calc_pll, 1625 &calc_pll_cs_init_data)) { 1626 ASSERT_CRITICAL(false); 1627 goto unexpected_failure; 1628 } 1629 1630 1631 calc_pll_cs_init_data_hdmi. 1632 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; 1633 calc_pll_cs_init_data_hdmi. 1634 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; 1635 1636 1637 if (!calc_pll_max_vco_construct( 1638 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { 1639 ASSERT_CRITICAL(false); 1640 goto unexpected_failure; 1641 } 1642 1643 return true; 1644 1645 unexpected_failure: 1646 return false; 1647 } 1648 1649 bool dce112_clk_src_construct( 1650 struct dce110_clk_src *clk_src, 1651 struct dc_context *ctx, 1652 struct dc_bios *bios, 1653 enum clock_source_id id, 1654 const struct dce110_clk_src_regs *regs, 1655 const struct dce110_clk_src_shift *cs_shift, 1656 const struct dce110_clk_src_mask *cs_mask) 1657 { 1658 clk_src->base.ctx = ctx; 1659 clk_src->bios = bios; 1660 clk_src->base.id = id; 1661 clk_src->base.funcs = &dce112_clk_src_funcs; 1662 1663 clk_src->regs = regs; 1664 clk_src->cs_shift = cs_shift; 1665 clk_src->cs_mask = cs_mask; 1666 1667 if (!clk_src->bios->fw_info_valid) { 1668 ASSERT_CRITICAL(false); 1669 return false; 1670 } 1671 1672 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1673 1674 return true; 1675 } 1676 1677 bool dcn20_clk_src_construct( 1678 struct dce110_clk_src *clk_src, 1679 struct dc_context *ctx, 1680 struct dc_bios *bios, 1681 enum clock_source_id id, 1682 const struct dce110_clk_src_regs *regs, 1683 const struct dce110_clk_src_shift *cs_shift, 1684 const struct dce110_clk_src_mask *cs_mask) 1685 { 1686 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1687 1688 clk_src->base.funcs = &dcn20_clk_src_funcs; 1689 1690 return ret; 1691 } 1692 1693 #if defined(CONFIG_DRM_AMD_DC_DCN) 1694 bool dcn3_clk_src_construct( 1695 struct dce110_clk_src *clk_src, 1696 struct dc_context *ctx, 1697 struct dc_bios *bios, 1698 enum clock_source_id id, 1699 const struct dce110_clk_src_regs *regs, 1700 const struct dce110_clk_src_shift *cs_shift, 1701 const struct dce110_clk_src_mask *cs_mask) 1702 { 1703 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1704 1705 clk_src->base.funcs = &dcn3_clk_src_funcs; 1706 1707 return ret; 1708 } 1709 #endif 1710 1711 #if defined(CONFIG_DRM_AMD_DC_DCN) 1712 bool dcn31_clk_src_construct( 1713 struct dce110_clk_src *clk_src, 1714 struct dc_context *ctx, 1715 struct dc_bios *bios, 1716 enum clock_source_id id, 1717 const struct dce110_clk_src_regs *regs, 1718 const struct dce110_clk_src_shift *cs_shift, 1719 const struct dce110_clk_src_mask *cs_mask) 1720 { 1721 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1722 1723 clk_src->base.funcs = &dcn31_clk_src_funcs; 1724 1725 return ret; 1726 } 1727 #endif 1728 1729 #if defined(CONFIG_DRM_AMD_DC_DCN) 1730 bool dcn301_clk_src_construct( 1731 struct dce110_clk_src *clk_src, 1732 struct dc_context *ctx, 1733 struct dc_bios *bios, 1734 enum clock_source_id id, 1735 const struct dce110_clk_src_regs *regs, 1736 const struct dce110_clk_src_shift *cs_shift, 1737 const struct dce110_clk_src_mask *cs_mask) 1738 { 1739 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1740 1741 clk_src->base.funcs = &dcn3_clk_src_funcs; 1742 1743 return ret; 1744 } 1745 #endif 1746