1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 struct abm_save_restore; 48 49 /* forward declaration */ 50 struct aux_payload; 51 struct set_config_cmd_payload; 52 struct dmub_notification; 53 54 #define DC_VER "3.2.265" 55 56 #define MAX_SURFACES 3 57 #define MAX_PLANES 6 58 #define MAX_STREAMS 6 59 #define MIN_VIEWPORT_SIZE 12 60 #define MAX_NUM_EDP 2 61 62 /* Display Core Interfaces */ 63 struct dc_versions { 64 const char *dc_ver; 65 struct dmcu_version dmcu_version; 66 }; 67 68 enum dp_protocol_version { 69 DP_VERSION_1_4 = 0, 70 DP_VERSION_2_1, 71 DP_VERSION_UNKNOWN, 72 }; 73 74 enum dc_plane_type { 75 DC_PLANE_TYPE_INVALID, 76 DC_PLANE_TYPE_DCE_RGB, 77 DC_PLANE_TYPE_DCE_UNDERLAY, 78 DC_PLANE_TYPE_DCN_UNIVERSAL, 79 }; 80 81 // Sizes defined as multiples of 64KB 82 enum det_size { 83 DET_SIZE_DEFAULT = 0, 84 DET_SIZE_192KB = 3, 85 DET_SIZE_256KB = 4, 86 DET_SIZE_320KB = 5, 87 DET_SIZE_384KB = 6 88 }; 89 90 91 struct dc_plane_cap { 92 enum dc_plane_type type; 93 uint32_t per_pixel_alpha : 1; 94 struct { 95 uint32_t argb8888 : 1; 96 uint32_t nv12 : 1; 97 uint32_t fp16 : 1; 98 uint32_t p010 : 1; 99 uint32_t ayuv : 1; 100 } pixel_format_support; 101 // max upscaling factor x1000 102 // upscaling factors are always >= 1 103 // for example, 1080p -> 8K is 4.0, or 4000 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_upscale_factor; 109 // max downscale factor x1000 110 // downscale factors are always <= 1 111 // for example, 8K -> 1080p is 0.25, or 250 raw value 112 struct { 113 uint32_t argb8888; 114 uint32_t nv12; 115 uint32_t fp16; 116 } max_downscale_factor; 117 // minimal width/height 118 uint32_t min_width; 119 uint32_t min_height; 120 }; 121 122 /** 123 * DOC: color-management-caps 124 * 125 * **Color management caps (DPP and MPC)** 126 * 127 * Modules/color calculates various color operations which are translated to 128 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 129 * DCN1, every new generation comes with fairly major differences in color 130 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 131 * decide mapping to HW block based on logical capabilities. 132 */ 133 134 /** 135 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 136 * @srgb: RGB color space transfer func 137 * @bt2020: BT.2020 transfer func 138 * @gamma2_2: standard gamma 139 * @pq: perceptual quantizer transfer function 140 * @hlg: hybrid log–gamma transfer function 141 */ 142 struct rom_curve_caps { 143 uint16_t srgb : 1; 144 uint16_t bt2020 : 1; 145 uint16_t gamma2_2 : 1; 146 uint16_t pq : 1; 147 uint16_t hlg : 1; 148 }; 149 150 /** 151 * struct dpp_color_caps - color pipeline capabilities for display pipe and 152 * plane blocks 153 * 154 * @dcn_arch: all DCE generations treated the same 155 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 156 * just plain 256-entry lookup 157 * @icsc: input color space conversion 158 * @dgam_ram: programmable degamma LUT 159 * @post_csc: post color space conversion, before gamut remap 160 * @gamma_corr: degamma correction 161 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 162 * with MPC by setting mpc:shared_3d_lut flag 163 * @ogam_ram: programmable out/blend gamma LUT 164 * @ocsc: output color space conversion 165 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 166 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 167 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 168 * 169 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 170 */ 171 struct dpp_color_caps { 172 uint16_t dcn_arch : 1; 173 uint16_t input_lut_shared : 1; 174 uint16_t icsc : 1; 175 uint16_t dgam_ram : 1; 176 uint16_t post_csc : 1; 177 uint16_t gamma_corr : 1; 178 uint16_t hw_3d_lut : 1; 179 uint16_t ogam_ram : 1; 180 uint16_t ocsc : 1; 181 uint16_t dgam_rom_for_yuv : 1; 182 struct rom_curve_caps dgam_rom_caps; 183 struct rom_curve_caps ogam_rom_caps; 184 }; 185 186 /** 187 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 188 * plane combined blocks 189 * 190 * @gamut_remap: color transformation matrix 191 * @ogam_ram: programmable out gamma LUT 192 * @ocsc: output color space conversion matrix 193 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 194 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 195 * instance 196 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 197 */ 198 struct mpc_color_caps { 199 uint16_t gamut_remap : 1; 200 uint16_t ogam_ram : 1; 201 uint16_t ocsc : 1; 202 uint16_t num_3dluts : 3; 203 uint16_t shared_3d_lut:1; 204 struct rom_curve_caps ogam_rom_caps; 205 }; 206 207 /** 208 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 209 * @dpp: color pipes caps for DPP 210 * @mpc: color pipes caps for MPC 211 */ 212 struct dc_color_caps { 213 struct dpp_color_caps dpp; 214 struct mpc_color_caps mpc; 215 }; 216 217 struct dc_dmub_caps { 218 bool psr; 219 bool mclk_sw; 220 bool subvp_psr; 221 bool gecc_enable; 222 }; 223 224 struct dc_caps { 225 uint32_t max_streams; 226 uint32_t max_links; 227 uint32_t max_audios; 228 uint32_t max_slave_planes; 229 uint32_t max_slave_yuv_planes; 230 uint32_t max_slave_rgb_planes; 231 uint32_t max_planes; 232 uint32_t max_downscale_ratio; 233 uint32_t i2c_speed_in_khz; 234 uint32_t i2c_speed_in_khz_hdcp; 235 uint32_t dmdata_alloc_size; 236 unsigned int max_cursor_size; 237 unsigned int max_video_width; 238 /* 239 * max video plane width that can be safely assumed to be always 240 * supported by single DPP pipe. 241 */ 242 unsigned int max_optimizable_video_width; 243 unsigned int min_horizontal_blanking_period; 244 int linear_pitch_alignment; 245 bool dcc_const_color; 246 bool dynamic_audio; 247 bool is_apu; 248 bool dual_link_dvi; 249 bool post_blend_color_processing; 250 bool force_dp_tps4_for_cp2520; 251 bool disable_dp_clk_share; 252 bool psp_setup_panel_mode; 253 bool extended_aux_timeout_support; 254 bool dmcub_support; 255 bool zstate_support; 256 bool ips_support; 257 uint32_t num_of_internal_disp; 258 enum dp_protocol_version max_dp_protocol_version; 259 unsigned int mall_size_per_mem_channel; 260 unsigned int mall_size_total; 261 unsigned int cursor_cache_size; 262 struct dc_plane_cap planes[MAX_PLANES]; 263 struct dc_color_caps color; 264 struct dc_dmub_caps dmub_caps; 265 bool dp_hpo; 266 bool dp_hdmi21_pcon_support; 267 bool edp_dsc_support; 268 bool vbios_lttpr_aware; 269 bool vbios_lttpr_enable; 270 uint32_t max_otg_num; 271 uint32_t max_cab_allocation_bytes; 272 uint32_t cache_line_size; 273 uint32_t cache_num_ways; 274 uint16_t subvp_fw_processing_delay_us; 275 uint8_t subvp_drr_max_vblank_margin_us; 276 uint16_t subvp_prefetch_end_to_mall_start_us; 277 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 278 uint16_t subvp_pstate_allow_width_us; 279 uint16_t subvp_vertical_int_margin_us; 280 bool seamless_odm; 281 uint32_t max_v_total; 282 uint32_t max_disp_clock_khz_at_vmin; 283 uint8_t subvp_drr_vblank_start_margin_us; 284 }; 285 286 struct dc_bug_wa { 287 bool no_connect_phy_config; 288 bool dedcn20_305_wa; 289 bool skip_clock_update; 290 bool lt_early_cr_pattern; 291 struct { 292 uint8_t uclk : 1; 293 uint8_t fclk : 1; 294 uint8_t dcfclk : 1; 295 uint8_t dcfclk_ds: 1; 296 } clock_update_disable_mask; 297 }; 298 struct dc_dcc_surface_param { 299 struct dc_size surface_size; 300 enum surface_pixel_format format; 301 enum swizzle_mode_values swizzle_mode; 302 enum dc_scan_direction scan; 303 }; 304 305 struct dc_dcc_setting { 306 unsigned int max_compressed_blk_size; 307 unsigned int max_uncompressed_blk_size; 308 bool independent_64b_blks; 309 //These bitfields to be used starting with DCN 310 struct { 311 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 312 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 313 uint32_t dcc_256_128_128 : 1; //available starting with DCN 314 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 315 } dcc_controls; 316 }; 317 318 struct dc_surface_dcc_cap { 319 union { 320 struct { 321 struct dc_dcc_setting rgb; 322 } grph; 323 324 struct { 325 struct dc_dcc_setting luma; 326 struct dc_dcc_setting chroma; 327 } video; 328 }; 329 330 bool capable; 331 bool const_color_support; 332 }; 333 334 struct dc_static_screen_params { 335 struct { 336 bool force_trigger; 337 bool cursor_update; 338 bool surface_update; 339 bool overlay_update; 340 } triggers; 341 unsigned int num_frames; 342 }; 343 344 345 /* Surface update type is used by dc_update_surfaces_and_stream 346 * The update type is determined at the very beginning of the function based 347 * on parameters passed in and decides how much programming (or updating) is 348 * going to be done during the call. 349 * 350 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 351 * logical calculations or hardware register programming. This update MUST be 352 * ISR safe on windows. Currently fast update will only be used to flip surface 353 * address. 354 * 355 * UPDATE_TYPE_MED is used for slower updates which require significant hw 356 * re-programming however do not affect bandwidth consumption or clock 357 * requirements. At present, this is the level at which front end updates 358 * that do not require us to run bw_calcs happen. These are in/out transfer func 359 * updates, viewport offset changes, recout size changes and pixel depth changes. 360 * This update can be done at ISR, but we want to minimize how often this happens. 361 * 362 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 363 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 364 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 365 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 366 * a full update. This cannot be done at ISR level and should be a rare event. 367 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 368 * underscan we don't expect to see this call at all. 369 */ 370 371 enum surface_update_type { 372 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 373 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 374 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 375 }; 376 377 /* Forward declaration*/ 378 struct dc; 379 struct dc_plane_state; 380 struct dc_state; 381 382 383 struct dc_cap_funcs { 384 bool (*get_dcc_compression_cap)(const struct dc *dc, 385 const struct dc_dcc_surface_param *input, 386 struct dc_surface_dcc_cap *output); 387 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 388 }; 389 390 struct link_training_settings; 391 392 union allow_lttpr_non_transparent_mode { 393 struct { 394 bool DP1_4A : 1; 395 bool DP2_0 : 1; 396 } bits; 397 unsigned char raw; 398 }; 399 400 /* Structure to hold configuration flags set by dm at dc creation. */ 401 struct dc_config { 402 bool gpu_vm_support; 403 bool disable_disp_pll_sharing; 404 bool fbc_support; 405 bool disable_fractional_pwm; 406 bool allow_seamless_boot_optimization; 407 bool seamless_boot_edp_requested; 408 bool edp_not_connected; 409 bool edp_no_power_sequencing; 410 bool force_enum_edp; 411 bool forced_clocks; 412 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 413 bool multi_mon_pp_mclk_switch; 414 bool disable_dmcu; 415 bool enable_4to1MPC; 416 bool enable_windowed_mpo_odm; 417 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 418 uint32_t allow_edp_hotplug_detection; 419 bool clamp_min_dcfclk; 420 uint64_t vblank_alignment_dto_params; 421 uint8_t vblank_alignment_max_frame_time_diff; 422 bool is_asymmetric_memory; 423 bool is_single_rank_dimm; 424 bool is_vmin_only_asic; 425 bool use_pipe_ctx_sync_logic; 426 bool ignore_dpref_ss; 427 bool enable_mipi_converter_optimization; 428 bool use_default_clock_table; 429 bool force_bios_enable_lttpr; 430 uint8_t force_bios_fixed_vs; 431 int sdpif_request_limit_words_per_umc; 432 bool use_old_fixed_vs_sequence; 433 bool dc_mode_clk_limit_support; 434 bool EnableMinDispClkODM; 435 bool enable_auto_dpm_test_logs; 436 unsigned int disable_ips; 437 }; 438 439 enum visual_confirm { 440 VISUAL_CONFIRM_DISABLE = 0, 441 VISUAL_CONFIRM_SURFACE = 1, 442 VISUAL_CONFIRM_HDR = 2, 443 VISUAL_CONFIRM_MPCTREE = 4, 444 VISUAL_CONFIRM_PSR = 5, 445 VISUAL_CONFIRM_SWAPCHAIN = 6, 446 VISUAL_CONFIRM_FAMS = 7, 447 VISUAL_CONFIRM_SWIZZLE = 9, 448 VISUAL_CONFIRM_REPLAY = 12, 449 VISUAL_CONFIRM_SUBVP = 14, 450 VISUAL_CONFIRM_MCLK_SWITCH = 16, 451 }; 452 453 enum dc_psr_power_opts { 454 psr_power_opt_invalid = 0x0, 455 psr_power_opt_smu_opt_static_screen = 0x1, 456 psr_power_opt_z10_static_screen = 0x10, 457 psr_power_opt_ds_disable_allow = 0x100, 458 }; 459 460 enum dml_hostvm_override_opts { 461 DML_HOSTVM_NO_OVERRIDE = 0x0, 462 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 463 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 464 }; 465 466 enum dcc_option { 467 DCC_ENABLE = 0, 468 DCC_DISABLE = 1, 469 DCC_HALF_REQ_DISALBE = 2, 470 }; 471 472 /** 473 * enum pipe_split_policy - Pipe split strategy supported by DCN 474 * 475 * This enum is used to define the pipe split policy supported by DCN. By 476 * default, DC favors MPC_SPLIT_DYNAMIC. 477 */ 478 enum pipe_split_policy { 479 /** 480 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 481 * pipe in order to bring the best trade-off between performance and 482 * power consumption. This is the recommended option. 483 */ 484 MPC_SPLIT_DYNAMIC = 0, 485 486 /** 487 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 488 * try any sort of split optimization. 489 */ 490 MPC_SPLIT_AVOID = 1, 491 492 /** 493 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 494 * optimize the pipe utilization when using a single display; if the 495 * user connects to a second display, DC will avoid pipe split. 496 */ 497 MPC_SPLIT_AVOID_MULT_DISP = 2, 498 }; 499 500 enum wm_report_mode { 501 WM_REPORT_DEFAULT = 0, 502 WM_REPORT_OVERRIDE = 1, 503 }; 504 enum dtm_pstate{ 505 dtm_level_p0 = 0,/*highest voltage*/ 506 dtm_level_p1, 507 dtm_level_p2, 508 dtm_level_p3, 509 dtm_level_p4,/*when active_display_count = 0*/ 510 }; 511 512 enum dcn_pwr_state { 513 DCN_PWR_STATE_UNKNOWN = -1, 514 DCN_PWR_STATE_MISSION_MODE = 0, 515 DCN_PWR_STATE_LOW_POWER = 3, 516 }; 517 518 enum dcn_zstate_support_state { 519 DCN_ZSTATE_SUPPORT_UNKNOWN, 520 DCN_ZSTATE_SUPPORT_ALLOW, 521 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 522 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 523 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 524 DCN_ZSTATE_SUPPORT_DISALLOW, 525 }; 526 527 /* 528 * struct dc_clocks - DC pipe clocks 529 * 530 * For any clocks that may differ per pipe only the max is stored in this 531 * structure 532 */ 533 struct dc_clocks { 534 int dispclk_khz; 535 int actual_dispclk_khz; 536 int dppclk_khz; 537 int actual_dppclk_khz; 538 int disp_dpp_voltage_level_khz; 539 int dcfclk_khz; 540 int socclk_khz; 541 int dcfclk_deep_sleep_khz; 542 int fclk_khz; 543 int phyclk_khz; 544 int dramclk_khz; 545 bool p_state_change_support; 546 enum dcn_zstate_support_state zstate_support; 547 bool dtbclk_en; 548 int ref_dtbclk_khz; 549 bool fclk_p_state_change_support; 550 enum dcn_pwr_state pwr_state; 551 /* 552 * Elements below are not compared for the purposes of 553 * optimization required 554 */ 555 bool prev_p_state_change_support; 556 bool fclk_prev_p_state_change_support; 557 int num_ways; 558 559 /* 560 * @fw_based_mclk_switching 561 * 562 * DC has a mechanism that leverage the variable refresh rate to switch 563 * memory clock in cases that we have a large latency to achieve the 564 * memory clock change and a short vblank window. DC has some 565 * requirements to enable this feature, and this field describes if the 566 * system support or not such a feature. 567 */ 568 bool fw_based_mclk_switching; 569 bool fw_based_mclk_switching_shut_down; 570 int prev_num_ways; 571 enum dtm_pstate dtm_level; 572 int max_supported_dppclk_khz; 573 int max_supported_dispclk_khz; 574 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 575 int bw_dispclk_khz; 576 }; 577 578 struct dc_bw_validation_profile { 579 bool enable; 580 581 unsigned long long total_ticks; 582 unsigned long long voltage_level_ticks; 583 unsigned long long watermark_ticks; 584 unsigned long long rq_dlg_ticks; 585 586 unsigned long long total_count; 587 unsigned long long skip_fast_count; 588 unsigned long long skip_pass_count; 589 unsigned long long skip_fail_count; 590 }; 591 592 #define BW_VAL_TRACE_SETUP() \ 593 unsigned long long end_tick = 0; \ 594 unsigned long long voltage_level_tick = 0; \ 595 unsigned long long watermark_tick = 0; \ 596 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 597 dm_get_timestamp(dc->ctx) : 0 598 599 #define BW_VAL_TRACE_COUNT() \ 600 if (dc->debug.bw_val_profile.enable) \ 601 dc->debug.bw_val_profile.total_count++ 602 603 #define BW_VAL_TRACE_SKIP(status) \ 604 if (dc->debug.bw_val_profile.enable) { \ 605 if (!voltage_level_tick) \ 606 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 607 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 608 } 609 610 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 611 if (dc->debug.bw_val_profile.enable) \ 612 voltage_level_tick = dm_get_timestamp(dc->ctx) 613 614 #define BW_VAL_TRACE_END_WATERMARKS() \ 615 if (dc->debug.bw_val_profile.enable) \ 616 watermark_tick = dm_get_timestamp(dc->ctx) 617 618 #define BW_VAL_TRACE_FINISH() \ 619 if (dc->debug.bw_val_profile.enable) { \ 620 end_tick = dm_get_timestamp(dc->ctx); \ 621 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 622 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 623 if (watermark_tick) { \ 624 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 625 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 626 } \ 627 } 628 629 union mem_low_power_enable_options { 630 struct { 631 bool vga: 1; 632 bool i2c: 1; 633 bool dmcu: 1; 634 bool dscl: 1; 635 bool cm: 1; 636 bool mpc: 1; 637 bool optc: 1; 638 bool vpg: 1; 639 bool afmt: 1; 640 } bits; 641 uint32_t u32All; 642 }; 643 644 union root_clock_optimization_options { 645 struct { 646 bool dpp: 1; 647 bool dsc: 1; 648 bool hdmistream: 1; 649 bool hdmichar: 1; 650 bool dpstream: 1; 651 bool symclk32_se: 1; 652 bool symclk32_le: 1; 653 bool symclk_fe: 1; 654 bool physymclk: 1; 655 bool dpiasymclk: 1; 656 uint32_t reserved: 22; 657 } bits; 658 uint32_t u32All; 659 }; 660 661 union fine_grain_clock_gating_enable_options { 662 struct { 663 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 664 bool dchub : 1; /* Display controller hub */ 665 bool dchubbub : 1; 666 bool dpp : 1; /* Display pipes and planes */ 667 bool opp : 1; /* Output pixel processing */ 668 bool optc : 1; /* Output pipe timing combiner */ 669 bool dio : 1; /* Display output */ 670 bool dwb : 1; /* Display writeback */ 671 bool mmhubbub : 1; /* Multimedia hub */ 672 bool dmu : 1; /* Display core management unit */ 673 bool az : 1; /* Azalia */ 674 bool dchvm : 1; 675 bool dsc : 1; /* Display stream compression */ 676 677 uint32_t reserved : 19; 678 } bits; 679 uint32_t u32All; 680 }; 681 682 enum pg_hw_pipe_resources { 683 PG_HUBP = 0, 684 PG_DPP, 685 PG_DSC, 686 PG_MPCC, 687 PG_OPP, 688 PG_OPTC, 689 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 690 }; 691 692 enum pg_hw_resources { 693 PG_DCCG = 0, 694 PG_DCIO, 695 PG_DIO, 696 PG_DCHUBBUB, 697 PG_DCHVM, 698 PG_DWB, 699 PG_HPO, 700 PG_HW_RESOURCES_NUM_ELEMENT 701 }; 702 703 struct pg_block_update { 704 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 705 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 706 }; 707 708 union dpia_debug_options { 709 struct { 710 uint32_t disable_dpia:1; /* bit 0 */ 711 uint32_t force_non_lttpr:1; /* bit 1 */ 712 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 713 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 714 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 715 uint32_t reserved:27; 716 } bits; 717 uint32_t raw; 718 }; 719 720 /* AUX wake work around options 721 * 0: enable/disable work around 722 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 723 * 15-2: reserved 724 * 31-16: timeout in ms 725 */ 726 union aux_wake_wa_options { 727 struct { 728 uint32_t enable_wa : 1; 729 uint32_t use_default_timeout : 1; 730 uint32_t rsvd: 14; 731 uint32_t timeout_ms : 16; 732 } bits; 733 uint32_t raw; 734 }; 735 736 struct dc_debug_data { 737 uint32_t ltFailCount; 738 uint32_t i2cErrorCount; 739 uint32_t auxErrorCount; 740 }; 741 742 struct dc_phy_addr_space_config { 743 struct { 744 uint64_t start_addr; 745 uint64_t end_addr; 746 uint64_t fb_top; 747 uint64_t fb_offset; 748 uint64_t fb_base; 749 uint64_t agp_top; 750 uint64_t agp_bot; 751 uint64_t agp_base; 752 } system_aperture; 753 754 struct { 755 uint64_t page_table_start_addr; 756 uint64_t page_table_end_addr; 757 uint64_t page_table_base_addr; 758 bool base_addr_is_mc_addr; 759 } gart_config; 760 761 bool valid; 762 bool is_hvm_enabled; 763 uint64_t page_table_default_page_addr; 764 }; 765 766 struct dc_virtual_addr_space_config { 767 uint64_t page_table_base_addr; 768 uint64_t page_table_start_addr; 769 uint64_t page_table_end_addr; 770 uint32_t page_table_block_size_in_bytes; 771 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 772 }; 773 774 struct dc_bounding_box_overrides { 775 int sr_exit_time_ns; 776 int sr_enter_plus_exit_time_ns; 777 int sr_exit_z8_time_ns; 778 int sr_enter_plus_exit_z8_time_ns; 779 int urgent_latency_ns; 780 int percent_of_ideal_drambw; 781 int dram_clock_change_latency_ns; 782 int dummy_clock_change_latency_ns; 783 int fclk_clock_change_latency_ns; 784 /* This forces a hard min on the DCFCLK we use 785 * for DML. Unlike the debug option for forcing 786 * DCFCLK, this override affects watermark calculations 787 */ 788 int min_dcfclk_mhz; 789 }; 790 791 struct dc_state; 792 struct resource_pool; 793 struct dce_hwseq; 794 struct link_service; 795 796 /* 797 * struct dc_debug_options - DC debug struct 798 * 799 * This struct provides a simple mechanism for developers to change some 800 * configurations, enable/disable features, and activate extra debug options. 801 * This can be very handy to narrow down whether some specific feature is 802 * causing an issue or not. 803 */ 804 struct dc_debug_options { 805 bool native422_support; 806 bool disable_dsc; 807 enum visual_confirm visual_confirm; 808 int visual_confirm_rect_height; 809 810 bool sanity_checks; 811 bool max_disp_clk; 812 bool surface_trace; 813 bool timing_trace; 814 bool clock_trace; 815 bool validation_trace; 816 bool bandwidth_calcs_trace; 817 int max_downscale_src_width; 818 819 /* stutter efficiency related */ 820 bool disable_stutter; 821 bool use_max_lb; 822 enum dcc_option disable_dcc; 823 824 /* 825 * @pipe_split_policy: Define which pipe split policy is used by the 826 * display core. 827 */ 828 enum pipe_split_policy pipe_split_policy; 829 bool force_single_disp_pipe_split; 830 bool voltage_align_fclk; 831 bool disable_min_fclk; 832 833 bool disable_dfs_bypass; 834 bool disable_dpp_power_gate; 835 bool disable_hubp_power_gate; 836 bool disable_dsc_power_gate; 837 bool disable_optc_power_gate; 838 bool disable_hpo_power_gate; 839 int dsc_min_slice_height_override; 840 int dsc_bpp_increment_div; 841 bool disable_pplib_wm_range; 842 enum wm_report_mode pplib_wm_report_mode; 843 unsigned int min_disp_clk_khz; 844 unsigned int min_dpp_clk_khz; 845 unsigned int min_dram_clk_khz; 846 int sr_exit_time_dpm0_ns; 847 int sr_enter_plus_exit_time_dpm0_ns; 848 int sr_exit_time_ns; 849 int sr_enter_plus_exit_time_ns; 850 int sr_exit_z8_time_ns; 851 int sr_enter_plus_exit_z8_time_ns; 852 int urgent_latency_ns; 853 uint32_t underflow_assert_delay_us; 854 int percent_of_ideal_drambw; 855 int dram_clock_change_latency_ns; 856 bool optimized_watermark; 857 int always_scale; 858 bool disable_pplib_clock_request; 859 bool disable_clock_gate; 860 bool disable_mem_low_power; 861 bool pstate_enabled; 862 bool disable_dmcu; 863 bool force_abm_enable; 864 bool disable_stereo_support; 865 bool vsr_support; 866 bool performance_trace; 867 bool az_endpoint_mute_only; 868 bool always_use_regamma; 869 bool recovery_enabled; 870 bool avoid_vbios_exec_table; 871 bool scl_reset_length10; 872 bool hdmi20_disable; 873 bool skip_detection_link_training; 874 uint32_t edid_read_retry_times; 875 unsigned int force_odm_combine; //bit vector based on otg inst 876 unsigned int seamless_boot_odm_combine; 877 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 878 int minimum_z8_residency_time; 879 int minimum_z10_residency_time; 880 bool disable_z9_mpc; 881 unsigned int force_fclk_khz; 882 bool enable_tri_buf; 883 bool dmub_offload_enabled; 884 bool dmcub_emulation; 885 bool disable_idle_power_optimizations; 886 unsigned int mall_size_override; 887 unsigned int mall_additional_timer_percent; 888 bool mall_error_as_fatal; 889 bool dmub_command_table; /* for testing only */ 890 struct dc_bw_validation_profile bw_val_profile; 891 bool disable_fec; 892 bool disable_48mhz_pwrdwn; 893 /* This forces a hard min on the DCFCLK requested to SMU/PP 894 * watermarks are not affected. 895 */ 896 unsigned int force_min_dcfclk_mhz; 897 int dwb_fi_phase; 898 bool disable_timing_sync; 899 bool cm_in_bypass; 900 int force_clock_mode;/*every mode change.*/ 901 902 bool disable_dram_clock_change_vactive_support; 903 bool validate_dml_output; 904 bool enable_dmcub_surface_flip; 905 bool usbc_combo_phy_reset_wa; 906 bool enable_dram_clock_change_one_display_vactive; 907 /* TODO - remove once tested */ 908 bool legacy_dp2_lt; 909 bool set_mst_en_for_sst; 910 bool disable_uhbr; 911 bool force_dp2_lt_fallback_method; 912 bool ignore_cable_id; 913 union mem_low_power_enable_options enable_mem_low_power; 914 union root_clock_optimization_options root_clock_optimization; 915 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 916 bool hpo_optimization; 917 bool force_vblank_alignment; 918 919 /* Enable dmub aux for legacy ddc */ 920 bool enable_dmub_aux_for_legacy_ddc; 921 bool disable_fams; 922 bool disable_fams_gaming; 923 /* FEC/PSR1 sequence enable delay in 100us */ 924 uint8_t fec_enable_delay_in100us; 925 bool enable_driver_sequence_debug; 926 enum det_size crb_alloc_policy; 927 int crb_alloc_policy_min_disp_count; 928 bool disable_z10; 929 bool enable_z9_disable_interface; 930 bool psr_skip_crtc_disable; 931 union dpia_debug_options dpia_debug; 932 bool disable_fixed_vs_aux_timeout_wa; 933 uint32_t fixed_vs_aux_delay_config_wa; 934 bool force_disable_subvp; 935 bool force_subvp_mclk_switch; 936 bool allow_sw_cursor_fallback; 937 unsigned int force_subvp_num_ways; 938 unsigned int force_mall_ss_num_ways; 939 bool alloc_extra_way_for_cursor; 940 uint32_t subvp_extra_lines; 941 bool force_usr_allow; 942 /* uses value at boot and disables switch */ 943 bool disable_dtb_ref_clk_switch; 944 bool extended_blank_optimization; 945 union aux_wake_wa_options aux_wake_wa; 946 uint32_t mst_start_top_delay; 947 uint8_t psr_power_use_phy_fsm; 948 enum dml_hostvm_override_opts dml_hostvm_override; 949 bool dml_disallow_alternate_prefetch_modes; 950 bool use_legacy_soc_bb_mechanism; 951 bool exit_idle_opt_for_cursor_updates; 952 bool using_dml2; 953 bool enable_single_display_2to1_odm_policy; 954 bool enable_double_buffered_dsc_pg_support; 955 bool enable_dp_dig_pixel_rate_div_policy; 956 enum lttpr_mode lttpr_mode_override; 957 unsigned int dsc_delay_factor_wa_x1000; 958 unsigned int min_prefetch_in_strobe_ns; 959 bool disable_unbounded_requesting; 960 bool dig_fifo_off_in_blank; 961 bool override_dispclk_programming; 962 bool otg_crc_db; 963 bool disallow_dispclk_dppclk_ds; 964 bool disable_fpo_optimizations; 965 bool support_eDP1_5; 966 uint32_t fpo_vactive_margin_us; 967 bool disable_fpo_vactive; 968 bool disable_boot_optimizations; 969 bool override_odm_optimization; 970 bool minimize_dispclk_using_odm; 971 bool disable_subvp_high_refresh; 972 bool disable_dp_plus_plus_wa; 973 uint32_t fpo_vactive_min_active_margin_us; 974 uint32_t fpo_vactive_max_blank_us; 975 bool enable_hpo_pg_support; 976 bool enable_legacy_fast_update; 977 bool disable_dc_mode_overwrite; 978 bool replay_skip_crtc_disabled; 979 bool ignore_pg;/*do nothing, let pmfw control it*/ 980 bool psp_disabled_wa; 981 unsigned int ips2_eval_delay_us; 982 unsigned int ips2_entry_delay_us; 983 bool disable_timeout; 984 bool disable_extblankadj; 985 unsigned int static_screen_wait_frames; 986 }; 987 988 struct gpu_info_soc_bounding_box_v1_0; 989 990 /* Generic structure that can be used to query properties of DC. More fields 991 * can be added as required. 992 */ 993 struct dc_current_properties { 994 unsigned int cursor_size_limit; 995 }; 996 997 struct dc { 998 struct dc_debug_options debug; 999 struct dc_versions versions; 1000 struct dc_caps caps; 1001 struct dc_cap_funcs cap_funcs; 1002 struct dc_config config; 1003 struct dc_bounding_box_overrides bb_overrides; 1004 struct dc_bug_wa work_arounds; 1005 struct dc_context *ctx; 1006 struct dc_phy_addr_space_config vm_pa_config; 1007 1008 uint8_t link_count; 1009 struct dc_link *links[MAX_PIPES * 2]; 1010 struct link_service *link_srv; 1011 1012 struct dc_state *current_state; 1013 struct resource_pool *res_pool; 1014 1015 struct clk_mgr *clk_mgr; 1016 1017 /* Display Engine Clock levels */ 1018 struct dm_pp_clock_levels sclk_lvls; 1019 1020 /* Inputs into BW and WM calculations. */ 1021 struct bw_calcs_dceip *bw_dceip; 1022 struct bw_calcs_vbios *bw_vbios; 1023 struct dcn_soc_bounding_box *dcn_soc; 1024 struct dcn_ip_params *dcn_ip; 1025 struct display_mode_lib dml; 1026 1027 /* HW functions */ 1028 struct hw_sequencer_funcs hwss; 1029 struct dce_hwseq *hwseq; 1030 1031 /* Require to optimize clocks and bandwidth for added/removed planes */ 1032 bool optimized_required; 1033 bool idle_optimizations_allowed; 1034 bool enable_c20_dtm_b0; 1035 1036 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1037 1038 /* FBC compressor */ 1039 struct compressor *fbc_compressor; 1040 1041 struct dc_debug_data debug_data; 1042 struct dpcd_vendor_signature vendor_signature; 1043 1044 const char *build_id; 1045 struct vm_helper *vm_helper; 1046 1047 uint32_t *dcn_reg_offsets; 1048 uint32_t *nbio_reg_offsets; 1049 uint32_t *clk_reg_offsets; 1050 1051 /* Scratch memory */ 1052 struct { 1053 struct { 1054 /* 1055 * For matching clock_limits table in driver with table 1056 * from PMFW. 1057 */ 1058 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1059 } update_bw_bounding_box; 1060 } scratch; 1061 1062 struct dml2_configuration_options dml2_options; 1063 }; 1064 1065 enum frame_buffer_mode { 1066 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1067 FRAME_BUFFER_MODE_ZFB_ONLY, 1068 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1069 } ; 1070 1071 struct dchub_init_data { 1072 int64_t zfb_phys_addr_base; 1073 int64_t zfb_mc_base_addr; 1074 uint64_t zfb_size_in_byte; 1075 enum frame_buffer_mode fb_mode; 1076 bool dchub_initialzied; 1077 bool dchub_info_valid; 1078 }; 1079 1080 struct dc_init_data { 1081 struct hw_asic_id asic_id; 1082 void *driver; /* ctx */ 1083 struct cgs_device *cgs_device; 1084 struct dc_bounding_box_overrides bb_overrides; 1085 1086 int num_virtual_links; 1087 /* 1088 * If 'vbios_override' not NULL, it will be called instead 1089 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1090 */ 1091 struct dc_bios *vbios_override; 1092 enum dce_environment dce_environment; 1093 1094 struct dmub_offload_funcs *dmub_if; 1095 struct dc_reg_helper_state *dmub_offload; 1096 1097 struct dc_config flags; 1098 uint64_t log_mask; 1099 1100 struct dpcd_vendor_signature vendor_signature; 1101 bool force_smu_not_present; 1102 /* 1103 * IP offset for run time initializaion of register addresses 1104 * 1105 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1106 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1107 * before them. 1108 */ 1109 uint32_t *dcn_reg_offsets; 1110 uint32_t *nbio_reg_offsets; 1111 uint32_t *clk_reg_offsets; 1112 }; 1113 1114 struct dc_callback_init { 1115 struct cp_psp cp_psp; 1116 }; 1117 1118 struct dc *dc_create(const struct dc_init_data *init_params); 1119 void dc_hardware_init(struct dc *dc); 1120 1121 int dc_get_vmid_use_vector(struct dc *dc); 1122 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1123 /* Returns the number of vmids supported */ 1124 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1125 void dc_init_callbacks(struct dc *dc, 1126 const struct dc_callback_init *init_params); 1127 void dc_deinit_callbacks(struct dc *dc); 1128 void dc_destroy(struct dc **dc); 1129 1130 /* Surface Interfaces */ 1131 1132 enum { 1133 TRANSFER_FUNC_POINTS = 1025 1134 }; 1135 1136 struct dc_hdr_static_metadata { 1137 /* display chromaticities and white point in units of 0.00001 */ 1138 unsigned int chromaticity_green_x; 1139 unsigned int chromaticity_green_y; 1140 unsigned int chromaticity_blue_x; 1141 unsigned int chromaticity_blue_y; 1142 unsigned int chromaticity_red_x; 1143 unsigned int chromaticity_red_y; 1144 unsigned int chromaticity_white_point_x; 1145 unsigned int chromaticity_white_point_y; 1146 1147 uint32_t min_luminance; 1148 uint32_t max_luminance; 1149 uint32_t maximum_content_light_level; 1150 uint32_t maximum_frame_average_light_level; 1151 }; 1152 1153 enum dc_transfer_func_type { 1154 TF_TYPE_PREDEFINED, 1155 TF_TYPE_DISTRIBUTED_POINTS, 1156 TF_TYPE_BYPASS, 1157 TF_TYPE_HWPWL 1158 }; 1159 1160 struct dc_transfer_func_distributed_points { 1161 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1162 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1163 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1164 1165 uint16_t end_exponent; 1166 uint16_t x_point_at_y1_red; 1167 uint16_t x_point_at_y1_green; 1168 uint16_t x_point_at_y1_blue; 1169 }; 1170 1171 enum dc_transfer_func_predefined { 1172 TRANSFER_FUNCTION_SRGB, 1173 TRANSFER_FUNCTION_BT709, 1174 TRANSFER_FUNCTION_PQ, 1175 TRANSFER_FUNCTION_LINEAR, 1176 TRANSFER_FUNCTION_UNITY, 1177 TRANSFER_FUNCTION_HLG, 1178 TRANSFER_FUNCTION_HLG12, 1179 TRANSFER_FUNCTION_GAMMA22, 1180 TRANSFER_FUNCTION_GAMMA24, 1181 TRANSFER_FUNCTION_GAMMA26 1182 }; 1183 1184 1185 struct dc_transfer_func { 1186 struct kref refcount; 1187 enum dc_transfer_func_type type; 1188 enum dc_transfer_func_predefined tf; 1189 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1190 uint32_t sdr_ref_white_level; 1191 union { 1192 struct pwl_params pwl; 1193 struct dc_transfer_func_distributed_points tf_pts; 1194 }; 1195 }; 1196 1197 1198 union dc_3dlut_state { 1199 struct { 1200 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1201 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1202 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1203 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1204 uint32_t mpc_rmu1_mux:4; 1205 uint32_t mpc_rmu2_mux:4; 1206 uint32_t reserved:15; 1207 } bits; 1208 uint32_t raw; 1209 }; 1210 1211 1212 struct dc_3dlut { 1213 struct kref refcount; 1214 struct tetrahedral_params lut_3d; 1215 struct fixed31_32 hdr_multiplier; 1216 union dc_3dlut_state state; 1217 }; 1218 /* 1219 * This structure is filled in by dc_surface_get_status and contains 1220 * the last requested address and the currently active address so the called 1221 * can determine if there are any outstanding flips 1222 */ 1223 struct dc_plane_status { 1224 struct dc_plane_address requested_address; 1225 struct dc_plane_address current_address; 1226 bool is_flip_pending; 1227 bool is_right_eye; 1228 }; 1229 1230 union surface_update_flags { 1231 1232 struct { 1233 uint32_t addr_update:1; 1234 /* Medium updates */ 1235 uint32_t dcc_change:1; 1236 uint32_t color_space_change:1; 1237 uint32_t horizontal_mirror_change:1; 1238 uint32_t per_pixel_alpha_change:1; 1239 uint32_t global_alpha_change:1; 1240 uint32_t hdr_mult:1; 1241 uint32_t rotation_change:1; 1242 uint32_t swizzle_change:1; 1243 uint32_t scaling_change:1; 1244 uint32_t position_change:1; 1245 uint32_t in_transfer_func_change:1; 1246 uint32_t input_csc_change:1; 1247 uint32_t coeff_reduction_change:1; 1248 uint32_t output_tf_change:1; 1249 uint32_t pixel_format_change:1; 1250 uint32_t plane_size_change:1; 1251 uint32_t gamut_remap_change:1; 1252 1253 /* Full updates */ 1254 uint32_t new_plane:1; 1255 uint32_t bpp_change:1; 1256 uint32_t gamma_change:1; 1257 uint32_t bandwidth_change:1; 1258 uint32_t clock_change:1; 1259 uint32_t stereo_format_change:1; 1260 uint32_t lut_3d:1; 1261 uint32_t tmz_changed:1; 1262 uint32_t full_update:1; 1263 } bits; 1264 1265 uint32_t raw; 1266 }; 1267 1268 struct dc_plane_state { 1269 struct dc_plane_address address; 1270 struct dc_plane_flip_time time; 1271 bool triplebuffer_flips; 1272 struct scaling_taps scaling_quality; 1273 struct rect src_rect; 1274 struct rect dst_rect; 1275 struct rect clip_rect; 1276 1277 struct plane_size plane_size; 1278 union dc_tiling_info tiling_info; 1279 1280 struct dc_plane_dcc_param dcc; 1281 1282 struct dc_gamma *gamma_correction; 1283 struct dc_transfer_func *in_transfer_func; 1284 struct dc_bias_and_scale *bias_and_scale; 1285 struct dc_csc_transform input_csc_color_matrix; 1286 struct fixed31_32 coeff_reduction_factor; 1287 struct fixed31_32 hdr_mult; 1288 struct colorspace_transform gamut_remap_matrix; 1289 1290 // TODO: No longer used, remove 1291 struct dc_hdr_static_metadata hdr_static_ctx; 1292 1293 enum dc_color_space color_space; 1294 1295 struct dc_3dlut *lut3d_func; 1296 struct dc_transfer_func *in_shaper_func; 1297 struct dc_transfer_func *blend_tf; 1298 1299 struct dc_transfer_func *gamcor_tf; 1300 enum surface_pixel_format format; 1301 enum dc_rotation_angle rotation; 1302 enum plane_stereo_format stereo_format; 1303 1304 bool is_tiling_rotated; 1305 bool per_pixel_alpha; 1306 bool pre_multiplied_alpha; 1307 bool global_alpha; 1308 int global_alpha_value; 1309 bool visible; 1310 bool flip_immediate; 1311 bool horizontal_mirror; 1312 int layer_index; 1313 1314 union surface_update_flags update_flags; 1315 bool flip_int_enabled; 1316 bool skip_manual_trigger; 1317 1318 /* private to DC core */ 1319 struct dc_plane_status status; 1320 struct dc_context *ctx; 1321 1322 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1323 bool force_full_update; 1324 1325 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1326 1327 /* private to dc_surface.c */ 1328 enum dc_irq_source irq_source; 1329 struct kref refcount; 1330 struct tg_color visual_confirm_color; 1331 1332 bool is_statically_allocated; 1333 }; 1334 1335 struct dc_plane_info { 1336 struct plane_size plane_size; 1337 union dc_tiling_info tiling_info; 1338 struct dc_plane_dcc_param dcc; 1339 enum surface_pixel_format format; 1340 enum dc_rotation_angle rotation; 1341 enum plane_stereo_format stereo_format; 1342 enum dc_color_space color_space; 1343 bool horizontal_mirror; 1344 bool visible; 1345 bool per_pixel_alpha; 1346 bool pre_multiplied_alpha; 1347 bool global_alpha; 1348 int global_alpha_value; 1349 bool input_csc_enabled; 1350 int layer_index; 1351 }; 1352 1353 struct dc_scaling_info { 1354 struct rect src_rect; 1355 struct rect dst_rect; 1356 struct rect clip_rect; 1357 struct scaling_taps scaling_quality; 1358 }; 1359 1360 struct dc_fast_update { 1361 const struct dc_flip_addrs *flip_addr; 1362 const struct dc_gamma *gamma; 1363 const struct colorspace_transform *gamut_remap_matrix; 1364 const struct dc_csc_transform *input_csc_color_matrix; 1365 const struct fixed31_32 *coeff_reduction_factor; 1366 struct dc_transfer_func *out_transfer_func; 1367 struct dc_csc_transform *output_csc_transform; 1368 }; 1369 1370 struct dc_surface_update { 1371 struct dc_plane_state *surface; 1372 1373 /* isr safe update parameters. null means no updates */ 1374 const struct dc_flip_addrs *flip_addr; 1375 const struct dc_plane_info *plane_info; 1376 const struct dc_scaling_info *scaling_info; 1377 struct fixed31_32 hdr_mult; 1378 /* following updates require alloc/sleep/spin that is not isr safe, 1379 * null means no updates 1380 */ 1381 const struct dc_gamma *gamma; 1382 const struct dc_transfer_func *in_transfer_func; 1383 1384 const struct dc_csc_transform *input_csc_color_matrix; 1385 const struct fixed31_32 *coeff_reduction_factor; 1386 const struct dc_transfer_func *func_shaper; 1387 const struct dc_3dlut *lut3d_func; 1388 const struct dc_transfer_func *blend_tf; 1389 const struct colorspace_transform *gamut_remap_matrix; 1390 }; 1391 1392 /* 1393 * Create a new surface with default parameters; 1394 */ 1395 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1396 void dc_gamma_release(struct dc_gamma **dc_gamma); 1397 struct dc_gamma *dc_create_gamma(void); 1398 1399 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1400 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1401 struct dc_transfer_func *dc_create_transfer_func(void); 1402 1403 struct dc_3dlut *dc_create_3dlut_func(void); 1404 void dc_3dlut_func_release(struct dc_3dlut *lut); 1405 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1406 1407 void dc_post_update_surfaces_to_stream( 1408 struct dc *dc); 1409 1410 #include "dc_stream.h" 1411 1412 /** 1413 * struct dc_validation_set - Struct to store surface/stream associations for validation 1414 */ 1415 struct dc_validation_set { 1416 /** 1417 * @stream: Stream state properties 1418 */ 1419 struct dc_stream_state *stream; 1420 1421 /** 1422 * @plane_states: Surface state 1423 */ 1424 struct dc_plane_state *plane_states[MAX_SURFACES]; 1425 1426 /** 1427 * @plane_count: Total of active planes 1428 */ 1429 uint8_t plane_count; 1430 }; 1431 1432 bool dc_validate_boot_timing(const struct dc *dc, 1433 const struct dc_sink *sink, 1434 struct dc_crtc_timing *crtc_timing); 1435 1436 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1437 1438 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1439 1440 enum dc_status dc_validate_with_context(struct dc *dc, 1441 const struct dc_validation_set set[], 1442 int set_count, 1443 struct dc_state *context, 1444 bool fast_validate); 1445 1446 bool dc_set_generic_gpio_for_stereo(bool enable, 1447 struct gpio_service *gpio_service); 1448 1449 /* 1450 * fast_validate: we return after determining if we can support the new state, 1451 * but before we populate the programming info 1452 */ 1453 enum dc_status dc_validate_global_state( 1454 struct dc *dc, 1455 struct dc_state *new_ctx, 1456 bool fast_validate); 1457 1458 bool dc_acquire_release_mpc_3dlut( 1459 struct dc *dc, bool acquire, 1460 struct dc_stream_state *stream, 1461 struct dc_3dlut **lut, 1462 struct dc_transfer_func **shaper); 1463 1464 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1465 void get_audio_check(struct audio_info *aud_modes, 1466 struct audio_check *aud_chk); 1467 1468 enum dc_status dc_commit_streams(struct dc *dc, 1469 struct dc_stream_state *streams[], 1470 uint8_t stream_count); 1471 1472 1473 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1474 struct dc_stream_state *stream, 1475 int mpcc_inst); 1476 1477 1478 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1479 1480 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1481 1482 /* The function returns minimum bandwidth required to drive a given timing 1483 * return - minimum required timing bandwidth in kbps. 1484 */ 1485 uint32_t dc_bandwidth_in_kbps_from_timing( 1486 const struct dc_crtc_timing *timing, 1487 const enum dc_link_encoding_format link_encoding); 1488 1489 /* Link Interfaces */ 1490 /* 1491 * A link contains one or more sinks and their connected status. 1492 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1493 */ 1494 struct dc_link { 1495 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1496 unsigned int sink_count; 1497 struct dc_sink *local_sink; 1498 unsigned int link_index; 1499 enum dc_connection_type type; 1500 enum signal_type connector_signal; 1501 enum dc_irq_source irq_source_hpd; 1502 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1503 1504 bool is_hpd_filter_disabled; 1505 bool dp_ss_off; 1506 1507 /** 1508 * @link_state_valid: 1509 * 1510 * If there is no link and local sink, this variable should be set to 1511 * false. Otherwise, it should be set to true; usually, the function 1512 * core_link_enable_stream sets this field to true. 1513 */ 1514 bool link_state_valid; 1515 bool aux_access_disabled; 1516 bool sync_lt_in_progress; 1517 bool skip_stream_reenable; 1518 bool is_internal_display; 1519 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1520 bool is_dig_mapping_flexible; 1521 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1522 bool is_hpd_pending; /* Indicates a new received hpd */ 1523 1524 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1525 * for every link training. This is incompatible with DP LL compliance automation, 1526 * which expects the same link settings to be used every retry on a link loss. 1527 * This flag is used to skip the fallback when link loss occurs during automation. 1528 */ 1529 bool skip_fallback_on_link_loss; 1530 1531 bool edp_sink_present; 1532 1533 struct dp_trace dp_trace; 1534 1535 /* caps is the same as reported_link_cap. link_traing use 1536 * reported_link_cap. Will clean up. TODO 1537 */ 1538 struct dc_link_settings reported_link_cap; 1539 struct dc_link_settings verified_link_cap; 1540 struct dc_link_settings cur_link_settings; 1541 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1542 struct dc_link_settings preferred_link_setting; 1543 /* preferred_training_settings are override values that 1544 * come from DM. DM is responsible for the memory 1545 * management of the override pointers. 1546 */ 1547 struct dc_link_training_overrides preferred_training_settings; 1548 struct dp_audio_test_data audio_test_data; 1549 1550 uint8_t ddc_hw_inst; 1551 1552 uint8_t hpd_src; 1553 1554 uint8_t link_enc_hw_inst; 1555 /* DIG link encoder ID. Used as index in link encoder resource pool. 1556 * For links with fixed mapping to DIG, this is not changed after dc_link 1557 * object creation. 1558 */ 1559 enum engine_id eng_id; 1560 enum engine_id dpia_preferred_eng_id; 1561 1562 bool test_pattern_enabled; 1563 enum dp_test_pattern current_test_pattern; 1564 union compliance_test_state compliance_test_state; 1565 1566 void *priv; 1567 1568 struct ddc_service *ddc; 1569 1570 enum dp_panel_mode panel_mode; 1571 bool aux_mode; 1572 1573 /* Private to DC core */ 1574 1575 const struct dc *dc; 1576 1577 struct dc_context *ctx; 1578 1579 struct panel_cntl *panel_cntl; 1580 struct link_encoder *link_enc; 1581 struct graphics_object_id link_id; 1582 /* Endpoint type distinguishes display endpoints which do not have entries 1583 * in the BIOS connector table from those that do. Helps when tracking link 1584 * encoder to display endpoint assignments. 1585 */ 1586 enum display_endpoint_type ep_type; 1587 union ddi_channel_mapping ddi_channel_mapping; 1588 struct connector_device_tag_info device_tag; 1589 struct dpcd_caps dpcd_caps; 1590 uint32_t dongle_max_pix_clk; 1591 unsigned short chip_caps; 1592 unsigned int dpcd_sink_count; 1593 struct hdcp_caps hdcp_caps; 1594 enum edp_revision edp_revision; 1595 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1596 1597 struct psr_settings psr_settings; 1598 1599 struct replay_settings replay_settings; 1600 1601 /* Drive settings read from integrated info table */ 1602 struct dc_lane_settings bios_forced_drive_settings; 1603 1604 /* Vendor specific LTTPR workaround variables */ 1605 uint8_t vendor_specific_lttpr_link_rate_wa; 1606 bool apply_vendor_specific_lttpr_link_rate_wa; 1607 1608 /* MST record stream using this link */ 1609 struct link_flags { 1610 bool dp_keep_receiver_powered; 1611 bool dp_skip_DID2; 1612 bool dp_skip_reset_segment; 1613 bool dp_skip_fs_144hz; 1614 bool dp_mot_reset_segment; 1615 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1616 bool dpia_mst_dsc_always_on; 1617 /* Forced DPIA into TBT3 compatibility mode. */ 1618 bool dpia_forced_tbt3_mode; 1619 bool dongle_mode_timing_override; 1620 bool blank_stream_on_ocs_change; 1621 bool read_dpcd204h_on_irq_hpd; 1622 } wa_flags; 1623 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1624 1625 struct dc_link_status link_status; 1626 struct dprx_states dprx_states; 1627 1628 struct gpio *hpd_gpio; 1629 enum dc_link_fec_state fec_state; 1630 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1631 1632 struct dc_panel_config panel_config; 1633 struct phy_state phy_state; 1634 // BW ALLOCATON USB4 ONLY 1635 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1636 bool skip_implict_edp_power_control; 1637 }; 1638 1639 /* Return an enumerated dc_link. 1640 * dc_link order is constant and determined at 1641 * boot time. They cannot be created or destroyed. 1642 * Use dc_get_caps() to get number of links. 1643 */ 1644 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1645 1646 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1647 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1648 const struct dc_link *link, 1649 unsigned int *inst_out); 1650 1651 /* Return an array of link pointers to edp links. */ 1652 void dc_get_edp_links(const struct dc *dc, 1653 struct dc_link **edp_links, 1654 int *edp_num); 1655 1656 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1657 bool powerOn); 1658 1659 /* The function initiates detection handshake over the given link. It first 1660 * determines if there are display connections over the link. If so it initiates 1661 * detection protocols supported by the connected receiver device. The function 1662 * contains protocol specific handshake sequences which are sometimes mandatory 1663 * to establish a proper connection between TX and RX. So it is always 1664 * recommended to call this function as the first link operation upon HPD event 1665 * or power up event. Upon completion, the function will update link structure 1666 * in place based on latest RX capabilities. The function may also cause dpms 1667 * to be reset to off for all currently enabled streams to the link. It is DM's 1668 * responsibility to serialize detection and DPMS updates. 1669 * 1670 * @reason - Indicate which event triggers this detection. dc may customize 1671 * detection flow depending on the triggering events. 1672 * return false - if detection is not fully completed. This could happen when 1673 * there is an unrecoverable error during detection or detection is partially 1674 * completed (detection has been delegated to dm mst manager ie. 1675 * link->connection_type == dc_connection_mst_branch when returning false). 1676 * return true - detection is completed, link has been fully updated with latest 1677 * detection result. 1678 */ 1679 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1680 1681 struct dc_sink_init_data; 1682 1683 /* When link connection type is dc_connection_mst_branch, remote sink can be 1684 * added to the link. The interface creates a remote sink and associates it with 1685 * current link. The sink will be retained by link until remove remote sink is 1686 * called. 1687 * 1688 * @dc_link - link the remote sink will be added to. 1689 * @edid - byte array of EDID raw data. 1690 * @len - size of the edid in byte 1691 * @init_data - 1692 */ 1693 struct dc_sink *dc_link_add_remote_sink( 1694 struct dc_link *dc_link, 1695 const uint8_t *edid, 1696 int len, 1697 struct dc_sink_init_data *init_data); 1698 1699 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1700 * @link - link the sink should be removed from 1701 * @sink - sink to be removed. 1702 */ 1703 void dc_link_remove_remote_sink( 1704 struct dc_link *link, 1705 struct dc_sink *sink); 1706 1707 /* Enable HPD interrupt handler for a given link */ 1708 void dc_link_enable_hpd(const struct dc_link *link); 1709 1710 /* Disable HPD interrupt handler for a given link */ 1711 void dc_link_disable_hpd(const struct dc_link *link); 1712 1713 /* determine if there is a sink connected to the link 1714 * 1715 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1716 * return - false if an unexpected error occurs, true otherwise. 1717 * 1718 * NOTE: This function doesn't detect downstream sink connections i.e 1719 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1720 * return dc_connection_single if the branch device is connected despite of 1721 * downstream sink's connection status. 1722 */ 1723 bool dc_link_detect_connection_type(struct dc_link *link, 1724 enum dc_connection_type *type); 1725 1726 /* query current hpd pin value 1727 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1728 * 1729 */ 1730 bool dc_link_get_hpd_state(struct dc_link *link); 1731 1732 /* Getter for cached link status from given link */ 1733 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1734 1735 /* enable/disable hardware HPD filter. 1736 * 1737 * @link - The link the HPD pin is associated with. 1738 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1739 * handler once after no HPD change has been detected within dc default HPD 1740 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1741 * pulses within default HPD interval, no HPD event will be received until HPD 1742 * toggles have stopped. Then HPD event will be queued to irq handler once after 1743 * dc default HPD filtering interval since last HPD event. 1744 * 1745 * @enable = false - disable hardware HPD filter. HPD event will be queued 1746 * immediately to irq handler after no HPD change has been detected within 1747 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1748 */ 1749 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1750 1751 /* submit i2c read/write payloads through ddc channel 1752 * @link_index - index to a link with ddc in i2c mode 1753 * @cmd - i2c command structure 1754 * return - true if success, false otherwise. 1755 */ 1756 bool dc_submit_i2c( 1757 struct dc *dc, 1758 uint32_t link_index, 1759 struct i2c_command *cmd); 1760 1761 /* submit i2c read/write payloads through oem channel 1762 * @link_index - index to a link with ddc in i2c mode 1763 * @cmd - i2c command structure 1764 * return - true if success, false otherwise. 1765 */ 1766 bool dc_submit_i2c_oem( 1767 struct dc *dc, 1768 struct i2c_command *cmd); 1769 1770 enum aux_return_code_type; 1771 /* Attempt to transfer the given aux payload. This function does not perform 1772 * retries or handle error states. The reply is returned in the payload->reply 1773 * and the result through operation_result. Returns the number of bytes 1774 * transferred,or -1 on a failure. 1775 */ 1776 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1777 struct aux_payload *payload, 1778 enum aux_return_code_type *operation_result); 1779 1780 bool dc_is_oem_i2c_device_present( 1781 struct dc *dc, 1782 size_t slave_address 1783 ); 1784 1785 /* return true if the connected receiver supports the hdcp version */ 1786 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1787 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1788 1789 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1790 * 1791 * TODO - When defer_handling is true the function will have a different purpose. 1792 * It no longer does complete hpd rx irq handling. We should create a separate 1793 * interface specifically for this case. 1794 * 1795 * Return: 1796 * true - Downstream port status changed. DM should call DC to do the 1797 * detection. 1798 * false - no change in Downstream port status. No further action required 1799 * from DM. 1800 */ 1801 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1802 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1803 bool defer_handling, bool *has_left_work); 1804 /* handle DP specs define test automation sequence*/ 1805 void dc_link_dp_handle_automated_test(struct dc_link *link); 1806 1807 /* handle DP Link loss sequence and try to recover RX link loss with best 1808 * effort 1809 */ 1810 void dc_link_dp_handle_link_loss(struct dc_link *link); 1811 1812 /* Determine if hpd rx irq should be handled or ignored 1813 * return true - hpd rx irq should be handled. 1814 * return false - it is safe to ignore hpd rx irq event 1815 */ 1816 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1817 1818 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1819 * @link - link the hpd irq data associated with 1820 * @hpd_irq_dpcd_data - input hpd irq data 1821 * return - true if hpd irq data indicates a link lost 1822 */ 1823 bool dc_link_check_link_loss_status(struct dc_link *link, 1824 union hpd_irq_data *hpd_irq_dpcd_data); 1825 1826 /* Read hpd rx irq data from a given link 1827 * @link - link where the hpd irq data should be read from 1828 * @irq_data - output hpd irq data 1829 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1830 * read has failed. 1831 */ 1832 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1833 struct dc_link *link, 1834 union hpd_irq_data *irq_data); 1835 1836 /* The function clears recorded DP RX states in the link. DM should call this 1837 * function when it is resuming from S3 power state to previously connected links. 1838 * 1839 * TODO - in the future we should consider to expand link resume interface to 1840 * support clearing previous rx states. So we don't have to rely on dm to call 1841 * this interface explicitly. 1842 */ 1843 void dc_link_clear_dprx_states(struct dc_link *link); 1844 1845 /* Destruct the mst topology of the link and reset the allocated payload table 1846 * 1847 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1848 * still wants to reset MST topology on an unplug event */ 1849 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1850 1851 /* The function calculates effective DP link bandwidth when a given link is 1852 * using the given link settings. 1853 * 1854 * return - total effective link bandwidth in kbps. 1855 */ 1856 uint32_t dc_link_bandwidth_kbps( 1857 const struct dc_link *link, 1858 const struct dc_link_settings *link_setting); 1859 1860 /* The function takes a snapshot of current link resource allocation state 1861 * @dc: pointer to dc of the dm calling this 1862 * @map: a dc link resource snapshot defined internally to dc. 1863 * 1864 * DM needs to capture a snapshot of current link resource allocation mapping 1865 * and store it in its persistent storage. 1866 * 1867 * Some of the link resource is using first come first serve policy. 1868 * The allocation mapping depends on original hotplug order. This information 1869 * is lost after driver is loaded next time. The snapshot is used in order to 1870 * restore link resource to its previous state so user will get consistent 1871 * link capability allocation across reboot. 1872 * 1873 */ 1874 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1875 1876 /* This function restores link resource allocation state from a snapshot 1877 * @dc: pointer to dc of the dm calling this 1878 * @map: a dc link resource snapshot defined internally to dc. 1879 * 1880 * DM needs to call this function after initial link detection on boot and 1881 * before first commit streams to restore link resource allocation state 1882 * from previous boot session. 1883 * 1884 * Some of the link resource is using first come first serve policy. 1885 * The allocation mapping depends on original hotplug order. This information 1886 * is lost after driver is loaded next time. The snapshot is used in order to 1887 * restore link resource to its previous state so user will get consistent 1888 * link capability allocation across reboot. 1889 * 1890 */ 1891 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1892 1893 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1894 * interface i.e stream_update->dsc_config 1895 */ 1896 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1897 1898 /* translate a raw link rate data to bandwidth in kbps */ 1899 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1900 1901 /* determine the optimal bandwidth given link and required bw. 1902 * @link - current detected link 1903 * @req_bw - requested bandwidth in kbps 1904 * @link_settings - returned most optimal link settings that can fit the 1905 * requested bandwidth 1906 * return - false if link can't support requested bandwidth, true if link 1907 * settings is found. 1908 */ 1909 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1910 struct dc_link_settings *link_settings, 1911 uint32_t req_bw); 1912 1913 /* return the max dp link settings can be driven by the link without considering 1914 * connected RX device and its capability 1915 */ 1916 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1917 struct dc_link_settings *max_link_enc_cap); 1918 1919 /* determine when the link is driving MST mode, what DP link channel coding 1920 * format will be used. The decision will remain unchanged until next HPD event. 1921 * 1922 * @link - a link with DP RX connection 1923 * return - if stream is committed to this link with MST signal type, type of 1924 * channel coding format dc will choose. 1925 */ 1926 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1927 const struct dc_link *link); 1928 1929 /* get max dp link settings the link can enable with all things considered. (i.e 1930 * TX/RX/Cable capabilities and dp override policies. 1931 * 1932 * @link - a link with DP RX connection 1933 * return - max dp link settings the link can enable. 1934 * 1935 */ 1936 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1937 1938 /* Get the highest encoding format that the link supports; highest meaning the 1939 * encoding format which supports the maximum bandwidth. 1940 * 1941 * @link - a link with DP RX connection 1942 * return - highest encoding format link supports. 1943 */ 1944 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 1945 1946 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1947 * to a link with dp connector signal type. 1948 * @link - a link with dp connector signal type 1949 * return - true if connected, false otherwise 1950 */ 1951 bool dc_link_is_dp_sink_present(struct dc_link *link); 1952 1953 /* Force DP lane settings update to main-link video signal and notify the change 1954 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1955 * tuning purpose. The interface assumes link has already been enabled with DP 1956 * signal. 1957 * 1958 * @lt_settings - a container structure with desired hw_lane_settings 1959 */ 1960 void dc_link_set_drive_settings(struct dc *dc, 1961 struct link_training_settings *lt_settings, 1962 struct dc_link *link); 1963 1964 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1965 * test or debugging purpose. The test pattern will remain until next un-plug. 1966 * 1967 * @link - active link with DP signal output enabled. 1968 * @test_pattern - desired test pattern to output. 1969 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1970 * @test_pattern_color_space - for video test pattern choose a desired color 1971 * space. 1972 * @p_link_settings - For PHY pattern choose a desired link settings 1973 * @p_custom_pattern - some test pattern will require a custom input to 1974 * customize some pattern details. Otherwise keep it to NULL. 1975 * @cust_pattern_size - size of the custom pattern input. 1976 * 1977 */ 1978 bool dc_link_dp_set_test_pattern( 1979 struct dc_link *link, 1980 enum dp_test_pattern test_pattern, 1981 enum dp_test_pattern_color_space test_pattern_color_space, 1982 const struct link_training_settings *p_link_settings, 1983 const unsigned char *p_custom_pattern, 1984 unsigned int cust_pattern_size); 1985 1986 /* Force DP link settings to always use a specific value until reboot to a 1987 * specific link. If link has already been enabled, the interface will also 1988 * switch to desired link settings immediately. This is a debug interface to 1989 * generic dp issue trouble shooting. 1990 */ 1991 void dc_link_set_preferred_link_settings(struct dc *dc, 1992 struct dc_link_settings *link_setting, 1993 struct dc_link *link); 1994 1995 /* Force DP link to customize a specific link training behavior by overriding to 1996 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1997 * display specific link training issues or apply some display specific 1998 * workaround in link training. 1999 * 2000 * @link_settings - if not NULL, force preferred link settings to the link. 2001 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2002 * will apply this particular override in future link training. If NULL is 2003 * passed in, dc resets previous overrides. 2004 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2005 * training settings. 2006 */ 2007 void dc_link_set_preferred_training_settings(struct dc *dc, 2008 struct dc_link_settings *link_setting, 2009 struct dc_link_training_overrides *lt_overrides, 2010 struct dc_link *link, 2011 bool skip_immediate_retrain); 2012 2013 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2014 bool dc_link_is_fec_supported(const struct dc_link *link); 2015 2016 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2017 * link enablement. 2018 * return - true if FEC should be enabled, false otherwise. 2019 */ 2020 bool dc_link_should_enable_fec(const struct dc_link *link); 2021 2022 /* determine lttpr mode the current link should be enabled with a specific link 2023 * settings. 2024 */ 2025 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2026 struct dc_link_settings *link_setting); 2027 2028 /* Force DP RX to update its power state. 2029 * NOTE: this interface doesn't update dp main-link. Calling this function will 2030 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2031 * RX power state back upon finish DM specific execution requiring DP RX in a 2032 * specific power state. 2033 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2034 * state. 2035 */ 2036 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2037 2038 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2039 * current value read from extended receiver cap from 02200h - 0220Fh. 2040 * Some DP RX has problems of providing accurate DP receiver caps from extended 2041 * field, this interface is a workaround to revert link back to use base caps. 2042 */ 2043 void dc_link_overwrite_extended_receiver_cap( 2044 struct dc_link *link); 2045 2046 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2047 bool wait_for_hpd); 2048 2049 /* Set backlight level of an embedded panel (eDP, LVDS). 2050 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2051 * and 16 bit fractional, where 1.0 is max backlight value. 2052 */ 2053 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2054 uint32_t backlight_pwm_u16_16, 2055 uint32_t frame_ramp); 2056 2057 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2058 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2059 bool isHDR, 2060 uint32_t backlight_millinits, 2061 uint32_t transition_time_in_ms); 2062 2063 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2064 uint32_t *backlight_millinits, 2065 uint32_t *backlight_millinits_peak); 2066 2067 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2068 2069 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2070 2071 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2072 bool wait, bool force_static, const unsigned int *power_opts); 2073 2074 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2075 2076 bool dc_link_setup_psr(struct dc_link *dc_link, 2077 const struct dc_stream_state *stream, struct psr_config *psr_config, 2078 struct psr_context *psr_context); 2079 2080 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2081 2082 /* On eDP links this function call will stall until T12 has elapsed. 2083 * If the panel is not in power off state, this function will return 2084 * immediately. 2085 */ 2086 bool dc_link_wait_for_t12(struct dc_link *link); 2087 2088 /* Determine if dp trace has been initialized to reflect upto date result * 2089 * return - true if trace is initialized and has valid data. False dp trace 2090 * doesn't have valid result. 2091 */ 2092 bool dc_dp_trace_is_initialized(struct dc_link *link); 2093 2094 /* Query a dp trace flag to indicate if the current dp trace data has been 2095 * logged before 2096 */ 2097 bool dc_dp_trace_is_logged(struct dc_link *link, 2098 bool in_detection); 2099 2100 /* Set dp trace flag to indicate whether DM has already logged the current dp 2101 * trace data. DM can set is_logged to true upon logging and check 2102 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2103 */ 2104 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2105 bool in_detection, 2106 bool is_logged); 2107 2108 /* Obtain driver time stamp for last dp link training end. The time stamp is 2109 * formatted based on dm_get_timestamp DM function. 2110 * @in_detection - true to get link training end time stamp of last link 2111 * training in detection sequence. false to get link training end time stamp 2112 * of last link training in commit (dpms) sequence 2113 */ 2114 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2115 bool in_detection); 2116 2117 /* Get how many link training attempts dc has done with latest sequence. 2118 * @in_detection - true to get link training count of last link 2119 * training in detection sequence. false to get link training count of last link 2120 * training in commit (dpms) sequence 2121 */ 2122 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2123 bool in_detection); 2124 2125 /* Get how many link loss has happened since last link training attempts */ 2126 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2127 2128 /* 2129 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2130 */ 2131 /* 2132 * Send a request from DP-Tx requesting to allocate BW remotely after 2133 * allocating it locally. This will get processed by CM and a CB function 2134 * will be called. 2135 * 2136 * @link: pointer to the dc_link struct instance 2137 * @req_bw: The requested bw in Kbyte to allocated 2138 * 2139 * return: none 2140 */ 2141 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2142 2143 /* 2144 * Handle function for when the status of the Request above is complete. 2145 * We will find out the result of allocating on CM and update structs. 2146 * 2147 * @link: pointer to the dc_link struct instance 2148 * @bw: Allocated or Estimated BW depending on the result 2149 * @result: Response type 2150 * 2151 * return: none 2152 */ 2153 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2154 uint8_t bw, uint8_t result); 2155 2156 /* 2157 * Handle the USB4 BW Allocation related functionality here: 2158 * Plug => Try to allocate max bw from timing parameters supported by the sink 2159 * Unplug => de-allocate bw 2160 * 2161 * @link: pointer to the dc_link struct instance 2162 * @peak_bw: Peak bw used by the link/sink 2163 * 2164 * return: allocated bw else return 0 2165 */ 2166 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2167 struct dc_link *link, int peak_bw); 2168 2169 /* 2170 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2171 * available BW for each host router 2172 * 2173 * @dc: pointer to dc struct 2174 * @stream: pointer to all possible streams 2175 * @count: number of valid DPIA streams 2176 * 2177 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2178 */ 2179 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2180 const unsigned int count); 2181 2182 /* Sink Interfaces - A sink corresponds to a display output device */ 2183 2184 struct dc_container_id { 2185 // 128bit GUID in binary form 2186 unsigned char guid[16]; 2187 // 8 byte port ID -> ELD.PortID 2188 unsigned int portId[2]; 2189 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2190 unsigned short manufacturerName; 2191 // 2 byte product code -> ELD.ProductCode 2192 unsigned short productCode; 2193 }; 2194 2195 2196 struct dc_sink_dsc_caps { 2197 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2198 // 'false' if they are sink's DSC caps 2199 bool is_virtual_dpcd_dsc; 2200 #if defined(CONFIG_DRM_AMD_DC_FP) 2201 // 'true' if MST topology supports DSC passthrough for sink 2202 // 'false' if MST topology does not support DSC passthrough 2203 bool is_dsc_passthrough_supported; 2204 #endif 2205 struct dsc_dec_dpcd_caps dsc_dec_caps; 2206 }; 2207 2208 struct dc_sink_fec_caps { 2209 bool is_rx_fec_supported; 2210 bool is_topology_fec_supported; 2211 }; 2212 2213 struct scdc_caps { 2214 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2215 union hdmi_scdc_device_id_data device_id; 2216 }; 2217 2218 /* 2219 * The sink structure contains EDID and other display device properties 2220 */ 2221 struct dc_sink { 2222 enum signal_type sink_signal; 2223 struct dc_edid dc_edid; /* raw edid */ 2224 struct dc_edid_caps edid_caps; /* parse display caps */ 2225 struct dc_container_id *dc_container_id; 2226 uint32_t dongle_max_pix_clk; 2227 void *priv; 2228 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2229 bool converter_disable_audio; 2230 2231 struct scdc_caps scdc_caps; 2232 struct dc_sink_dsc_caps dsc_caps; 2233 struct dc_sink_fec_caps fec_caps; 2234 2235 bool is_vsc_sdp_colorimetry_supported; 2236 2237 /* private to DC core */ 2238 struct dc_link *link; 2239 struct dc_context *ctx; 2240 2241 uint32_t sink_id; 2242 2243 /* private to dc_sink.c */ 2244 // refcount must be the last member in dc_sink, since we want the 2245 // sink structure to be logically cloneable up to (but not including) 2246 // refcount 2247 struct kref refcount; 2248 }; 2249 2250 void dc_sink_retain(struct dc_sink *sink); 2251 void dc_sink_release(struct dc_sink *sink); 2252 2253 struct dc_sink_init_data { 2254 enum signal_type sink_signal; 2255 struct dc_link *link; 2256 uint32_t dongle_max_pix_clk; 2257 bool converter_disable_audio; 2258 }; 2259 2260 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2261 2262 /* Newer interfaces */ 2263 struct dc_cursor { 2264 struct dc_plane_address address; 2265 struct dc_cursor_attributes attributes; 2266 }; 2267 2268 2269 /* Interrupt interfaces */ 2270 enum dc_irq_source dc_interrupt_to_irq_source( 2271 struct dc *dc, 2272 uint32_t src_id, 2273 uint32_t ext_id); 2274 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2275 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2276 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2277 struct dc *dc, uint32_t link_index); 2278 2279 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2280 2281 /* Power Interfaces */ 2282 2283 void dc_set_power_state( 2284 struct dc *dc, 2285 enum dc_acpi_cm_power_state power_state); 2286 void dc_resume(struct dc *dc); 2287 2288 void dc_power_down_on_boot(struct dc *dc); 2289 2290 /* 2291 * HDCP Interfaces 2292 */ 2293 enum hdcp_message_status dc_process_hdcp_msg( 2294 enum signal_type signal, 2295 struct dc_link *link, 2296 struct hdcp_protection_message *message_info); 2297 bool dc_is_dmcu_initialized(struct dc *dc); 2298 2299 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2300 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2301 2302 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2303 struct dc_cursor_attributes *cursor_attr); 2304 2305 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2306 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2307 2308 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2309 void dc_unlock_memory_clock_frequency(struct dc *dc); 2310 2311 /* set min memory clock to the min required for current mode, max to maxDPM */ 2312 void dc_lock_memory_clock_frequency(struct dc *dc); 2313 2314 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2315 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2316 2317 /* cleanup on driver unload */ 2318 void dc_hardware_release(struct dc *dc); 2319 2320 /* disables fw based mclk switch */ 2321 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2322 2323 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2324 void dc_z10_restore(const struct dc *dc); 2325 void dc_z10_save_init(struct dc *dc); 2326 2327 bool dc_is_dmub_outbox_supported(struct dc *dc); 2328 bool dc_enable_dmub_notifications(struct dc *dc); 2329 2330 bool dc_abm_save_restore( 2331 struct dc *dc, 2332 struct dc_stream_state *stream, 2333 struct abm_save_restore *pData); 2334 2335 void dc_enable_dmub_outbox(struct dc *dc); 2336 2337 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2338 uint32_t link_index, 2339 struct aux_payload *payload); 2340 2341 /* Get dc link index from dpia port index */ 2342 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2343 uint8_t dpia_port_index); 2344 2345 bool dc_process_dmub_set_config_async(struct dc *dc, 2346 uint32_t link_index, 2347 struct set_config_cmd_payload *payload, 2348 struct dmub_notification *notify); 2349 2350 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2351 uint32_t link_index, 2352 uint8_t mst_alloc_slots, 2353 uint8_t *mst_slots_in_use); 2354 2355 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2356 uint32_t hpd_int_enable); 2357 2358 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2359 2360 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2361 2362 struct dc_power_profile { 2363 int power_level; /* Lower is better */ 2364 }; 2365 2366 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2367 2368 /* DSC Interfaces */ 2369 #include "dc_dsc.h" 2370 2371 /* Disable acc mode Interfaces */ 2372 void dc_disable_accelerated_mode(struct dc *dc); 2373 2374 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2375 struct dc_stream_state *new_stream); 2376 2377 #endif /* DC_INTERFACE_H_ */ 2378