1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "hwss/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 #include "dml2/dml2_wrapper.h" 44 45 struct abm_save_restore; 46 47 /* forward declaration */ 48 struct aux_payload; 49 struct set_config_cmd_payload; 50 struct dmub_notification; 51 52 #define DC_VER "3.2.255" 53 54 #define MAX_SURFACES 3 55 #define MAX_PLANES 6 56 #define MAX_STREAMS 6 57 #define MIN_VIEWPORT_SIZE 12 58 #define MAX_NUM_EDP 2 59 60 /* Display Core Interfaces */ 61 struct dc_versions { 62 const char *dc_ver; 63 struct dmcu_version dmcu_version; 64 }; 65 66 enum dp_protocol_version { 67 DP_VERSION_1_4 = 0, 68 DP_VERSION_2_1, 69 DP_VERSION_UNKNOWN, 70 }; 71 72 enum dc_plane_type { 73 DC_PLANE_TYPE_INVALID, 74 DC_PLANE_TYPE_DCE_RGB, 75 DC_PLANE_TYPE_DCE_UNDERLAY, 76 DC_PLANE_TYPE_DCN_UNIVERSAL, 77 }; 78 79 // Sizes defined as multiples of 64KB 80 enum det_size { 81 DET_SIZE_DEFAULT = 0, 82 DET_SIZE_192KB = 3, 83 DET_SIZE_256KB = 4, 84 DET_SIZE_320KB = 5, 85 DET_SIZE_384KB = 6 86 }; 87 88 89 struct dc_plane_cap { 90 enum dc_plane_type type; 91 uint32_t per_pixel_alpha : 1; 92 struct { 93 uint32_t argb8888 : 1; 94 uint32_t nv12 : 1; 95 uint32_t fp16 : 1; 96 uint32_t p010 : 1; 97 uint32_t ayuv : 1; 98 } pixel_format_support; 99 // max upscaling factor x1000 100 // upscaling factors are always >= 1 101 // for example, 1080p -> 8K is 4.0, or 4000 raw value 102 struct { 103 uint32_t argb8888; 104 uint32_t nv12; 105 uint32_t fp16; 106 } max_upscale_factor; 107 // max downscale factor x1000 108 // downscale factors are always <= 1 109 // for example, 8K -> 1080p is 0.25, or 250 raw value 110 struct { 111 uint32_t argb8888; 112 uint32_t nv12; 113 uint32_t fp16; 114 } max_downscale_factor; 115 // minimal width/height 116 uint32_t min_width; 117 uint32_t min_height; 118 }; 119 120 /** 121 * DOC: color-management-caps 122 * 123 * **Color management caps (DPP and MPC)** 124 * 125 * Modules/color calculates various color operations which are translated to 126 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 127 * DCN1, every new generation comes with fairly major differences in color 128 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 129 * decide mapping to HW block based on logical capabilities. 130 */ 131 132 /** 133 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 134 * @srgb: RGB color space transfer func 135 * @bt2020: BT.2020 transfer func 136 * @gamma2_2: standard gamma 137 * @pq: perceptual quantizer transfer function 138 * @hlg: hybrid log–gamma transfer function 139 */ 140 struct rom_curve_caps { 141 uint16_t srgb : 1; 142 uint16_t bt2020 : 1; 143 uint16_t gamma2_2 : 1; 144 uint16_t pq : 1; 145 uint16_t hlg : 1; 146 }; 147 148 /** 149 * struct dpp_color_caps - color pipeline capabilities for display pipe and 150 * plane blocks 151 * 152 * @dcn_arch: all DCE generations treated the same 153 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 154 * just plain 256-entry lookup 155 * @icsc: input color space conversion 156 * @dgam_ram: programmable degamma LUT 157 * @post_csc: post color space conversion, before gamut remap 158 * @gamma_corr: degamma correction 159 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 160 * with MPC by setting mpc:shared_3d_lut flag 161 * @ogam_ram: programmable out/blend gamma LUT 162 * @ocsc: output color space conversion 163 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 164 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 165 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 166 * 167 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 168 */ 169 struct dpp_color_caps { 170 uint16_t dcn_arch : 1; 171 uint16_t input_lut_shared : 1; 172 uint16_t icsc : 1; 173 uint16_t dgam_ram : 1; 174 uint16_t post_csc : 1; 175 uint16_t gamma_corr : 1; 176 uint16_t hw_3d_lut : 1; 177 uint16_t ogam_ram : 1; 178 uint16_t ocsc : 1; 179 uint16_t dgam_rom_for_yuv : 1; 180 struct rom_curve_caps dgam_rom_caps; 181 struct rom_curve_caps ogam_rom_caps; 182 }; 183 184 /** 185 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 186 * plane combined blocks 187 * 188 * @gamut_remap: color transformation matrix 189 * @ogam_ram: programmable out gamma LUT 190 * @ocsc: output color space conversion matrix 191 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 192 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 193 * instance 194 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 195 */ 196 struct mpc_color_caps { 197 uint16_t gamut_remap : 1; 198 uint16_t ogam_ram : 1; 199 uint16_t ocsc : 1; 200 uint16_t num_3dluts : 3; 201 uint16_t shared_3d_lut:1; 202 struct rom_curve_caps ogam_rom_caps; 203 }; 204 205 /** 206 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 207 * @dpp: color pipes caps for DPP 208 * @mpc: color pipes caps for MPC 209 */ 210 struct dc_color_caps { 211 struct dpp_color_caps dpp; 212 struct mpc_color_caps mpc; 213 }; 214 215 struct dc_dmub_caps { 216 bool psr; 217 bool mclk_sw; 218 bool subvp_psr; 219 bool gecc_enable; 220 }; 221 222 struct dc_caps { 223 uint32_t max_streams; 224 uint32_t max_links; 225 uint32_t max_audios; 226 uint32_t max_slave_planes; 227 uint32_t max_slave_yuv_planes; 228 uint32_t max_slave_rgb_planes; 229 uint32_t max_planes; 230 uint32_t max_downscale_ratio; 231 uint32_t i2c_speed_in_khz; 232 uint32_t i2c_speed_in_khz_hdcp; 233 uint32_t dmdata_alloc_size; 234 unsigned int max_cursor_size; 235 unsigned int max_video_width; 236 /* 237 * max video plane width that can be safely assumed to be always 238 * supported by single DPP pipe. 239 */ 240 unsigned int max_optimizable_video_width; 241 unsigned int min_horizontal_blanking_period; 242 int linear_pitch_alignment; 243 bool dcc_const_color; 244 bool dynamic_audio; 245 bool is_apu; 246 bool dual_link_dvi; 247 bool post_blend_color_processing; 248 bool force_dp_tps4_for_cp2520; 249 bool disable_dp_clk_share; 250 bool psp_setup_panel_mode; 251 bool extended_aux_timeout_support; 252 bool dmcub_support; 253 bool zstate_support; 254 bool ips_support; 255 uint32_t num_of_internal_disp; 256 enum dp_protocol_version max_dp_protocol_version; 257 unsigned int mall_size_per_mem_channel; 258 unsigned int mall_size_total; 259 unsigned int cursor_cache_size; 260 struct dc_plane_cap planes[MAX_PLANES]; 261 struct dc_color_caps color; 262 struct dc_dmub_caps dmub_caps; 263 bool dp_hpo; 264 bool dp_hdmi21_pcon_support; 265 bool edp_dsc_support; 266 bool vbios_lttpr_aware; 267 bool vbios_lttpr_enable; 268 uint32_t max_otg_num; 269 uint32_t max_cab_allocation_bytes; 270 uint32_t cache_line_size; 271 uint32_t cache_num_ways; 272 uint16_t subvp_fw_processing_delay_us; 273 uint8_t subvp_drr_max_vblank_margin_us; 274 uint16_t subvp_prefetch_end_to_mall_start_us; 275 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 276 uint16_t subvp_pstate_allow_width_us; 277 uint16_t subvp_vertical_int_margin_us; 278 bool seamless_odm; 279 uint32_t max_v_total; 280 uint32_t max_disp_clock_khz_at_vmin; 281 uint8_t subvp_drr_vblank_start_margin_us; 282 }; 283 284 struct dc_bug_wa { 285 bool no_connect_phy_config; 286 bool dedcn20_305_wa; 287 bool skip_clock_update; 288 bool lt_early_cr_pattern; 289 struct { 290 uint8_t uclk : 1; 291 uint8_t fclk : 1; 292 uint8_t dcfclk : 1; 293 uint8_t dcfclk_ds: 1; 294 } clock_update_disable_mask; 295 }; 296 struct dc_dcc_surface_param { 297 struct dc_size surface_size; 298 enum surface_pixel_format format; 299 enum swizzle_mode_values swizzle_mode; 300 enum dc_scan_direction scan; 301 }; 302 303 struct dc_dcc_setting { 304 unsigned int max_compressed_blk_size; 305 unsigned int max_uncompressed_blk_size; 306 bool independent_64b_blks; 307 //These bitfields to be used starting with DCN 308 struct { 309 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 310 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 311 uint32_t dcc_256_128_128 : 1; //available starting with DCN 312 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 313 } dcc_controls; 314 }; 315 316 struct dc_surface_dcc_cap { 317 union { 318 struct { 319 struct dc_dcc_setting rgb; 320 } grph; 321 322 struct { 323 struct dc_dcc_setting luma; 324 struct dc_dcc_setting chroma; 325 } video; 326 }; 327 328 bool capable; 329 bool const_color_support; 330 }; 331 332 struct dc_static_screen_params { 333 struct { 334 bool force_trigger; 335 bool cursor_update; 336 bool surface_update; 337 bool overlay_update; 338 } triggers; 339 unsigned int num_frames; 340 }; 341 342 343 /* Surface update type is used by dc_update_surfaces_and_stream 344 * The update type is determined at the very beginning of the function based 345 * on parameters passed in and decides how much programming (or updating) is 346 * going to be done during the call. 347 * 348 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 349 * logical calculations or hardware register programming. This update MUST be 350 * ISR safe on windows. Currently fast update will only be used to flip surface 351 * address. 352 * 353 * UPDATE_TYPE_MED is used for slower updates which require significant hw 354 * re-programming however do not affect bandwidth consumption or clock 355 * requirements. At present, this is the level at which front end updates 356 * that do not require us to run bw_calcs happen. These are in/out transfer func 357 * updates, viewport offset changes, recout size changes and pixel depth changes. 358 * This update can be done at ISR, but we want to minimize how often this happens. 359 * 360 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 361 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 362 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 363 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 364 * a full update. This cannot be done at ISR level and should be a rare event. 365 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 366 * underscan we don't expect to see this call at all. 367 */ 368 369 enum surface_update_type { 370 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 371 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 372 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 373 }; 374 375 /* Forward declaration*/ 376 struct dc; 377 struct dc_plane_state; 378 struct dc_state; 379 380 381 struct dc_cap_funcs { 382 bool (*get_dcc_compression_cap)(const struct dc *dc, 383 const struct dc_dcc_surface_param *input, 384 struct dc_surface_dcc_cap *output); 385 }; 386 387 struct link_training_settings; 388 389 union allow_lttpr_non_transparent_mode { 390 struct { 391 bool DP1_4A : 1; 392 bool DP2_0 : 1; 393 } bits; 394 unsigned char raw; 395 }; 396 397 /* Structure to hold configuration flags set by dm at dc creation. */ 398 struct dc_config { 399 bool gpu_vm_support; 400 bool disable_disp_pll_sharing; 401 bool fbc_support; 402 bool disable_fractional_pwm; 403 bool allow_seamless_boot_optimization; 404 bool seamless_boot_edp_requested; 405 bool edp_not_connected; 406 bool edp_no_power_sequencing; 407 bool force_enum_edp; 408 bool forced_clocks; 409 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 410 bool multi_mon_pp_mclk_switch; 411 bool disable_dmcu; 412 bool enable_4to1MPC; 413 bool enable_windowed_mpo_odm; 414 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 415 uint32_t allow_edp_hotplug_detection; 416 bool clamp_min_dcfclk; 417 uint64_t vblank_alignment_dto_params; 418 uint8_t vblank_alignment_max_frame_time_diff; 419 bool is_asymmetric_memory; 420 bool is_single_rank_dimm; 421 bool is_vmin_only_asic; 422 bool use_pipe_ctx_sync_logic; 423 bool ignore_dpref_ss; 424 bool enable_mipi_converter_optimization; 425 bool use_default_clock_table; 426 bool force_bios_enable_lttpr; 427 uint8_t force_bios_fixed_vs; 428 int sdpif_request_limit_words_per_umc; 429 bool use_old_fixed_vs_sequence; 430 bool dc_mode_clk_limit_support; 431 bool EnableMinDispClkODM; 432 bool enable_auto_dpm_test_logs; 433 unsigned int disable_ips; 434 }; 435 436 enum visual_confirm { 437 VISUAL_CONFIRM_DISABLE = 0, 438 VISUAL_CONFIRM_SURFACE = 1, 439 VISUAL_CONFIRM_HDR = 2, 440 VISUAL_CONFIRM_MPCTREE = 4, 441 VISUAL_CONFIRM_PSR = 5, 442 VISUAL_CONFIRM_SWAPCHAIN = 6, 443 VISUAL_CONFIRM_FAMS = 7, 444 VISUAL_CONFIRM_SWIZZLE = 9, 445 VISUAL_CONFIRM_REPLAY = 12, 446 VISUAL_CONFIRM_SUBVP = 14, 447 VISUAL_CONFIRM_MCLK_SWITCH = 16, 448 }; 449 450 enum dc_psr_power_opts { 451 psr_power_opt_invalid = 0x0, 452 psr_power_opt_smu_opt_static_screen = 0x1, 453 psr_power_opt_z10_static_screen = 0x10, 454 psr_power_opt_ds_disable_allow = 0x100, 455 }; 456 457 enum dml_hostvm_override_opts { 458 DML_HOSTVM_NO_OVERRIDE = 0x0, 459 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 460 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 461 }; 462 463 enum dcc_option { 464 DCC_ENABLE = 0, 465 DCC_DISABLE = 1, 466 DCC_HALF_REQ_DISALBE = 2, 467 }; 468 469 /** 470 * enum pipe_split_policy - Pipe split strategy supported by DCN 471 * 472 * This enum is used to define the pipe split policy supported by DCN. By 473 * default, DC favors MPC_SPLIT_DYNAMIC. 474 */ 475 enum pipe_split_policy { 476 /** 477 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 478 * pipe in order to bring the best trade-off between performance and 479 * power consumption. This is the recommended option. 480 */ 481 MPC_SPLIT_DYNAMIC = 0, 482 483 /** 484 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 485 * try any sort of split optimization. 486 */ 487 MPC_SPLIT_AVOID = 1, 488 489 /** 490 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 491 * optimize the pipe utilization when using a single display; if the 492 * user connects to a second display, DC will avoid pipe split. 493 */ 494 MPC_SPLIT_AVOID_MULT_DISP = 2, 495 }; 496 497 enum wm_report_mode { 498 WM_REPORT_DEFAULT = 0, 499 WM_REPORT_OVERRIDE = 1, 500 }; 501 enum dtm_pstate{ 502 dtm_level_p0 = 0,/*highest voltage*/ 503 dtm_level_p1, 504 dtm_level_p2, 505 dtm_level_p3, 506 dtm_level_p4,/*when active_display_count = 0*/ 507 }; 508 509 enum dcn_pwr_state { 510 DCN_PWR_STATE_UNKNOWN = -1, 511 DCN_PWR_STATE_MISSION_MODE = 0, 512 DCN_PWR_STATE_LOW_POWER = 3, 513 }; 514 515 enum dcn_zstate_support_state { 516 DCN_ZSTATE_SUPPORT_UNKNOWN, 517 DCN_ZSTATE_SUPPORT_ALLOW, 518 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 519 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 520 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 521 DCN_ZSTATE_SUPPORT_DISALLOW, 522 }; 523 524 /* 525 * struct dc_clocks - DC pipe clocks 526 * 527 * For any clocks that may differ per pipe only the max is stored in this 528 * structure 529 */ 530 struct dc_clocks { 531 int dispclk_khz; 532 int actual_dispclk_khz; 533 int dppclk_khz; 534 int actual_dppclk_khz; 535 int disp_dpp_voltage_level_khz; 536 int dcfclk_khz; 537 int socclk_khz; 538 int dcfclk_deep_sleep_khz; 539 int fclk_khz; 540 int phyclk_khz; 541 int dramclk_khz; 542 bool p_state_change_support; 543 enum dcn_zstate_support_state zstate_support; 544 bool dtbclk_en; 545 int ref_dtbclk_khz; 546 bool fclk_p_state_change_support; 547 enum dcn_pwr_state pwr_state; 548 /* 549 * Elements below are not compared for the purposes of 550 * optimization required 551 */ 552 bool prev_p_state_change_support; 553 bool fclk_prev_p_state_change_support; 554 int num_ways; 555 556 /* 557 * @fw_based_mclk_switching 558 * 559 * DC has a mechanism that leverage the variable refresh rate to switch 560 * memory clock in cases that we have a large latency to achieve the 561 * memory clock change and a short vblank window. DC has some 562 * requirements to enable this feature, and this field describes if the 563 * system support or not such a feature. 564 */ 565 bool fw_based_mclk_switching; 566 bool fw_based_mclk_switching_shut_down; 567 int prev_num_ways; 568 enum dtm_pstate dtm_level; 569 int max_supported_dppclk_khz; 570 int max_supported_dispclk_khz; 571 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 572 int bw_dispclk_khz; 573 }; 574 575 struct dc_bw_validation_profile { 576 bool enable; 577 578 unsigned long long total_ticks; 579 unsigned long long voltage_level_ticks; 580 unsigned long long watermark_ticks; 581 unsigned long long rq_dlg_ticks; 582 583 unsigned long long total_count; 584 unsigned long long skip_fast_count; 585 unsigned long long skip_pass_count; 586 unsigned long long skip_fail_count; 587 }; 588 589 #define BW_VAL_TRACE_SETUP() \ 590 unsigned long long end_tick = 0; \ 591 unsigned long long voltage_level_tick = 0; \ 592 unsigned long long watermark_tick = 0; \ 593 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 594 dm_get_timestamp(dc->ctx) : 0 595 596 #define BW_VAL_TRACE_COUNT() \ 597 if (dc->debug.bw_val_profile.enable) \ 598 dc->debug.bw_val_profile.total_count++ 599 600 #define BW_VAL_TRACE_SKIP(status) \ 601 if (dc->debug.bw_val_profile.enable) { \ 602 if (!voltage_level_tick) \ 603 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 604 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 605 } 606 607 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 608 if (dc->debug.bw_val_profile.enable) \ 609 voltage_level_tick = dm_get_timestamp(dc->ctx) 610 611 #define BW_VAL_TRACE_END_WATERMARKS() \ 612 if (dc->debug.bw_val_profile.enable) \ 613 watermark_tick = dm_get_timestamp(dc->ctx) 614 615 #define BW_VAL_TRACE_FINISH() \ 616 if (dc->debug.bw_val_profile.enable) { \ 617 end_tick = dm_get_timestamp(dc->ctx); \ 618 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 619 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 620 if (watermark_tick) { \ 621 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 622 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 623 } \ 624 } 625 626 union mem_low_power_enable_options { 627 struct { 628 bool vga: 1; 629 bool i2c: 1; 630 bool dmcu: 1; 631 bool dscl: 1; 632 bool cm: 1; 633 bool mpc: 1; 634 bool optc: 1; 635 bool vpg: 1; 636 bool afmt: 1; 637 } bits; 638 uint32_t u32All; 639 }; 640 641 union root_clock_optimization_options { 642 struct { 643 bool dpp: 1; 644 bool dsc: 1; 645 bool hdmistream: 1; 646 bool hdmichar: 1; 647 bool dpstream: 1; 648 bool symclk32_se: 1; 649 bool symclk32_le: 1; 650 bool symclk_fe: 1; 651 bool physymclk: 1; 652 bool dpiasymclk: 1; 653 uint32_t reserved: 22; 654 } bits; 655 uint32_t u32All; 656 }; 657 658 union fine_grain_clock_gating_enable_options { 659 struct { 660 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 661 bool dchub : 1; /* Display controller hub */ 662 bool dchubbub : 1; 663 bool dpp : 1; /* Display pipes and planes */ 664 bool opp : 1; /* Output pixel processing */ 665 bool optc : 1; /* Output pipe timing combiner */ 666 bool dio : 1; /* Display output */ 667 bool dwb : 1; /* Display writeback */ 668 bool mmhubbub : 1; /* Multimedia hub */ 669 bool dmu : 1; /* Display core management unit */ 670 bool az : 1; /* Azalia */ 671 bool dchvm : 1; 672 bool dsc : 1; /* Display stream compression */ 673 674 uint32_t reserved : 19; 675 } bits; 676 uint32_t u32All; 677 }; 678 679 enum pg_hw_pipe_resources { 680 PG_HUBP = 0, 681 PG_DPP, 682 PG_DSC, 683 PG_MPCC, 684 PG_OPP, 685 PG_OPTC, 686 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 687 }; 688 689 enum pg_hw_resources { 690 PG_DCCG = 0, 691 PG_DCIO, 692 PG_DIO, 693 PG_DCHUBBUB, 694 PG_DCHVM, 695 PG_DWB, 696 PG_HPO, 697 PG_HW_RESOURCES_NUM_ELEMENT 698 }; 699 700 struct pg_block_update { 701 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 702 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 703 }; 704 705 union dpia_debug_options { 706 struct { 707 uint32_t disable_dpia:1; /* bit 0 */ 708 uint32_t force_non_lttpr:1; /* bit 1 */ 709 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 710 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 711 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 712 uint32_t reserved:27; 713 } bits; 714 uint32_t raw; 715 }; 716 717 /* AUX wake work around options 718 * 0: enable/disable work around 719 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 720 * 15-2: reserved 721 * 31-16: timeout in ms 722 */ 723 union aux_wake_wa_options { 724 struct { 725 uint32_t enable_wa : 1; 726 uint32_t use_default_timeout : 1; 727 uint32_t rsvd: 14; 728 uint32_t timeout_ms : 16; 729 } bits; 730 uint32_t raw; 731 }; 732 733 struct dc_debug_data { 734 uint32_t ltFailCount; 735 uint32_t i2cErrorCount; 736 uint32_t auxErrorCount; 737 }; 738 739 struct dc_phy_addr_space_config { 740 struct { 741 uint64_t start_addr; 742 uint64_t end_addr; 743 uint64_t fb_top; 744 uint64_t fb_offset; 745 uint64_t fb_base; 746 uint64_t agp_top; 747 uint64_t agp_bot; 748 uint64_t agp_base; 749 } system_aperture; 750 751 struct { 752 uint64_t page_table_start_addr; 753 uint64_t page_table_end_addr; 754 uint64_t page_table_base_addr; 755 bool base_addr_is_mc_addr; 756 } gart_config; 757 758 bool valid; 759 bool is_hvm_enabled; 760 uint64_t page_table_default_page_addr; 761 }; 762 763 struct dc_virtual_addr_space_config { 764 uint64_t page_table_base_addr; 765 uint64_t page_table_start_addr; 766 uint64_t page_table_end_addr; 767 uint32_t page_table_block_size_in_bytes; 768 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 769 }; 770 771 struct dc_bounding_box_overrides { 772 int sr_exit_time_ns; 773 int sr_enter_plus_exit_time_ns; 774 int sr_exit_z8_time_ns; 775 int sr_enter_plus_exit_z8_time_ns; 776 int urgent_latency_ns; 777 int percent_of_ideal_drambw; 778 int dram_clock_change_latency_ns; 779 int dummy_clock_change_latency_ns; 780 int fclk_clock_change_latency_ns; 781 /* This forces a hard min on the DCFCLK we use 782 * for DML. Unlike the debug option for forcing 783 * DCFCLK, this override affects watermark calculations 784 */ 785 int min_dcfclk_mhz; 786 }; 787 788 struct dc_state; 789 struct resource_pool; 790 struct dce_hwseq; 791 struct link_service; 792 793 /* 794 * struct dc_debug_options - DC debug struct 795 * 796 * This struct provides a simple mechanism for developers to change some 797 * configurations, enable/disable features, and activate extra debug options. 798 * This can be very handy to narrow down whether some specific feature is 799 * causing an issue or not. 800 */ 801 struct dc_debug_options { 802 bool native422_support; 803 bool disable_dsc; 804 enum visual_confirm visual_confirm; 805 int visual_confirm_rect_height; 806 807 bool sanity_checks; 808 bool max_disp_clk; 809 bool surface_trace; 810 bool timing_trace; 811 bool clock_trace; 812 bool validation_trace; 813 bool bandwidth_calcs_trace; 814 int max_downscale_src_width; 815 816 /* stutter efficiency related */ 817 bool disable_stutter; 818 bool use_max_lb; 819 enum dcc_option disable_dcc; 820 821 /* 822 * @pipe_split_policy: Define which pipe split policy is used by the 823 * display core. 824 */ 825 enum pipe_split_policy pipe_split_policy; 826 bool force_single_disp_pipe_split; 827 bool voltage_align_fclk; 828 bool disable_min_fclk; 829 830 bool disable_dfs_bypass; 831 bool disable_dpp_power_gate; 832 bool disable_hubp_power_gate; 833 bool disable_dsc_power_gate; 834 bool disable_optc_power_gate; 835 bool disable_hpo_power_gate; 836 int dsc_min_slice_height_override; 837 int dsc_bpp_increment_div; 838 bool disable_pplib_wm_range; 839 enum wm_report_mode pplib_wm_report_mode; 840 unsigned int min_disp_clk_khz; 841 unsigned int min_dpp_clk_khz; 842 unsigned int min_dram_clk_khz; 843 int sr_exit_time_dpm0_ns; 844 int sr_enter_plus_exit_time_dpm0_ns; 845 int sr_exit_time_ns; 846 int sr_enter_plus_exit_time_ns; 847 int sr_exit_z8_time_ns; 848 int sr_enter_plus_exit_z8_time_ns; 849 int urgent_latency_ns; 850 uint32_t underflow_assert_delay_us; 851 int percent_of_ideal_drambw; 852 int dram_clock_change_latency_ns; 853 bool optimized_watermark; 854 int always_scale; 855 bool disable_pplib_clock_request; 856 bool disable_clock_gate; 857 bool disable_mem_low_power; 858 bool pstate_enabled; 859 bool disable_dmcu; 860 bool force_abm_enable; 861 bool disable_stereo_support; 862 bool vsr_support; 863 bool performance_trace; 864 bool az_endpoint_mute_only; 865 bool always_use_regamma; 866 bool recovery_enabled; 867 bool avoid_vbios_exec_table; 868 bool scl_reset_length10; 869 bool hdmi20_disable; 870 bool skip_detection_link_training; 871 uint32_t edid_read_retry_times; 872 unsigned int force_odm_combine; //bit vector based on otg inst 873 unsigned int seamless_boot_odm_combine; 874 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 875 int minimum_z8_residency_time; 876 bool disable_z9_mpc; 877 unsigned int force_fclk_khz; 878 bool enable_tri_buf; 879 bool dmub_offload_enabled; 880 bool dmcub_emulation; 881 bool disable_idle_power_optimizations; 882 unsigned int mall_size_override; 883 unsigned int mall_additional_timer_percent; 884 bool mall_error_as_fatal; 885 bool dmub_command_table; /* for testing only */ 886 struct dc_bw_validation_profile bw_val_profile; 887 bool disable_fec; 888 bool disable_48mhz_pwrdwn; 889 /* This forces a hard min on the DCFCLK requested to SMU/PP 890 * watermarks are not affected. 891 */ 892 unsigned int force_min_dcfclk_mhz; 893 int dwb_fi_phase; 894 bool disable_timing_sync; 895 bool cm_in_bypass; 896 int force_clock_mode;/*every mode change.*/ 897 898 bool disable_dram_clock_change_vactive_support; 899 bool validate_dml_output; 900 bool enable_dmcub_surface_flip; 901 bool usbc_combo_phy_reset_wa; 902 bool enable_dram_clock_change_one_display_vactive; 903 /* TODO - remove once tested */ 904 bool legacy_dp2_lt; 905 bool set_mst_en_for_sst; 906 bool disable_uhbr; 907 bool force_dp2_lt_fallback_method; 908 bool ignore_cable_id; 909 union mem_low_power_enable_options enable_mem_low_power; 910 union root_clock_optimization_options root_clock_optimization; 911 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 912 bool hpo_optimization; 913 bool force_vblank_alignment; 914 915 /* Enable dmub aux for legacy ddc */ 916 bool enable_dmub_aux_for_legacy_ddc; 917 bool disable_fams; 918 bool disable_fams_gaming; 919 /* FEC/PSR1 sequence enable delay in 100us */ 920 uint8_t fec_enable_delay_in100us; 921 bool enable_driver_sequence_debug; 922 enum det_size crb_alloc_policy; 923 int crb_alloc_policy_min_disp_count; 924 bool disable_z10; 925 bool enable_z9_disable_interface; 926 bool psr_skip_crtc_disable; 927 union dpia_debug_options dpia_debug; 928 bool disable_fixed_vs_aux_timeout_wa; 929 uint32_t fixed_vs_aux_delay_config_wa; 930 bool force_disable_subvp; 931 bool force_subvp_mclk_switch; 932 bool allow_sw_cursor_fallback; 933 unsigned int force_subvp_num_ways; 934 unsigned int force_mall_ss_num_ways; 935 bool alloc_extra_way_for_cursor; 936 uint32_t subvp_extra_lines; 937 bool force_usr_allow; 938 /* uses value at boot and disables switch */ 939 bool disable_dtb_ref_clk_switch; 940 bool extended_blank_optimization; 941 union aux_wake_wa_options aux_wake_wa; 942 uint32_t mst_start_top_delay; 943 uint8_t psr_power_use_phy_fsm; 944 enum dml_hostvm_override_opts dml_hostvm_override; 945 bool dml_disallow_alternate_prefetch_modes; 946 bool use_legacy_soc_bb_mechanism; 947 bool exit_idle_opt_for_cursor_updates; 948 bool using_dml2; 949 bool enable_single_display_2to1_odm_policy; 950 bool enable_double_buffered_dsc_pg_support; 951 bool enable_dp_dig_pixel_rate_div_policy; 952 enum lttpr_mode lttpr_mode_override; 953 unsigned int dsc_delay_factor_wa_x1000; 954 unsigned int min_prefetch_in_strobe_ns; 955 bool disable_unbounded_requesting; 956 bool dig_fifo_off_in_blank; 957 bool temp_mst_deallocation_sequence; 958 bool override_dispclk_programming; 959 bool otg_crc_db; 960 bool disallow_dispclk_dppclk_ds; 961 bool disable_fpo_optimizations; 962 bool support_eDP1_5; 963 uint32_t fpo_vactive_margin_us; 964 bool disable_fpo_vactive; 965 bool disable_boot_optimizations; 966 bool override_odm_optimization; 967 bool minimize_dispclk_using_odm; 968 bool disable_subvp_high_refresh; 969 bool disable_dp_plus_plus_wa; 970 uint32_t fpo_vactive_min_active_margin_us; 971 uint32_t fpo_vactive_max_blank_us; 972 bool enable_hpo_pg_support; 973 bool enable_legacy_fast_update; 974 bool disable_dc_mode_overwrite; 975 bool replay_skip_crtc_disabled; 976 bool ignore_pg;/*do nothing, let pmfw control it*/ 977 bool psp_disabled_wa; 978 unsigned int ips2_eval_delay_us; 979 unsigned int ips2_entry_delay_us; 980 }; 981 982 struct gpu_info_soc_bounding_box_v1_0; 983 984 /* Generic structure that can be used to query properties of DC. More fields 985 * can be added as required. 986 */ 987 struct dc_current_properties { 988 unsigned int cursor_size_limit; 989 }; 990 991 struct dc { 992 struct dc_debug_options debug; 993 struct dc_versions versions; 994 struct dc_caps caps; 995 struct dc_cap_funcs cap_funcs; 996 struct dc_config config; 997 struct dc_bounding_box_overrides bb_overrides; 998 struct dc_bug_wa work_arounds; 999 struct dc_context *ctx; 1000 struct dc_phy_addr_space_config vm_pa_config; 1001 1002 uint8_t link_count; 1003 struct dc_link *links[MAX_PIPES * 2]; 1004 struct link_service *link_srv; 1005 1006 struct dc_state *current_state; 1007 struct resource_pool *res_pool; 1008 1009 struct clk_mgr *clk_mgr; 1010 1011 /* Display Engine Clock levels */ 1012 struct dm_pp_clock_levels sclk_lvls; 1013 1014 /* Inputs into BW and WM calculations. */ 1015 struct bw_calcs_dceip *bw_dceip; 1016 struct bw_calcs_vbios *bw_vbios; 1017 struct dcn_soc_bounding_box *dcn_soc; 1018 struct dcn_ip_params *dcn_ip; 1019 struct display_mode_lib dml; 1020 1021 /* HW functions */ 1022 struct hw_sequencer_funcs hwss; 1023 struct dce_hwseq *hwseq; 1024 1025 /* Require to optimize clocks and bandwidth for added/removed planes */ 1026 bool optimized_required; 1027 bool wm_optimized_required; 1028 bool idle_optimizations_allowed; 1029 bool enable_c20_dtm_b0; 1030 1031 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1032 1033 /* FBC compressor */ 1034 struct compressor *fbc_compressor; 1035 1036 struct dc_debug_data debug_data; 1037 struct dpcd_vendor_signature vendor_signature; 1038 1039 const char *build_id; 1040 struct vm_helper *vm_helper; 1041 1042 uint32_t *dcn_reg_offsets; 1043 uint32_t *nbio_reg_offsets; 1044 uint32_t *clk_reg_offsets; 1045 1046 /* Scratch memory */ 1047 struct { 1048 struct { 1049 /* 1050 * For matching clock_limits table in driver with table 1051 * from PMFW. 1052 */ 1053 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1054 } update_bw_bounding_box; 1055 } scratch; 1056 1057 struct dml2_configuration_options dml2_options; 1058 }; 1059 1060 enum frame_buffer_mode { 1061 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1062 FRAME_BUFFER_MODE_ZFB_ONLY, 1063 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1064 } ; 1065 1066 struct dchub_init_data { 1067 int64_t zfb_phys_addr_base; 1068 int64_t zfb_mc_base_addr; 1069 uint64_t zfb_size_in_byte; 1070 enum frame_buffer_mode fb_mode; 1071 bool dchub_initialzied; 1072 bool dchub_info_valid; 1073 }; 1074 1075 struct dc_init_data { 1076 struct hw_asic_id asic_id; 1077 void *driver; /* ctx */ 1078 struct cgs_device *cgs_device; 1079 struct dc_bounding_box_overrides bb_overrides; 1080 1081 int num_virtual_links; 1082 /* 1083 * If 'vbios_override' not NULL, it will be called instead 1084 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1085 */ 1086 struct dc_bios *vbios_override; 1087 enum dce_environment dce_environment; 1088 1089 struct dmub_offload_funcs *dmub_if; 1090 struct dc_reg_helper_state *dmub_offload; 1091 1092 struct dc_config flags; 1093 uint64_t log_mask; 1094 1095 struct dpcd_vendor_signature vendor_signature; 1096 bool force_smu_not_present; 1097 /* 1098 * IP offset for run time initializaion of register addresses 1099 * 1100 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1101 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1102 * before them. 1103 */ 1104 uint32_t *dcn_reg_offsets; 1105 uint32_t *nbio_reg_offsets; 1106 uint32_t *clk_reg_offsets; 1107 }; 1108 1109 struct dc_callback_init { 1110 struct cp_psp cp_psp; 1111 }; 1112 1113 struct dc *dc_create(const struct dc_init_data *init_params); 1114 void dc_hardware_init(struct dc *dc); 1115 1116 int dc_get_vmid_use_vector(struct dc *dc); 1117 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1118 /* Returns the number of vmids supported */ 1119 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1120 void dc_init_callbacks(struct dc *dc, 1121 const struct dc_callback_init *init_params); 1122 void dc_deinit_callbacks(struct dc *dc); 1123 void dc_destroy(struct dc **dc); 1124 1125 /* Surface Interfaces */ 1126 1127 enum { 1128 TRANSFER_FUNC_POINTS = 1025 1129 }; 1130 1131 struct dc_hdr_static_metadata { 1132 /* display chromaticities and white point in units of 0.00001 */ 1133 unsigned int chromaticity_green_x; 1134 unsigned int chromaticity_green_y; 1135 unsigned int chromaticity_blue_x; 1136 unsigned int chromaticity_blue_y; 1137 unsigned int chromaticity_red_x; 1138 unsigned int chromaticity_red_y; 1139 unsigned int chromaticity_white_point_x; 1140 unsigned int chromaticity_white_point_y; 1141 1142 uint32_t min_luminance; 1143 uint32_t max_luminance; 1144 uint32_t maximum_content_light_level; 1145 uint32_t maximum_frame_average_light_level; 1146 }; 1147 1148 enum dc_transfer_func_type { 1149 TF_TYPE_PREDEFINED, 1150 TF_TYPE_DISTRIBUTED_POINTS, 1151 TF_TYPE_BYPASS, 1152 TF_TYPE_HWPWL 1153 }; 1154 1155 struct dc_transfer_func_distributed_points { 1156 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1157 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1158 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1159 1160 uint16_t end_exponent; 1161 uint16_t x_point_at_y1_red; 1162 uint16_t x_point_at_y1_green; 1163 uint16_t x_point_at_y1_blue; 1164 }; 1165 1166 enum dc_transfer_func_predefined { 1167 TRANSFER_FUNCTION_SRGB, 1168 TRANSFER_FUNCTION_BT709, 1169 TRANSFER_FUNCTION_PQ, 1170 TRANSFER_FUNCTION_LINEAR, 1171 TRANSFER_FUNCTION_UNITY, 1172 TRANSFER_FUNCTION_HLG, 1173 TRANSFER_FUNCTION_HLG12, 1174 TRANSFER_FUNCTION_GAMMA22, 1175 TRANSFER_FUNCTION_GAMMA24, 1176 TRANSFER_FUNCTION_GAMMA26 1177 }; 1178 1179 1180 struct dc_transfer_func { 1181 struct kref refcount; 1182 enum dc_transfer_func_type type; 1183 enum dc_transfer_func_predefined tf; 1184 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1185 uint32_t sdr_ref_white_level; 1186 union { 1187 struct pwl_params pwl; 1188 struct dc_transfer_func_distributed_points tf_pts; 1189 }; 1190 }; 1191 1192 1193 union dc_3dlut_state { 1194 struct { 1195 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1196 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1197 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1198 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1199 uint32_t mpc_rmu1_mux:4; 1200 uint32_t mpc_rmu2_mux:4; 1201 uint32_t reserved:15; 1202 } bits; 1203 uint32_t raw; 1204 }; 1205 1206 1207 struct dc_3dlut { 1208 struct kref refcount; 1209 struct tetrahedral_params lut_3d; 1210 struct fixed31_32 hdr_multiplier; 1211 union dc_3dlut_state state; 1212 }; 1213 /* 1214 * This structure is filled in by dc_surface_get_status and contains 1215 * the last requested address and the currently active address so the called 1216 * can determine if there are any outstanding flips 1217 */ 1218 struct dc_plane_status { 1219 struct dc_plane_address requested_address; 1220 struct dc_plane_address current_address; 1221 bool is_flip_pending; 1222 bool is_right_eye; 1223 }; 1224 1225 union surface_update_flags { 1226 1227 struct { 1228 uint32_t addr_update:1; 1229 /* Medium updates */ 1230 uint32_t dcc_change:1; 1231 uint32_t color_space_change:1; 1232 uint32_t horizontal_mirror_change:1; 1233 uint32_t per_pixel_alpha_change:1; 1234 uint32_t global_alpha_change:1; 1235 uint32_t hdr_mult:1; 1236 uint32_t rotation_change:1; 1237 uint32_t swizzle_change:1; 1238 uint32_t scaling_change:1; 1239 uint32_t position_change:1; 1240 uint32_t in_transfer_func_change:1; 1241 uint32_t input_csc_change:1; 1242 uint32_t coeff_reduction_change:1; 1243 uint32_t output_tf_change:1; 1244 uint32_t pixel_format_change:1; 1245 uint32_t plane_size_change:1; 1246 uint32_t gamut_remap_change:1; 1247 1248 /* Full updates */ 1249 uint32_t new_plane:1; 1250 uint32_t bpp_change:1; 1251 uint32_t gamma_change:1; 1252 uint32_t bandwidth_change:1; 1253 uint32_t clock_change:1; 1254 uint32_t stereo_format_change:1; 1255 uint32_t lut_3d:1; 1256 uint32_t tmz_changed:1; 1257 uint32_t full_update:1; 1258 } bits; 1259 1260 uint32_t raw; 1261 }; 1262 1263 struct dc_plane_state { 1264 struct dc_plane_address address; 1265 struct dc_plane_flip_time time; 1266 bool triplebuffer_flips; 1267 struct scaling_taps scaling_quality; 1268 struct rect src_rect; 1269 struct rect dst_rect; 1270 struct rect clip_rect; 1271 1272 struct plane_size plane_size; 1273 union dc_tiling_info tiling_info; 1274 1275 struct dc_plane_dcc_param dcc; 1276 1277 struct dc_gamma *gamma_correction; 1278 struct dc_transfer_func *in_transfer_func; 1279 struct dc_bias_and_scale *bias_and_scale; 1280 struct dc_csc_transform input_csc_color_matrix; 1281 struct fixed31_32 coeff_reduction_factor; 1282 struct fixed31_32 hdr_mult; 1283 struct colorspace_transform gamut_remap_matrix; 1284 1285 // TODO: No longer used, remove 1286 struct dc_hdr_static_metadata hdr_static_ctx; 1287 1288 enum dc_color_space color_space; 1289 1290 struct dc_3dlut *lut3d_func; 1291 struct dc_transfer_func *in_shaper_func; 1292 struct dc_transfer_func *blend_tf; 1293 1294 struct dc_transfer_func *gamcor_tf; 1295 enum surface_pixel_format format; 1296 enum dc_rotation_angle rotation; 1297 enum plane_stereo_format stereo_format; 1298 1299 bool is_tiling_rotated; 1300 bool per_pixel_alpha; 1301 bool pre_multiplied_alpha; 1302 bool global_alpha; 1303 int global_alpha_value; 1304 bool visible; 1305 bool flip_immediate; 1306 bool horizontal_mirror; 1307 int layer_index; 1308 1309 union surface_update_flags update_flags; 1310 bool flip_int_enabled; 1311 bool skip_manual_trigger; 1312 1313 /* private to DC core */ 1314 struct dc_plane_status status; 1315 struct dc_context *ctx; 1316 1317 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1318 bool force_full_update; 1319 1320 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1321 1322 /* private to dc_surface.c */ 1323 enum dc_irq_source irq_source; 1324 struct kref refcount; 1325 struct tg_color visual_confirm_color; 1326 1327 bool is_statically_allocated; 1328 }; 1329 1330 struct dc_plane_info { 1331 struct plane_size plane_size; 1332 union dc_tiling_info tiling_info; 1333 struct dc_plane_dcc_param dcc; 1334 enum surface_pixel_format format; 1335 enum dc_rotation_angle rotation; 1336 enum plane_stereo_format stereo_format; 1337 enum dc_color_space color_space; 1338 bool horizontal_mirror; 1339 bool visible; 1340 bool per_pixel_alpha; 1341 bool pre_multiplied_alpha; 1342 bool global_alpha; 1343 int global_alpha_value; 1344 bool input_csc_enabled; 1345 int layer_index; 1346 }; 1347 1348 struct dc_scaling_info { 1349 struct rect src_rect; 1350 struct rect dst_rect; 1351 struct rect clip_rect; 1352 struct scaling_taps scaling_quality; 1353 }; 1354 1355 struct dc_fast_update { 1356 const struct dc_flip_addrs *flip_addr; 1357 const struct dc_gamma *gamma; 1358 const struct colorspace_transform *gamut_remap_matrix; 1359 const struct dc_csc_transform *input_csc_color_matrix; 1360 const struct fixed31_32 *coeff_reduction_factor; 1361 struct dc_transfer_func *out_transfer_func; 1362 struct dc_csc_transform *output_csc_transform; 1363 }; 1364 1365 struct dc_surface_update { 1366 struct dc_plane_state *surface; 1367 1368 /* isr safe update parameters. null means no updates */ 1369 const struct dc_flip_addrs *flip_addr; 1370 const struct dc_plane_info *plane_info; 1371 const struct dc_scaling_info *scaling_info; 1372 struct fixed31_32 hdr_mult; 1373 /* following updates require alloc/sleep/spin that is not isr safe, 1374 * null means no updates 1375 */ 1376 const struct dc_gamma *gamma; 1377 const struct dc_transfer_func *in_transfer_func; 1378 1379 const struct dc_csc_transform *input_csc_color_matrix; 1380 const struct fixed31_32 *coeff_reduction_factor; 1381 const struct dc_transfer_func *func_shaper; 1382 const struct dc_3dlut *lut3d_func; 1383 const struct dc_transfer_func *blend_tf; 1384 const struct colorspace_transform *gamut_remap_matrix; 1385 }; 1386 1387 /* 1388 * Create a new surface with default parameters; 1389 */ 1390 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1391 const struct dc_plane_status *dc_plane_get_status( 1392 const struct dc_plane_state *plane_state); 1393 1394 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1395 void dc_plane_state_release(struct dc_plane_state *plane_state); 1396 1397 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1398 void dc_gamma_release(struct dc_gamma **dc_gamma); 1399 struct dc_gamma *dc_create_gamma(void); 1400 1401 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1402 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1403 struct dc_transfer_func *dc_create_transfer_func(void); 1404 1405 struct dc_3dlut *dc_create_3dlut_func(void); 1406 void dc_3dlut_func_release(struct dc_3dlut *lut); 1407 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1408 1409 void dc_post_update_surfaces_to_stream( 1410 struct dc *dc); 1411 1412 #include "dc_stream.h" 1413 1414 /** 1415 * struct dc_validation_set - Struct to store surface/stream associations for validation 1416 */ 1417 struct dc_validation_set { 1418 /** 1419 * @stream: Stream state properties 1420 */ 1421 struct dc_stream_state *stream; 1422 1423 /** 1424 * @plane_states: Surface state 1425 */ 1426 struct dc_plane_state *plane_states[MAX_SURFACES]; 1427 1428 /** 1429 * @plane_count: Total of active planes 1430 */ 1431 uint8_t plane_count; 1432 }; 1433 1434 bool dc_validate_boot_timing(const struct dc *dc, 1435 const struct dc_sink *sink, 1436 struct dc_crtc_timing *crtc_timing); 1437 1438 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1439 1440 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1441 1442 enum dc_status dc_validate_with_context(struct dc *dc, 1443 const struct dc_validation_set set[], 1444 int set_count, 1445 struct dc_state *context, 1446 bool fast_validate); 1447 1448 bool dc_set_generic_gpio_for_stereo(bool enable, 1449 struct gpio_service *gpio_service); 1450 1451 /* 1452 * fast_validate: we return after determining if we can support the new state, 1453 * but before we populate the programming info 1454 */ 1455 enum dc_status dc_validate_global_state( 1456 struct dc *dc, 1457 struct dc_state *new_ctx, 1458 bool fast_validate); 1459 1460 1461 void dc_resource_state_construct( 1462 const struct dc *dc, 1463 struct dc_state *dst_ctx); 1464 1465 bool dc_acquire_release_mpc_3dlut( 1466 struct dc *dc, bool acquire, 1467 struct dc_stream_state *stream, 1468 struct dc_3dlut **lut, 1469 struct dc_transfer_func **shaper); 1470 1471 void dc_resource_state_copy_construct( 1472 const struct dc_state *src_ctx, 1473 struct dc_state *dst_ctx); 1474 1475 void dc_resource_state_copy_construct_current( 1476 const struct dc *dc, 1477 struct dc_state *dst_ctx); 1478 1479 void dc_resource_state_destruct(struct dc_state *context); 1480 1481 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1482 1483 enum dc_status dc_commit_streams(struct dc *dc, 1484 struct dc_stream_state *streams[], 1485 uint8_t stream_count); 1486 1487 struct dc_state *dc_create_state(struct dc *dc); 1488 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1489 void dc_retain_state(struct dc_state *context); 1490 void dc_release_state(struct dc_state *context); 1491 1492 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1493 struct dc_stream_state *stream, 1494 int mpcc_inst); 1495 1496 1497 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1498 1499 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1500 1501 /* The function returns minimum bandwidth required to drive a given timing 1502 * return - minimum required timing bandwidth in kbps. 1503 */ 1504 uint32_t dc_bandwidth_in_kbps_from_timing( 1505 const struct dc_crtc_timing *timing, 1506 const enum dc_link_encoding_format link_encoding); 1507 1508 /* Link Interfaces */ 1509 /* 1510 * A link contains one or more sinks and their connected status. 1511 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1512 */ 1513 struct dc_link { 1514 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1515 unsigned int sink_count; 1516 struct dc_sink *local_sink; 1517 unsigned int link_index; 1518 enum dc_connection_type type; 1519 enum signal_type connector_signal; 1520 enum dc_irq_source irq_source_hpd; 1521 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1522 1523 bool is_hpd_filter_disabled; 1524 bool dp_ss_off; 1525 1526 /** 1527 * @link_state_valid: 1528 * 1529 * If there is no link and local sink, this variable should be set to 1530 * false. Otherwise, it should be set to true; usually, the function 1531 * core_link_enable_stream sets this field to true. 1532 */ 1533 bool link_state_valid; 1534 bool aux_access_disabled; 1535 bool sync_lt_in_progress; 1536 bool skip_stream_reenable; 1537 bool is_internal_display; 1538 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1539 bool is_dig_mapping_flexible; 1540 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1541 bool is_hpd_pending; /* Indicates a new received hpd */ 1542 bool is_automated; /* Indicates automated testing */ 1543 1544 bool edp_sink_present; 1545 1546 struct dp_trace dp_trace; 1547 1548 /* caps is the same as reported_link_cap. link_traing use 1549 * reported_link_cap. Will clean up. TODO 1550 */ 1551 struct dc_link_settings reported_link_cap; 1552 struct dc_link_settings verified_link_cap; 1553 struct dc_link_settings cur_link_settings; 1554 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1555 struct dc_link_settings preferred_link_setting; 1556 /* preferred_training_settings are override values that 1557 * come from DM. DM is responsible for the memory 1558 * management of the override pointers. 1559 */ 1560 struct dc_link_training_overrides preferred_training_settings; 1561 struct dp_audio_test_data audio_test_data; 1562 1563 uint8_t ddc_hw_inst; 1564 1565 uint8_t hpd_src; 1566 1567 uint8_t link_enc_hw_inst; 1568 /* DIG link encoder ID. Used as index in link encoder resource pool. 1569 * For links with fixed mapping to DIG, this is not changed after dc_link 1570 * object creation. 1571 */ 1572 enum engine_id eng_id; 1573 enum engine_id dpia_preferred_eng_id; 1574 1575 bool test_pattern_enabled; 1576 enum dp_test_pattern current_test_pattern; 1577 union compliance_test_state compliance_test_state; 1578 1579 void *priv; 1580 1581 struct ddc_service *ddc; 1582 1583 enum dp_panel_mode panel_mode; 1584 bool aux_mode; 1585 1586 /* Private to DC core */ 1587 1588 const struct dc *dc; 1589 1590 struct dc_context *ctx; 1591 1592 struct panel_cntl *panel_cntl; 1593 struct link_encoder *link_enc; 1594 struct graphics_object_id link_id; 1595 /* Endpoint type distinguishes display endpoints which do not have entries 1596 * in the BIOS connector table from those that do. Helps when tracking link 1597 * encoder to display endpoint assignments. 1598 */ 1599 enum display_endpoint_type ep_type; 1600 union ddi_channel_mapping ddi_channel_mapping; 1601 struct connector_device_tag_info device_tag; 1602 struct dpcd_caps dpcd_caps; 1603 uint32_t dongle_max_pix_clk; 1604 unsigned short chip_caps; 1605 unsigned int dpcd_sink_count; 1606 struct hdcp_caps hdcp_caps; 1607 enum edp_revision edp_revision; 1608 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1609 1610 struct backlight_settings backlight_settings; 1611 struct psr_settings psr_settings; 1612 1613 struct replay_settings replay_settings; 1614 1615 /* Drive settings read from integrated info table */ 1616 struct dc_lane_settings bios_forced_drive_settings; 1617 1618 /* Vendor specific LTTPR workaround variables */ 1619 uint8_t vendor_specific_lttpr_link_rate_wa; 1620 bool apply_vendor_specific_lttpr_link_rate_wa; 1621 1622 /* MST record stream using this link */ 1623 struct link_flags { 1624 bool dp_keep_receiver_powered; 1625 bool dp_skip_DID2; 1626 bool dp_skip_reset_segment; 1627 bool dp_skip_fs_144hz; 1628 bool dp_mot_reset_segment; 1629 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1630 bool dpia_mst_dsc_always_on; 1631 /* Forced DPIA into TBT3 compatibility mode. */ 1632 bool dpia_forced_tbt3_mode; 1633 bool dongle_mode_timing_override; 1634 bool blank_stream_on_ocs_change; 1635 bool read_dpcd204h_on_irq_hpd; 1636 } wa_flags; 1637 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1638 1639 struct dc_link_status link_status; 1640 struct dprx_states dprx_states; 1641 1642 struct gpio *hpd_gpio; 1643 enum dc_link_fec_state fec_state; 1644 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1645 1646 struct dc_panel_config panel_config; 1647 struct phy_state phy_state; 1648 // BW ALLOCATON USB4 ONLY 1649 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1650 bool skip_implict_edp_power_control; 1651 }; 1652 1653 /* Return an enumerated dc_link. 1654 * dc_link order is constant and determined at 1655 * boot time. They cannot be created or destroyed. 1656 * Use dc_get_caps() to get number of links. 1657 */ 1658 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1659 1660 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1661 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1662 const struct dc_link *link, 1663 unsigned int *inst_out); 1664 1665 /* Return an array of link pointers to edp links. */ 1666 void dc_get_edp_links(const struct dc *dc, 1667 struct dc_link **edp_links, 1668 int *edp_num); 1669 1670 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1671 bool powerOn); 1672 1673 /* The function initiates detection handshake over the given link. It first 1674 * determines if there are display connections over the link. If so it initiates 1675 * detection protocols supported by the connected receiver device. The function 1676 * contains protocol specific handshake sequences which are sometimes mandatory 1677 * to establish a proper connection between TX and RX. So it is always 1678 * recommended to call this function as the first link operation upon HPD event 1679 * or power up event. Upon completion, the function will update link structure 1680 * in place based on latest RX capabilities. The function may also cause dpms 1681 * to be reset to off for all currently enabled streams to the link. It is DM's 1682 * responsibility to serialize detection and DPMS updates. 1683 * 1684 * @reason - Indicate which event triggers this detection. dc may customize 1685 * detection flow depending on the triggering events. 1686 * return false - if detection is not fully completed. This could happen when 1687 * there is an unrecoverable error during detection or detection is partially 1688 * completed (detection has been delegated to dm mst manager ie. 1689 * link->connection_type == dc_connection_mst_branch when returning false). 1690 * return true - detection is completed, link has been fully updated with latest 1691 * detection result. 1692 */ 1693 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1694 1695 struct dc_sink_init_data; 1696 1697 /* When link connection type is dc_connection_mst_branch, remote sink can be 1698 * added to the link. The interface creates a remote sink and associates it with 1699 * current link. The sink will be retained by link until remove remote sink is 1700 * called. 1701 * 1702 * @dc_link - link the remote sink will be added to. 1703 * @edid - byte array of EDID raw data. 1704 * @len - size of the edid in byte 1705 * @init_data - 1706 */ 1707 struct dc_sink *dc_link_add_remote_sink( 1708 struct dc_link *dc_link, 1709 const uint8_t *edid, 1710 int len, 1711 struct dc_sink_init_data *init_data); 1712 1713 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1714 * @link - link the sink should be removed from 1715 * @sink - sink to be removed. 1716 */ 1717 void dc_link_remove_remote_sink( 1718 struct dc_link *link, 1719 struct dc_sink *sink); 1720 1721 /* Enable HPD interrupt handler for a given link */ 1722 void dc_link_enable_hpd(const struct dc_link *link); 1723 1724 /* Disable HPD interrupt handler for a given link */ 1725 void dc_link_disable_hpd(const struct dc_link *link); 1726 1727 /* determine if there is a sink connected to the link 1728 * 1729 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1730 * return - false if an unexpected error occurs, true otherwise. 1731 * 1732 * NOTE: This function doesn't detect downstream sink connections i.e 1733 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1734 * return dc_connection_single if the branch device is connected despite of 1735 * downstream sink's connection status. 1736 */ 1737 bool dc_link_detect_connection_type(struct dc_link *link, 1738 enum dc_connection_type *type); 1739 1740 /* query current hpd pin value 1741 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1742 * 1743 */ 1744 bool dc_link_get_hpd_state(struct dc_link *link); 1745 1746 /* Getter for cached link status from given link */ 1747 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1748 1749 /* enable/disable hardware HPD filter. 1750 * 1751 * @link - The link the HPD pin is associated with. 1752 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1753 * handler once after no HPD change has been detected within dc default HPD 1754 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1755 * pulses within default HPD interval, no HPD event will be received until HPD 1756 * toggles have stopped. Then HPD event will be queued to irq handler once after 1757 * dc default HPD filtering interval since last HPD event. 1758 * 1759 * @enable = false - disable hardware HPD filter. HPD event will be queued 1760 * immediately to irq handler after no HPD change has been detected within 1761 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1762 */ 1763 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1764 1765 /* submit i2c read/write payloads through ddc channel 1766 * @link_index - index to a link with ddc in i2c mode 1767 * @cmd - i2c command structure 1768 * return - true if success, false otherwise. 1769 */ 1770 bool dc_submit_i2c( 1771 struct dc *dc, 1772 uint32_t link_index, 1773 struct i2c_command *cmd); 1774 1775 /* submit i2c read/write payloads through oem channel 1776 * @link_index - index to a link with ddc in i2c mode 1777 * @cmd - i2c command structure 1778 * return - true if success, false otherwise. 1779 */ 1780 bool dc_submit_i2c_oem( 1781 struct dc *dc, 1782 struct i2c_command *cmd); 1783 1784 enum aux_return_code_type; 1785 /* Attempt to transfer the given aux payload. This function does not perform 1786 * retries or handle error states. The reply is returned in the payload->reply 1787 * and the result through operation_result. Returns the number of bytes 1788 * transferred,or -1 on a failure. 1789 */ 1790 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1791 struct aux_payload *payload, 1792 enum aux_return_code_type *operation_result); 1793 1794 bool dc_is_oem_i2c_device_present( 1795 struct dc *dc, 1796 size_t slave_address 1797 ); 1798 1799 /* return true if the connected receiver supports the hdcp version */ 1800 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1801 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1802 1803 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1804 * 1805 * TODO - When defer_handling is true the function will have a different purpose. 1806 * It no longer does complete hpd rx irq handling. We should create a separate 1807 * interface specifically for this case. 1808 * 1809 * Return: 1810 * true - Downstream port status changed. DM should call DC to do the 1811 * detection. 1812 * false - no change in Downstream port status. No further action required 1813 * from DM. 1814 */ 1815 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1816 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1817 bool defer_handling, bool *has_left_work); 1818 /* handle DP specs define test automation sequence*/ 1819 void dc_link_dp_handle_automated_test(struct dc_link *link); 1820 1821 /* handle DP Link loss sequence and try to recover RX link loss with best 1822 * effort 1823 */ 1824 void dc_link_dp_handle_link_loss(struct dc_link *link); 1825 1826 /* Determine if hpd rx irq should be handled or ignored 1827 * return true - hpd rx irq should be handled. 1828 * return false - it is safe to ignore hpd rx irq event 1829 */ 1830 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1831 1832 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1833 * @link - link the hpd irq data associated with 1834 * @hpd_irq_dpcd_data - input hpd irq data 1835 * return - true if hpd irq data indicates a link lost 1836 */ 1837 bool dc_link_check_link_loss_status(struct dc_link *link, 1838 union hpd_irq_data *hpd_irq_dpcd_data); 1839 1840 /* Read hpd rx irq data from a given link 1841 * @link - link where the hpd irq data should be read from 1842 * @irq_data - output hpd irq data 1843 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1844 * read has failed. 1845 */ 1846 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1847 struct dc_link *link, 1848 union hpd_irq_data *irq_data); 1849 1850 /* The function clears recorded DP RX states in the link. DM should call this 1851 * function when it is resuming from S3 power state to previously connected links. 1852 * 1853 * TODO - in the future we should consider to expand link resume interface to 1854 * support clearing previous rx states. So we don't have to rely on dm to call 1855 * this interface explicitly. 1856 */ 1857 void dc_link_clear_dprx_states(struct dc_link *link); 1858 1859 /* Destruct the mst topology of the link and reset the allocated payload table 1860 * 1861 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1862 * still wants to reset MST topology on an unplug event */ 1863 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1864 1865 /* The function calculates effective DP link bandwidth when a given link is 1866 * using the given link settings. 1867 * 1868 * return - total effective link bandwidth in kbps. 1869 */ 1870 uint32_t dc_link_bandwidth_kbps( 1871 const struct dc_link *link, 1872 const struct dc_link_settings *link_setting); 1873 1874 /* The function takes a snapshot of current link resource allocation state 1875 * @dc: pointer to dc of the dm calling this 1876 * @map: a dc link resource snapshot defined internally to dc. 1877 * 1878 * DM needs to capture a snapshot of current link resource allocation mapping 1879 * and store it in its persistent storage. 1880 * 1881 * Some of the link resource is using first come first serve policy. 1882 * The allocation mapping depends on original hotplug order. This information 1883 * is lost after driver is loaded next time. The snapshot is used in order to 1884 * restore link resource to its previous state so user will get consistent 1885 * link capability allocation across reboot. 1886 * 1887 */ 1888 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1889 1890 /* This function restores link resource allocation state from a snapshot 1891 * @dc: pointer to dc of the dm calling this 1892 * @map: a dc link resource snapshot defined internally to dc. 1893 * 1894 * DM needs to call this function after initial link detection on boot and 1895 * before first commit streams to restore link resource allocation state 1896 * from previous boot session. 1897 * 1898 * Some of the link resource is using first come first serve policy. 1899 * The allocation mapping depends on original hotplug order. This information 1900 * is lost after driver is loaded next time. The snapshot is used in order to 1901 * restore link resource to its previous state so user will get consistent 1902 * link capability allocation across reboot. 1903 * 1904 */ 1905 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1906 1907 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1908 * interface i.e stream_update->dsc_config 1909 */ 1910 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1911 1912 /* translate a raw link rate data to bandwidth in kbps */ 1913 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1914 1915 /* determine the optimal bandwidth given link and required bw. 1916 * @link - current detected link 1917 * @req_bw - requested bandwidth in kbps 1918 * @link_settings - returned most optimal link settings that can fit the 1919 * requested bandwidth 1920 * return - false if link can't support requested bandwidth, true if link 1921 * settings is found. 1922 */ 1923 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1924 struct dc_link_settings *link_settings, 1925 uint32_t req_bw); 1926 1927 /* return the max dp link settings can be driven by the link without considering 1928 * connected RX device and its capability 1929 */ 1930 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1931 struct dc_link_settings *max_link_enc_cap); 1932 1933 /* determine when the link is driving MST mode, what DP link channel coding 1934 * format will be used. The decision will remain unchanged until next HPD event. 1935 * 1936 * @link - a link with DP RX connection 1937 * return - if stream is committed to this link with MST signal type, type of 1938 * channel coding format dc will choose. 1939 */ 1940 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1941 const struct dc_link *link); 1942 1943 /* get max dp link settings the link can enable with all things considered. (i.e 1944 * TX/RX/Cable capabilities and dp override policies. 1945 * 1946 * @link - a link with DP RX connection 1947 * return - max dp link settings the link can enable. 1948 * 1949 */ 1950 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1951 1952 /* Get the highest encoding format that the link supports; highest meaning the 1953 * encoding format which supports the maximum bandwidth. 1954 * 1955 * @link - a link with DP RX connection 1956 * return - highest encoding format link supports. 1957 */ 1958 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 1959 1960 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1961 * to a link with dp connector signal type. 1962 * @link - a link with dp connector signal type 1963 * return - true if connected, false otherwise 1964 */ 1965 bool dc_link_is_dp_sink_present(struct dc_link *link); 1966 1967 /* Force DP lane settings update to main-link video signal and notify the change 1968 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1969 * tuning purpose. The interface assumes link has already been enabled with DP 1970 * signal. 1971 * 1972 * @lt_settings - a container structure with desired hw_lane_settings 1973 */ 1974 void dc_link_set_drive_settings(struct dc *dc, 1975 struct link_training_settings *lt_settings, 1976 struct dc_link *link); 1977 1978 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1979 * test or debugging purpose. The test pattern will remain until next un-plug. 1980 * 1981 * @link - active link with DP signal output enabled. 1982 * @test_pattern - desired test pattern to output. 1983 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1984 * @test_pattern_color_space - for video test pattern choose a desired color 1985 * space. 1986 * @p_link_settings - For PHY pattern choose a desired link settings 1987 * @p_custom_pattern - some test pattern will require a custom input to 1988 * customize some pattern details. Otherwise keep it to NULL. 1989 * @cust_pattern_size - size of the custom pattern input. 1990 * 1991 */ 1992 bool dc_link_dp_set_test_pattern( 1993 struct dc_link *link, 1994 enum dp_test_pattern test_pattern, 1995 enum dp_test_pattern_color_space test_pattern_color_space, 1996 const struct link_training_settings *p_link_settings, 1997 const unsigned char *p_custom_pattern, 1998 unsigned int cust_pattern_size); 1999 2000 /* Force DP link settings to always use a specific value until reboot to a 2001 * specific link. If link has already been enabled, the interface will also 2002 * switch to desired link settings immediately. This is a debug interface to 2003 * generic dp issue trouble shooting. 2004 */ 2005 void dc_link_set_preferred_link_settings(struct dc *dc, 2006 struct dc_link_settings *link_setting, 2007 struct dc_link *link); 2008 2009 /* Force DP link to customize a specific link training behavior by overriding to 2010 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2011 * display specific link training issues or apply some display specific 2012 * workaround in link training. 2013 * 2014 * @link_settings - if not NULL, force preferred link settings to the link. 2015 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2016 * will apply this particular override in future link training. If NULL is 2017 * passed in, dc resets previous overrides. 2018 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2019 * training settings. 2020 */ 2021 void dc_link_set_preferred_training_settings(struct dc *dc, 2022 struct dc_link_settings *link_setting, 2023 struct dc_link_training_overrides *lt_overrides, 2024 struct dc_link *link, 2025 bool skip_immediate_retrain); 2026 2027 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2028 bool dc_link_is_fec_supported(const struct dc_link *link); 2029 2030 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2031 * link enablement. 2032 * return - true if FEC should be enabled, false otherwise. 2033 */ 2034 bool dc_link_should_enable_fec(const struct dc_link *link); 2035 2036 /* determine lttpr mode the current link should be enabled with a specific link 2037 * settings. 2038 */ 2039 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2040 struct dc_link_settings *link_setting); 2041 2042 /* Force DP RX to update its power state. 2043 * NOTE: this interface doesn't update dp main-link. Calling this function will 2044 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2045 * RX power state back upon finish DM specific execution requiring DP RX in a 2046 * specific power state. 2047 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2048 * state. 2049 */ 2050 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2051 2052 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2053 * current value read from extended receiver cap from 02200h - 0220Fh. 2054 * Some DP RX has problems of providing accurate DP receiver caps from extended 2055 * field, this interface is a workaround to revert link back to use base caps. 2056 */ 2057 void dc_link_overwrite_extended_receiver_cap( 2058 struct dc_link *link); 2059 2060 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2061 bool wait_for_hpd); 2062 2063 /* Set backlight level of an embedded panel (eDP, LVDS). 2064 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2065 * and 16 bit fractional, where 1.0 is max backlight value. 2066 */ 2067 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2068 uint32_t backlight_pwm_u16_16, 2069 uint32_t frame_ramp); 2070 2071 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2072 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2073 bool isHDR, 2074 uint32_t backlight_millinits, 2075 uint32_t transition_time_in_ms); 2076 2077 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2078 uint32_t *backlight_millinits, 2079 uint32_t *backlight_millinits_peak); 2080 2081 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2082 2083 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2084 2085 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2086 bool wait, bool force_static, const unsigned int *power_opts); 2087 2088 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2089 2090 bool dc_link_setup_psr(struct dc_link *dc_link, 2091 const struct dc_stream_state *stream, struct psr_config *psr_config, 2092 struct psr_context *psr_context); 2093 2094 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2095 2096 /* On eDP links this function call will stall until T12 has elapsed. 2097 * If the panel is not in power off state, this function will return 2098 * immediately. 2099 */ 2100 bool dc_link_wait_for_t12(struct dc_link *link); 2101 2102 /* Determine if dp trace has been initialized to reflect upto date result * 2103 * return - true if trace is initialized and has valid data. False dp trace 2104 * doesn't have valid result. 2105 */ 2106 bool dc_dp_trace_is_initialized(struct dc_link *link); 2107 2108 /* Query a dp trace flag to indicate if the current dp trace data has been 2109 * logged before 2110 */ 2111 bool dc_dp_trace_is_logged(struct dc_link *link, 2112 bool in_detection); 2113 2114 /* Set dp trace flag to indicate whether DM has already logged the current dp 2115 * trace data. DM can set is_logged to true upon logging and check 2116 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2117 */ 2118 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2119 bool in_detection, 2120 bool is_logged); 2121 2122 /* Obtain driver time stamp for last dp link training end. The time stamp is 2123 * formatted based on dm_get_timestamp DM function. 2124 * @in_detection - true to get link training end time stamp of last link 2125 * training in detection sequence. false to get link training end time stamp 2126 * of last link training in commit (dpms) sequence 2127 */ 2128 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2129 bool in_detection); 2130 2131 /* Get how many link training attempts dc has done with latest sequence. 2132 * @in_detection - true to get link training count of last link 2133 * training in detection sequence. false to get link training count of last link 2134 * training in commit (dpms) sequence 2135 */ 2136 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2137 bool in_detection); 2138 2139 /* Get how many link loss has happened since last link training attempts */ 2140 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2141 2142 /* 2143 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2144 */ 2145 /* 2146 * Send a request from DP-Tx requesting to allocate BW remotely after 2147 * allocating it locally. This will get processed by CM and a CB function 2148 * will be called. 2149 * 2150 * @link: pointer to the dc_link struct instance 2151 * @req_bw: The requested bw in Kbyte to allocated 2152 * 2153 * return: none 2154 */ 2155 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2156 2157 /* 2158 * Handle function for when the status of the Request above is complete. 2159 * We will find out the result of allocating on CM and update structs. 2160 * 2161 * @link: pointer to the dc_link struct instance 2162 * @bw: Allocated or Estimated BW depending on the result 2163 * @result: Response type 2164 * 2165 * return: none 2166 */ 2167 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2168 uint8_t bw, uint8_t result); 2169 2170 /* 2171 * Handle the USB4 BW Allocation related functionality here: 2172 * Plug => Try to allocate max bw from timing parameters supported by the sink 2173 * Unplug => de-allocate bw 2174 * 2175 * @link: pointer to the dc_link struct instance 2176 * @peak_bw: Peak bw used by the link/sink 2177 * 2178 * return: allocated bw else return 0 2179 */ 2180 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2181 struct dc_link *link, int peak_bw); 2182 2183 /* 2184 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2185 * available BW for each host router 2186 * 2187 * @dc: pointer to dc struct 2188 * @stream: pointer to all possible streams 2189 * @num_streams: number of valid DPIA streams 2190 * 2191 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2192 */ 2193 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2194 const unsigned int count); 2195 2196 /* Sink Interfaces - A sink corresponds to a display output device */ 2197 2198 struct dc_container_id { 2199 // 128bit GUID in binary form 2200 unsigned char guid[16]; 2201 // 8 byte port ID -> ELD.PortID 2202 unsigned int portId[2]; 2203 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2204 unsigned short manufacturerName; 2205 // 2 byte product code -> ELD.ProductCode 2206 unsigned short productCode; 2207 }; 2208 2209 2210 struct dc_sink_dsc_caps { 2211 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2212 // 'false' if they are sink's DSC caps 2213 bool is_virtual_dpcd_dsc; 2214 #if defined(CONFIG_DRM_AMD_DC_FP) 2215 // 'true' if MST topology supports DSC passthrough for sink 2216 // 'false' if MST topology does not support DSC passthrough 2217 bool is_dsc_passthrough_supported; 2218 #endif 2219 struct dsc_dec_dpcd_caps dsc_dec_caps; 2220 }; 2221 2222 struct dc_sink_fec_caps { 2223 bool is_rx_fec_supported; 2224 bool is_topology_fec_supported; 2225 }; 2226 2227 struct scdc_caps { 2228 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2229 union hdmi_scdc_device_id_data device_id; 2230 }; 2231 2232 /* 2233 * The sink structure contains EDID and other display device properties 2234 */ 2235 struct dc_sink { 2236 enum signal_type sink_signal; 2237 struct dc_edid dc_edid; /* raw edid */ 2238 struct dc_edid_caps edid_caps; /* parse display caps */ 2239 struct dc_container_id *dc_container_id; 2240 uint32_t dongle_max_pix_clk; 2241 void *priv; 2242 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2243 bool converter_disable_audio; 2244 2245 struct scdc_caps scdc_caps; 2246 struct dc_sink_dsc_caps dsc_caps; 2247 struct dc_sink_fec_caps fec_caps; 2248 2249 bool is_vsc_sdp_colorimetry_supported; 2250 2251 /* private to DC core */ 2252 struct dc_link *link; 2253 struct dc_context *ctx; 2254 2255 uint32_t sink_id; 2256 2257 /* private to dc_sink.c */ 2258 // refcount must be the last member in dc_sink, since we want the 2259 // sink structure to be logically cloneable up to (but not including) 2260 // refcount 2261 struct kref refcount; 2262 }; 2263 2264 void dc_sink_retain(struct dc_sink *sink); 2265 void dc_sink_release(struct dc_sink *sink); 2266 2267 struct dc_sink_init_data { 2268 enum signal_type sink_signal; 2269 struct dc_link *link; 2270 uint32_t dongle_max_pix_clk; 2271 bool converter_disable_audio; 2272 }; 2273 2274 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2275 2276 /* Newer interfaces */ 2277 struct dc_cursor { 2278 struct dc_plane_address address; 2279 struct dc_cursor_attributes attributes; 2280 }; 2281 2282 2283 /* Interrupt interfaces */ 2284 enum dc_irq_source dc_interrupt_to_irq_source( 2285 struct dc *dc, 2286 uint32_t src_id, 2287 uint32_t ext_id); 2288 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2289 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2290 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2291 struct dc *dc, uint32_t link_index); 2292 2293 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2294 2295 /* Power Interfaces */ 2296 2297 void dc_set_power_state( 2298 struct dc *dc, 2299 enum dc_acpi_cm_power_state power_state); 2300 void dc_resume(struct dc *dc); 2301 2302 void dc_power_down_on_boot(struct dc *dc); 2303 2304 /* 2305 * HDCP Interfaces 2306 */ 2307 enum hdcp_message_status dc_process_hdcp_msg( 2308 enum signal_type signal, 2309 struct dc_link *link, 2310 struct hdcp_protection_message *message_info); 2311 bool dc_is_dmcu_initialized(struct dc *dc); 2312 2313 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2314 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2315 2316 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2317 struct dc_cursor_attributes *cursor_attr); 2318 2319 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2320 2321 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2322 void dc_unlock_memory_clock_frequency(struct dc *dc); 2323 2324 /* set min memory clock to the min required for current mode, max to maxDPM */ 2325 void dc_lock_memory_clock_frequency(struct dc *dc); 2326 2327 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2328 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2329 2330 /* cleanup on driver unload */ 2331 void dc_hardware_release(struct dc *dc); 2332 2333 /* disables fw based mclk switch */ 2334 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2335 2336 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2337 void dc_z10_restore(const struct dc *dc); 2338 void dc_z10_save_init(struct dc *dc); 2339 2340 bool dc_is_dmub_outbox_supported(struct dc *dc); 2341 bool dc_enable_dmub_notifications(struct dc *dc); 2342 2343 bool dc_abm_save_restore( 2344 struct dc *dc, 2345 struct dc_stream_state *stream, 2346 struct abm_save_restore *pData); 2347 2348 void dc_enable_dmub_outbox(struct dc *dc); 2349 2350 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2351 uint32_t link_index, 2352 struct aux_payload *payload); 2353 2354 /* Get dc link index from dpia port index */ 2355 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2356 uint8_t dpia_port_index); 2357 2358 bool dc_process_dmub_set_config_async(struct dc *dc, 2359 uint32_t link_index, 2360 struct set_config_cmd_payload *payload, 2361 struct dmub_notification *notify); 2362 2363 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2364 uint32_t link_index, 2365 uint8_t mst_alloc_slots, 2366 uint8_t *mst_slots_in_use); 2367 2368 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2369 uint32_t hpd_int_enable); 2370 2371 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2372 2373 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2374 2375 struct dc_power_profile { 2376 int power_level; /* Lower is better */ 2377 }; 2378 2379 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2380 2381 /* DSC Interfaces */ 2382 #include "dc_dsc.h" 2383 2384 /* Disable acc mode Interfaces */ 2385 void dc_disable_accelerated_mode(struct dc *dc); 2386 2387 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2388 struct dc_stream_state *new_stream); 2389 2390 #endif /* DC_INTERFACE_H_ */ 2391