1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 struct abm_save_restore; 50 51 /* forward declaration */ 52 struct aux_payload; 53 struct set_config_cmd_payload; 54 struct dmub_notification; 55 56 #define DC_VER "3.2.319" 57 58 #define MAX_SURFACES 4 59 #define MAX_PLANES 6 60 #define MAX_STREAMS 6 61 #define MIN_VIEWPORT_SIZE 12 62 #define MAX_NUM_EDP 2 63 #define MAX_HOST_ROUTERS_NUM 2 64 65 /* Display Core Interfaces */ 66 struct dc_versions { 67 const char *dc_ver; 68 struct dmcu_version dmcu_version; 69 }; 70 71 enum dp_protocol_version { 72 DP_VERSION_1_4 = 0, 73 DP_VERSION_2_1, 74 DP_VERSION_UNKNOWN, 75 }; 76 77 enum dc_plane_type { 78 DC_PLANE_TYPE_INVALID, 79 DC_PLANE_TYPE_DCE_RGB, 80 DC_PLANE_TYPE_DCE_UNDERLAY, 81 DC_PLANE_TYPE_DCN_UNIVERSAL, 82 }; 83 84 // Sizes defined as multiples of 64KB 85 enum det_size { 86 DET_SIZE_DEFAULT = 0, 87 DET_SIZE_192KB = 3, 88 DET_SIZE_256KB = 4, 89 DET_SIZE_320KB = 5, 90 DET_SIZE_384KB = 6 91 }; 92 93 94 struct dc_plane_cap { 95 enum dc_plane_type type; 96 uint32_t per_pixel_alpha : 1; 97 struct { 98 uint32_t argb8888 : 1; 99 uint32_t nv12 : 1; 100 uint32_t fp16 : 1; 101 uint32_t p010 : 1; 102 uint32_t ayuv : 1; 103 } pixel_format_support; 104 // max upscaling factor x1000 105 // upscaling factors are always >= 1 106 // for example, 1080p -> 8K is 4.0, or 4000 raw value 107 struct { 108 uint32_t argb8888; 109 uint32_t nv12; 110 uint32_t fp16; 111 } max_upscale_factor; 112 // max downscale factor x1000 113 // downscale factors are always <= 1 114 // for example, 8K -> 1080p is 0.25, or 250 raw value 115 struct { 116 uint32_t argb8888; 117 uint32_t nv12; 118 uint32_t fp16; 119 } max_downscale_factor; 120 // minimal width/height 121 uint32_t min_width; 122 uint32_t min_height; 123 }; 124 125 /** 126 * DOC: color-management-caps 127 * 128 * **Color management caps (DPP and MPC)** 129 * 130 * Modules/color calculates various color operations which are translated to 131 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 132 * DCN1, every new generation comes with fairly major differences in color 133 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 134 * decide mapping to HW block based on logical capabilities. 135 */ 136 137 /** 138 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 139 * @srgb: RGB color space transfer func 140 * @bt2020: BT.2020 transfer func 141 * @gamma2_2: standard gamma 142 * @pq: perceptual quantizer transfer function 143 * @hlg: hybrid log–gamma transfer function 144 */ 145 struct rom_curve_caps { 146 uint16_t srgb : 1; 147 uint16_t bt2020 : 1; 148 uint16_t gamma2_2 : 1; 149 uint16_t pq : 1; 150 uint16_t hlg : 1; 151 }; 152 153 /** 154 * struct dpp_color_caps - color pipeline capabilities for display pipe and 155 * plane blocks 156 * 157 * @dcn_arch: all DCE generations treated the same 158 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 159 * just plain 256-entry lookup 160 * @icsc: input color space conversion 161 * @dgam_ram: programmable degamma LUT 162 * @post_csc: post color space conversion, before gamut remap 163 * @gamma_corr: degamma correction 164 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 165 * with MPC by setting mpc:shared_3d_lut flag 166 * @ogam_ram: programmable out/blend gamma LUT 167 * @ocsc: output color space conversion 168 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 169 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 170 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 171 * 172 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 173 */ 174 struct dpp_color_caps { 175 uint16_t dcn_arch : 1; 176 uint16_t input_lut_shared : 1; 177 uint16_t icsc : 1; 178 uint16_t dgam_ram : 1; 179 uint16_t post_csc : 1; 180 uint16_t gamma_corr : 1; 181 uint16_t hw_3d_lut : 1; 182 uint16_t ogam_ram : 1; 183 uint16_t ocsc : 1; 184 uint16_t dgam_rom_for_yuv : 1; 185 struct rom_curve_caps dgam_rom_caps; 186 struct rom_curve_caps ogam_rom_caps; 187 }; 188 189 /** 190 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 191 * plane combined blocks 192 * 193 * @gamut_remap: color transformation matrix 194 * @ogam_ram: programmable out gamma LUT 195 * @ocsc: output color space conversion matrix 196 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 197 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 198 * instance 199 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 200 */ 201 struct mpc_color_caps { 202 uint16_t gamut_remap : 1; 203 uint16_t ogam_ram : 1; 204 uint16_t ocsc : 1; 205 uint16_t num_3dluts : 3; 206 uint16_t shared_3d_lut:1; 207 struct rom_curve_caps ogam_rom_caps; 208 }; 209 210 /** 211 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 212 * @dpp: color pipes caps for DPP 213 * @mpc: color pipes caps for MPC 214 */ 215 struct dc_color_caps { 216 struct dpp_color_caps dpp; 217 struct mpc_color_caps mpc; 218 }; 219 220 struct dc_dmub_caps { 221 bool psr; 222 bool mclk_sw; 223 bool subvp_psr; 224 bool gecc_enable; 225 uint8_t fams_ver; 226 bool aux_backlight_support; 227 }; 228 229 struct dc_scl_caps { 230 bool sharpener_support; 231 }; 232 233 struct dc_caps { 234 uint32_t max_streams; 235 uint32_t max_links; 236 uint32_t max_audios; 237 uint32_t max_slave_planes; 238 uint32_t max_slave_yuv_planes; 239 uint32_t max_slave_rgb_planes; 240 uint32_t max_planes; 241 uint32_t max_downscale_ratio; 242 uint32_t i2c_speed_in_khz; 243 uint32_t i2c_speed_in_khz_hdcp; 244 uint32_t dmdata_alloc_size; 245 unsigned int max_cursor_size; 246 unsigned int max_video_width; 247 /* 248 * max video plane width that can be safely assumed to be always 249 * supported by single DPP pipe. 250 */ 251 unsigned int max_optimizable_video_width; 252 unsigned int min_horizontal_blanking_period; 253 int linear_pitch_alignment; 254 bool dcc_const_color; 255 bool dynamic_audio; 256 bool is_apu; 257 bool dual_link_dvi; 258 bool post_blend_color_processing; 259 bool force_dp_tps4_for_cp2520; 260 bool disable_dp_clk_share; 261 bool psp_setup_panel_mode; 262 bool extended_aux_timeout_support; 263 bool dmcub_support; 264 bool zstate_support; 265 bool ips_support; 266 uint32_t num_of_internal_disp; 267 enum dp_protocol_version max_dp_protocol_version; 268 unsigned int mall_size_per_mem_channel; 269 unsigned int mall_size_total; 270 unsigned int cursor_cache_size; 271 struct dc_plane_cap planes[MAX_PLANES]; 272 struct dc_color_caps color; 273 struct dc_dmub_caps dmub_caps; 274 bool dp_hpo; 275 bool dp_hdmi21_pcon_support; 276 bool edp_dsc_support; 277 bool vbios_lttpr_aware; 278 bool vbios_lttpr_enable; 279 uint32_t max_otg_num; 280 uint32_t max_cab_allocation_bytes; 281 uint32_t cache_line_size; 282 uint32_t cache_num_ways; 283 uint16_t subvp_fw_processing_delay_us; 284 uint8_t subvp_drr_max_vblank_margin_us; 285 uint16_t subvp_prefetch_end_to_mall_start_us; 286 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 287 uint16_t subvp_pstate_allow_width_us; 288 uint16_t subvp_vertical_int_margin_us; 289 bool seamless_odm; 290 uint32_t max_v_total; 291 bool vtotal_limited_by_fp2; 292 uint32_t max_disp_clock_khz_at_vmin; 293 uint8_t subvp_drr_vblank_start_margin_us; 294 bool cursor_not_scaled; 295 bool dcmode_power_limits_present; 296 bool sequential_ono; 297 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 298 uint32_t dcc_plane_width_limit; 299 struct dc_scl_caps scl_caps; 300 }; 301 302 struct dc_bug_wa { 303 bool no_connect_phy_config; 304 bool dedcn20_305_wa; 305 bool skip_clock_update; 306 bool lt_early_cr_pattern; 307 struct { 308 uint8_t uclk : 1; 309 uint8_t fclk : 1; 310 uint8_t dcfclk : 1; 311 uint8_t dcfclk_ds: 1; 312 } clock_update_disable_mask; 313 bool skip_psr_ips_crtc_disable; 314 }; 315 struct dc_dcc_surface_param { 316 struct dc_size surface_size; 317 enum surface_pixel_format format; 318 unsigned int plane0_pitch; 319 struct dc_size plane1_size; 320 unsigned int plane1_pitch; 321 union { 322 enum swizzle_mode_values swizzle_mode; 323 enum swizzle_mode_addr3_values swizzle_mode_addr3; 324 }; 325 enum dc_scan_direction scan; 326 }; 327 328 struct dc_dcc_setting { 329 unsigned int max_compressed_blk_size; 330 unsigned int max_uncompressed_blk_size; 331 bool independent_64b_blks; 332 //These bitfields to be used starting with DCN 3.0 333 struct { 334 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 335 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 336 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 337 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 338 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 339 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 340 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 341 } dcc_controls; 342 }; 343 344 struct dc_surface_dcc_cap { 345 union { 346 struct { 347 struct dc_dcc_setting rgb; 348 } grph; 349 350 struct { 351 struct dc_dcc_setting luma; 352 struct dc_dcc_setting chroma; 353 } video; 354 }; 355 356 bool capable; 357 bool const_color_support; 358 }; 359 360 struct dc_static_screen_params { 361 struct { 362 bool force_trigger; 363 bool cursor_update; 364 bool surface_update; 365 bool overlay_update; 366 } triggers; 367 unsigned int num_frames; 368 }; 369 370 371 /* Surface update type is used by dc_update_surfaces_and_stream 372 * The update type is determined at the very beginning of the function based 373 * on parameters passed in and decides how much programming (or updating) is 374 * going to be done during the call. 375 * 376 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 377 * logical calculations or hardware register programming. This update MUST be 378 * ISR safe on windows. Currently fast update will only be used to flip surface 379 * address. 380 * 381 * UPDATE_TYPE_MED is used for slower updates which require significant hw 382 * re-programming however do not affect bandwidth consumption or clock 383 * requirements. At present, this is the level at which front end updates 384 * that do not require us to run bw_calcs happen. These are in/out transfer func 385 * updates, viewport offset changes, recout size changes and pixel depth changes. 386 * This update can be done at ISR, but we want to minimize how often this happens. 387 * 388 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 389 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 390 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 391 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 392 * a full update. This cannot be done at ISR level and should be a rare event. 393 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 394 * underscan we don't expect to see this call at all. 395 */ 396 397 enum surface_update_type { 398 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 399 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 400 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 401 }; 402 403 /* Forward declaration*/ 404 struct dc; 405 struct dc_plane_state; 406 struct dc_state; 407 408 struct dc_cap_funcs { 409 bool (*get_dcc_compression_cap)(const struct dc *dc, 410 const struct dc_dcc_surface_param *input, 411 struct dc_surface_dcc_cap *output); 412 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 413 }; 414 415 struct link_training_settings; 416 417 union allow_lttpr_non_transparent_mode { 418 struct { 419 bool DP1_4A : 1; 420 bool DP2_0 : 1; 421 } bits; 422 unsigned char raw; 423 }; 424 425 /* Structure to hold configuration flags set by dm at dc creation. */ 426 struct dc_config { 427 bool gpu_vm_support; 428 bool disable_disp_pll_sharing; 429 bool fbc_support; 430 bool disable_fractional_pwm; 431 bool allow_seamless_boot_optimization; 432 bool seamless_boot_edp_requested; 433 bool edp_not_connected; 434 bool edp_no_power_sequencing; 435 bool force_enum_edp; 436 bool forced_clocks; 437 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 438 bool multi_mon_pp_mclk_switch; 439 bool disable_dmcu; 440 bool enable_4to1MPC; 441 bool enable_windowed_mpo_odm; 442 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 443 uint32_t allow_edp_hotplug_detection; 444 bool clamp_min_dcfclk; 445 uint64_t vblank_alignment_dto_params; 446 uint8_t vblank_alignment_max_frame_time_diff; 447 bool is_asymmetric_memory; 448 bool is_single_rank_dimm; 449 bool is_vmin_only_asic; 450 bool use_spl; 451 bool prefer_easf; 452 bool use_pipe_ctx_sync_logic; 453 bool ignore_dpref_ss; 454 bool enable_mipi_converter_optimization; 455 bool use_default_clock_table; 456 bool force_bios_enable_lttpr; 457 uint8_t force_bios_fixed_vs; 458 int sdpif_request_limit_words_per_umc; 459 bool dc_mode_clk_limit_support; 460 bool EnableMinDispClkODM; 461 bool enable_auto_dpm_test_logs; 462 unsigned int disable_ips; 463 unsigned int disable_ips_in_vpb; 464 bool disable_ips_in_dpms_off; 465 bool usb4_bw_alloc_support; 466 bool allow_0_dtb_clk; 467 bool use_assr_psp_message; 468 bool support_edp0_on_dp1; 469 unsigned int enable_fpo_flicker_detection; 470 bool disable_hbr_audio_dp2; 471 bool consolidated_dpia_dp_lt; 472 bool set_pipe_unlock_order; 473 bool enable_dpia_pre_training; 474 bool unify_link_enc_assignment; 475 }; 476 477 enum visual_confirm { 478 VISUAL_CONFIRM_DISABLE = 0, 479 VISUAL_CONFIRM_SURFACE = 1, 480 VISUAL_CONFIRM_HDR = 2, 481 VISUAL_CONFIRM_MPCTREE = 4, 482 VISUAL_CONFIRM_PSR = 5, 483 VISUAL_CONFIRM_SWAPCHAIN = 6, 484 VISUAL_CONFIRM_FAMS = 7, 485 VISUAL_CONFIRM_SWIZZLE = 9, 486 VISUAL_CONFIRM_REPLAY = 12, 487 VISUAL_CONFIRM_SUBVP = 14, 488 VISUAL_CONFIRM_MCLK_SWITCH = 16, 489 VISUAL_CONFIRM_FAMS2 = 19, 490 VISUAL_CONFIRM_HW_CURSOR = 20, 491 VISUAL_CONFIRM_VABC = 21, 492 }; 493 494 enum dc_psr_power_opts { 495 psr_power_opt_invalid = 0x0, 496 psr_power_opt_smu_opt_static_screen = 0x1, 497 psr_power_opt_z10_static_screen = 0x10, 498 psr_power_opt_ds_disable_allow = 0x100, 499 }; 500 501 enum dml_hostvm_override_opts { 502 DML_HOSTVM_NO_OVERRIDE = 0x0, 503 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 504 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 505 }; 506 507 enum dc_replay_power_opts { 508 replay_power_opt_invalid = 0x0, 509 replay_power_opt_smu_opt_static_screen = 0x1, 510 replay_power_opt_z10_static_screen = 0x10, 511 }; 512 513 enum dcc_option { 514 DCC_ENABLE = 0, 515 DCC_DISABLE = 1, 516 DCC_HALF_REQ_DISALBE = 2, 517 }; 518 519 enum in_game_fams_config { 520 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 521 INGAME_FAMS_DISABLE, // disable in-game fams 522 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 523 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 524 }; 525 526 /** 527 * enum pipe_split_policy - Pipe split strategy supported by DCN 528 * 529 * This enum is used to define the pipe split policy supported by DCN. By 530 * default, DC favors MPC_SPLIT_DYNAMIC. 531 */ 532 enum pipe_split_policy { 533 /** 534 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 535 * pipe in order to bring the best trade-off between performance and 536 * power consumption. This is the recommended option. 537 */ 538 MPC_SPLIT_DYNAMIC = 0, 539 540 /** 541 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 542 * try any sort of split optimization. 543 */ 544 MPC_SPLIT_AVOID = 1, 545 546 /** 547 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 548 * optimize the pipe utilization when using a single display; if the 549 * user connects to a second display, DC will avoid pipe split. 550 */ 551 MPC_SPLIT_AVOID_MULT_DISP = 2, 552 }; 553 554 enum wm_report_mode { 555 WM_REPORT_DEFAULT = 0, 556 WM_REPORT_OVERRIDE = 1, 557 }; 558 enum dtm_pstate{ 559 dtm_level_p0 = 0,/*highest voltage*/ 560 dtm_level_p1, 561 dtm_level_p2, 562 dtm_level_p3, 563 dtm_level_p4,/*when active_display_count = 0*/ 564 }; 565 566 enum dcn_pwr_state { 567 DCN_PWR_STATE_UNKNOWN = -1, 568 DCN_PWR_STATE_MISSION_MODE = 0, 569 DCN_PWR_STATE_LOW_POWER = 3, 570 }; 571 572 enum dcn_zstate_support_state { 573 DCN_ZSTATE_SUPPORT_UNKNOWN, 574 DCN_ZSTATE_SUPPORT_ALLOW, 575 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 576 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 577 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 578 DCN_ZSTATE_SUPPORT_DISALLOW, 579 }; 580 581 /* 582 * struct dc_clocks - DC pipe clocks 583 * 584 * For any clocks that may differ per pipe only the max is stored in this 585 * structure 586 */ 587 struct dc_clocks { 588 int dispclk_khz; 589 int actual_dispclk_khz; 590 int dppclk_khz; 591 int actual_dppclk_khz; 592 int disp_dpp_voltage_level_khz; 593 int dcfclk_khz; 594 int socclk_khz; 595 int dcfclk_deep_sleep_khz; 596 int fclk_khz; 597 int phyclk_khz; 598 int dramclk_khz; 599 bool p_state_change_support; 600 enum dcn_zstate_support_state zstate_support; 601 bool dtbclk_en; 602 int ref_dtbclk_khz; 603 bool fclk_p_state_change_support; 604 enum dcn_pwr_state pwr_state; 605 /* 606 * Elements below are not compared for the purposes of 607 * optimization required 608 */ 609 bool prev_p_state_change_support; 610 bool fclk_prev_p_state_change_support; 611 int num_ways; 612 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 613 614 /* 615 * @fw_based_mclk_switching 616 * 617 * DC has a mechanism that leverage the variable refresh rate to switch 618 * memory clock in cases that we have a large latency to achieve the 619 * memory clock change and a short vblank window. DC has some 620 * requirements to enable this feature, and this field describes if the 621 * system support or not such a feature. 622 */ 623 bool fw_based_mclk_switching; 624 bool fw_based_mclk_switching_shut_down; 625 int prev_num_ways; 626 enum dtm_pstate dtm_level; 627 int max_supported_dppclk_khz; 628 int max_supported_dispclk_khz; 629 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 630 int bw_dispclk_khz; 631 int idle_dramclk_khz; 632 int idle_fclk_khz; 633 int subvp_prefetch_dramclk_khz; 634 int subvp_prefetch_fclk_khz; 635 }; 636 637 struct dc_bw_validation_profile { 638 bool enable; 639 640 unsigned long long total_ticks; 641 unsigned long long voltage_level_ticks; 642 unsigned long long watermark_ticks; 643 unsigned long long rq_dlg_ticks; 644 645 unsigned long long total_count; 646 unsigned long long skip_fast_count; 647 unsigned long long skip_pass_count; 648 unsigned long long skip_fail_count; 649 }; 650 651 #define BW_VAL_TRACE_SETUP() \ 652 unsigned long long end_tick = 0; \ 653 unsigned long long voltage_level_tick = 0; \ 654 unsigned long long watermark_tick = 0; \ 655 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 656 dm_get_timestamp(dc->ctx) : 0 657 658 #define BW_VAL_TRACE_COUNT() \ 659 if (dc->debug.bw_val_profile.enable) \ 660 dc->debug.bw_val_profile.total_count++ 661 662 #define BW_VAL_TRACE_SKIP(status) \ 663 if (dc->debug.bw_val_profile.enable) { \ 664 if (!voltage_level_tick) \ 665 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 666 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 667 } 668 669 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 670 if (dc->debug.bw_val_profile.enable) \ 671 voltage_level_tick = dm_get_timestamp(dc->ctx) 672 673 #define BW_VAL_TRACE_END_WATERMARKS() \ 674 if (dc->debug.bw_val_profile.enable) \ 675 watermark_tick = dm_get_timestamp(dc->ctx) 676 677 #define BW_VAL_TRACE_FINISH() \ 678 if (dc->debug.bw_val_profile.enable) { \ 679 end_tick = dm_get_timestamp(dc->ctx); \ 680 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 681 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 682 if (watermark_tick) { \ 683 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 684 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 685 } \ 686 } 687 688 union mem_low_power_enable_options { 689 struct { 690 bool vga: 1; 691 bool i2c: 1; 692 bool dmcu: 1; 693 bool dscl: 1; 694 bool cm: 1; 695 bool mpc: 1; 696 bool optc: 1; 697 bool vpg: 1; 698 bool afmt: 1; 699 } bits; 700 uint32_t u32All; 701 }; 702 703 union root_clock_optimization_options { 704 struct { 705 bool dpp: 1; 706 bool dsc: 1; 707 bool hdmistream: 1; 708 bool hdmichar: 1; 709 bool dpstream: 1; 710 bool symclk32_se: 1; 711 bool symclk32_le: 1; 712 bool symclk_fe: 1; 713 bool physymclk: 1; 714 bool dpiasymclk: 1; 715 uint32_t reserved: 22; 716 } bits; 717 uint32_t u32All; 718 }; 719 720 union fine_grain_clock_gating_enable_options { 721 struct { 722 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 723 bool dchub : 1; /* Display controller hub */ 724 bool dchubbub : 1; 725 bool dpp : 1; /* Display pipes and planes */ 726 bool opp : 1; /* Output pixel processing */ 727 bool optc : 1; /* Output pipe timing combiner */ 728 bool dio : 1; /* Display output */ 729 bool dwb : 1; /* Display writeback */ 730 bool mmhubbub : 1; /* Multimedia hub */ 731 bool dmu : 1; /* Display core management unit */ 732 bool az : 1; /* Azalia */ 733 bool dchvm : 1; 734 bool dsc : 1; /* Display stream compression */ 735 736 uint32_t reserved : 19; 737 } bits; 738 uint32_t u32All; 739 }; 740 741 enum pg_hw_pipe_resources { 742 PG_HUBP = 0, 743 PG_DPP, 744 PG_DSC, 745 PG_MPCC, 746 PG_OPP, 747 PG_OPTC, 748 PG_DPSTREAM, 749 PG_HDMISTREAM, 750 PG_PHYSYMCLK, 751 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 752 }; 753 754 enum pg_hw_resources { 755 PG_DCCG = 0, 756 PG_DCIO, 757 PG_DIO, 758 PG_DCHUBBUB, 759 PG_DCHVM, 760 PG_DWB, 761 PG_HPO, 762 PG_HW_RESOURCES_NUM_ELEMENT 763 }; 764 765 struct pg_block_update { 766 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 767 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 768 }; 769 770 union dpia_debug_options { 771 struct { 772 uint32_t disable_dpia:1; /* bit 0 */ 773 uint32_t force_non_lttpr:1; /* bit 1 */ 774 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 775 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 776 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 777 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 778 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 779 uint32_t enable_dpia_pre_training:1; /* bit 7 */ 780 uint32_t unify_link_enc_assignment:1; /* bit 8 */ 781 uint32_t reserved:24; 782 } bits; 783 uint32_t raw; 784 }; 785 786 /* AUX wake work around options 787 * 0: enable/disable work around 788 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 789 * 15-2: reserved 790 * 31-16: timeout in ms 791 */ 792 union aux_wake_wa_options { 793 struct { 794 uint32_t enable_wa : 1; 795 uint32_t use_default_timeout : 1; 796 uint32_t rsvd: 14; 797 uint32_t timeout_ms : 16; 798 } bits; 799 uint32_t raw; 800 }; 801 802 struct dc_debug_data { 803 uint32_t ltFailCount; 804 uint32_t i2cErrorCount; 805 uint32_t auxErrorCount; 806 }; 807 808 struct dc_phy_addr_space_config { 809 struct { 810 uint64_t start_addr; 811 uint64_t end_addr; 812 uint64_t fb_top; 813 uint64_t fb_offset; 814 uint64_t fb_base; 815 uint64_t agp_top; 816 uint64_t agp_bot; 817 uint64_t agp_base; 818 } system_aperture; 819 820 struct { 821 uint64_t page_table_start_addr; 822 uint64_t page_table_end_addr; 823 uint64_t page_table_base_addr; 824 bool base_addr_is_mc_addr; 825 } gart_config; 826 827 bool valid; 828 bool is_hvm_enabled; 829 uint64_t page_table_default_page_addr; 830 }; 831 832 struct dc_virtual_addr_space_config { 833 uint64_t page_table_base_addr; 834 uint64_t page_table_start_addr; 835 uint64_t page_table_end_addr; 836 uint32_t page_table_block_size_in_bytes; 837 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 838 }; 839 840 struct dc_bounding_box_overrides { 841 int sr_exit_time_ns; 842 int sr_enter_plus_exit_time_ns; 843 int sr_exit_z8_time_ns; 844 int sr_enter_plus_exit_z8_time_ns; 845 int urgent_latency_ns; 846 int percent_of_ideal_drambw; 847 int dram_clock_change_latency_ns; 848 int dummy_clock_change_latency_ns; 849 int fclk_clock_change_latency_ns; 850 /* This forces a hard min on the DCFCLK we use 851 * for DML. Unlike the debug option for forcing 852 * DCFCLK, this override affects watermark calculations 853 */ 854 int min_dcfclk_mhz; 855 }; 856 857 struct dc_state; 858 struct resource_pool; 859 struct dce_hwseq; 860 struct link_service; 861 862 /* 863 * struct dc_debug_options - DC debug struct 864 * 865 * This struct provides a simple mechanism for developers to change some 866 * configurations, enable/disable features, and activate extra debug options. 867 * This can be very handy to narrow down whether some specific feature is 868 * causing an issue or not. 869 */ 870 struct dc_debug_options { 871 bool native422_support; 872 bool disable_dsc; 873 enum visual_confirm visual_confirm; 874 int visual_confirm_rect_height; 875 876 bool sanity_checks; 877 bool max_disp_clk; 878 bool surface_trace; 879 bool clock_trace; 880 bool validation_trace; 881 bool bandwidth_calcs_trace; 882 int max_downscale_src_width; 883 884 /* stutter efficiency related */ 885 bool disable_stutter; 886 bool use_max_lb; 887 enum dcc_option disable_dcc; 888 889 /* 890 * @pipe_split_policy: Define which pipe split policy is used by the 891 * display core. 892 */ 893 enum pipe_split_policy pipe_split_policy; 894 bool force_single_disp_pipe_split; 895 bool voltage_align_fclk; 896 bool disable_min_fclk; 897 898 bool disable_dfs_bypass; 899 bool disable_dpp_power_gate; 900 bool disable_hubp_power_gate; 901 bool disable_dsc_power_gate; 902 bool disable_optc_power_gate; 903 bool disable_hpo_power_gate; 904 int dsc_min_slice_height_override; 905 int dsc_bpp_increment_div; 906 bool disable_pplib_wm_range; 907 enum wm_report_mode pplib_wm_report_mode; 908 unsigned int min_disp_clk_khz; 909 unsigned int min_dpp_clk_khz; 910 unsigned int min_dram_clk_khz; 911 int sr_exit_time_dpm0_ns; 912 int sr_enter_plus_exit_time_dpm0_ns; 913 int sr_exit_time_ns; 914 int sr_enter_plus_exit_time_ns; 915 int sr_exit_z8_time_ns; 916 int sr_enter_plus_exit_z8_time_ns; 917 int urgent_latency_ns; 918 uint32_t underflow_assert_delay_us; 919 int percent_of_ideal_drambw; 920 int dram_clock_change_latency_ns; 921 bool optimized_watermark; 922 int always_scale; 923 bool disable_pplib_clock_request; 924 bool disable_clock_gate; 925 bool disable_mem_low_power; 926 bool pstate_enabled; 927 bool disable_dmcu; 928 bool force_abm_enable; 929 bool disable_stereo_support; 930 bool vsr_support; 931 bool performance_trace; 932 bool az_endpoint_mute_only; 933 bool always_use_regamma; 934 bool recovery_enabled; 935 bool avoid_vbios_exec_table; 936 bool scl_reset_length10; 937 bool hdmi20_disable; 938 bool skip_detection_link_training; 939 uint32_t edid_read_retry_times; 940 unsigned int force_odm_combine; //bit vector based on otg inst 941 unsigned int seamless_boot_odm_combine; 942 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 943 int minimum_z8_residency_time; 944 int minimum_z10_residency_time; 945 bool disable_z9_mpc; 946 unsigned int force_fclk_khz; 947 bool enable_tri_buf; 948 bool ips_disallow_entry; 949 bool dmub_offload_enabled; 950 bool dmcub_emulation; 951 bool disable_idle_power_optimizations; 952 unsigned int mall_size_override; 953 unsigned int mall_additional_timer_percent; 954 bool mall_error_as_fatal; 955 bool dmub_command_table; /* for testing only */ 956 struct dc_bw_validation_profile bw_val_profile; 957 bool disable_fec; 958 bool disable_48mhz_pwrdwn; 959 /* This forces a hard min on the DCFCLK requested to SMU/PP 960 * watermarks are not affected. 961 */ 962 unsigned int force_min_dcfclk_mhz; 963 int dwb_fi_phase; 964 bool disable_timing_sync; 965 bool cm_in_bypass; 966 int force_clock_mode;/*every mode change.*/ 967 968 bool disable_dram_clock_change_vactive_support; 969 bool validate_dml_output; 970 bool enable_dmcub_surface_flip; 971 bool usbc_combo_phy_reset_wa; 972 bool enable_dram_clock_change_one_display_vactive; 973 /* TODO - remove once tested */ 974 bool legacy_dp2_lt; 975 bool set_mst_en_for_sst; 976 bool disable_uhbr; 977 bool force_dp2_lt_fallback_method; 978 bool ignore_cable_id; 979 union mem_low_power_enable_options enable_mem_low_power; 980 union root_clock_optimization_options root_clock_optimization; 981 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 982 bool hpo_optimization; 983 bool force_vblank_alignment; 984 985 /* Enable dmub aux for legacy ddc */ 986 bool enable_dmub_aux_for_legacy_ddc; 987 bool disable_fams; 988 enum in_game_fams_config disable_fams_gaming; 989 /* FEC/PSR1 sequence enable delay in 100us */ 990 uint8_t fec_enable_delay_in100us; 991 bool enable_driver_sequence_debug; 992 enum det_size crb_alloc_policy; 993 int crb_alloc_policy_min_disp_count; 994 bool disable_z10; 995 bool enable_z9_disable_interface; 996 bool psr_skip_crtc_disable; 997 uint32_t ips_skip_crtc_disable_mask; 998 union dpia_debug_options dpia_debug; 999 bool disable_fixed_vs_aux_timeout_wa; 1000 uint32_t fixed_vs_aux_delay_config_wa; 1001 bool force_disable_subvp; 1002 bool force_subvp_mclk_switch; 1003 bool allow_sw_cursor_fallback; 1004 unsigned int force_subvp_num_ways; 1005 unsigned int force_mall_ss_num_ways; 1006 bool alloc_extra_way_for_cursor; 1007 uint32_t subvp_extra_lines; 1008 bool force_usr_allow; 1009 /* uses value at boot and disables switch */ 1010 bool disable_dtb_ref_clk_switch; 1011 bool extended_blank_optimization; 1012 union aux_wake_wa_options aux_wake_wa; 1013 uint32_t mst_start_top_delay; 1014 uint8_t psr_power_use_phy_fsm; 1015 enum dml_hostvm_override_opts dml_hostvm_override; 1016 bool dml_disallow_alternate_prefetch_modes; 1017 bool use_legacy_soc_bb_mechanism; 1018 bool exit_idle_opt_for_cursor_updates; 1019 bool using_dml2; 1020 bool enable_single_display_2to1_odm_policy; 1021 bool enable_double_buffered_dsc_pg_support; 1022 bool enable_dp_dig_pixel_rate_div_policy; 1023 bool using_dml21; 1024 enum lttpr_mode lttpr_mode_override; 1025 unsigned int dsc_delay_factor_wa_x1000; 1026 unsigned int min_prefetch_in_strobe_ns; 1027 bool disable_unbounded_requesting; 1028 bool dig_fifo_off_in_blank; 1029 bool override_dispclk_programming; 1030 bool otg_crc_db; 1031 bool disallow_dispclk_dppclk_ds; 1032 bool disable_fpo_optimizations; 1033 bool support_eDP1_5; 1034 uint32_t fpo_vactive_margin_us; 1035 bool disable_fpo_vactive; 1036 bool disable_boot_optimizations; 1037 bool override_odm_optimization; 1038 bool minimize_dispclk_using_odm; 1039 bool disable_subvp_high_refresh; 1040 bool disable_dp_plus_plus_wa; 1041 uint32_t fpo_vactive_min_active_margin_us; 1042 uint32_t fpo_vactive_max_blank_us; 1043 bool enable_hpo_pg_support; 1044 bool enable_legacy_fast_update; 1045 bool disable_dc_mode_overwrite; 1046 bool replay_skip_crtc_disabled; 1047 bool ignore_pg;/*do nothing, let pmfw control it*/ 1048 bool psp_disabled_wa; 1049 unsigned int ips2_eval_delay_us; 1050 unsigned int ips2_entry_delay_us; 1051 bool optimize_ips_handshake; 1052 bool disable_dmub_reallow_idle; 1053 bool disable_timeout; 1054 bool disable_extblankadj; 1055 bool enable_idle_reg_checks; 1056 unsigned int static_screen_wait_frames; 1057 uint32_t pwm_freq; 1058 bool force_chroma_subsampling_1tap; 1059 unsigned int dcc_meta_propagation_delay_us; 1060 bool disable_422_left_edge_pixel; 1061 bool dml21_force_pstate_method; 1062 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1063 uint32_t dml21_disable_pstate_method_mask; 1064 union fw_assisted_mclk_switch_version fams_version; 1065 union dmub_fams2_global_feature_config fams2_config; 1066 unsigned int force_cositing; 1067 unsigned int disable_spl; 1068 unsigned int force_easf; 1069 unsigned int force_sharpness; 1070 unsigned int force_sharpness_level; 1071 unsigned int force_lls; 1072 bool notify_dpia_hr_bw; 1073 bool enable_ips_visual_confirm; 1074 unsigned int sharpen_policy; 1075 unsigned int scale_to_sharpness_policy; 1076 bool skip_full_updated_if_possible; 1077 unsigned int enable_oled_edp_power_up_opt; 1078 bool enable_hblank_borrow; 1079 bool force_subvp_df_throttle; 1080 }; 1081 1082 1083 /* Generic structure that can be used to query properties of DC. More fields 1084 * can be added as required. 1085 */ 1086 struct dc_current_properties { 1087 unsigned int cursor_size_limit; 1088 }; 1089 1090 enum frame_buffer_mode { 1091 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1092 FRAME_BUFFER_MODE_ZFB_ONLY, 1093 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1094 } ; 1095 1096 struct dchub_init_data { 1097 int64_t zfb_phys_addr_base; 1098 int64_t zfb_mc_base_addr; 1099 uint64_t zfb_size_in_byte; 1100 enum frame_buffer_mode fb_mode; 1101 bool dchub_initialzied; 1102 bool dchub_info_valid; 1103 }; 1104 1105 struct dml2_soc_bb; 1106 1107 struct dc_init_data { 1108 struct hw_asic_id asic_id; 1109 void *driver; /* ctx */ 1110 struct cgs_device *cgs_device; 1111 struct dc_bounding_box_overrides bb_overrides; 1112 1113 int num_virtual_links; 1114 /* 1115 * If 'vbios_override' not NULL, it will be called instead 1116 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1117 */ 1118 struct dc_bios *vbios_override; 1119 enum dce_environment dce_environment; 1120 1121 struct dmub_offload_funcs *dmub_if; 1122 struct dc_reg_helper_state *dmub_offload; 1123 1124 struct dc_config flags; 1125 uint64_t log_mask; 1126 1127 struct dpcd_vendor_signature vendor_signature; 1128 bool force_smu_not_present; 1129 /* 1130 * IP offset for run time initializaion of register addresses 1131 * 1132 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1133 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1134 * before them. 1135 */ 1136 uint32_t *dcn_reg_offsets; 1137 uint32_t *nbio_reg_offsets; 1138 uint32_t *clk_reg_offsets; 1139 struct dml2_soc_bb *bb_from_dmub; 1140 }; 1141 1142 struct dc_callback_init { 1143 struct cp_psp cp_psp; 1144 }; 1145 1146 struct dc *dc_create(const struct dc_init_data *init_params); 1147 void dc_hardware_init(struct dc *dc); 1148 1149 int dc_get_vmid_use_vector(struct dc *dc); 1150 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1151 /* Returns the number of vmids supported */ 1152 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1153 void dc_init_callbacks(struct dc *dc, 1154 const struct dc_callback_init *init_params); 1155 void dc_deinit_callbacks(struct dc *dc); 1156 void dc_destroy(struct dc **dc); 1157 1158 /* Surface Interfaces */ 1159 1160 enum { 1161 TRANSFER_FUNC_POINTS = 1025 1162 }; 1163 1164 struct dc_hdr_static_metadata { 1165 /* display chromaticities and white point in units of 0.00001 */ 1166 unsigned int chromaticity_green_x; 1167 unsigned int chromaticity_green_y; 1168 unsigned int chromaticity_blue_x; 1169 unsigned int chromaticity_blue_y; 1170 unsigned int chromaticity_red_x; 1171 unsigned int chromaticity_red_y; 1172 unsigned int chromaticity_white_point_x; 1173 unsigned int chromaticity_white_point_y; 1174 1175 uint32_t min_luminance; 1176 uint32_t max_luminance; 1177 uint32_t maximum_content_light_level; 1178 uint32_t maximum_frame_average_light_level; 1179 }; 1180 1181 enum dc_transfer_func_type { 1182 TF_TYPE_PREDEFINED, 1183 TF_TYPE_DISTRIBUTED_POINTS, 1184 TF_TYPE_BYPASS, 1185 TF_TYPE_HWPWL 1186 }; 1187 1188 struct dc_transfer_func_distributed_points { 1189 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1190 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1191 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1192 1193 uint16_t end_exponent; 1194 uint16_t x_point_at_y1_red; 1195 uint16_t x_point_at_y1_green; 1196 uint16_t x_point_at_y1_blue; 1197 }; 1198 1199 enum dc_transfer_func_predefined { 1200 TRANSFER_FUNCTION_SRGB, 1201 TRANSFER_FUNCTION_BT709, 1202 TRANSFER_FUNCTION_PQ, 1203 TRANSFER_FUNCTION_LINEAR, 1204 TRANSFER_FUNCTION_UNITY, 1205 TRANSFER_FUNCTION_HLG, 1206 TRANSFER_FUNCTION_HLG12, 1207 TRANSFER_FUNCTION_GAMMA22, 1208 TRANSFER_FUNCTION_GAMMA24, 1209 TRANSFER_FUNCTION_GAMMA26 1210 }; 1211 1212 1213 struct dc_transfer_func { 1214 struct kref refcount; 1215 enum dc_transfer_func_type type; 1216 enum dc_transfer_func_predefined tf; 1217 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1218 uint32_t sdr_ref_white_level; 1219 union { 1220 struct pwl_params pwl; 1221 struct dc_transfer_func_distributed_points tf_pts; 1222 }; 1223 }; 1224 1225 1226 union dc_3dlut_state { 1227 struct { 1228 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1229 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1230 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1231 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1232 uint32_t mpc_rmu1_mux:4; 1233 uint32_t mpc_rmu2_mux:4; 1234 uint32_t reserved:15; 1235 } bits; 1236 uint32_t raw; 1237 }; 1238 1239 1240 struct dc_3dlut { 1241 struct kref refcount; 1242 struct tetrahedral_params lut_3d; 1243 struct fixed31_32 hdr_multiplier; 1244 union dc_3dlut_state state; 1245 }; 1246 /* 1247 * This structure is filled in by dc_surface_get_status and contains 1248 * the last requested address and the currently active address so the called 1249 * can determine if there are any outstanding flips 1250 */ 1251 struct dc_plane_status { 1252 struct dc_plane_address requested_address; 1253 struct dc_plane_address current_address; 1254 bool is_flip_pending; 1255 bool is_right_eye; 1256 }; 1257 1258 union surface_update_flags { 1259 1260 struct { 1261 uint32_t addr_update:1; 1262 /* Medium updates */ 1263 uint32_t dcc_change:1; 1264 uint32_t color_space_change:1; 1265 uint32_t horizontal_mirror_change:1; 1266 uint32_t per_pixel_alpha_change:1; 1267 uint32_t global_alpha_change:1; 1268 uint32_t hdr_mult:1; 1269 uint32_t rotation_change:1; 1270 uint32_t swizzle_change:1; 1271 uint32_t scaling_change:1; 1272 uint32_t position_change:1; 1273 uint32_t in_transfer_func_change:1; 1274 uint32_t input_csc_change:1; 1275 uint32_t coeff_reduction_change:1; 1276 uint32_t output_tf_change:1; 1277 uint32_t pixel_format_change:1; 1278 uint32_t plane_size_change:1; 1279 uint32_t gamut_remap_change:1; 1280 1281 /* Full updates */ 1282 uint32_t new_plane:1; 1283 uint32_t bpp_change:1; 1284 uint32_t gamma_change:1; 1285 uint32_t bandwidth_change:1; 1286 uint32_t clock_change:1; 1287 uint32_t stereo_format_change:1; 1288 uint32_t lut_3d:1; 1289 uint32_t tmz_changed:1; 1290 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1291 uint32_t full_update:1; 1292 uint32_t sdr_white_level_nits:1; 1293 } bits; 1294 1295 uint32_t raw; 1296 }; 1297 1298 #define DC_REMOVE_PLANE_POINTERS 1 1299 1300 struct dc_plane_state { 1301 struct dc_plane_address address; 1302 struct dc_plane_flip_time time; 1303 bool triplebuffer_flips; 1304 struct scaling_taps scaling_quality; 1305 struct rect src_rect; 1306 struct rect dst_rect; 1307 struct rect clip_rect; 1308 1309 struct plane_size plane_size; 1310 struct dc_tiling_info tiling_info; 1311 1312 struct dc_plane_dcc_param dcc; 1313 1314 struct dc_gamma gamma_correction; 1315 struct dc_transfer_func in_transfer_func; 1316 struct dc_bias_and_scale bias_and_scale; 1317 struct dc_csc_transform input_csc_color_matrix; 1318 struct fixed31_32 coeff_reduction_factor; 1319 struct fixed31_32 hdr_mult; 1320 struct colorspace_transform gamut_remap_matrix; 1321 1322 // TODO: No longer used, remove 1323 struct dc_hdr_static_metadata hdr_static_ctx; 1324 1325 enum dc_color_space color_space; 1326 1327 struct dc_3dlut lut3d_func; 1328 struct dc_transfer_func in_shaper_func; 1329 struct dc_transfer_func blend_tf; 1330 1331 struct dc_transfer_func *gamcor_tf; 1332 enum surface_pixel_format format; 1333 enum dc_rotation_angle rotation; 1334 enum plane_stereo_format stereo_format; 1335 1336 bool is_tiling_rotated; 1337 bool per_pixel_alpha; 1338 bool pre_multiplied_alpha; 1339 bool global_alpha; 1340 int global_alpha_value; 1341 bool visible; 1342 bool flip_immediate; 1343 bool horizontal_mirror; 1344 int layer_index; 1345 1346 union surface_update_flags update_flags; 1347 bool flip_int_enabled; 1348 bool skip_manual_trigger; 1349 1350 /* private to DC core */ 1351 struct dc_plane_status status; 1352 struct dc_context *ctx; 1353 1354 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1355 bool force_full_update; 1356 1357 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1358 1359 /* private to dc_surface.c */ 1360 enum dc_irq_source irq_source; 1361 struct kref refcount; 1362 struct tg_color visual_confirm_color; 1363 1364 bool is_statically_allocated; 1365 enum chroma_cositing cositing; 1366 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1367 bool mcm_lut1d_enable; 1368 struct dc_cm2_func_luts mcm_luts; 1369 bool lut_bank_a; 1370 enum mpcc_movable_cm_location mcm_location; 1371 struct dc_csc_transform cursor_csc_color_matrix; 1372 bool adaptive_sharpness_en; 1373 int adaptive_sharpness_policy; 1374 int sharpness_level; 1375 enum linear_light_scaling linear_light_scaling; 1376 unsigned int sdr_white_level_nits; 1377 }; 1378 1379 struct dc_plane_info { 1380 struct plane_size plane_size; 1381 struct dc_tiling_info tiling_info; 1382 struct dc_plane_dcc_param dcc; 1383 enum surface_pixel_format format; 1384 enum dc_rotation_angle rotation; 1385 enum plane_stereo_format stereo_format; 1386 enum dc_color_space color_space; 1387 bool horizontal_mirror; 1388 bool visible; 1389 bool per_pixel_alpha; 1390 bool pre_multiplied_alpha; 1391 bool global_alpha; 1392 int global_alpha_value; 1393 bool input_csc_enabled; 1394 int layer_index; 1395 enum chroma_cositing cositing; 1396 }; 1397 1398 #include "dc_stream.h" 1399 1400 struct dc_scratch_space { 1401 /* used to temporarily backup plane states of a stream during 1402 * dc update. The reason is that plane states are overwritten 1403 * with surface updates in dc update. Once they are overwritten 1404 * current state is no longer valid. We want to temporarily 1405 * store current value in plane states so we can still recover 1406 * a valid current state during dc update. 1407 */ 1408 struct dc_plane_state plane_states[MAX_SURFACES]; 1409 1410 struct dc_stream_state stream_state; 1411 }; 1412 1413 struct dc { 1414 struct dc_debug_options debug; 1415 struct dc_versions versions; 1416 struct dc_caps caps; 1417 struct dc_cap_funcs cap_funcs; 1418 struct dc_config config; 1419 struct dc_bounding_box_overrides bb_overrides; 1420 struct dc_bug_wa work_arounds; 1421 struct dc_context *ctx; 1422 struct dc_phy_addr_space_config vm_pa_config; 1423 1424 uint8_t link_count; 1425 struct dc_link *links[MAX_LINKS]; 1426 struct link_service *link_srv; 1427 1428 struct dc_state *current_state; 1429 struct resource_pool *res_pool; 1430 1431 struct clk_mgr *clk_mgr; 1432 1433 /* Display Engine Clock levels */ 1434 struct dm_pp_clock_levels sclk_lvls; 1435 1436 /* Inputs into BW and WM calculations. */ 1437 struct bw_calcs_dceip *bw_dceip; 1438 struct bw_calcs_vbios *bw_vbios; 1439 struct dcn_soc_bounding_box *dcn_soc; 1440 struct dcn_ip_params *dcn_ip; 1441 struct display_mode_lib dml; 1442 1443 /* HW functions */ 1444 struct hw_sequencer_funcs hwss; 1445 struct dce_hwseq *hwseq; 1446 1447 /* Require to optimize clocks and bandwidth for added/removed planes */ 1448 bool optimized_required; 1449 bool wm_optimized_required; 1450 bool idle_optimizations_allowed; 1451 bool enable_c20_dtm_b0; 1452 1453 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1454 1455 /* FBC compressor */ 1456 struct compressor *fbc_compressor; 1457 1458 struct dc_debug_data debug_data; 1459 struct dpcd_vendor_signature vendor_signature; 1460 1461 const char *build_id; 1462 struct vm_helper *vm_helper; 1463 1464 uint32_t *dcn_reg_offsets; 1465 uint32_t *nbio_reg_offsets; 1466 uint32_t *clk_reg_offsets; 1467 1468 /* Scratch memory */ 1469 struct { 1470 struct { 1471 /* 1472 * For matching clock_limits table in driver with table 1473 * from PMFW. 1474 */ 1475 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1476 } update_bw_bounding_box; 1477 struct dc_scratch_space current_state; 1478 struct dc_scratch_space new_state; 1479 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1480 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1481 } scratch; 1482 1483 struct dml2_configuration_options dml2_options; 1484 struct dml2_configuration_options dml2_tmp; 1485 enum dc_acpi_cm_power_state power_state; 1486 1487 }; 1488 1489 struct dc_scaling_info { 1490 struct rect src_rect; 1491 struct rect dst_rect; 1492 struct rect clip_rect; 1493 struct scaling_taps scaling_quality; 1494 }; 1495 1496 struct dc_fast_update { 1497 const struct dc_flip_addrs *flip_addr; 1498 const struct dc_gamma *gamma; 1499 const struct colorspace_transform *gamut_remap_matrix; 1500 const struct dc_csc_transform *input_csc_color_matrix; 1501 const struct fixed31_32 *coeff_reduction_factor; 1502 struct dc_transfer_func *out_transfer_func; 1503 struct dc_csc_transform *output_csc_transform; 1504 const struct dc_csc_transform *cursor_csc_color_matrix; 1505 }; 1506 1507 struct dc_surface_update { 1508 struct dc_plane_state *surface; 1509 1510 /* isr safe update parameters. null means no updates */ 1511 const struct dc_flip_addrs *flip_addr; 1512 const struct dc_plane_info *plane_info; 1513 const struct dc_scaling_info *scaling_info; 1514 struct fixed31_32 hdr_mult; 1515 /* following updates require alloc/sleep/spin that is not isr safe, 1516 * null means no updates 1517 */ 1518 const struct dc_gamma *gamma; 1519 const struct dc_transfer_func *in_transfer_func; 1520 1521 const struct dc_csc_transform *input_csc_color_matrix; 1522 const struct fixed31_32 *coeff_reduction_factor; 1523 const struct dc_transfer_func *func_shaper; 1524 const struct dc_3dlut *lut3d_func; 1525 const struct dc_transfer_func *blend_tf; 1526 const struct colorspace_transform *gamut_remap_matrix; 1527 /* 1528 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1529 * 1530 * change cm2_params.component_settings: Full update 1531 * change cm2_params.cm2_luts: Fast update 1532 */ 1533 const struct dc_cm2_parameters *cm2_params; 1534 const struct dc_csc_transform *cursor_csc_color_matrix; 1535 unsigned int sdr_white_level_nits; 1536 struct dc_bias_and_scale bias_and_scale; 1537 }; 1538 1539 /* 1540 * Create a new surface with default parameters; 1541 */ 1542 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1543 void dc_gamma_release(struct dc_gamma **dc_gamma); 1544 struct dc_gamma *dc_create_gamma(void); 1545 1546 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1547 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1548 struct dc_transfer_func *dc_create_transfer_func(void); 1549 1550 struct dc_3dlut *dc_create_3dlut_func(void); 1551 void dc_3dlut_func_release(struct dc_3dlut *lut); 1552 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1553 1554 void dc_post_update_surfaces_to_stream( 1555 struct dc *dc); 1556 1557 #include "dc_stream.h" 1558 1559 /** 1560 * struct dc_validation_set - Struct to store surface/stream associations for validation 1561 */ 1562 struct dc_validation_set { 1563 /** 1564 * @stream: Stream state properties 1565 */ 1566 struct dc_stream_state *stream; 1567 1568 /** 1569 * @plane_states: Surface state 1570 */ 1571 struct dc_plane_state *plane_states[MAX_SURFACES]; 1572 1573 /** 1574 * @plane_count: Total of active planes 1575 */ 1576 uint8_t plane_count; 1577 }; 1578 1579 bool dc_validate_boot_timing(const struct dc *dc, 1580 const struct dc_sink *sink, 1581 struct dc_crtc_timing *crtc_timing); 1582 1583 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1584 1585 enum dc_status dc_validate_with_context(struct dc *dc, 1586 const struct dc_validation_set set[], 1587 int set_count, 1588 struct dc_state *context, 1589 bool fast_validate); 1590 1591 bool dc_set_generic_gpio_for_stereo(bool enable, 1592 struct gpio_service *gpio_service); 1593 1594 /* 1595 * fast_validate: we return after determining if we can support the new state, 1596 * but before we populate the programming info 1597 */ 1598 enum dc_status dc_validate_global_state( 1599 struct dc *dc, 1600 struct dc_state *new_ctx, 1601 bool fast_validate); 1602 1603 bool dc_acquire_release_mpc_3dlut( 1604 struct dc *dc, bool acquire, 1605 struct dc_stream_state *stream, 1606 struct dc_3dlut **lut, 1607 struct dc_transfer_func **shaper); 1608 1609 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1610 void get_audio_check(struct audio_info *aud_modes, 1611 struct audio_check *aud_chk); 1612 1613 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1614 void populate_fast_updates(struct dc_fast_update *fast_update, 1615 struct dc_surface_update *srf_updates, 1616 int surface_count, 1617 struct dc_stream_update *stream_update); 1618 /* 1619 * Set up streams and links associated to drive sinks 1620 * The streams parameter is an absolute set of all active streams. 1621 * 1622 * After this call: 1623 * Phy, Encoder, Timing Generator are programmed and enabled. 1624 * New streams are enabled with blank stream; no memory read. 1625 */ 1626 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1627 1628 1629 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1630 struct dc_stream_state *stream, 1631 int mpcc_inst); 1632 1633 1634 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1635 1636 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1637 1638 /* The function returns minimum bandwidth required to drive a given timing 1639 * return - minimum required timing bandwidth in kbps. 1640 */ 1641 uint32_t dc_bandwidth_in_kbps_from_timing( 1642 const struct dc_crtc_timing *timing, 1643 const enum dc_link_encoding_format link_encoding); 1644 1645 /* Link Interfaces */ 1646 /* 1647 * A link contains one or more sinks and their connected status. 1648 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1649 */ 1650 struct dc_link { 1651 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1652 unsigned int sink_count; 1653 struct dc_sink *local_sink; 1654 unsigned int link_index; 1655 enum dc_connection_type type; 1656 enum signal_type connector_signal; 1657 enum dc_irq_source irq_source_hpd; 1658 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1659 1660 bool is_hpd_filter_disabled; 1661 bool dp_ss_off; 1662 1663 /** 1664 * @link_state_valid: 1665 * 1666 * If there is no link and local sink, this variable should be set to 1667 * false. Otherwise, it should be set to true; usually, the function 1668 * core_link_enable_stream sets this field to true. 1669 */ 1670 bool link_state_valid; 1671 bool aux_access_disabled; 1672 bool sync_lt_in_progress; 1673 bool skip_stream_reenable; 1674 bool is_internal_display; 1675 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1676 bool is_dig_mapping_flexible; 1677 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1678 bool is_hpd_pending; /* Indicates a new received hpd */ 1679 1680 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1681 * for every link training. This is incompatible with DP LL compliance automation, 1682 * which expects the same link settings to be used every retry on a link loss. 1683 * This flag is used to skip the fallback when link loss occurs during automation. 1684 */ 1685 bool skip_fallback_on_link_loss; 1686 1687 bool edp_sink_present; 1688 1689 struct dp_trace dp_trace; 1690 1691 /* caps is the same as reported_link_cap. link_traing use 1692 * reported_link_cap. Will clean up. TODO 1693 */ 1694 struct dc_link_settings reported_link_cap; 1695 struct dc_link_settings verified_link_cap; 1696 struct dc_link_settings cur_link_settings; 1697 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1698 struct dc_link_settings preferred_link_setting; 1699 /* preferred_training_settings are override values that 1700 * come from DM. DM is responsible for the memory 1701 * management of the override pointers. 1702 */ 1703 struct dc_link_training_overrides preferred_training_settings; 1704 struct dp_audio_test_data audio_test_data; 1705 1706 uint8_t ddc_hw_inst; 1707 1708 uint8_t hpd_src; 1709 1710 uint8_t link_enc_hw_inst; 1711 /* DIG link encoder ID. Used as index in link encoder resource pool. 1712 * For links with fixed mapping to DIG, this is not changed after dc_link 1713 * object creation. 1714 */ 1715 enum engine_id eng_id; 1716 enum engine_id dpia_preferred_eng_id; 1717 1718 bool test_pattern_enabled; 1719 /* Pending/Current test pattern are only used to perform and track 1720 * FIXED_VS retimer test pattern/lane adjustment override state. 1721 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1722 * to perform specific lane adjust overrides before setting certain 1723 * PHY test patterns. In cases when lane adjust and set test pattern 1724 * calls are not performed atomically (i.e. performing link training), 1725 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1726 * and current_test_pattern will contain required context for any future 1727 * set pattern/set lane adjust to transition between override state(s). 1728 * */ 1729 enum dp_test_pattern current_test_pattern; 1730 enum dp_test_pattern pending_test_pattern; 1731 1732 union compliance_test_state compliance_test_state; 1733 1734 void *priv; 1735 1736 struct ddc_service *ddc; 1737 1738 enum dp_panel_mode panel_mode; 1739 bool aux_mode; 1740 1741 /* Private to DC core */ 1742 1743 const struct dc *dc; 1744 1745 struct dc_context *ctx; 1746 1747 struct panel_cntl *panel_cntl; 1748 struct link_encoder *link_enc; 1749 struct graphics_object_id link_id; 1750 /* Endpoint type distinguishes display endpoints which do not have entries 1751 * in the BIOS connector table from those that do. Helps when tracking link 1752 * encoder to display endpoint assignments. 1753 */ 1754 enum display_endpoint_type ep_type; 1755 union ddi_channel_mapping ddi_channel_mapping; 1756 struct connector_device_tag_info device_tag; 1757 struct dpcd_caps dpcd_caps; 1758 uint32_t dongle_max_pix_clk; 1759 unsigned short chip_caps; 1760 unsigned int dpcd_sink_count; 1761 struct hdcp_caps hdcp_caps; 1762 enum edp_revision edp_revision; 1763 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1764 1765 struct psr_settings psr_settings; 1766 struct replay_settings replay_settings; 1767 1768 /* Drive settings read from integrated info table */ 1769 struct dc_lane_settings bios_forced_drive_settings; 1770 1771 /* Vendor specific LTTPR workaround variables */ 1772 uint8_t vendor_specific_lttpr_link_rate_wa; 1773 bool apply_vendor_specific_lttpr_link_rate_wa; 1774 1775 /* MST record stream using this link */ 1776 struct link_flags { 1777 bool dp_keep_receiver_powered; 1778 bool dp_skip_DID2; 1779 bool dp_skip_reset_segment; 1780 bool dp_skip_fs_144hz; 1781 bool dp_mot_reset_segment; 1782 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1783 bool dpia_mst_dsc_always_on; 1784 /* Forced DPIA into TBT3 compatibility mode. */ 1785 bool dpia_forced_tbt3_mode; 1786 bool dongle_mode_timing_override; 1787 bool blank_stream_on_ocs_change; 1788 bool read_dpcd204h_on_irq_hpd; 1789 } wa_flags; 1790 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1791 1792 struct dc_link_status link_status; 1793 struct dprx_states dprx_states; 1794 1795 struct gpio *hpd_gpio; 1796 enum dc_link_fec_state fec_state; 1797 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1798 1799 struct dc_panel_config panel_config; 1800 struct phy_state phy_state; 1801 // BW ALLOCATON USB4 ONLY 1802 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1803 bool skip_implict_edp_power_control; 1804 enum backlight_control_type backlight_control_type; 1805 }; 1806 1807 /* Return an enumerated dc_link. 1808 * dc_link order is constant and determined at 1809 * boot time. They cannot be created or destroyed. 1810 * Use dc_get_caps() to get number of links. 1811 */ 1812 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1813 1814 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1815 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1816 const struct dc_link *link, 1817 unsigned int *inst_out); 1818 1819 /* Return an array of link pointers to edp links. */ 1820 void dc_get_edp_links(const struct dc *dc, 1821 struct dc_link **edp_links, 1822 int *edp_num); 1823 1824 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1825 bool powerOn); 1826 1827 /* The function initiates detection handshake over the given link. It first 1828 * determines if there are display connections over the link. If so it initiates 1829 * detection protocols supported by the connected receiver device. The function 1830 * contains protocol specific handshake sequences which are sometimes mandatory 1831 * to establish a proper connection between TX and RX. So it is always 1832 * recommended to call this function as the first link operation upon HPD event 1833 * or power up event. Upon completion, the function will update link structure 1834 * in place based on latest RX capabilities. The function may also cause dpms 1835 * to be reset to off for all currently enabled streams to the link. It is DM's 1836 * responsibility to serialize detection and DPMS updates. 1837 * 1838 * @reason - Indicate which event triggers this detection. dc may customize 1839 * detection flow depending on the triggering events. 1840 * return false - if detection is not fully completed. This could happen when 1841 * there is an unrecoverable error during detection or detection is partially 1842 * completed (detection has been delegated to dm mst manager ie. 1843 * link->connection_type == dc_connection_mst_branch when returning false). 1844 * return true - detection is completed, link has been fully updated with latest 1845 * detection result. 1846 */ 1847 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1848 1849 struct dc_sink_init_data; 1850 1851 /* When link connection type is dc_connection_mst_branch, remote sink can be 1852 * added to the link. The interface creates a remote sink and associates it with 1853 * current link. The sink will be retained by link until remove remote sink is 1854 * called. 1855 * 1856 * @dc_link - link the remote sink will be added to. 1857 * @edid - byte array of EDID raw data. 1858 * @len - size of the edid in byte 1859 * @init_data - 1860 */ 1861 struct dc_sink *dc_link_add_remote_sink( 1862 struct dc_link *dc_link, 1863 const uint8_t *edid, 1864 int len, 1865 struct dc_sink_init_data *init_data); 1866 1867 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1868 * @link - link the sink should be removed from 1869 * @sink - sink to be removed. 1870 */ 1871 void dc_link_remove_remote_sink( 1872 struct dc_link *link, 1873 struct dc_sink *sink); 1874 1875 /* Enable HPD interrupt handler for a given link */ 1876 void dc_link_enable_hpd(const struct dc_link *link); 1877 1878 /* Disable HPD interrupt handler for a given link */ 1879 void dc_link_disable_hpd(const struct dc_link *link); 1880 1881 /* determine if there is a sink connected to the link 1882 * 1883 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1884 * return - false if an unexpected error occurs, true otherwise. 1885 * 1886 * NOTE: This function doesn't detect downstream sink connections i.e 1887 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1888 * return dc_connection_single if the branch device is connected despite of 1889 * downstream sink's connection status. 1890 */ 1891 bool dc_link_detect_connection_type(struct dc_link *link, 1892 enum dc_connection_type *type); 1893 1894 /* query current hpd pin value 1895 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1896 * 1897 */ 1898 bool dc_link_get_hpd_state(struct dc_link *link); 1899 1900 /* Getter for cached link status from given link */ 1901 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1902 1903 /* enable/disable hardware HPD filter. 1904 * 1905 * @link - The link the HPD pin is associated with. 1906 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1907 * handler once after no HPD change has been detected within dc default HPD 1908 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1909 * pulses within default HPD interval, no HPD event will be received until HPD 1910 * toggles have stopped. Then HPD event will be queued to irq handler once after 1911 * dc default HPD filtering interval since last HPD event. 1912 * 1913 * @enable = false - disable hardware HPD filter. HPD event will be queued 1914 * immediately to irq handler after no HPD change has been detected within 1915 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1916 */ 1917 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1918 1919 /* submit i2c read/write payloads through ddc channel 1920 * @link_index - index to a link with ddc in i2c mode 1921 * @cmd - i2c command structure 1922 * return - true if success, false otherwise. 1923 */ 1924 bool dc_submit_i2c( 1925 struct dc *dc, 1926 uint32_t link_index, 1927 struct i2c_command *cmd); 1928 1929 /* submit i2c read/write payloads through oem channel 1930 * @link_index - index to a link with ddc in i2c mode 1931 * @cmd - i2c command structure 1932 * return - true if success, false otherwise. 1933 */ 1934 bool dc_submit_i2c_oem( 1935 struct dc *dc, 1936 struct i2c_command *cmd); 1937 1938 enum aux_return_code_type; 1939 /* Attempt to transfer the given aux payload. This function does not perform 1940 * retries or handle error states. The reply is returned in the payload->reply 1941 * and the result through operation_result. Returns the number of bytes 1942 * transferred,or -1 on a failure. 1943 */ 1944 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1945 struct aux_payload *payload, 1946 enum aux_return_code_type *operation_result); 1947 1948 struct ddc_service * 1949 dc_get_oem_i2c_device(struct dc *dc); 1950 1951 bool dc_is_oem_i2c_device_present( 1952 struct dc *dc, 1953 size_t slave_address 1954 ); 1955 1956 /* return true if the connected receiver supports the hdcp version */ 1957 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1958 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1959 1960 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1961 * 1962 * TODO - When defer_handling is true the function will have a different purpose. 1963 * It no longer does complete hpd rx irq handling. We should create a separate 1964 * interface specifically for this case. 1965 * 1966 * Return: 1967 * true - Downstream port status changed. DM should call DC to do the 1968 * detection. 1969 * false - no change in Downstream port status. No further action required 1970 * from DM. 1971 */ 1972 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1973 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1974 bool defer_handling, bool *has_left_work); 1975 /* handle DP specs define test automation sequence*/ 1976 void dc_link_dp_handle_automated_test(struct dc_link *link); 1977 1978 /* handle DP Link loss sequence and try to recover RX link loss with best 1979 * effort 1980 */ 1981 void dc_link_dp_handle_link_loss(struct dc_link *link); 1982 1983 /* Determine if hpd rx irq should be handled or ignored 1984 * return true - hpd rx irq should be handled. 1985 * return false - it is safe to ignore hpd rx irq event 1986 */ 1987 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1988 1989 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1990 * @link - link the hpd irq data associated with 1991 * @hpd_irq_dpcd_data - input hpd irq data 1992 * return - true if hpd irq data indicates a link lost 1993 */ 1994 bool dc_link_check_link_loss_status(struct dc_link *link, 1995 union hpd_irq_data *hpd_irq_dpcd_data); 1996 1997 /* Read hpd rx irq data from a given link 1998 * @link - link where the hpd irq data should be read from 1999 * @irq_data - output hpd irq data 2000 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2001 * read has failed. 2002 */ 2003 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2004 struct dc_link *link, 2005 union hpd_irq_data *irq_data); 2006 2007 /* The function clears recorded DP RX states in the link. DM should call this 2008 * function when it is resuming from S3 power state to previously connected links. 2009 * 2010 * TODO - in the future we should consider to expand link resume interface to 2011 * support clearing previous rx states. So we don't have to rely on dm to call 2012 * this interface explicitly. 2013 */ 2014 void dc_link_clear_dprx_states(struct dc_link *link); 2015 2016 /* Destruct the mst topology of the link and reset the allocated payload table 2017 * 2018 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2019 * still wants to reset MST topology on an unplug event */ 2020 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2021 2022 /* The function calculates effective DP link bandwidth when a given link is 2023 * using the given link settings. 2024 * 2025 * return - total effective link bandwidth in kbps. 2026 */ 2027 uint32_t dc_link_bandwidth_kbps( 2028 const struct dc_link *link, 2029 const struct dc_link_settings *link_setting); 2030 2031 struct dp_audio_bandwidth_params { 2032 const struct dc_crtc_timing *crtc_timing; 2033 enum dp_link_encoding link_encoding; 2034 uint32_t channel_count; 2035 uint32_t sample_rate_hz; 2036 }; 2037 2038 /* The function calculates the minimum size of hblank (in bytes) needed to 2039 * support the specified channel count and sample rate combination, given the 2040 * link encoding and timing to be used. This calculation is not supported 2041 * for 8b/10b SST. 2042 * 2043 * return - min hblank size in bytes, 0 if 8b/10b SST. 2044 */ 2045 uint32_t dc_link_required_hblank_size_bytes( 2046 const struct dc_link *link, 2047 struct dp_audio_bandwidth_params *audio_params); 2048 2049 /* The function takes a snapshot of current link resource allocation state 2050 * @dc: pointer to dc of the dm calling this 2051 * @map: a dc link resource snapshot defined internally to dc. 2052 * 2053 * DM needs to capture a snapshot of current link resource allocation mapping 2054 * and store it in its persistent storage. 2055 * 2056 * Some of the link resource is using first come first serve policy. 2057 * The allocation mapping depends on original hotplug order. This information 2058 * is lost after driver is loaded next time. The snapshot is used in order to 2059 * restore link resource to its previous state so user will get consistent 2060 * link capability allocation across reboot. 2061 * 2062 */ 2063 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2064 2065 /* This function restores link resource allocation state from a snapshot 2066 * @dc: pointer to dc of the dm calling this 2067 * @map: a dc link resource snapshot defined internally to dc. 2068 * 2069 * DM needs to call this function after initial link detection on boot and 2070 * before first commit streams to restore link resource allocation state 2071 * from previous boot session. 2072 * 2073 * Some of the link resource is using first come first serve policy. 2074 * The allocation mapping depends on original hotplug order. This information 2075 * is lost after driver is loaded next time. The snapshot is used in order to 2076 * restore link resource to its previous state so user will get consistent 2077 * link capability allocation across reboot. 2078 * 2079 */ 2080 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2081 2082 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2083 * interface i.e stream_update->dsc_config 2084 */ 2085 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2086 2087 /* translate a raw link rate data to bandwidth in kbps */ 2088 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2089 2090 /* determine the optimal bandwidth given link and required bw. 2091 * @link - current detected link 2092 * @req_bw - requested bandwidth in kbps 2093 * @link_settings - returned most optimal link settings that can fit the 2094 * requested bandwidth 2095 * return - false if link can't support requested bandwidth, true if link 2096 * settings is found. 2097 */ 2098 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2099 struct dc_link_settings *link_settings, 2100 uint32_t req_bw); 2101 2102 /* return the max dp link settings can be driven by the link without considering 2103 * connected RX device and its capability 2104 */ 2105 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2106 struct dc_link_settings *max_link_enc_cap); 2107 2108 /* determine when the link is driving MST mode, what DP link channel coding 2109 * format will be used. The decision will remain unchanged until next HPD event. 2110 * 2111 * @link - a link with DP RX connection 2112 * return - if stream is committed to this link with MST signal type, type of 2113 * channel coding format dc will choose. 2114 */ 2115 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2116 const struct dc_link *link); 2117 2118 /* get max dp link settings the link can enable with all things considered. (i.e 2119 * TX/RX/Cable capabilities and dp override policies. 2120 * 2121 * @link - a link with DP RX connection 2122 * return - max dp link settings the link can enable. 2123 * 2124 */ 2125 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2126 2127 /* Get the highest encoding format that the link supports; highest meaning the 2128 * encoding format which supports the maximum bandwidth. 2129 * 2130 * @link - a link with DP RX connection 2131 * return - highest encoding format link supports. 2132 */ 2133 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2134 2135 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2136 * to a link with dp connector signal type. 2137 * @link - a link with dp connector signal type 2138 * return - true if connected, false otherwise 2139 */ 2140 bool dc_link_is_dp_sink_present(struct dc_link *link); 2141 2142 /* Force DP lane settings update to main-link video signal and notify the change 2143 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2144 * tuning purpose. The interface assumes link has already been enabled with DP 2145 * signal. 2146 * 2147 * @lt_settings - a container structure with desired hw_lane_settings 2148 */ 2149 void dc_link_set_drive_settings(struct dc *dc, 2150 struct link_training_settings *lt_settings, 2151 struct dc_link *link); 2152 2153 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2154 * test or debugging purpose. The test pattern will remain until next un-plug. 2155 * 2156 * @link - active link with DP signal output enabled. 2157 * @test_pattern - desired test pattern to output. 2158 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2159 * @test_pattern_color_space - for video test pattern choose a desired color 2160 * space. 2161 * @p_link_settings - For PHY pattern choose a desired link settings 2162 * @p_custom_pattern - some test pattern will require a custom input to 2163 * customize some pattern details. Otherwise keep it to NULL. 2164 * @cust_pattern_size - size of the custom pattern input. 2165 * 2166 */ 2167 bool dc_link_dp_set_test_pattern( 2168 struct dc_link *link, 2169 enum dp_test_pattern test_pattern, 2170 enum dp_test_pattern_color_space test_pattern_color_space, 2171 const struct link_training_settings *p_link_settings, 2172 const unsigned char *p_custom_pattern, 2173 unsigned int cust_pattern_size); 2174 2175 /* Force DP link settings to always use a specific value until reboot to a 2176 * specific link. If link has already been enabled, the interface will also 2177 * switch to desired link settings immediately. This is a debug interface to 2178 * generic dp issue trouble shooting. 2179 */ 2180 void dc_link_set_preferred_link_settings(struct dc *dc, 2181 struct dc_link_settings *link_setting, 2182 struct dc_link *link); 2183 2184 /* Force DP link to customize a specific link training behavior by overriding to 2185 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2186 * display specific link training issues or apply some display specific 2187 * workaround in link training. 2188 * 2189 * @link_settings - if not NULL, force preferred link settings to the link. 2190 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2191 * will apply this particular override in future link training. If NULL is 2192 * passed in, dc resets previous overrides. 2193 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2194 * training settings. 2195 */ 2196 void dc_link_set_preferred_training_settings(struct dc *dc, 2197 struct dc_link_settings *link_setting, 2198 struct dc_link_training_overrides *lt_overrides, 2199 struct dc_link *link, 2200 bool skip_immediate_retrain); 2201 2202 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2203 bool dc_link_is_fec_supported(const struct dc_link *link); 2204 2205 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2206 * link enablement. 2207 * return - true if FEC should be enabled, false otherwise. 2208 */ 2209 bool dc_link_should_enable_fec(const struct dc_link *link); 2210 2211 /* determine lttpr mode the current link should be enabled with a specific link 2212 * settings. 2213 */ 2214 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2215 struct dc_link_settings *link_setting); 2216 2217 /* Force DP RX to update its power state. 2218 * NOTE: this interface doesn't update dp main-link. Calling this function will 2219 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2220 * RX power state back upon finish DM specific execution requiring DP RX in a 2221 * specific power state. 2222 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2223 * state. 2224 */ 2225 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2226 2227 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2228 * current value read from extended receiver cap from 02200h - 0220Fh. 2229 * Some DP RX has problems of providing accurate DP receiver caps from extended 2230 * field, this interface is a workaround to revert link back to use base caps. 2231 */ 2232 void dc_link_overwrite_extended_receiver_cap( 2233 struct dc_link *link); 2234 2235 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2236 bool wait_for_hpd); 2237 2238 /* Set backlight level of an embedded panel (eDP, LVDS). 2239 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2240 * and 16 bit fractional, where 1.0 is max backlight value. 2241 */ 2242 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2243 struct set_backlight_level_params *backlight_level_params); 2244 2245 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2246 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2247 bool isHDR, 2248 uint32_t backlight_millinits, 2249 uint32_t transition_time_in_ms); 2250 2251 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2252 uint32_t *backlight_millinits, 2253 uint32_t *backlight_millinits_peak); 2254 2255 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2256 2257 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2258 2259 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2260 bool wait, bool force_static, const unsigned int *power_opts); 2261 2262 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2263 2264 bool dc_link_setup_psr(struct dc_link *dc_link, 2265 const struct dc_stream_state *stream, struct psr_config *psr_config, 2266 struct psr_context *psr_context); 2267 2268 /* 2269 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2270 * 2271 * @link: pointer to the dc_link struct instance 2272 * @enable: enable(active) or disable(inactive) replay 2273 * @wait: state transition need to wait the active set completed. 2274 * @force_static: force disable(inactive) the replay 2275 * @power_opts: set power optimazation parameters to DMUB. 2276 * 2277 * return: allow Replay active will return true, else will return false. 2278 */ 2279 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2280 bool wait, bool force_static, const unsigned int *power_opts); 2281 2282 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2283 2284 /* On eDP links this function call will stall until T12 has elapsed. 2285 * If the panel is not in power off state, this function will return 2286 * immediately. 2287 */ 2288 bool dc_link_wait_for_t12(struct dc_link *link); 2289 2290 /* Determine if dp trace has been initialized to reflect upto date result * 2291 * return - true if trace is initialized and has valid data. False dp trace 2292 * doesn't have valid result. 2293 */ 2294 bool dc_dp_trace_is_initialized(struct dc_link *link); 2295 2296 /* Query a dp trace flag to indicate if the current dp trace data has been 2297 * logged before 2298 */ 2299 bool dc_dp_trace_is_logged(struct dc_link *link, 2300 bool in_detection); 2301 2302 /* Set dp trace flag to indicate whether DM has already logged the current dp 2303 * trace data. DM can set is_logged to true upon logging and check 2304 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2305 */ 2306 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2307 bool in_detection, 2308 bool is_logged); 2309 2310 /* Obtain driver time stamp for last dp link training end. The time stamp is 2311 * formatted based on dm_get_timestamp DM function. 2312 * @in_detection - true to get link training end time stamp of last link 2313 * training in detection sequence. false to get link training end time stamp 2314 * of last link training in commit (dpms) sequence 2315 */ 2316 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2317 bool in_detection); 2318 2319 /* Get how many link training attempts dc has done with latest sequence. 2320 * @in_detection - true to get link training count of last link 2321 * training in detection sequence. false to get link training count of last link 2322 * training in commit (dpms) sequence 2323 */ 2324 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2325 bool in_detection); 2326 2327 /* Get how many link loss has happened since last link training attempts */ 2328 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2329 2330 /* 2331 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2332 */ 2333 /* 2334 * Send a request from DP-Tx requesting to allocate BW remotely after 2335 * allocating it locally. This will get processed by CM and a CB function 2336 * will be called. 2337 * 2338 * @link: pointer to the dc_link struct instance 2339 * @req_bw: The requested bw in Kbyte to allocated 2340 * 2341 * return: none 2342 */ 2343 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2344 2345 /* 2346 * Handle function for when the status of the Request above is complete. 2347 * We will find out the result of allocating on CM and update structs. 2348 * 2349 * @link: pointer to the dc_link struct instance 2350 * @bw: Allocated or Estimated BW depending on the result 2351 * @result: Response type 2352 * 2353 * return: none 2354 */ 2355 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2356 uint8_t bw, uint8_t result); 2357 2358 /* 2359 * Handle the USB4 BW Allocation related functionality here: 2360 * Plug => Try to allocate max bw from timing parameters supported by the sink 2361 * Unplug => de-allocate bw 2362 * 2363 * @link: pointer to the dc_link struct instance 2364 * @peak_bw: Peak bw used by the link/sink 2365 * 2366 * return: allocated bw else return 0 2367 */ 2368 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2369 struct dc_link *link, int peak_bw); 2370 2371 /* 2372 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2373 * available BW for each host router 2374 * 2375 * @dc: pointer to dc struct 2376 * @stream: pointer to all possible streams 2377 * @count: number of valid DPIA streams 2378 * 2379 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2380 */ 2381 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2382 const unsigned int count); 2383 2384 /* Sink Interfaces - A sink corresponds to a display output device */ 2385 2386 struct dc_container_id { 2387 // 128bit GUID in binary form 2388 unsigned char guid[16]; 2389 // 8 byte port ID -> ELD.PortID 2390 unsigned int portId[2]; 2391 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2392 unsigned short manufacturerName; 2393 // 2 byte product code -> ELD.ProductCode 2394 unsigned short productCode; 2395 }; 2396 2397 2398 struct dc_sink_dsc_caps { 2399 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2400 // 'false' if they are sink's DSC caps 2401 bool is_virtual_dpcd_dsc; 2402 // 'true' if MST topology supports DSC passthrough for sink 2403 // 'false' if MST topology does not support DSC passthrough 2404 bool is_dsc_passthrough_supported; 2405 struct dsc_dec_dpcd_caps dsc_dec_caps; 2406 }; 2407 2408 struct dc_sink_hblank_expansion_caps { 2409 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2410 // 'false' if they are sink's HBlank expansion caps 2411 bool is_virtual_dpcd_hblank_expansion; 2412 struct hblank_expansion_dpcd_caps dpcd_caps; 2413 }; 2414 2415 struct dc_sink_fec_caps { 2416 bool is_rx_fec_supported; 2417 bool is_topology_fec_supported; 2418 }; 2419 2420 struct scdc_caps { 2421 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2422 union hdmi_scdc_device_id_data device_id; 2423 }; 2424 2425 /* 2426 * The sink structure contains EDID and other display device properties 2427 */ 2428 struct dc_sink { 2429 enum signal_type sink_signal; 2430 struct dc_edid dc_edid; /* raw edid */ 2431 struct dc_edid_caps edid_caps; /* parse display caps */ 2432 struct dc_container_id *dc_container_id; 2433 uint32_t dongle_max_pix_clk; 2434 void *priv; 2435 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2436 bool converter_disable_audio; 2437 2438 struct scdc_caps scdc_caps; 2439 struct dc_sink_dsc_caps dsc_caps; 2440 struct dc_sink_fec_caps fec_caps; 2441 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2442 2443 bool is_vsc_sdp_colorimetry_supported; 2444 2445 /* private to DC core */ 2446 struct dc_link *link; 2447 struct dc_context *ctx; 2448 2449 uint32_t sink_id; 2450 2451 /* private to dc_sink.c */ 2452 // refcount must be the last member in dc_sink, since we want the 2453 // sink structure to be logically cloneable up to (but not including) 2454 // refcount 2455 struct kref refcount; 2456 }; 2457 2458 void dc_sink_retain(struct dc_sink *sink); 2459 void dc_sink_release(struct dc_sink *sink); 2460 2461 struct dc_sink_init_data { 2462 enum signal_type sink_signal; 2463 struct dc_link *link; 2464 uint32_t dongle_max_pix_clk; 2465 bool converter_disable_audio; 2466 }; 2467 2468 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2469 2470 /* Newer interfaces */ 2471 struct dc_cursor { 2472 struct dc_plane_address address; 2473 struct dc_cursor_attributes attributes; 2474 }; 2475 2476 2477 /* Interrupt interfaces */ 2478 enum dc_irq_source dc_interrupt_to_irq_source( 2479 struct dc *dc, 2480 uint32_t src_id, 2481 uint32_t ext_id); 2482 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2483 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2484 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2485 struct dc *dc, uint32_t link_index); 2486 2487 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2488 2489 /* Power Interfaces */ 2490 2491 void dc_set_power_state( 2492 struct dc *dc, 2493 enum dc_acpi_cm_power_state power_state); 2494 void dc_resume(struct dc *dc); 2495 2496 void dc_power_down_on_boot(struct dc *dc); 2497 2498 /* 2499 * HDCP Interfaces 2500 */ 2501 enum hdcp_message_status dc_process_hdcp_msg( 2502 enum signal_type signal, 2503 struct dc_link *link, 2504 struct hdcp_protection_message *message_info); 2505 bool dc_is_dmcu_initialized(struct dc *dc); 2506 2507 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2508 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2509 2510 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2511 unsigned int pitch, 2512 unsigned int height, 2513 enum surface_pixel_format format, 2514 struct dc_cursor_attributes *cursor_attr); 2515 2516 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2517 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2518 2519 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2520 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2521 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2522 2523 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2524 void dc_unlock_memory_clock_frequency(struct dc *dc); 2525 2526 /* set min memory clock to the min required for current mode, max to maxDPM */ 2527 void dc_lock_memory_clock_frequency(struct dc *dc); 2528 2529 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2530 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2531 2532 /* cleanup on driver unload */ 2533 void dc_hardware_release(struct dc *dc); 2534 2535 /* disables fw based mclk switch */ 2536 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2537 2538 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2539 2540 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2541 2542 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2543 2544 void dc_z10_restore(const struct dc *dc); 2545 void dc_z10_save_init(struct dc *dc); 2546 2547 bool dc_is_dmub_outbox_supported(struct dc *dc); 2548 bool dc_enable_dmub_notifications(struct dc *dc); 2549 2550 bool dc_abm_save_restore( 2551 struct dc *dc, 2552 struct dc_stream_state *stream, 2553 struct abm_save_restore *pData); 2554 2555 void dc_enable_dmub_outbox(struct dc *dc); 2556 2557 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2558 uint32_t link_index, 2559 struct aux_payload *payload); 2560 2561 /* Get dc link index from dpia port index */ 2562 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2563 uint8_t dpia_port_index); 2564 2565 bool dc_process_dmub_set_config_async(struct dc *dc, 2566 uint32_t link_index, 2567 struct set_config_cmd_payload *payload, 2568 struct dmub_notification *notify); 2569 2570 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2571 uint32_t link_index, 2572 uint8_t mst_alloc_slots, 2573 uint8_t *mst_slots_in_use); 2574 2575 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2576 2577 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2578 uint32_t hpd_int_enable); 2579 2580 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2581 2582 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2583 2584 struct dc_power_profile { 2585 int power_level; /* Lower is better */ 2586 }; 2587 2588 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2589 2590 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2591 2592 /* DSC Interfaces */ 2593 #include "dc_dsc.h" 2594 2595 /* Disable acc mode Interfaces */ 2596 void dc_disable_accelerated_mode(struct dc *dc); 2597 2598 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2599 struct dc_stream_state *new_stream); 2600 2601 #endif /* DC_INTERFACE_H_ */ 2602