1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 case DCE_VERSION_11_22: 56 *h = dal_cmd_tbl_helper_dce112_get_table2(); 57 return true; 58 #if defined(CONFIG_DRM_AMD_DC_DCN) 59 case DCN_VERSION_1_0: 60 case DCN_VERSION_1_01: 61 *h = dal_cmd_tbl_helper_dce112_get_table2(); 62 return true; 63 #endif 64 65 case DCN_VERSION_2_0: 66 *h = dal_cmd_tbl_helper_dce112_get_table2(); 67 return true; 68 case DCN_VERSION_2_1: 69 *h = dal_cmd_tbl_helper_dce112_get_table2(); 70 return true; 71 case DCE_VERSION_12_0: 72 case DCE_VERSION_12_1: 73 *h = dal_cmd_tbl_helper_dce112_get_table2(); 74 return true; 75 76 default: 77 /* Unsupported DCE */ 78 BREAK_TO_DEBUGGER(); 79 return false; 80 } 81 } 82 83 /* real implementations */ 84 85 bool dal_cmd_table_helper_controller_id_to_atom2( 86 enum controller_id id, 87 uint8_t *atom_id) 88 { 89 if (atom_id == NULL) { 90 BREAK_TO_DEBUGGER(); 91 return false; 92 } 93 94 switch (id) { 95 case CONTROLLER_ID_D0: 96 *atom_id = ATOM_CRTC1; 97 return true; 98 case CONTROLLER_ID_D1: 99 *atom_id = ATOM_CRTC2; 100 return true; 101 case CONTROLLER_ID_D2: 102 *atom_id = ATOM_CRTC3; 103 return true; 104 case CONTROLLER_ID_D3: 105 *atom_id = ATOM_CRTC4; 106 return true; 107 case CONTROLLER_ID_D4: 108 *atom_id = ATOM_CRTC5; 109 return true; 110 case CONTROLLER_ID_D5: 111 *atom_id = ATOM_CRTC6; 112 return true; 113 /* TODO :case CONTROLLER_ID_UNDERLAY0: 114 *atom_id = ATOM_UNDERLAY_PIPE0; 115 return true; 116 */ 117 case CONTROLLER_ID_UNDEFINED: 118 *atom_id = ATOM_CRTC_INVALID; 119 return true; 120 default: 121 /* Wrong controller id */ 122 BREAK_TO_DEBUGGER(); 123 return false; 124 } 125 } 126 127 /** 128 * translate_transmitter_bp_to_atom 129 * 130 * @brief 131 * Translate the Transmitter to the corresponding ATOM BIOS value 132 * 133 * @param 134 * input transmitter 135 * output digitalTransmitter 136 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 137 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 138 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 139 */ 140 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 141 enum transmitter t) 142 { 143 switch (t) { 144 case TRANSMITTER_UNIPHY_A: 145 case TRANSMITTER_UNIPHY_B: 146 case TRANSMITTER_TRAVIS_LCD: 147 return 0; 148 case TRANSMITTER_UNIPHY_C: 149 case TRANSMITTER_UNIPHY_D: 150 return 1; 151 case TRANSMITTER_UNIPHY_E: 152 case TRANSMITTER_UNIPHY_F: 153 return 2; 154 default: 155 /* Invalid Transmitter Type! */ 156 BREAK_TO_DEBUGGER(); 157 return 0; 158 } 159 } 160 161 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 162 enum signal_type s, 163 bool enable_dp_audio) 164 { 165 switch (s) { 166 case SIGNAL_TYPE_DVI_SINGLE_LINK: 167 case SIGNAL_TYPE_DVI_DUAL_LINK: 168 return ATOM_ENCODER_MODE_DVI; 169 case SIGNAL_TYPE_HDMI_TYPE_A: 170 return ATOM_ENCODER_MODE_HDMI; 171 case SIGNAL_TYPE_LVDS: 172 return ATOM_ENCODER_MODE_LVDS; 173 case SIGNAL_TYPE_EDP: 174 case SIGNAL_TYPE_DISPLAY_PORT_MST: 175 case SIGNAL_TYPE_DISPLAY_PORT: 176 case SIGNAL_TYPE_VIRTUAL: 177 if (enable_dp_audio) 178 return ATOM_ENCODER_MODE_DP_AUDIO; 179 else 180 return ATOM_ENCODER_MODE_DP; 181 case SIGNAL_TYPE_RGB: 182 return ATOM_ENCODER_MODE_CRT; 183 default: 184 return ATOM_ENCODER_MODE_CRT; 185 } 186 } 187 188 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 189 enum clock_source_id id, 190 uint32_t *ref_clk_src_id) 191 { 192 if (ref_clk_src_id == NULL) { 193 BREAK_TO_DEBUGGER(); 194 return false; 195 } 196 197 switch (id) { 198 case CLOCK_SOURCE_ID_PLL1: 199 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 200 return true; 201 case CLOCK_SOURCE_ID_PLL2: 202 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 203 return true; 204 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 205 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 206 return true; 207 */ 208 case CLOCK_SOURCE_ID_EXTERNAL: 209 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 210 return true; 211 case CLOCK_SOURCE_ID_UNDEFINED: 212 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 213 return true; 214 default: 215 /* Unsupported clock source id */ 216 BREAK_TO_DEBUGGER(); 217 return false; 218 } 219 } 220 221 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 222 enum encoder_id id) 223 { 224 switch (id) { 225 case ENCODER_ID_INTERNAL_LVDS: 226 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 227 case ENCODER_ID_INTERNAL_TMDS1: 228 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 229 case ENCODER_ID_INTERNAL_TMDS2: 230 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 231 case ENCODER_ID_INTERNAL_DAC1: 232 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 233 case ENCODER_ID_INTERNAL_DAC2: 234 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 235 case ENCODER_ID_INTERNAL_LVTM1: 236 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 237 case ENCODER_ID_INTERNAL_HDMI: 238 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 239 case ENCODER_ID_EXTERNAL_TRAVIS: 240 return ENCODER_OBJECT_ID_TRAVIS; 241 case ENCODER_ID_EXTERNAL_NUTMEG: 242 return ENCODER_OBJECT_ID_NUTMEG; 243 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 244 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 245 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 246 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 247 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 248 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 249 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 250 return ENCODER_OBJECT_ID_MVPU_FPGA; 251 case ENCODER_ID_INTERNAL_DDI: 252 return ENCODER_OBJECT_ID_INTERNAL_DDI; 253 case ENCODER_ID_INTERNAL_UNIPHY: 254 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 255 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 256 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 257 case ENCODER_ID_INTERNAL_UNIPHY1: 258 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 259 case ENCODER_ID_INTERNAL_UNIPHY2: 260 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 261 case ENCODER_ID_INTERNAL_UNIPHY3: 262 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 263 case ENCODER_ID_INTERNAL_WIRELESS: 264 return ENCODER_OBJECT_ID_INTERNAL_VCE; 265 case ENCODER_ID_INTERNAL_VIRTUAL: 266 return ENCODER_OBJECT_ID_NONE; 267 case ENCODER_ID_UNKNOWN: 268 return ENCODER_OBJECT_ID_NONE; 269 default: 270 /* Invalid encoder id */ 271 BREAK_TO_DEBUGGER(); 272 return ENCODER_OBJECT_ID_NONE; 273 } 274 } 275