1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 *h = dal_cmd_tbl_helper_dce112_get_table2(); 56 return true; 57 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 58 case DCN_VERSION_1_0: 59 *h = dal_cmd_tbl_helper_dce112_get_table2(); 60 return true; 61 #endif 62 63 case DCE_VERSION_12_0: 64 *h = dal_cmd_tbl_helper_dce112_get_table2(); 65 return true; 66 67 default: 68 /* Unsupported DCE */ 69 BREAK_TO_DEBUGGER(); 70 return false; 71 } 72 } 73 74 /* real implementations */ 75 76 bool dal_cmd_table_helper_controller_id_to_atom2( 77 enum controller_id id, 78 uint8_t *atom_id) 79 { 80 if (atom_id == NULL) { 81 BREAK_TO_DEBUGGER(); 82 return false; 83 } 84 85 switch (id) { 86 case CONTROLLER_ID_D0: 87 *atom_id = ATOM_CRTC1; 88 return true; 89 case CONTROLLER_ID_D1: 90 *atom_id = ATOM_CRTC2; 91 return true; 92 case CONTROLLER_ID_D2: 93 *atom_id = ATOM_CRTC3; 94 return true; 95 case CONTROLLER_ID_D3: 96 *atom_id = ATOM_CRTC4; 97 return true; 98 case CONTROLLER_ID_D4: 99 *atom_id = ATOM_CRTC5; 100 return true; 101 case CONTROLLER_ID_D5: 102 *atom_id = ATOM_CRTC6; 103 return true; 104 /* TODO :case CONTROLLER_ID_UNDERLAY0: 105 *atom_id = ATOM_UNDERLAY_PIPE0; 106 return true; 107 */ 108 case CONTROLLER_ID_UNDEFINED: 109 *atom_id = ATOM_CRTC_INVALID; 110 return true; 111 default: 112 /* Wrong controller id */ 113 BREAK_TO_DEBUGGER(); 114 return false; 115 } 116 } 117 118 /** 119 * translate_transmitter_bp_to_atom 120 * 121 * @brief 122 * Translate the Transmitter to the corresponding ATOM BIOS value 123 * 124 * @param 125 * input transmitter 126 * output digitalTransmitter 127 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 128 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 129 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 130 */ 131 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 132 enum transmitter t) 133 { 134 switch (t) { 135 case TRANSMITTER_UNIPHY_A: 136 case TRANSMITTER_UNIPHY_B: 137 case TRANSMITTER_TRAVIS_LCD: 138 return 0; 139 case TRANSMITTER_UNIPHY_C: 140 case TRANSMITTER_UNIPHY_D: 141 return 1; 142 case TRANSMITTER_UNIPHY_E: 143 case TRANSMITTER_UNIPHY_F: 144 return 2; 145 default: 146 /* Invalid Transmitter Type! */ 147 BREAK_TO_DEBUGGER(); 148 return 0; 149 } 150 } 151 152 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 153 enum signal_type s, 154 bool enable_dp_audio) 155 { 156 switch (s) { 157 case SIGNAL_TYPE_DVI_SINGLE_LINK: 158 case SIGNAL_TYPE_DVI_DUAL_LINK: 159 return ATOM_ENCODER_MODE_DVI; 160 case SIGNAL_TYPE_HDMI_TYPE_A: 161 return ATOM_ENCODER_MODE_HDMI; 162 case SIGNAL_TYPE_LVDS: 163 return ATOM_ENCODER_MODE_LVDS; 164 case SIGNAL_TYPE_EDP: 165 case SIGNAL_TYPE_DISPLAY_PORT_MST: 166 case SIGNAL_TYPE_DISPLAY_PORT: 167 case SIGNAL_TYPE_VIRTUAL: 168 if (enable_dp_audio) 169 return ATOM_ENCODER_MODE_DP_AUDIO; 170 else 171 return ATOM_ENCODER_MODE_DP; 172 case SIGNAL_TYPE_RGB: 173 return ATOM_ENCODER_MODE_CRT; 174 default: 175 return ATOM_ENCODER_MODE_CRT; 176 } 177 } 178 179 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 180 enum clock_source_id id, 181 uint32_t *ref_clk_src_id) 182 { 183 if (ref_clk_src_id == NULL) { 184 BREAK_TO_DEBUGGER(); 185 return false; 186 } 187 188 switch (id) { 189 case CLOCK_SOURCE_ID_PLL1: 190 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 191 return true; 192 case CLOCK_SOURCE_ID_PLL2: 193 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 194 return true; 195 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 196 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 197 return true; 198 */ 199 case CLOCK_SOURCE_ID_EXTERNAL: 200 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 201 return true; 202 case CLOCK_SOURCE_ID_UNDEFINED: 203 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 204 return true; 205 default: 206 /* Unsupported clock source id */ 207 BREAK_TO_DEBUGGER(); 208 return false; 209 } 210 } 211 212 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 213 enum encoder_id id) 214 { 215 switch (id) { 216 case ENCODER_ID_INTERNAL_LVDS: 217 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 218 case ENCODER_ID_INTERNAL_TMDS1: 219 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 220 case ENCODER_ID_INTERNAL_TMDS2: 221 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 222 case ENCODER_ID_INTERNAL_DAC1: 223 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 224 case ENCODER_ID_INTERNAL_DAC2: 225 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 226 case ENCODER_ID_INTERNAL_LVTM1: 227 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 228 case ENCODER_ID_INTERNAL_HDMI: 229 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 230 case ENCODER_ID_EXTERNAL_TRAVIS: 231 return ENCODER_OBJECT_ID_TRAVIS; 232 case ENCODER_ID_EXTERNAL_NUTMEG: 233 return ENCODER_OBJECT_ID_NUTMEG; 234 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 235 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 236 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 237 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 238 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 239 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 240 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 241 return ENCODER_OBJECT_ID_MVPU_FPGA; 242 case ENCODER_ID_INTERNAL_DDI: 243 return ENCODER_OBJECT_ID_INTERNAL_DDI; 244 case ENCODER_ID_INTERNAL_UNIPHY: 245 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 246 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 247 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 248 case ENCODER_ID_INTERNAL_UNIPHY1: 249 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 250 case ENCODER_ID_INTERNAL_UNIPHY2: 251 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 252 case ENCODER_ID_INTERNAL_UNIPHY3: 253 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 254 case ENCODER_ID_INTERNAL_WIRELESS: 255 return ENCODER_OBJECT_ID_INTERNAL_VCE; 256 case ENCODER_ID_INTERNAL_VIRTUAL: 257 return ENCODER_OBJECT_ID_NONE; 258 case ENCODER_ID_UNKNOWN: 259 return ENCODER_OBJECT_ID_NONE; 260 default: 261 /* Invalid encoder id */ 262 BREAK_TO_DEBUGGER(); 263 return ENCODER_OBJECT_ID_NONE; 264 } 265 } 266