1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 case DCE_VERSION_11_22: 56 *h = dal_cmd_tbl_helper_dce112_get_table2(); 57 return true; 58 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 59 case DCN_VERSION_1_0: 60 case DCN_VERSION_1_01: 61 *h = dal_cmd_tbl_helper_dce112_get_table2(); 62 return true; 63 #endif 64 65 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 66 case DCN_VERSION_2_0: 67 *h = dal_cmd_tbl_helper_dce112_get_table2(); 68 return true; 69 #endif 70 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 71 case DCN_VERSION_2_1: 72 *h = dal_cmd_tbl_helper_dce112_get_table2(); 73 return true; 74 #endif 75 case DCE_VERSION_12_0: 76 case DCE_VERSION_12_1: 77 *h = dal_cmd_tbl_helper_dce112_get_table2(); 78 return true; 79 80 default: 81 /* Unsupported DCE */ 82 BREAK_TO_DEBUGGER(); 83 return false; 84 } 85 } 86 87 /* real implementations */ 88 89 bool dal_cmd_table_helper_controller_id_to_atom2( 90 enum controller_id id, 91 uint8_t *atom_id) 92 { 93 if (atom_id == NULL) { 94 BREAK_TO_DEBUGGER(); 95 return false; 96 } 97 98 switch (id) { 99 case CONTROLLER_ID_D0: 100 *atom_id = ATOM_CRTC1; 101 return true; 102 case CONTROLLER_ID_D1: 103 *atom_id = ATOM_CRTC2; 104 return true; 105 case CONTROLLER_ID_D2: 106 *atom_id = ATOM_CRTC3; 107 return true; 108 case CONTROLLER_ID_D3: 109 *atom_id = ATOM_CRTC4; 110 return true; 111 case CONTROLLER_ID_D4: 112 *atom_id = ATOM_CRTC5; 113 return true; 114 case CONTROLLER_ID_D5: 115 *atom_id = ATOM_CRTC6; 116 return true; 117 /* TODO :case CONTROLLER_ID_UNDERLAY0: 118 *atom_id = ATOM_UNDERLAY_PIPE0; 119 return true; 120 */ 121 case CONTROLLER_ID_UNDEFINED: 122 *atom_id = ATOM_CRTC_INVALID; 123 return true; 124 default: 125 /* Wrong controller id */ 126 BREAK_TO_DEBUGGER(); 127 return false; 128 } 129 } 130 131 /** 132 * translate_transmitter_bp_to_atom 133 * 134 * @brief 135 * Translate the Transmitter to the corresponding ATOM BIOS value 136 * 137 * @param 138 * input transmitter 139 * output digitalTransmitter 140 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 141 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 142 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 143 */ 144 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 145 enum transmitter t) 146 { 147 switch (t) { 148 case TRANSMITTER_UNIPHY_A: 149 case TRANSMITTER_UNIPHY_B: 150 case TRANSMITTER_TRAVIS_LCD: 151 return 0; 152 case TRANSMITTER_UNIPHY_C: 153 case TRANSMITTER_UNIPHY_D: 154 return 1; 155 case TRANSMITTER_UNIPHY_E: 156 case TRANSMITTER_UNIPHY_F: 157 return 2; 158 default: 159 /* Invalid Transmitter Type! */ 160 BREAK_TO_DEBUGGER(); 161 return 0; 162 } 163 } 164 165 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 166 enum signal_type s, 167 bool enable_dp_audio) 168 { 169 switch (s) { 170 case SIGNAL_TYPE_DVI_SINGLE_LINK: 171 case SIGNAL_TYPE_DVI_DUAL_LINK: 172 return ATOM_ENCODER_MODE_DVI; 173 case SIGNAL_TYPE_HDMI_TYPE_A: 174 return ATOM_ENCODER_MODE_HDMI; 175 case SIGNAL_TYPE_LVDS: 176 return ATOM_ENCODER_MODE_LVDS; 177 case SIGNAL_TYPE_EDP: 178 case SIGNAL_TYPE_DISPLAY_PORT_MST: 179 case SIGNAL_TYPE_DISPLAY_PORT: 180 case SIGNAL_TYPE_VIRTUAL: 181 if (enable_dp_audio) 182 return ATOM_ENCODER_MODE_DP_AUDIO; 183 else 184 return ATOM_ENCODER_MODE_DP; 185 case SIGNAL_TYPE_RGB: 186 return ATOM_ENCODER_MODE_CRT; 187 default: 188 return ATOM_ENCODER_MODE_CRT; 189 } 190 } 191 192 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 193 enum clock_source_id id, 194 uint32_t *ref_clk_src_id) 195 { 196 if (ref_clk_src_id == NULL) { 197 BREAK_TO_DEBUGGER(); 198 return false; 199 } 200 201 switch (id) { 202 case CLOCK_SOURCE_ID_PLL1: 203 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 204 return true; 205 case CLOCK_SOURCE_ID_PLL2: 206 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 207 return true; 208 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 209 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 210 return true; 211 */ 212 case CLOCK_SOURCE_ID_EXTERNAL: 213 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 214 return true; 215 case CLOCK_SOURCE_ID_UNDEFINED: 216 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 217 return true; 218 default: 219 /* Unsupported clock source id */ 220 BREAK_TO_DEBUGGER(); 221 return false; 222 } 223 } 224 225 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 226 enum encoder_id id) 227 { 228 switch (id) { 229 case ENCODER_ID_INTERNAL_LVDS: 230 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 231 case ENCODER_ID_INTERNAL_TMDS1: 232 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 233 case ENCODER_ID_INTERNAL_TMDS2: 234 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 235 case ENCODER_ID_INTERNAL_DAC1: 236 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 237 case ENCODER_ID_INTERNAL_DAC2: 238 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 239 case ENCODER_ID_INTERNAL_LVTM1: 240 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 241 case ENCODER_ID_INTERNAL_HDMI: 242 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 243 case ENCODER_ID_EXTERNAL_TRAVIS: 244 return ENCODER_OBJECT_ID_TRAVIS; 245 case ENCODER_ID_EXTERNAL_NUTMEG: 246 return ENCODER_OBJECT_ID_NUTMEG; 247 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 248 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 249 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 250 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 251 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 252 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 253 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 254 return ENCODER_OBJECT_ID_MVPU_FPGA; 255 case ENCODER_ID_INTERNAL_DDI: 256 return ENCODER_OBJECT_ID_INTERNAL_DDI; 257 case ENCODER_ID_INTERNAL_UNIPHY: 258 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 259 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 260 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 261 case ENCODER_ID_INTERNAL_UNIPHY1: 262 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 263 case ENCODER_ID_INTERNAL_UNIPHY2: 264 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 265 case ENCODER_ID_INTERNAL_UNIPHY3: 266 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 267 case ENCODER_ID_INTERNAL_WIRELESS: 268 return ENCODER_OBJECT_ID_INTERNAL_VCE; 269 case ENCODER_ID_INTERNAL_VIRTUAL: 270 return ENCODER_OBJECT_ID_NONE; 271 case ENCODER_ID_UNKNOWN: 272 return ENCODER_OBJECT_ID_NONE; 273 default: 274 /* Invalid encoder id */ 275 BREAK_TO_DEBUGGER(); 276 return ENCODER_OBJECT_ID_NONE; 277 } 278 } 279