1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 case DCE_VERSION_11_22: 56 *h = dal_cmd_tbl_helper_dce112_get_table2(); 57 return true; 58 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 59 case DCN_VERSION_1_0: 60 case DCN_VERSION_1_01: 61 *h = dal_cmd_tbl_helper_dce112_get_table2(); 62 return true; 63 #endif 64 65 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 66 case DCN_VERSION_2_0: 67 *h = dal_cmd_tbl_helper_dce112_get_table2(); 68 return true; 69 #endif 70 case DCE_VERSION_12_0: 71 case DCE_VERSION_12_1: 72 *h = dal_cmd_tbl_helper_dce112_get_table2(); 73 return true; 74 75 default: 76 /* Unsupported DCE */ 77 BREAK_TO_DEBUGGER(); 78 return false; 79 } 80 } 81 82 /* real implementations */ 83 84 bool dal_cmd_table_helper_controller_id_to_atom2( 85 enum controller_id id, 86 uint8_t *atom_id) 87 { 88 if (atom_id == NULL) { 89 BREAK_TO_DEBUGGER(); 90 return false; 91 } 92 93 switch (id) { 94 case CONTROLLER_ID_D0: 95 *atom_id = ATOM_CRTC1; 96 return true; 97 case CONTROLLER_ID_D1: 98 *atom_id = ATOM_CRTC2; 99 return true; 100 case CONTROLLER_ID_D2: 101 *atom_id = ATOM_CRTC3; 102 return true; 103 case CONTROLLER_ID_D3: 104 *atom_id = ATOM_CRTC4; 105 return true; 106 case CONTROLLER_ID_D4: 107 *atom_id = ATOM_CRTC5; 108 return true; 109 case CONTROLLER_ID_D5: 110 *atom_id = ATOM_CRTC6; 111 return true; 112 /* TODO :case CONTROLLER_ID_UNDERLAY0: 113 *atom_id = ATOM_UNDERLAY_PIPE0; 114 return true; 115 */ 116 case CONTROLLER_ID_UNDEFINED: 117 *atom_id = ATOM_CRTC_INVALID; 118 return true; 119 default: 120 /* Wrong controller id */ 121 BREAK_TO_DEBUGGER(); 122 return false; 123 } 124 } 125 126 /** 127 * translate_transmitter_bp_to_atom 128 * 129 * @brief 130 * Translate the Transmitter to the corresponding ATOM BIOS value 131 * 132 * @param 133 * input transmitter 134 * output digitalTransmitter 135 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 136 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 137 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 138 */ 139 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 140 enum transmitter t) 141 { 142 switch (t) { 143 case TRANSMITTER_UNIPHY_A: 144 case TRANSMITTER_UNIPHY_B: 145 case TRANSMITTER_TRAVIS_LCD: 146 return 0; 147 case TRANSMITTER_UNIPHY_C: 148 case TRANSMITTER_UNIPHY_D: 149 return 1; 150 case TRANSMITTER_UNIPHY_E: 151 case TRANSMITTER_UNIPHY_F: 152 return 2; 153 default: 154 /* Invalid Transmitter Type! */ 155 BREAK_TO_DEBUGGER(); 156 return 0; 157 } 158 } 159 160 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 161 enum signal_type s, 162 bool enable_dp_audio) 163 { 164 switch (s) { 165 case SIGNAL_TYPE_DVI_SINGLE_LINK: 166 case SIGNAL_TYPE_DVI_DUAL_LINK: 167 return ATOM_ENCODER_MODE_DVI; 168 case SIGNAL_TYPE_HDMI_TYPE_A: 169 return ATOM_ENCODER_MODE_HDMI; 170 case SIGNAL_TYPE_LVDS: 171 return ATOM_ENCODER_MODE_LVDS; 172 case SIGNAL_TYPE_EDP: 173 case SIGNAL_TYPE_DISPLAY_PORT_MST: 174 case SIGNAL_TYPE_DISPLAY_PORT: 175 case SIGNAL_TYPE_VIRTUAL: 176 if (enable_dp_audio) 177 return ATOM_ENCODER_MODE_DP_AUDIO; 178 else 179 return ATOM_ENCODER_MODE_DP; 180 case SIGNAL_TYPE_RGB: 181 return ATOM_ENCODER_MODE_CRT; 182 default: 183 return ATOM_ENCODER_MODE_CRT; 184 } 185 } 186 187 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 188 enum clock_source_id id, 189 uint32_t *ref_clk_src_id) 190 { 191 if (ref_clk_src_id == NULL) { 192 BREAK_TO_DEBUGGER(); 193 return false; 194 } 195 196 switch (id) { 197 case CLOCK_SOURCE_ID_PLL1: 198 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 199 return true; 200 case CLOCK_SOURCE_ID_PLL2: 201 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 202 return true; 203 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 204 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 205 return true; 206 */ 207 case CLOCK_SOURCE_ID_EXTERNAL: 208 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 209 return true; 210 case CLOCK_SOURCE_ID_UNDEFINED: 211 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 212 return true; 213 default: 214 /* Unsupported clock source id */ 215 BREAK_TO_DEBUGGER(); 216 return false; 217 } 218 } 219 220 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 221 enum encoder_id id) 222 { 223 switch (id) { 224 case ENCODER_ID_INTERNAL_LVDS: 225 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 226 case ENCODER_ID_INTERNAL_TMDS1: 227 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 228 case ENCODER_ID_INTERNAL_TMDS2: 229 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 230 case ENCODER_ID_INTERNAL_DAC1: 231 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 232 case ENCODER_ID_INTERNAL_DAC2: 233 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 234 case ENCODER_ID_INTERNAL_LVTM1: 235 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 236 case ENCODER_ID_INTERNAL_HDMI: 237 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 238 case ENCODER_ID_EXTERNAL_TRAVIS: 239 return ENCODER_OBJECT_ID_TRAVIS; 240 case ENCODER_ID_EXTERNAL_NUTMEG: 241 return ENCODER_OBJECT_ID_NUTMEG; 242 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 243 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 244 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 245 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 246 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 247 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 248 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 249 return ENCODER_OBJECT_ID_MVPU_FPGA; 250 case ENCODER_ID_INTERNAL_DDI: 251 return ENCODER_OBJECT_ID_INTERNAL_DDI; 252 case ENCODER_ID_INTERNAL_UNIPHY: 253 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 254 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 255 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 256 case ENCODER_ID_INTERNAL_UNIPHY1: 257 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 258 case ENCODER_ID_INTERNAL_UNIPHY2: 259 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 260 case ENCODER_ID_INTERNAL_UNIPHY3: 261 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 262 case ENCODER_ID_INTERNAL_WIRELESS: 263 return ENCODER_OBJECT_ID_INTERNAL_VCE; 264 case ENCODER_ID_INTERNAL_VIRTUAL: 265 return ENCODER_OBJECT_ID_NONE; 266 case ENCODER_ID_UNKNOWN: 267 return ENCODER_OBJECT_ID_NONE; 268 default: 269 /* Invalid encoder id */ 270 BREAK_TO_DEBUGGER(); 271 return ENCODER_OBJECT_ID_NONE; 272 } 273 } 274