1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 case DCE_VERSION_11_22: 56 *h = dal_cmd_tbl_helper_dce112_get_table2(); 57 return true; 58 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 59 case DCN_VERSION_1_0: 60 *h = dal_cmd_tbl_helper_dce112_get_table2(); 61 return true; 62 #endif 63 64 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 65 case DCN_VERSION_1_01: 66 *h = dal_cmd_tbl_helper_dce112_get_table2(); 67 return true; 68 #endif 69 case DCE_VERSION_12_0: 70 *h = dal_cmd_tbl_helper_dce112_get_table2(); 71 return true; 72 73 default: 74 /* Unsupported DCE */ 75 BREAK_TO_DEBUGGER(); 76 return false; 77 } 78 } 79 80 /* real implementations */ 81 82 bool dal_cmd_table_helper_controller_id_to_atom2( 83 enum controller_id id, 84 uint8_t *atom_id) 85 { 86 if (atom_id == NULL) { 87 BREAK_TO_DEBUGGER(); 88 return false; 89 } 90 91 switch (id) { 92 case CONTROLLER_ID_D0: 93 *atom_id = ATOM_CRTC1; 94 return true; 95 case CONTROLLER_ID_D1: 96 *atom_id = ATOM_CRTC2; 97 return true; 98 case CONTROLLER_ID_D2: 99 *atom_id = ATOM_CRTC3; 100 return true; 101 case CONTROLLER_ID_D3: 102 *atom_id = ATOM_CRTC4; 103 return true; 104 case CONTROLLER_ID_D4: 105 *atom_id = ATOM_CRTC5; 106 return true; 107 case CONTROLLER_ID_D5: 108 *atom_id = ATOM_CRTC6; 109 return true; 110 /* TODO :case CONTROLLER_ID_UNDERLAY0: 111 *atom_id = ATOM_UNDERLAY_PIPE0; 112 return true; 113 */ 114 case CONTROLLER_ID_UNDEFINED: 115 *atom_id = ATOM_CRTC_INVALID; 116 return true; 117 default: 118 /* Wrong controller id */ 119 BREAK_TO_DEBUGGER(); 120 return false; 121 } 122 } 123 124 /** 125 * translate_transmitter_bp_to_atom 126 * 127 * @brief 128 * Translate the Transmitter to the corresponding ATOM BIOS value 129 * 130 * @param 131 * input transmitter 132 * output digitalTransmitter 133 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 134 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 135 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 136 */ 137 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 138 enum transmitter t) 139 { 140 switch (t) { 141 case TRANSMITTER_UNIPHY_A: 142 case TRANSMITTER_UNIPHY_B: 143 case TRANSMITTER_TRAVIS_LCD: 144 return 0; 145 case TRANSMITTER_UNIPHY_C: 146 case TRANSMITTER_UNIPHY_D: 147 return 1; 148 case TRANSMITTER_UNIPHY_E: 149 case TRANSMITTER_UNIPHY_F: 150 return 2; 151 default: 152 /* Invalid Transmitter Type! */ 153 BREAK_TO_DEBUGGER(); 154 return 0; 155 } 156 } 157 158 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 159 enum signal_type s, 160 bool enable_dp_audio) 161 { 162 switch (s) { 163 case SIGNAL_TYPE_DVI_SINGLE_LINK: 164 case SIGNAL_TYPE_DVI_DUAL_LINK: 165 return ATOM_ENCODER_MODE_DVI; 166 case SIGNAL_TYPE_HDMI_TYPE_A: 167 return ATOM_ENCODER_MODE_HDMI; 168 case SIGNAL_TYPE_LVDS: 169 return ATOM_ENCODER_MODE_LVDS; 170 case SIGNAL_TYPE_EDP: 171 case SIGNAL_TYPE_DISPLAY_PORT_MST: 172 case SIGNAL_TYPE_DISPLAY_PORT: 173 case SIGNAL_TYPE_VIRTUAL: 174 if (enable_dp_audio) 175 return ATOM_ENCODER_MODE_DP_AUDIO; 176 else 177 return ATOM_ENCODER_MODE_DP; 178 case SIGNAL_TYPE_RGB: 179 return ATOM_ENCODER_MODE_CRT; 180 default: 181 return ATOM_ENCODER_MODE_CRT; 182 } 183 } 184 185 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 186 enum clock_source_id id, 187 uint32_t *ref_clk_src_id) 188 { 189 if (ref_clk_src_id == NULL) { 190 BREAK_TO_DEBUGGER(); 191 return false; 192 } 193 194 switch (id) { 195 case CLOCK_SOURCE_ID_PLL1: 196 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 197 return true; 198 case CLOCK_SOURCE_ID_PLL2: 199 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 200 return true; 201 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 202 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 203 return true; 204 */ 205 case CLOCK_SOURCE_ID_EXTERNAL: 206 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 207 return true; 208 case CLOCK_SOURCE_ID_UNDEFINED: 209 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 210 return true; 211 default: 212 /* Unsupported clock source id */ 213 BREAK_TO_DEBUGGER(); 214 return false; 215 } 216 } 217 218 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 219 enum encoder_id id) 220 { 221 switch (id) { 222 case ENCODER_ID_INTERNAL_LVDS: 223 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 224 case ENCODER_ID_INTERNAL_TMDS1: 225 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 226 case ENCODER_ID_INTERNAL_TMDS2: 227 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 228 case ENCODER_ID_INTERNAL_DAC1: 229 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 230 case ENCODER_ID_INTERNAL_DAC2: 231 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 232 case ENCODER_ID_INTERNAL_LVTM1: 233 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 234 case ENCODER_ID_INTERNAL_HDMI: 235 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 236 case ENCODER_ID_EXTERNAL_TRAVIS: 237 return ENCODER_OBJECT_ID_TRAVIS; 238 case ENCODER_ID_EXTERNAL_NUTMEG: 239 return ENCODER_OBJECT_ID_NUTMEG; 240 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 241 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 242 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 243 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 244 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 245 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 246 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 247 return ENCODER_OBJECT_ID_MVPU_FPGA; 248 case ENCODER_ID_INTERNAL_DDI: 249 return ENCODER_OBJECT_ID_INTERNAL_DDI; 250 case ENCODER_ID_INTERNAL_UNIPHY: 251 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 252 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 253 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 254 case ENCODER_ID_INTERNAL_UNIPHY1: 255 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 256 case ENCODER_ID_INTERNAL_UNIPHY2: 257 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 258 case ENCODER_ID_INTERNAL_UNIPHY3: 259 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 260 case ENCODER_ID_INTERNAL_WIRELESS: 261 return ENCODER_OBJECT_ID_INTERNAL_VCE; 262 case ENCODER_ID_INTERNAL_VIRTUAL: 263 return ENCODER_OBJECT_ID_NONE; 264 case ENCODER_ID_UNKNOWN: 265 return ENCODER_OBJECT_ID_NONE; 266 default: 267 /* Invalid encoder id */ 268 BREAK_TO_DEBUGGER(); 269 return ENCODER_OBJECT_ID_NONE; 270 } 271 } 272