1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #undef TRACE_SYSTEM 27 #define TRACE_SYSTEM amdgpu_dm 28 29 #if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) 30 #define _AMDGPU_DM_TRACE_H_ 31 32 #include <linux/tracepoint.h> 33 #include <drm/drm_connector.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_plane.h> 36 #include <drm/drm_fourcc.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_atomic.h> 39 40 DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, 41 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), 42 TP_ARGS(count, reg, value), 43 44 TP_STRUCT__entry( 45 __field(uint32_t, reg) 46 __field(uint32_t, value) 47 ), 48 49 TP_fast_assign( 50 __entry->reg = reg; 51 __entry->value = value; 52 *count = *count + 1; 53 ), 54 55 TP_printk("reg=0x%08lx, value=0x%08lx", 56 (unsigned long)__entry->reg, 57 (unsigned long)__entry->value) 58 ); 59 60 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg, 61 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), 62 TP_ARGS(count, reg, value)); 63 64 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg, 65 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), 66 TP_ARGS(count, reg, value)); 67 68 TRACE_EVENT(amdgpu_dc_performance, 69 TP_PROTO(unsigned long read_count, unsigned long write_count, 70 unsigned long *last_read, unsigned long *last_write, 71 const char *func, unsigned int line), 72 TP_ARGS(read_count, write_count, last_read, last_write, func, line), 73 TP_STRUCT__entry( 74 __field(uint32_t, reads) 75 __field(uint32_t, writes) 76 __field(uint32_t, read_delta) 77 __field(uint32_t, write_delta) 78 __string(func, func) 79 __field(uint32_t, line) 80 ), 81 TP_fast_assign( 82 __entry->reads = read_count; 83 __entry->writes = write_count; 84 __entry->read_delta = read_count - *last_read; 85 __entry->write_delta = write_count - *last_write; 86 __assign_str(func, func); 87 __entry->line = line; 88 *last_read = read_count; 89 *last_write = write_count; 90 ), 91 TP_printk("%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)", 92 __get_str(func), __entry->line, 93 (unsigned long)__entry->read_delta, 94 (unsigned long)__entry->reads, 95 (unsigned long)__entry->write_delta, 96 (unsigned long)__entry->writes) 97 ); 98 99 TRACE_EVENT(amdgpu_dm_connector_atomic_check, 100 TP_PROTO(const struct drm_connector_state *state), 101 TP_ARGS(state), 102 103 TP_STRUCT__entry( 104 __field(uint32_t, conn_id) 105 __field(const struct drm_connector_state *, conn_state) 106 __field(const struct drm_atomic_state *, state) 107 __field(const struct drm_crtc_commit *, commit) 108 __field(uint32_t, crtc_id) 109 __field(uint32_t, best_encoder_id) 110 __field(enum drm_link_status, link_status) 111 __field(bool, self_refresh_aware) 112 __field(enum hdmi_picture_aspect, picture_aspect_ratio) 113 __field(unsigned int, content_type) 114 __field(unsigned int, hdcp_content_type) 115 __field(unsigned int, content_protection) 116 __field(unsigned int, scaling_mode) 117 __field(u32, colorspace) 118 __field(u8, max_requested_bpc) 119 __field(u8, max_bpc) 120 ), 121 122 TP_fast_assign( 123 __entry->conn_id = state->connector->base.id; 124 __entry->conn_state = state; 125 __entry->state = state->state; 126 __entry->commit = state->commit; 127 __entry->crtc_id = state->crtc ? state->crtc->base.id : 0; 128 __entry->best_encoder_id = state->best_encoder ? 129 state->best_encoder->base.id : 0; 130 __entry->link_status = state->link_status; 131 __entry->self_refresh_aware = state->self_refresh_aware; 132 __entry->picture_aspect_ratio = state->picture_aspect_ratio; 133 __entry->content_type = state->content_type; 134 __entry->hdcp_content_type = state->hdcp_content_type; 135 __entry->content_protection = state->content_protection; 136 __entry->scaling_mode = state->scaling_mode; 137 __entry->colorspace = state->colorspace; 138 __entry->max_requested_bpc = state->max_requested_bpc; 139 __entry->max_bpc = state->max_bpc; 140 ), 141 142 TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " 143 "best_encoder_id=%u link_status=%d self_refresh_aware=%d " 144 "picture_aspect_ratio=%d content_type=%u " 145 "hdcp_content_type=%u content_protection=%u scaling_mode=%u " 146 "colorspace=%u max_requested_bpc=%u max_bpc=%u", 147 __entry->conn_id, __entry->conn_state, __entry->state, 148 __entry->commit, __entry->crtc_id, __entry->best_encoder_id, 149 __entry->link_status, __entry->self_refresh_aware, 150 __entry->picture_aspect_ratio, __entry->content_type, 151 __entry->hdcp_content_type, __entry->content_protection, 152 __entry->scaling_mode, __entry->colorspace, 153 __entry->max_requested_bpc, __entry->max_bpc) 154 ); 155 156 TRACE_EVENT(amdgpu_dm_crtc_atomic_check, 157 TP_PROTO(const struct drm_crtc_state *state), 158 TP_ARGS(state), 159 160 TP_STRUCT__entry( 161 __field(const struct drm_atomic_state *, state) 162 __field(const struct drm_crtc_state *, crtc_state) 163 __field(const struct drm_crtc_commit *, commit) 164 __field(uint32_t, crtc_id) 165 __field(bool, enable) 166 __field(bool, active) 167 __field(bool, planes_changed) 168 __field(bool, mode_changed) 169 __field(bool, active_changed) 170 __field(bool, connectors_changed) 171 __field(bool, zpos_changed) 172 __field(bool, color_mgmt_changed) 173 __field(bool, no_vblank) 174 __field(bool, async_flip) 175 __field(bool, vrr_enabled) 176 __field(bool, self_refresh_active) 177 __field(u32, plane_mask) 178 __field(u32, connector_mask) 179 __field(u32, encoder_mask) 180 ), 181 182 TP_fast_assign( 183 __entry->state = state->state; 184 __entry->crtc_state = state; 185 __entry->crtc_id = state->crtc->base.id; 186 __entry->commit = state->commit; 187 __entry->enable = state->enable; 188 __entry->active = state->active; 189 __entry->planes_changed = state->planes_changed; 190 __entry->mode_changed = state->mode_changed; 191 __entry->active_changed = state->active_changed; 192 __entry->connectors_changed = state->connectors_changed; 193 __entry->zpos_changed = state->zpos_changed; 194 __entry->color_mgmt_changed = state->color_mgmt_changed; 195 __entry->no_vblank = state->no_vblank; 196 __entry->async_flip = state->async_flip; 197 __entry->vrr_enabled = state->vrr_enabled; 198 __entry->self_refresh_active = state->self_refresh_active; 199 __entry->plane_mask = state->plane_mask; 200 __entry->connector_mask = state->connector_mask; 201 __entry->encoder_mask = state->encoder_mask; 202 ), 203 204 TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" 205 "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " 206 "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " 207 "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " 208 "enc=%x)", 209 __entry->crtc_id, __entry->crtc_state, __entry->state, 210 __entry->commit, __entry->planes_changed, 211 __entry->mode_changed, __entry->active_changed, 212 __entry->connectors_changed, __entry->zpos_changed, 213 __entry->color_mgmt_changed, __entry->enable, __entry->active, 214 __entry->async_flip, __entry->vrr_enabled, 215 __entry->self_refresh_active, __entry->no_vblank, 216 __entry->plane_mask, __entry->connector_mask, 217 __entry->encoder_mask) 218 ); 219 220 DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template, 221 TP_PROTO(const struct drm_plane_state *state), 222 TP_ARGS(state), 223 TP_STRUCT__entry( 224 __field(uint32_t, plane_id) 225 __field(enum drm_plane_type, plane_type) 226 __field(const struct drm_plane_state *, plane_state) 227 __field(const struct drm_atomic_state *, state) 228 __field(uint32_t, crtc_id) 229 __field(uint32_t, fb_id) 230 __field(uint32_t, fb_format) 231 __field(uint8_t, fb_planes) 232 __field(uint64_t, fb_modifier) 233 __field(const struct dma_fence *, fence) 234 __field(int32_t, crtc_x) 235 __field(int32_t, crtc_y) 236 __field(uint32_t, crtc_w) 237 __field(uint32_t, crtc_h) 238 __field(uint32_t, src_x) 239 __field(uint32_t, src_y) 240 __field(uint32_t, src_w) 241 __field(uint32_t, src_h) 242 __field(u32, alpha) 243 __field(uint32_t, pixel_blend_mode) 244 __field(unsigned int, rotation) 245 __field(unsigned int, zpos) 246 __field(unsigned int, normalized_zpos) 247 __field(enum drm_color_encoding, color_encoding) 248 __field(enum drm_color_range, color_range) 249 __field(bool, visible) 250 ), 251 252 TP_fast_assign( 253 __entry->plane_id = state->plane->base.id; 254 __entry->plane_type = state->plane->type; 255 __entry->plane_state = state; 256 __entry->state = state->state; 257 __entry->crtc_id = state->crtc ? state->crtc->base.id : 0; 258 __entry->fb_id = state->fb ? state->fb->base.id : 0; 259 __entry->fb_format = state->fb ? state->fb->format->format : 0; 260 __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0; 261 __entry->fb_modifier = state->fb ? state->fb->modifier : 0; 262 __entry->fence = state->fence; 263 __entry->crtc_x = state->crtc_x; 264 __entry->crtc_y = state->crtc_y; 265 __entry->crtc_w = state->crtc_w; 266 __entry->crtc_h = state->crtc_h; 267 __entry->src_x = state->src_x >> 16; 268 __entry->src_y = state->src_y >> 16; 269 __entry->src_w = state->src_w >> 16; 270 __entry->src_h = state->src_h >> 16; 271 __entry->alpha = state->alpha; 272 __entry->pixel_blend_mode = state->pixel_blend_mode; 273 __entry->rotation = state->rotation; 274 __entry->zpos = state->zpos; 275 __entry->normalized_zpos = state->normalized_zpos; 276 __entry->color_encoding = state->color_encoding; 277 __entry->color_range = state->color_range; 278 __entry->visible = state->visible; 279 ), 280 281 TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p " 282 "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) " 283 "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u " 284 "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u " 285 "pixel_blend_mode=%u rotation=%u zpos=%u " 286 "normalized_zpos=%u color_encoding=%d color_range=%d " 287 "visible=%d", 288 __entry->plane_id, __entry->plane_type, __entry->plane_state, 289 __entry->state, __entry->crtc_id, __entry->fb_id, 290 (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N', 291 ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O', 292 ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N', 293 ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E', 294 __entry->fb_planes, 295 __entry->fb_modifier, __entry->fence, __entry->crtc_x, 296 __entry->crtc_y, __entry->crtc_w, __entry->crtc_h, 297 __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h, 298 __entry->alpha, __entry->pixel_blend_mode, __entry->rotation, 299 __entry->zpos, __entry->normalized_zpos, 300 __entry->color_encoding, __entry->color_range, 301 __entry->visible) 302 ); 303 304 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check, 305 TP_PROTO(const struct drm_plane_state *state), 306 TP_ARGS(state)); 307 308 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor, 309 TP_PROTO(const struct drm_plane_state *state), 310 TP_ARGS(state)); 311 312 TRACE_EVENT(amdgpu_dm_atomic_state_template, 313 TP_PROTO(const struct drm_atomic_state *state), 314 TP_ARGS(state), 315 316 TP_STRUCT__entry( 317 __field(const struct drm_atomic_state *, state) 318 __field(bool, allow_modeset) 319 __field(bool, legacy_cursor_update) 320 __field(bool, async_update) 321 __field(bool, duplicated) 322 __field(int, num_connector) 323 __field(int, num_private_objs) 324 ), 325 326 TP_fast_assign( 327 __entry->state = state; 328 __entry->allow_modeset = state->allow_modeset; 329 __entry->legacy_cursor_update = state->legacy_cursor_update; 330 __entry->async_update = state->async_update; 331 __entry->duplicated = state->duplicated; 332 __entry->num_connector = state->num_connector; 333 __entry->num_private_objs = state->num_private_objs; 334 ), 335 336 TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " 337 "async_update=%d duplicated=%d num_connector=%d " 338 "num_private_objs=%d", 339 __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, 340 __entry->async_update, __entry->duplicated, __entry->num_connector, 341 __entry->num_private_objs) 342 ); 343 344 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin, 345 TP_PROTO(const struct drm_atomic_state *state), 346 TP_ARGS(state)); 347 348 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish, 349 TP_PROTO(const struct drm_atomic_state *state), 350 TP_ARGS(state)); 351 352 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin, 353 TP_PROTO(const struct drm_atomic_state *state), 354 TP_ARGS(state)); 355 356 TRACE_EVENT(amdgpu_dm_atomic_check_finish, 357 TP_PROTO(const struct drm_atomic_state *state, int res), 358 TP_ARGS(state, res), 359 360 TP_STRUCT__entry( 361 __field(const struct drm_atomic_state *, state) 362 __field(int, res) 363 __field(bool, async_update) 364 __field(bool, allow_modeset) 365 ), 366 367 TP_fast_assign( 368 __entry->state = state; 369 __entry->res = res; 370 __entry->async_update = state->async_update; 371 __entry->allow_modeset = state->allow_modeset; 372 ), 373 374 TP_printk("state=%p res=%d async_update=%d allow_modeset=%d", 375 __entry->state, __entry->res, 376 __entry->async_update, __entry->allow_modeset) 377 ); 378 379 #endif /* _AMDGPU_DM_TRACE_H_ */ 380 381 #undef TRACE_INCLUDE_PATH 382 #define TRACE_INCLUDE_PATH . 383 #define TRACE_INCLUDE_FILE amdgpu_dm_trace 384 #include <trace/define_trace.h> 385