15d945cbcSRodrigo Siqueira // SPDX-License-Identifier: MIT 25d945cbcSRodrigo Siqueira /* 35d945cbcSRodrigo Siqueira * Copyright 2022 Advanced Micro Devices, Inc. 45d945cbcSRodrigo Siqueira * 55d945cbcSRodrigo Siqueira * Permission is hereby granted, free of charge, to any person obtaining a 65d945cbcSRodrigo Siqueira * copy of this software and associated documentation files (the "Software"), 75d945cbcSRodrigo Siqueira * to deal in the Software without restriction, including without limitation 85d945cbcSRodrigo Siqueira * the rights to use, copy, modify, merge, publish, distribute, sublicense, 95d945cbcSRodrigo Siqueira * and/or sell copies of the Software, and to permit persons to whom the 105d945cbcSRodrigo Siqueira * Software is furnished to do so, subject to the following conditions: 115d945cbcSRodrigo Siqueira * 125d945cbcSRodrigo Siqueira * The above copyright notice and this permission notice shall be included in 135d945cbcSRodrigo Siqueira * all copies or substantial portions of the Software. 145d945cbcSRodrigo Siqueira * 155d945cbcSRodrigo Siqueira * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 165d945cbcSRodrigo Siqueira * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 175d945cbcSRodrigo Siqueira * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 185d945cbcSRodrigo Siqueira * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 195d945cbcSRodrigo Siqueira * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 205d945cbcSRodrigo Siqueira * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 215d945cbcSRodrigo Siqueira * OTHER DEALINGS IN THE SOFTWARE. 225d945cbcSRodrigo Siqueira * 235d945cbcSRodrigo Siqueira * Authors: AMD 245d945cbcSRodrigo Siqueira * 255d945cbcSRodrigo Siqueira */ 265d945cbcSRodrigo Siqueira 275d945cbcSRodrigo Siqueira #ifndef __AMDGPU_DM_PLANE_H__ 285d945cbcSRodrigo Siqueira #define __AMDGPU_DM_PLANE_H__ 295d945cbcSRodrigo Siqueira 305d945cbcSRodrigo Siqueira #include "dc.h" 315d945cbcSRodrigo Siqueira 3266eba12aSHarry Wentland int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 3366eba12aSHarry Wentland struct dc_cursor_position *position); 3466eba12aSHarry Wentland 358bf0d9cdSDavid Tadokoro void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 365d945cbcSRodrigo Siqueira struct drm_plane_state *old_plane_state); 375d945cbcSRodrigo Siqueira 388bf0d9cdSDavid Tadokoro int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 395d945cbcSRodrigo Siqueira const struct drm_plane_state *state, 405d945cbcSRodrigo Siqueira struct dc_scaling_info *scaling_info); 415d945cbcSRodrigo Siqueira 428bf0d9cdSDavid Tadokoro int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 435d945cbcSRodrigo Siqueira struct drm_crtc_state *new_crtc_state); 445d945cbcSRodrigo Siqueira 458bf0d9cdSDavid Tadokoro int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 465d945cbcSRodrigo Siqueira const struct amdgpu_framebuffer *afb, 475d945cbcSRodrigo Siqueira const enum surface_pixel_format format, 485d945cbcSRodrigo Siqueira const enum dc_rotation_angle rotation, 495d945cbcSRodrigo Siqueira const uint64_t tiling_flags, 50*080950cbSKarthi Kandasamy struct dc_tiling_info *tiling_info, 515d945cbcSRodrigo Siqueira struct plane_size *plane_size, 525d945cbcSRodrigo Siqueira struct dc_plane_dcc_param *dcc, 535d945cbcSRodrigo Siqueira struct dc_plane_address *address, 5404d6273fSRodrigo Siqueira bool tmz_surface); 555d945cbcSRodrigo Siqueira 565d945cbcSRodrigo Siqueira int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 575d945cbcSRodrigo Siqueira struct drm_plane *plane, 585d945cbcSRodrigo Siqueira unsigned long possible_crtcs, 595d945cbcSRodrigo Siqueira const struct dc_plane_cap *plane_cap); 605d945cbcSRodrigo Siqueira 618bf0d9cdSDavid Tadokoro const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); 625d945cbcSRodrigo Siqueira 638bf0d9cdSDavid Tadokoro void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 645d945cbcSRodrigo Siqueira bool *per_pixel_alpha, bool *pre_multiplied_alpha, 655d945cbcSRodrigo Siqueira bool *global_alpha, int *global_alpha_value); 665d945cbcSRodrigo Siqueira 67c4066d8bSRodrigo Siqueira bool amdgpu_dm_plane_is_video_format(uint32_t format); 685d945cbcSRodrigo Siqueira #endif 69