1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_blend.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_fourcc.h> 32 33 #include "amdgpu.h" 34 #include "dal_asic_id.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_dm_trace.h" 37 #include "amdgpu_dm_plane.h" 38 #include "gc/gc_11_0_0_offset.h" 39 #include "gc/gc_11_0_0_sh_mask.h" 40 41 /* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47 static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62 }; 63 64 static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74 }; 75 76 static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80 }; 81 82 static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84 }; 85 86 enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91 }; 92 93 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94 { 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96 } 97 98 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101 { 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 108 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 109 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 110 static const uint32_t alpha_formats[] = { 111 DRM_FORMAT_ARGB8888, 112 DRM_FORMAT_RGBA8888, 113 DRM_FORMAT_ABGR8888, 114 DRM_FORMAT_ARGB2101010, 115 DRM_FORMAT_ABGR2101010, 116 DRM_FORMAT_ARGB16161616, 117 DRM_FORMAT_ABGR16161616, 118 DRM_FORMAT_ARGB16161616F, 119 }; 120 uint32_t format = plane_state->fb->format->format; 121 unsigned int i; 122 123 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 124 if (format == alpha_formats[i]) { 125 *per_pixel_alpha = true; 126 break; 127 } 128 } 129 130 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 131 *pre_multiplied_alpha = false; 132 } 133 134 if (plane_state->alpha < 0xffff) { 135 *global_alpha = true; 136 *global_alpha_value = plane_state->alpha >> 8; 137 } 138 } 139 140 static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 141 { 142 if (!*mods) 143 return; 144 145 if (*cap - *size < 1) { 146 uint64_t new_cap = *cap * 2; 147 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 148 149 if (!new_mods) { 150 kfree(*mods); 151 *mods = NULL; 152 return; 153 } 154 155 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 156 kfree(*mods); 157 *mods = new_mods; 158 *cap = new_cap; 159 } 160 161 (*mods)[*size] = mod; 162 *size += 1; 163 } 164 165 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) 166 { 167 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 168 } 169 170 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) 171 { 172 if (modifier == DRM_FORMAT_MOD_LINEAR) 173 return 0; 174 175 return AMD_FMT_MOD_GET(TILE, modifier); 176 } 177 178 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 179 uint64_t tiling_flags) 180 { 181 /* Fill GFX8 params */ 182 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 183 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 184 185 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 186 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 187 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 188 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 189 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 190 191 /* XXX fix me for VI */ 192 tiling_info->gfx8.num_banks = num_banks; 193 tiling_info->gfx8.array_mode = 194 DC_ARRAY_2D_TILED_THIN1; 195 tiling_info->gfx8.tile_split = tile_split; 196 tiling_info->gfx8.bank_width = bankw; 197 tiling_info->gfx8.bank_height = bankh; 198 tiling_info->gfx8.tile_aspect = mtaspect; 199 tiling_info->gfx8.tile_mode = 200 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 201 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 202 == DC_ARRAY_1D_TILED_THIN1) { 203 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 204 } 205 206 tiling_info->gfx8.pipe_config = 207 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 208 } 209 210 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 211 union dc_tiling_info *tiling_info) 212 { 213 /* Fill GFX9 params */ 214 tiling_info->gfx9.num_pipes = 215 adev->gfx.config.gb_addr_config_fields.num_pipes; 216 tiling_info->gfx9.num_banks = 217 adev->gfx.config.gb_addr_config_fields.num_banks; 218 tiling_info->gfx9.pipe_interleave = 219 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 220 tiling_info->gfx9.num_shader_engines = 221 adev->gfx.config.gb_addr_config_fields.num_se; 222 tiling_info->gfx9.max_compressed_frags = 223 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 224 tiling_info->gfx9.num_rb_per_se = 225 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 226 tiling_info->gfx9.shaderEnable = 1; 227 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 228 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 229 } 230 231 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 232 union dc_tiling_info *tiling_info, 233 uint64_t modifier) 234 { 235 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 236 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 237 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 238 unsigned int pipes_log2; 239 240 pipes_log2 = min(5u, mod_pipe_xor_bits); 241 242 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 243 244 if (!IS_AMD_FMT_MOD(modifier)) 245 return; 246 247 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 248 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 249 250 if (adev->family >= AMDGPU_FAMILY_NV) { 251 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 252 } else { 253 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 254 255 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 256 } 257 } 258 259 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, 260 const enum surface_pixel_format format, 261 const enum dc_rotation_angle rotation, 262 const union dc_tiling_info *tiling_info, 263 const struct dc_plane_dcc_param *dcc, 264 const struct dc_plane_address *address, 265 const struct plane_size *plane_size) 266 { 267 struct dc *dc = adev->dm.dc; 268 struct dc_dcc_surface_param input; 269 struct dc_surface_dcc_cap output; 270 271 memset(&input, 0, sizeof(input)); 272 memset(&output, 0, sizeof(output)); 273 274 if (!dcc->enable) 275 return 0; 276 277 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 278 !dc->cap_funcs.get_dcc_compression_cap) 279 return -EINVAL; 280 281 input.format = format; 282 input.surface_size.width = plane_size->surface_size.width; 283 input.surface_size.height = plane_size->surface_size.height; 284 input.swizzle_mode = tiling_info->gfx9.swizzle; 285 286 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 287 input.scan = SCAN_DIRECTION_HORIZONTAL; 288 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 289 input.scan = SCAN_DIRECTION_VERTICAL; 290 291 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 292 return -EINVAL; 293 294 if (!output.capable) 295 return -EINVAL; 296 297 if (dcc->independent_64b_blks == 0 && 298 output.grph.rgb.independent_64b_blks != 0) 299 return -EINVAL; 300 301 return 0; 302 } 303 304 static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 305 const struct amdgpu_framebuffer *afb, 306 const enum surface_pixel_format format, 307 const enum dc_rotation_angle rotation, 308 const struct plane_size *plane_size, 309 union dc_tiling_info *tiling_info, 310 struct dc_plane_dcc_param *dcc, 311 struct dc_plane_address *address, 312 const bool force_disable_dcc) 313 { 314 const uint64_t modifier = afb->base.modifier; 315 int ret = 0; 316 317 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 318 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 319 320 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 321 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 322 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 323 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 324 325 dcc->enable = 1; 326 dcc->meta_pitch = afb->base.pitches[1]; 327 dcc->independent_64b_blks = independent_64b_blks; 328 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 329 if (independent_64b_blks && independent_128b_blks) 330 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 331 else if (independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_128b; 333 else if (independent_64b_blks && !independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_64b; 335 else 336 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 337 } else { 338 if (independent_64b_blks) 339 dcc->dcc_ind_blk = hubp_ind_block_64b; 340 else 341 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 342 } 343 344 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 345 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 346 } 347 348 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 349 if (ret) 350 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 351 352 return ret; 353 } 354 355 static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev, 356 uint64_t **mods, 357 uint64_t *size, 358 uint64_t *capacity) 359 { 360 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 361 362 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 363 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 364 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 365 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 366 AMD_FMT_MOD_SET(DCC, 1) | 367 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 368 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 369 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 370 371 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 372 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 373 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 374 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 375 AMD_FMT_MOD_SET(DCC, 1) | 376 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 377 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 378 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 379 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 380 381 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 382 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 383 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 384 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 385 386 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 387 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 388 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 389 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 390 391 392 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 393 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 394 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 395 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 396 397 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 398 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 399 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 400 } 401 402 static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev, 403 uint64_t **mods, 404 uint64_t *size, 405 uint64_t *capacity) 406 { 407 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 408 int pipe_xor_bits = min(8, pipes + 409 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 410 int bank_xor_bits = min(8 - pipe_xor_bits, 411 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 412 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 413 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 414 415 416 if (adev->family == AMDGPU_FAMILY_RV) { 417 /* Raven2 and later */ 418 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 419 420 /* 421 * No _D DCC swizzles yet because we only allow 32bpp, which 422 * doesn't support _D on DCN 423 */ 424 425 if (has_constant_encode) { 426 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 427 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 428 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 429 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 430 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 431 AMD_FMT_MOD_SET(DCC, 1) | 432 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 433 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 434 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 435 } 436 437 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 438 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 439 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 440 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 441 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 442 AMD_FMT_MOD_SET(DCC, 1) | 443 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 444 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 445 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 446 447 if (has_constant_encode) { 448 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 449 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 450 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 451 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 452 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 453 AMD_FMT_MOD_SET(DCC, 1) | 454 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 455 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 456 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 457 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 458 AMD_FMT_MOD_SET(RB, rb) | 459 AMD_FMT_MOD_SET(PIPE, pipes)); 460 } 461 462 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 463 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 464 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 465 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 466 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 467 AMD_FMT_MOD_SET(DCC, 1) | 468 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 469 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 470 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 471 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 472 AMD_FMT_MOD_SET(RB, rb) | 473 AMD_FMT_MOD_SET(PIPE, pipes)); 474 } 475 476 /* 477 * Only supported for 64bpp on Raven, will be filtered on format in 478 * amdgpu_dm_plane_format_mod_supported. 479 */ 480 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 481 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 482 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 483 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 484 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 485 486 if (adev->family == AMDGPU_FAMILY_RV) { 487 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 488 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 489 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 490 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 491 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 492 } 493 494 /* 495 * Only supported for 64bpp on Raven, will be filtered on format in 496 * amdgpu_dm_plane_format_mod_supported. 497 */ 498 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 499 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 500 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 501 502 if (adev->family == AMDGPU_FAMILY_RV) { 503 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 504 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 505 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 506 } 507 } 508 509 static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev, 510 uint64_t **mods, 511 uint64_t *size, 512 uint64_t *capacity) 513 { 514 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 515 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 516 517 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 518 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 519 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 520 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 521 AMD_FMT_MOD_SET(PACKERS, pkrs) | 522 AMD_FMT_MOD_SET(DCC, 1) | 523 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 524 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 525 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 526 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 527 528 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 529 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 530 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 531 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 532 AMD_FMT_MOD_SET(PACKERS, pkrs) | 533 AMD_FMT_MOD_SET(DCC, 1) | 534 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 535 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 536 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 537 538 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 539 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 540 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 541 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 542 AMD_FMT_MOD_SET(PACKERS, pkrs) | 543 AMD_FMT_MOD_SET(DCC, 1) | 544 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 545 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 546 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 547 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 548 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 549 550 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 551 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 552 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 553 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 554 AMD_FMT_MOD_SET(PACKERS, pkrs) | 555 AMD_FMT_MOD_SET(DCC, 1) | 556 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 557 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 558 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 559 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 560 561 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 562 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 563 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 564 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 565 AMD_FMT_MOD_SET(PACKERS, pkrs)); 566 567 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 568 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 569 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 570 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 571 AMD_FMT_MOD_SET(PACKERS, pkrs)); 572 573 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 574 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 575 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 576 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 577 578 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 579 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 580 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 581 } 582 583 static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev, 584 uint64_t **mods, uint64_t *size, uint64_t *capacity) 585 { 586 int num_pipes = 0; 587 int pipe_xor_bits = 0; 588 int num_pkrs = 0; 589 int pkrs = 0; 590 u32 gb_addr_config; 591 u8 i = 0; 592 unsigned int swizzle_r_x; 593 uint64_t modifier_r_x; 594 uint64_t modifier_dcc_best; 595 uint64_t modifier_dcc_4k; 596 597 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 598 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 599 */ 600 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 601 ASSERT(gb_addr_config != 0); 602 603 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 604 pkrs = ilog2(num_pkrs); 605 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 606 pipe_xor_bits = ilog2(num_pipes); 607 608 for (i = 0; i < 2; i++) { 609 /* Insert the best one first. */ 610 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 611 if (num_pipes > 16) 612 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 613 else 614 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 615 616 modifier_r_x = AMD_FMT_MOD | 617 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 618 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 619 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 620 AMD_FMT_MOD_SET(PACKERS, pkrs); 621 622 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 623 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 624 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 625 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 626 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 627 628 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 629 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 630 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 631 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 632 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 633 634 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best); 635 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k); 636 637 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 638 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 639 640 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x); 641 } 642 643 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 644 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 645 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 646 } 647 648 static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, 649 uint64_t **mods, uint64_t *size, uint64_t *capacity) 650 { 651 uint64_t mod_64K_2D = AMD_FMT_MOD | 652 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | 653 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D); 654 655 /* 64K without DCC */ 656 amdgpu_dm_plane_add_modifier(mods, size, capacity, mod_64K_2D); 657 amdgpu_dm_plane_add_modifier(mods, size, capacity, DRM_FORMAT_MOD_LINEAR); 658 } 659 660 static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 661 { 662 uint64_t size = 0, capacity = 128; 663 *mods = NULL; 664 665 /* We have not hooked up any pre-GFX9 modifiers. */ 666 if (adev->family < AMDGPU_FAMILY_AI) 667 return 0; 668 669 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 670 671 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 672 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 673 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 674 return *mods ? 0 : -ENOMEM; 675 } 676 677 switch (adev->family) { 678 case AMDGPU_FAMILY_AI: 679 case AMDGPU_FAMILY_RV: 680 amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity); 681 break; 682 case AMDGPU_FAMILY_NV: 683 case AMDGPU_FAMILY_VGH: 684 case AMDGPU_FAMILY_YC: 685 case AMDGPU_FAMILY_GC_10_3_6: 686 case AMDGPU_FAMILY_GC_10_3_7: 687 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 688 amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity); 689 else 690 amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity); 691 break; 692 case AMDGPU_FAMILY_GC_11_0_0: 693 case AMDGPU_FAMILY_GC_11_0_1: 694 case AMDGPU_FAMILY_GC_11_5_0: 695 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); 696 break; 697 case AMDGPU_FAMILY_GC_12_0_0: 698 amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity); 699 break; 700 } 701 702 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 703 704 /* INVALID marks the end of the list. */ 705 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 706 707 if (!*mods) 708 return -ENOMEM; 709 710 return 0; 711 } 712 713 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, 714 const struct dc_plane_cap *plane_cap, 715 uint32_t *formats, int max_formats) 716 { 717 int i, num_formats = 0; 718 719 /* 720 * TODO: Query support for each group of formats directly from 721 * DC plane caps. This will require adding more formats to the 722 * caps list. 723 */ 724 725 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 726 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 727 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 728 if (num_formats >= max_formats) 729 break; 730 731 formats[num_formats++] = rgb_formats[i]; 732 } 733 734 if (plane_cap && plane_cap->pixel_format_support.nv12) 735 formats[num_formats++] = DRM_FORMAT_NV12; 736 if (plane_cap && plane_cap->pixel_format_support.p010) 737 formats[num_formats++] = DRM_FORMAT_P010; 738 if (plane_cap && plane_cap->pixel_format_support.fp16) { 739 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 740 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 741 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 742 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 743 } 744 } else { 745 switch (plane->type) { 746 case DRM_PLANE_TYPE_OVERLAY: 747 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 748 if (num_formats >= max_formats) 749 break; 750 751 formats[num_formats++] = overlay_formats[i]; 752 } 753 break; 754 755 case DRM_PLANE_TYPE_CURSOR: 756 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 757 if (num_formats >= max_formats) 758 break; 759 760 formats[num_formats++] = cursor_formats[i]; 761 } 762 break; 763 764 default: 765 break; 766 } 767 } 768 769 return num_formats; 770 } 771 772 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 773 const struct amdgpu_framebuffer *afb, 774 const enum surface_pixel_format format, 775 const enum dc_rotation_angle rotation, 776 const uint64_t tiling_flags, 777 union dc_tiling_info *tiling_info, 778 struct plane_size *plane_size, 779 struct dc_plane_dcc_param *dcc, 780 struct dc_plane_address *address, 781 bool tmz_surface, 782 bool force_disable_dcc) 783 { 784 const struct drm_framebuffer *fb = &afb->base; 785 int ret; 786 787 memset(tiling_info, 0, sizeof(*tiling_info)); 788 memset(plane_size, 0, sizeof(*plane_size)); 789 memset(dcc, 0, sizeof(*dcc)); 790 memset(address, 0, sizeof(*address)); 791 792 address->tmz_surface = tmz_surface; 793 794 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 795 uint64_t addr = afb->address + fb->offsets[0]; 796 797 plane_size->surface_size.x = 0; 798 plane_size->surface_size.y = 0; 799 plane_size->surface_size.width = fb->width; 800 plane_size->surface_size.height = fb->height; 801 plane_size->surface_pitch = 802 fb->pitches[0] / fb->format->cpp[0]; 803 804 address->type = PLN_ADDR_TYPE_GRAPHICS; 805 address->grph.addr.low_part = lower_32_bits(addr); 806 address->grph.addr.high_part = upper_32_bits(addr); 807 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 808 uint64_t luma_addr = afb->address + fb->offsets[0]; 809 uint64_t chroma_addr = afb->address + fb->offsets[1]; 810 811 plane_size->surface_size.x = 0; 812 plane_size->surface_size.y = 0; 813 plane_size->surface_size.width = fb->width; 814 plane_size->surface_size.height = fb->height; 815 plane_size->surface_pitch = 816 fb->pitches[0] / fb->format->cpp[0]; 817 818 plane_size->chroma_size.x = 0; 819 plane_size->chroma_size.y = 0; 820 /* TODO: set these based on surface format */ 821 plane_size->chroma_size.width = fb->width / 2; 822 plane_size->chroma_size.height = fb->height / 2; 823 824 plane_size->chroma_pitch = 825 fb->pitches[1] / fb->format->cpp[1]; 826 827 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 828 address->video_progressive.luma_addr.low_part = 829 lower_32_bits(luma_addr); 830 address->video_progressive.luma_addr.high_part = 831 upper_32_bits(luma_addr); 832 address->video_progressive.chroma_addr.low_part = 833 lower_32_bits(chroma_addr); 834 address->video_progressive.chroma_addr.high_part = 835 upper_32_bits(chroma_addr); 836 } 837 838 if (adev->family >= AMDGPU_FAMILY_AI) { 839 ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 840 rotation, plane_size, 841 tiling_info, dcc, 842 address, 843 force_disable_dcc); 844 if (ret) 845 return ret; 846 } else { 847 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 848 } 849 850 return 0; 851 } 852 853 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, 854 struct drm_plane_state *new_state) 855 { 856 struct amdgpu_framebuffer *afb; 857 struct drm_gem_object *obj; 858 struct amdgpu_device *adev; 859 struct amdgpu_bo *rbo; 860 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 861 uint32_t domain; 862 int r; 863 864 if (!new_state->fb) { 865 DRM_DEBUG_KMS("No FB bound\n"); 866 return 0; 867 } 868 869 afb = to_amdgpu_framebuffer(new_state->fb); 870 obj = new_state->fb->obj[0]; 871 rbo = gem_to_amdgpu_bo(obj); 872 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 873 874 r = amdgpu_bo_reserve(rbo, true); 875 if (r) { 876 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 877 return r; 878 } 879 880 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 881 if (r) { 882 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 883 goto error_unlock; 884 } 885 886 if (plane->type != DRM_PLANE_TYPE_CURSOR) 887 domain = amdgpu_display_supported_domains(adev, rbo->flags); 888 else 889 domain = AMDGPU_GEM_DOMAIN_VRAM; 890 891 r = amdgpu_bo_pin(rbo, domain); 892 if (unlikely(r != 0)) { 893 if (r != -ERESTARTSYS) 894 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 895 goto error_unlock; 896 } 897 898 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 899 if (unlikely(r != 0)) { 900 DRM_ERROR("%p bind failed\n", rbo); 901 goto error_unpin; 902 } 903 904 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 905 if (unlikely(r != 0)) 906 goto error_unpin; 907 908 amdgpu_bo_unreserve(rbo); 909 910 afb->address = amdgpu_bo_gpu_offset(rbo); 911 912 amdgpu_bo_ref(rbo); 913 914 /** 915 * We don't do surface updates on planes that have been newly created, 916 * but we also don't have the afb->address during atomic check. 917 * 918 * Fill in buffer attributes depending on the address here, but only on 919 * newly created planes since they're not being used by DC yet and this 920 * won't modify global state. 921 */ 922 dm_plane_state_old = to_dm_plane_state(plane->state); 923 dm_plane_state_new = to_dm_plane_state(new_state); 924 925 if (dm_plane_state_new->dc_state && 926 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 927 struct dc_plane_state *plane_state = 928 dm_plane_state_new->dc_state; 929 bool force_disable_dcc = !plane_state->dcc.enable; 930 931 amdgpu_dm_plane_fill_plane_buffer_attributes( 932 adev, afb, plane_state->format, plane_state->rotation, 933 afb->tiling_flags, 934 &plane_state->tiling_info, &plane_state->plane_size, 935 &plane_state->dcc, &plane_state->address, 936 afb->tmz_surface, force_disable_dcc); 937 } 938 939 return 0; 940 941 error_unpin: 942 amdgpu_bo_unpin(rbo); 943 944 error_unlock: 945 amdgpu_bo_unreserve(rbo); 946 return r; 947 } 948 949 static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, 950 struct drm_plane_state *old_state) 951 { 952 struct amdgpu_bo *rbo; 953 int r; 954 955 if (!old_state->fb) 956 return; 957 958 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 959 r = amdgpu_bo_reserve(rbo, false); 960 if (unlikely(r)) { 961 DRM_ERROR("failed to reserve rbo before unpin\n"); 962 return; 963 } 964 965 amdgpu_bo_unpin(rbo); 966 amdgpu_bo_unreserve(rbo); 967 amdgpu_bo_unref(&rbo); 968 } 969 970 static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, 971 struct drm_framebuffer *fb, 972 int *min_downscale, int *max_upscale) 973 { 974 struct amdgpu_device *adev = drm_to_adev(dev); 975 struct dc *dc = adev->dm.dc; 976 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 977 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 978 979 switch (fb->format->format) { 980 case DRM_FORMAT_P010: 981 case DRM_FORMAT_NV12: 982 case DRM_FORMAT_NV21: 983 *max_upscale = plane_cap->max_upscale_factor.nv12; 984 *min_downscale = plane_cap->max_downscale_factor.nv12; 985 break; 986 987 case DRM_FORMAT_XRGB16161616F: 988 case DRM_FORMAT_ARGB16161616F: 989 case DRM_FORMAT_XBGR16161616F: 990 case DRM_FORMAT_ABGR16161616F: 991 *max_upscale = plane_cap->max_upscale_factor.fp16; 992 *min_downscale = plane_cap->max_downscale_factor.fp16; 993 break; 994 995 default: 996 *max_upscale = plane_cap->max_upscale_factor.argb8888; 997 *min_downscale = plane_cap->max_downscale_factor.argb8888; 998 break; 999 } 1000 1001 /* 1002 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 1003 * scaling factor of 1.0 == 1000 units. 1004 */ 1005 if (*max_upscale == 1) 1006 *max_upscale = 1000; 1007 1008 if (*min_downscale == 1) 1009 *min_downscale = 1000; 1010 } 1011 1012 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 1013 struct drm_crtc_state *new_crtc_state) 1014 { 1015 struct drm_framebuffer *fb = state->fb; 1016 int min_downscale, max_upscale; 1017 int min_scale = 0; 1018 int max_scale = INT_MAX; 1019 1020 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1021 if (fb && state->crtc) { 1022 /* Validate viewport to cover the case when only the position changes */ 1023 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1024 int viewport_width = state->crtc_w; 1025 int viewport_height = state->crtc_h; 1026 1027 if (state->crtc_x < 0) 1028 viewport_width += state->crtc_x; 1029 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1030 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1031 1032 if (state->crtc_y < 0) 1033 viewport_height += state->crtc_y; 1034 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1035 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1036 1037 if (viewport_width < 0 || viewport_height < 0) { 1038 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1039 return -EINVAL; 1040 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1041 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1042 return -EINVAL; 1043 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1044 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1045 return -EINVAL; 1046 } 1047 1048 } 1049 1050 /* Get min/max allowed scaling factors from plane caps. */ 1051 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1052 &min_downscale, &max_upscale); 1053 /* 1054 * Convert to drm convention: 16.16 fixed point, instead of dc's 1055 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1056 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1057 */ 1058 min_scale = (1000 << 16) / max_upscale; 1059 max_scale = (1000 << 16) / min_downscale; 1060 } 1061 1062 return drm_atomic_helper_check_plane_state( 1063 state, new_crtc_state, min_scale, max_scale, true, true); 1064 } 1065 1066 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1067 const struct drm_plane_state *state, 1068 struct dc_scaling_info *scaling_info) 1069 { 1070 int scale_w, scale_h, min_downscale, max_upscale; 1071 1072 memset(scaling_info, 0, sizeof(*scaling_info)); 1073 1074 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1075 scaling_info->src_rect.x = state->src_x >> 16; 1076 scaling_info->src_rect.y = state->src_y >> 16; 1077 1078 /* 1079 * For reasons we don't (yet) fully understand a non-zero 1080 * src_y coordinate into an NV12 buffer can cause a 1081 * system hang on DCN1x. 1082 * To avoid hangs (and maybe be overly cautious) 1083 * let's reject both non-zero src_x and src_y. 1084 * 1085 * We currently know of only one use-case to reproduce a 1086 * scenario with non-zero src_x and src_y for NV12, which 1087 * is to gesture the YouTube Android app into full screen 1088 * on ChromeOS. 1089 */ 1090 if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1091 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && 1092 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1093 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1094 return -EINVAL; 1095 1096 scaling_info->src_rect.width = state->src_w >> 16; 1097 if (scaling_info->src_rect.width == 0) 1098 return -EINVAL; 1099 1100 scaling_info->src_rect.height = state->src_h >> 16; 1101 if (scaling_info->src_rect.height == 0) 1102 return -EINVAL; 1103 1104 scaling_info->dst_rect.x = state->crtc_x; 1105 scaling_info->dst_rect.y = state->crtc_y; 1106 1107 if (state->crtc_w == 0) 1108 return -EINVAL; 1109 1110 scaling_info->dst_rect.width = state->crtc_w; 1111 1112 if (state->crtc_h == 0) 1113 return -EINVAL; 1114 1115 scaling_info->dst_rect.height = state->crtc_h; 1116 1117 /* DRM doesn't specify clipping on destination output. */ 1118 scaling_info->clip_rect = scaling_info->dst_rect; 1119 1120 /* Validate scaling per-format with DC plane caps */ 1121 if (state->plane && state->plane->dev && state->fb) { 1122 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1123 &min_downscale, &max_upscale); 1124 } else { 1125 min_downscale = 250; 1126 max_upscale = 16000; 1127 } 1128 1129 scale_w = scaling_info->dst_rect.width * 1000 / 1130 scaling_info->src_rect.width; 1131 1132 if (scale_w < min_downscale || scale_w > max_upscale) 1133 return -EINVAL; 1134 1135 scale_h = scaling_info->dst_rect.height * 1000 / 1136 scaling_info->src_rect.height; 1137 1138 if (scale_h < min_downscale || scale_h > max_upscale) 1139 return -EINVAL; 1140 1141 /* 1142 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1143 * assume reasonable defaults based on the format. 1144 */ 1145 1146 return 0; 1147 } 1148 1149 static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, 1150 struct drm_atomic_state *state) 1151 { 1152 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1153 plane); 1154 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1155 struct dc *dc = adev->dm.dc; 1156 struct dm_plane_state *dm_plane_state; 1157 struct dc_scaling_info scaling_info; 1158 struct drm_crtc_state *new_crtc_state; 1159 int ret; 1160 1161 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1162 1163 dm_plane_state = to_dm_plane_state(new_plane_state); 1164 1165 if (!dm_plane_state->dc_state) 1166 return 0; 1167 1168 new_crtc_state = 1169 drm_atomic_get_new_crtc_state(state, 1170 new_plane_state->crtc); 1171 if (!new_crtc_state) 1172 return -EINVAL; 1173 1174 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1175 if (ret) 1176 return ret; 1177 1178 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1179 if (ret) 1180 return ret; 1181 1182 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1183 return 0; 1184 1185 return -EINVAL; 1186 } 1187 1188 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, 1189 struct drm_atomic_state *state) 1190 { 1191 struct drm_crtc_state *new_crtc_state; 1192 struct drm_plane_state *new_plane_state; 1193 struct dm_crtc_state *dm_new_crtc_state; 1194 1195 /* Only support async updates on cursor planes. */ 1196 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1197 return -EINVAL; 1198 1199 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 1200 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 1201 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1202 /* Reject overlay cursors for now*/ 1203 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 1204 return -EINVAL; 1205 1206 return 0; 1207 } 1208 1209 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1210 struct dc_cursor_position *position) 1211 { 1212 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1213 int x, y; 1214 int xorigin = 0, yorigin = 0; 1215 1216 if (!crtc || !plane->state->fb) 1217 return 0; 1218 1219 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1220 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1221 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1222 __func__, 1223 plane->state->crtc_w, 1224 plane->state->crtc_h); 1225 return -EINVAL; 1226 } 1227 1228 x = plane->state->crtc_x; 1229 y = plane->state->crtc_y; 1230 1231 if (x <= -amdgpu_crtc->max_cursor_width || 1232 y <= -amdgpu_crtc->max_cursor_height) 1233 return 0; 1234 1235 if (x < 0) { 1236 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1237 x = 0; 1238 } 1239 if (y < 0) { 1240 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1241 y = 0; 1242 } 1243 position->enable = true; 1244 position->translate_by_source = true; 1245 position->x = x; 1246 position->y = y; 1247 position->x_hotspot = xorigin; 1248 position->y_hotspot = yorigin; 1249 1250 return 0; 1251 } 1252 1253 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1254 struct drm_plane_state *old_plane_state) 1255 { 1256 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1257 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1258 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1259 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1260 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1261 uint64_t address = afb ? afb->address : 0; 1262 struct dc_cursor_position position = {0}; 1263 struct dc_cursor_attributes attributes; 1264 int ret; 1265 1266 if (!plane->state->fb && !old_plane_state->fb) 1267 return; 1268 1269 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 1270 amdgpu_crtc->crtc_id, plane->state->crtc_w, 1271 plane->state->crtc_h); 1272 1273 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 1274 if (ret) 1275 return; 1276 1277 if (!position.enable) { 1278 /* turn off cursor */ 1279 if (crtc_state && crtc_state->stream) { 1280 mutex_lock(&adev->dm.dc_lock); 1281 dc_stream_program_cursor_position(crtc_state->stream, 1282 &position); 1283 mutex_unlock(&adev->dm.dc_lock); 1284 } 1285 return; 1286 } 1287 1288 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1289 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1290 1291 memset(&attributes, 0, sizeof(attributes)); 1292 attributes.address.high_part = upper_32_bits(address); 1293 attributes.address.low_part = lower_32_bits(address); 1294 attributes.width = plane->state->crtc_w; 1295 attributes.height = plane->state->crtc_h; 1296 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1297 attributes.rotation_angle = 0; 1298 attributes.attribute_flags.value = 0; 1299 1300 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 1301 * legacy gamma setup. 1302 */ 1303 if (crtc_state->cm_is_degamma_srgb && 1304 adev->dm.dc->caps.color.dpp.gamma_corr) 1305 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 1306 1307 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1308 1309 if (crtc_state->stream) { 1310 mutex_lock(&adev->dm.dc_lock); 1311 if (!dc_stream_program_cursor_attributes(crtc_state->stream, 1312 &attributes)) 1313 DRM_ERROR("DC failed to set cursor attributes\n"); 1314 1315 if (!dc_stream_program_cursor_position(crtc_state->stream, 1316 &position)) 1317 DRM_ERROR("DC failed to set cursor position\n"); 1318 mutex_unlock(&adev->dm.dc_lock); 1319 } 1320 } 1321 1322 static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, 1323 struct drm_atomic_state *state) 1324 { 1325 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1326 plane); 1327 struct drm_plane_state *old_state = 1328 drm_atomic_get_old_plane_state(state, plane); 1329 1330 trace_amdgpu_dm_atomic_update_cursor(new_state); 1331 1332 swap(plane->state->fb, new_state->fb); 1333 1334 plane->state->src_x = new_state->src_x; 1335 plane->state->src_y = new_state->src_y; 1336 plane->state->src_w = new_state->src_w; 1337 plane->state->src_h = new_state->src_h; 1338 plane->state->crtc_x = new_state->crtc_x; 1339 plane->state->crtc_y = new_state->crtc_y; 1340 plane->state->crtc_w = new_state->crtc_w; 1341 plane->state->crtc_h = new_state->crtc_h; 1342 1343 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1344 } 1345 1346 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1347 .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, 1348 .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, 1349 .atomic_check = amdgpu_dm_plane_atomic_check, 1350 .atomic_async_check = amdgpu_dm_plane_atomic_async_check, 1351 .atomic_async_update = amdgpu_dm_plane_atomic_async_update 1352 }; 1353 1354 static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) 1355 { 1356 struct dm_plane_state *amdgpu_state = NULL; 1357 1358 if (plane->state) 1359 plane->funcs->atomic_destroy_state(plane, plane->state); 1360 1361 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1362 WARN_ON(amdgpu_state == NULL); 1363 1364 if (!amdgpu_state) 1365 return; 1366 1367 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1368 amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1369 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; 1370 amdgpu_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1371 amdgpu_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1372 } 1373 1374 static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane) 1375 { 1376 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1377 1378 old_dm_plane_state = to_dm_plane_state(plane->state); 1379 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1380 if (!dm_plane_state) 1381 return NULL; 1382 1383 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1384 1385 if (old_dm_plane_state->dc_state) { 1386 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1387 dc_plane_state_retain(dm_plane_state->dc_state); 1388 } 1389 1390 if (old_dm_plane_state->degamma_lut) 1391 dm_plane_state->degamma_lut = 1392 drm_property_blob_get(old_dm_plane_state->degamma_lut); 1393 if (old_dm_plane_state->ctm) 1394 dm_plane_state->ctm = 1395 drm_property_blob_get(old_dm_plane_state->ctm); 1396 if (old_dm_plane_state->shaper_lut) 1397 dm_plane_state->shaper_lut = 1398 drm_property_blob_get(old_dm_plane_state->shaper_lut); 1399 if (old_dm_plane_state->lut3d) 1400 dm_plane_state->lut3d = 1401 drm_property_blob_get(old_dm_plane_state->lut3d); 1402 if (old_dm_plane_state->blend_lut) 1403 dm_plane_state->blend_lut = 1404 drm_property_blob_get(old_dm_plane_state->blend_lut); 1405 1406 dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf; 1407 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult; 1408 dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf; 1409 dm_plane_state->blend_tf = old_dm_plane_state->blend_tf; 1410 1411 return &dm_plane_state->base; 1412 } 1413 1414 static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, 1415 uint32_t format, 1416 uint64_t modifier) 1417 { 1418 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1419 const struct drm_format_info *info = drm_format_info(format); 1420 int i; 1421 1422 if (!info) 1423 return false; 1424 1425 /* 1426 * We always have to allow these modifiers: 1427 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1428 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1429 */ 1430 if (modifier == DRM_FORMAT_MOD_LINEAR || 1431 modifier == DRM_FORMAT_MOD_INVALID) { 1432 return true; 1433 } 1434 1435 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1436 for (i = 0; i < plane->modifier_count; i++) { 1437 if (modifier == plane->modifiers[i]) 1438 break; 1439 } 1440 if (i == plane->modifier_count) 1441 return false; 1442 1443 /* GFX12 doesn't have these limitations. */ 1444 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11) { 1445 enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3; 1446 1447 /* 1448 * For D swizzle the canonical modifier depends on the bpp, so check 1449 * it here. 1450 */ 1451 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1452 adev->family >= AMDGPU_FAMILY_NV) { 1453 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1454 return false; 1455 } 1456 1457 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1458 info->cpp[0] < 8) 1459 return false; 1460 1461 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) { 1462 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1463 if (info->cpp[0] != 4) 1464 return false; 1465 /* We support multi-planar formats, but not when combined with 1466 * additional DCC metadata planes. 1467 */ 1468 if (info->num_planes > 1) 1469 return false; 1470 } 1471 } 1472 1473 return true; 1474 } 1475 1476 static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, 1477 struct drm_plane_state *state) 1478 { 1479 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1480 1481 if (dm_plane_state->degamma_lut) 1482 drm_property_blob_put(dm_plane_state->degamma_lut); 1483 if (dm_plane_state->ctm) 1484 drm_property_blob_put(dm_plane_state->ctm); 1485 if (dm_plane_state->lut3d) 1486 drm_property_blob_put(dm_plane_state->lut3d); 1487 if (dm_plane_state->shaper_lut) 1488 drm_property_blob_put(dm_plane_state->shaper_lut); 1489 if (dm_plane_state->blend_lut) 1490 drm_property_blob_put(dm_plane_state->blend_lut); 1491 1492 if (dm_plane_state->dc_state) 1493 dc_plane_state_release(dm_plane_state->dc_state); 1494 1495 drm_atomic_helper_plane_destroy_state(plane, state); 1496 } 1497 1498 #ifdef AMD_PRIVATE_COLOR 1499 static void 1500 dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, 1501 struct drm_plane *plane) 1502 { 1503 struct amdgpu_mode_info mode_info = dm->adev->mode_info; 1504 struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp; 1505 1506 /* Check HW color pipeline capabilities on DPP block (pre-blending) 1507 * before exposing related properties. 1508 */ 1509 if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) { 1510 drm_object_attach_property(&plane->base, 1511 mode_info.plane_degamma_lut_property, 1512 0); 1513 drm_object_attach_property(&plane->base, 1514 mode_info.plane_degamma_lut_size_property, 1515 MAX_COLOR_LUT_ENTRIES); 1516 drm_object_attach_property(&plane->base, 1517 dm->adev->mode_info.plane_degamma_tf_property, 1518 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1519 } 1520 /* HDR MULT is always available */ 1521 drm_object_attach_property(&plane->base, 1522 dm->adev->mode_info.plane_hdr_mult_property, 1523 AMDGPU_HDR_MULT_DEFAULT); 1524 1525 /* Only enable plane CTM if both DPP and MPC gamut remap is available. */ 1526 if (dm->dc->caps.color.mpc.gamut_remap) 1527 drm_object_attach_property(&plane->base, 1528 dm->adev->mode_info.plane_ctm_property, 0); 1529 1530 if (dpp_color_caps.hw_3d_lut) { 1531 drm_object_attach_property(&plane->base, 1532 mode_info.plane_shaper_lut_property, 0); 1533 drm_object_attach_property(&plane->base, 1534 mode_info.plane_shaper_lut_size_property, 1535 MAX_COLOR_LUT_ENTRIES); 1536 drm_object_attach_property(&plane->base, 1537 mode_info.plane_shaper_tf_property, 1538 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1539 drm_object_attach_property(&plane->base, 1540 mode_info.plane_lut3d_property, 0); 1541 drm_object_attach_property(&plane->base, 1542 mode_info.plane_lut3d_size_property, 1543 MAX_COLOR_3DLUT_SIZE); 1544 } 1545 1546 if (dpp_color_caps.ogam_ram) { 1547 drm_object_attach_property(&plane->base, 1548 mode_info.plane_blend_lut_property, 0); 1549 drm_object_attach_property(&plane->base, 1550 mode_info.plane_blend_lut_size_property, 1551 MAX_COLOR_LUT_ENTRIES); 1552 drm_object_attach_property(&plane->base, 1553 mode_info.plane_blend_tf_property, 1554 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1555 } 1556 } 1557 1558 static int 1559 dm_atomic_plane_set_property(struct drm_plane *plane, 1560 struct drm_plane_state *state, 1561 struct drm_property *property, 1562 uint64_t val) 1563 { 1564 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1565 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1566 bool replaced = false; 1567 int ret; 1568 1569 if (property == adev->mode_info.plane_degamma_lut_property) { 1570 ret = drm_property_replace_blob_from_id(plane->dev, 1571 &dm_plane_state->degamma_lut, 1572 val, -1, 1573 sizeof(struct drm_color_lut), 1574 &replaced); 1575 dm_plane_state->base.color_mgmt_changed |= replaced; 1576 return ret; 1577 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1578 if (dm_plane_state->degamma_tf != val) { 1579 dm_plane_state->degamma_tf = val; 1580 dm_plane_state->base.color_mgmt_changed = 1; 1581 } 1582 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1583 if (dm_plane_state->hdr_mult != val) { 1584 dm_plane_state->hdr_mult = val; 1585 dm_plane_state->base.color_mgmt_changed = 1; 1586 } 1587 } else if (property == adev->mode_info.plane_ctm_property) { 1588 ret = drm_property_replace_blob_from_id(plane->dev, 1589 &dm_plane_state->ctm, 1590 val, 1591 sizeof(struct drm_color_ctm_3x4), -1, 1592 &replaced); 1593 dm_plane_state->base.color_mgmt_changed |= replaced; 1594 return ret; 1595 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1596 ret = drm_property_replace_blob_from_id(plane->dev, 1597 &dm_plane_state->shaper_lut, 1598 val, -1, 1599 sizeof(struct drm_color_lut), 1600 &replaced); 1601 dm_plane_state->base.color_mgmt_changed |= replaced; 1602 return ret; 1603 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1604 if (dm_plane_state->shaper_tf != val) { 1605 dm_plane_state->shaper_tf = val; 1606 dm_plane_state->base.color_mgmt_changed = 1; 1607 } 1608 } else if (property == adev->mode_info.plane_lut3d_property) { 1609 ret = drm_property_replace_blob_from_id(plane->dev, 1610 &dm_plane_state->lut3d, 1611 val, -1, 1612 sizeof(struct drm_color_lut), 1613 &replaced); 1614 dm_plane_state->base.color_mgmt_changed |= replaced; 1615 return ret; 1616 } else if (property == adev->mode_info.plane_blend_lut_property) { 1617 ret = drm_property_replace_blob_from_id(plane->dev, 1618 &dm_plane_state->blend_lut, 1619 val, -1, 1620 sizeof(struct drm_color_lut), 1621 &replaced); 1622 dm_plane_state->base.color_mgmt_changed |= replaced; 1623 return ret; 1624 } else if (property == adev->mode_info.plane_blend_tf_property) { 1625 if (dm_plane_state->blend_tf != val) { 1626 dm_plane_state->blend_tf = val; 1627 dm_plane_state->base.color_mgmt_changed = 1; 1628 } 1629 } else { 1630 drm_dbg_atomic(plane->dev, 1631 "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", 1632 plane->base.id, plane->name, 1633 property->base.id, property->name); 1634 return -EINVAL; 1635 } 1636 1637 return 0; 1638 } 1639 1640 static int 1641 dm_atomic_plane_get_property(struct drm_plane *plane, 1642 const struct drm_plane_state *state, 1643 struct drm_property *property, 1644 uint64_t *val) 1645 { 1646 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1647 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1648 1649 if (property == adev->mode_info.plane_degamma_lut_property) { 1650 *val = (dm_plane_state->degamma_lut) ? 1651 dm_plane_state->degamma_lut->base.id : 0; 1652 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1653 *val = dm_plane_state->degamma_tf; 1654 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1655 *val = dm_plane_state->hdr_mult; 1656 } else if (property == adev->mode_info.plane_ctm_property) { 1657 *val = (dm_plane_state->ctm) ? 1658 dm_plane_state->ctm->base.id : 0; 1659 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1660 *val = (dm_plane_state->shaper_lut) ? 1661 dm_plane_state->shaper_lut->base.id : 0; 1662 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1663 *val = dm_plane_state->shaper_tf; 1664 } else if (property == adev->mode_info.plane_lut3d_property) { 1665 *val = (dm_plane_state->lut3d) ? 1666 dm_plane_state->lut3d->base.id : 0; 1667 } else if (property == adev->mode_info.plane_blend_lut_property) { 1668 *val = (dm_plane_state->blend_lut) ? 1669 dm_plane_state->blend_lut->base.id : 0; 1670 } else if (property == adev->mode_info.plane_blend_tf_property) { 1671 *val = dm_plane_state->blend_tf; 1672 1673 } else { 1674 return -EINVAL; 1675 } 1676 1677 return 0; 1678 } 1679 #endif 1680 1681 static const struct drm_plane_funcs dm_plane_funcs = { 1682 .update_plane = drm_atomic_helper_update_plane, 1683 .disable_plane = drm_atomic_helper_disable_plane, 1684 .destroy = drm_plane_helper_destroy, 1685 .reset = amdgpu_dm_plane_drm_plane_reset, 1686 .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, 1687 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, 1688 .format_mod_supported = amdgpu_dm_plane_format_mod_supported, 1689 #ifdef AMD_PRIVATE_COLOR 1690 .atomic_set_property = dm_atomic_plane_set_property, 1691 .atomic_get_property = dm_atomic_plane_get_property, 1692 #endif 1693 }; 1694 1695 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1696 struct drm_plane *plane, 1697 unsigned long possible_crtcs, 1698 const struct dc_plane_cap *plane_cap) 1699 { 1700 uint32_t formats[32]; 1701 int num_formats; 1702 int res = -EPERM; 1703 unsigned int supported_rotations; 1704 uint64_t *modifiers = NULL; 1705 unsigned int primary_zpos = dm->dc->caps.max_slave_planes; 1706 1707 num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, 1708 ARRAY_SIZE(formats)); 1709 1710 res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); 1711 if (res) 1712 return res; 1713 1714 if (modifiers == NULL) 1715 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1716 1717 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1718 &dm_plane_funcs, formats, num_formats, 1719 modifiers, plane->type, NULL); 1720 kfree(modifiers); 1721 if (res) 1722 return res; 1723 1724 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1725 plane_cap && plane_cap->per_pixel_alpha) { 1726 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1727 BIT(DRM_MODE_BLEND_PREMULTI) | 1728 BIT(DRM_MODE_BLEND_COVERAGE); 1729 1730 drm_plane_create_alpha_property(plane); 1731 drm_plane_create_blend_mode_property(plane, blend_caps); 1732 } 1733 1734 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1735 /* 1736 * Allow OVERLAY planes to be used as underlays by assigning an 1737 * immutable zpos = # of OVERLAY planes to the PRIMARY plane. 1738 */ 1739 drm_plane_create_zpos_immutable_property(plane, primary_zpos); 1740 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1741 /* 1742 * OVERLAY planes can be below or above the PRIMARY, but cannot 1743 * be above the CURSOR plane. 1744 */ 1745 unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane); 1746 1747 drm_plane_create_zpos_property(plane, zpos, 0, 254); 1748 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1749 drm_plane_create_zpos_immutable_property(plane, 255); 1750 } 1751 1752 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1753 plane_cap && 1754 (plane_cap->pixel_format_support.nv12 || 1755 plane_cap->pixel_format_support.p010)) { 1756 /* This only affects YUV formats. */ 1757 drm_plane_create_color_properties( 1758 plane, 1759 BIT(DRM_COLOR_YCBCR_BT601) | 1760 BIT(DRM_COLOR_YCBCR_BT709) | 1761 BIT(DRM_COLOR_YCBCR_BT2020), 1762 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1763 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1764 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1765 } 1766 1767 supported_rotations = 1768 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1769 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1770 1771 if (dm->adev->asic_type >= CHIP_BONAIRE && 1772 plane->type != DRM_PLANE_TYPE_CURSOR) 1773 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1774 supported_rotations); 1775 1776 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) > IP_VERSION(3, 0, 1) && 1777 plane->type != DRM_PLANE_TYPE_CURSOR) 1778 drm_plane_enable_fb_damage_clips(plane); 1779 1780 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1781 1782 #ifdef AMD_PRIVATE_COLOR 1783 dm_atomic_plane_attach_color_mgmt_properties(dm, plane); 1784 #endif 1785 /* Create (reset) the plane state */ 1786 if (plane->funcs->reset) 1787 plane->funcs->reset(plane); 1788 1789 return 0; 1790 } 1791 1792 bool amdgpu_dm_plane_is_video_format(uint32_t format) 1793 { 1794 int i; 1795 1796 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1797 if (format == video_formats[i]) 1798 return true; 1799 1800 return false; 1801 } 1802 1803