1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_blend.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_fourcc.h> 32 33 #include "amdgpu.h" 34 #include "dal_asic_id.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_dm_trace.h" 37 #include "amdgpu_dm_plane.h" 38 #include "gc/gc_11_0_0_offset.h" 39 #include "gc/gc_11_0_0_sh_mask.h" 40 41 /* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47 static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62 }; 63 64 static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74 }; 75 76 static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80 }; 81 82 static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84 }; 85 86 enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91 }; 92 93 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94 { 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96 } 97 98 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101 { 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 108 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 109 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 110 static const uint32_t alpha_formats[] = { 111 DRM_FORMAT_ARGB8888, 112 DRM_FORMAT_RGBA8888, 113 DRM_FORMAT_ABGR8888, 114 DRM_FORMAT_ARGB2101010, 115 DRM_FORMAT_ABGR2101010, 116 DRM_FORMAT_ARGB16161616, 117 DRM_FORMAT_ABGR16161616, 118 DRM_FORMAT_ARGB16161616F, 119 }; 120 uint32_t format = plane_state->fb->format->format; 121 unsigned int i; 122 123 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 124 if (format == alpha_formats[i]) { 125 *per_pixel_alpha = true; 126 break; 127 } 128 } 129 130 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 131 *pre_multiplied_alpha = false; 132 } 133 134 if (plane_state->alpha < 0xffff) { 135 *global_alpha = true; 136 *global_alpha_value = plane_state->alpha >> 8; 137 } 138 } 139 140 static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 141 { 142 if (!*mods) 143 return; 144 145 if (*cap - *size < 1) { 146 uint64_t new_cap = *cap * 2; 147 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 148 149 if (!new_mods) { 150 kfree(*mods); 151 *mods = NULL; 152 return; 153 } 154 155 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 156 kfree(*mods); 157 *mods = new_mods; 158 *cap = new_cap; 159 } 160 161 (*mods)[*size] = mod; 162 *size += 1; 163 } 164 165 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) 166 { 167 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 168 } 169 170 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) 171 { 172 if (modifier == DRM_FORMAT_MOD_LINEAR) 173 return 0; 174 175 return AMD_FMT_MOD_GET(TILE, modifier); 176 } 177 178 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 179 uint64_t tiling_flags) 180 { 181 /* Fill GFX8 params */ 182 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 183 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 184 185 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 186 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 187 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 188 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 189 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 190 191 /* XXX fix me for VI */ 192 tiling_info->gfx8.num_banks = num_banks; 193 tiling_info->gfx8.array_mode = 194 DC_ARRAY_2D_TILED_THIN1; 195 tiling_info->gfx8.tile_split = tile_split; 196 tiling_info->gfx8.bank_width = bankw; 197 tiling_info->gfx8.bank_height = bankh; 198 tiling_info->gfx8.tile_aspect = mtaspect; 199 tiling_info->gfx8.tile_mode = 200 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 201 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 202 == DC_ARRAY_1D_TILED_THIN1) { 203 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 204 } 205 206 tiling_info->gfx8.pipe_config = 207 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 208 } 209 210 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 211 union dc_tiling_info *tiling_info) 212 { 213 /* Fill GFX9 params */ 214 tiling_info->gfx9.num_pipes = 215 adev->gfx.config.gb_addr_config_fields.num_pipes; 216 tiling_info->gfx9.num_banks = 217 adev->gfx.config.gb_addr_config_fields.num_banks; 218 tiling_info->gfx9.pipe_interleave = 219 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 220 tiling_info->gfx9.num_shader_engines = 221 adev->gfx.config.gb_addr_config_fields.num_se; 222 tiling_info->gfx9.max_compressed_frags = 223 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 224 tiling_info->gfx9.num_rb_per_se = 225 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 226 tiling_info->gfx9.shaderEnable = 1; 227 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 228 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 229 } 230 231 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 232 union dc_tiling_info *tiling_info, 233 uint64_t modifier) 234 { 235 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 236 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 237 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 238 unsigned int pipes_log2; 239 240 pipes_log2 = min(5u, mod_pipe_xor_bits); 241 242 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 243 244 if (!IS_AMD_FMT_MOD(modifier)) 245 return; 246 247 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 248 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 249 250 if (adev->family >= AMDGPU_FAMILY_NV) { 251 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 252 } else { 253 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 254 255 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 256 } 257 } 258 259 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, 260 const enum surface_pixel_format format, 261 const enum dc_rotation_angle rotation, 262 const union dc_tiling_info *tiling_info, 263 const struct dc_plane_dcc_param *dcc, 264 const struct dc_plane_address *address, 265 const struct plane_size *plane_size) 266 { 267 struct dc *dc = adev->dm.dc; 268 struct dc_dcc_surface_param input; 269 struct dc_surface_dcc_cap output; 270 271 memset(&input, 0, sizeof(input)); 272 memset(&output, 0, sizeof(output)); 273 274 if (!dcc->enable) 275 return 0; 276 277 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 278 !dc->cap_funcs.get_dcc_compression_cap) 279 return -EINVAL; 280 281 input.format = format; 282 input.surface_size.width = plane_size->surface_size.width; 283 input.surface_size.height = plane_size->surface_size.height; 284 input.swizzle_mode = tiling_info->gfx9.swizzle; 285 286 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 287 input.scan = SCAN_DIRECTION_HORIZONTAL; 288 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 289 input.scan = SCAN_DIRECTION_VERTICAL; 290 291 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 292 return -EINVAL; 293 294 if (!output.capable) 295 return -EINVAL; 296 297 if (dcc->independent_64b_blks == 0 && 298 output.grph.rgb.independent_64b_blks != 0) 299 return -EINVAL; 300 301 return 0; 302 } 303 304 static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 305 const struct amdgpu_framebuffer *afb, 306 const enum surface_pixel_format format, 307 const enum dc_rotation_angle rotation, 308 const struct plane_size *plane_size, 309 union dc_tiling_info *tiling_info, 310 struct dc_plane_dcc_param *dcc, 311 struct dc_plane_address *address, 312 const bool force_disable_dcc) 313 { 314 const uint64_t modifier = afb->base.modifier; 315 int ret = 0; 316 317 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 318 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 319 320 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 321 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 322 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 323 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 324 325 dcc->enable = 1; 326 dcc->meta_pitch = afb->base.pitches[1]; 327 dcc->independent_64b_blks = independent_64b_blks; 328 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 329 if (independent_64b_blks && independent_128b_blks) 330 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 331 else if (independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_128b; 333 else if (independent_64b_blks && !independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_64b; 335 else 336 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 337 } else { 338 if (independent_64b_blks) 339 dcc->dcc_ind_blk = hubp_ind_block_64b; 340 else 341 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 342 } 343 344 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 345 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 346 } 347 348 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 349 if (ret) 350 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 351 352 return ret; 353 } 354 355 static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, 356 const struct amdgpu_framebuffer *afb, 357 const enum surface_pixel_format format, 358 const enum dc_rotation_angle rotation, 359 const struct plane_size *plane_size, 360 union dc_tiling_info *tiling_info, 361 struct dc_plane_dcc_param *dcc, 362 struct dc_plane_address *address, 363 const bool force_disable_dcc) 364 { 365 const uint64_t modifier = afb->base.modifier; 366 int ret = 0; 367 368 /* TODO: Most of this function shouldn't be needed on GFX12. */ 369 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 370 371 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 372 373 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 374 int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); 375 376 dcc->enable = 1; 377 dcc->independent_64b_blks = max_compressed_block == 0; 378 379 if (max_compressed_block == 0) 380 dcc->dcc_ind_blk = hubp_ind_block_64b; 381 else if (max_compressed_block == 1) 382 dcc->dcc_ind_blk = hubp_ind_block_128b; 383 else 384 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 385 } 386 387 /* TODO: This seems wrong because there is no DCC plane on GFX12. */ 388 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 389 if (ret) 390 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 391 392 return ret; 393 } 394 395 static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev, 396 uint64_t **mods, 397 uint64_t *size, 398 uint64_t *capacity) 399 { 400 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 401 402 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 403 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 404 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 405 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 406 AMD_FMT_MOD_SET(DCC, 1) | 407 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 408 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 409 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 410 411 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 412 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 413 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 414 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 415 AMD_FMT_MOD_SET(DCC, 1) | 416 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 417 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 418 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 419 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 420 421 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 422 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 423 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 424 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 425 426 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 427 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 428 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 429 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 430 431 432 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 433 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 434 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 435 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 436 437 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 438 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 439 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 440 } 441 442 static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev, 443 uint64_t **mods, 444 uint64_t *size, 445 uint64_t *capacity) 446 { 447 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 448 int pipe_xor_bits = min(8, pipes + 449 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 450 int bank_xor_bits = min(8 - pipe_xor_bits, 451 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 452 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 453 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 454 455 456 if (adev->family == AMDGPU_FAMILY_RV) { 457 /* Raven2 and later */ 458 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 459 460 /* 461 * No _D DCC swizzles yet because we only allow 32bpp, which 462 * doesn't support _D on DCN 463 */ 464 465 if (has_constant_encode) { 466 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 467 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 468 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 469 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 470 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 471 AMD_FMT_MOD_SET(DCC, 1) | 472 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 473 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 474 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 475 } 476 477 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 478 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 479 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 480 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 481 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 482 AMD_FMT_MOD_SET(DCC, 1) | 483 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 484 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 485 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 486 487 if (has_constant_encode) { 488 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 489 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 490 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 491 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 492 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 493 AMD_FMT_MOD_SET(DCC, 1) | 494 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 495 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 496 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 497 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 498 AMD_FMT_MOD_SET(RB, rb) | 499 AMD_FMT_MOD_SET(PIPE, pipes)); 500 } 501 502 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 503 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 504 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 505 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 506 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 507 AMD_FMT_MOD_SET(DCC, 1) | 508 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 509 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 510 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 511 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 512 AMD_FMT_MOD_SET(RB, rb) | 513 AMD_FMT_MOD_SET(PIPE, pipes)); 514 } 515 516 /* 517 * Only supported for 64bpp on Raven, will be filtered on format in 518 * amdgpu_dm_plane_format_mod_supported. 519 */ 520 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 521 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 522 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 523 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 524 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 525 526 if (adev->family == AMDGPU_FAMILY_RV) { 527 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 528 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 529 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 530 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 531 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 532 } 533 534 /* 535 * Only supported for 64bpp on Raven, will be filtered on format in 536 * amdgpu_dm_plane_format_mod_supported. 537 */ 538 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 539 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 540 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 541 542 if (adev->family == AMDGPU_FAMILY_RV) { 543 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 544 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 545 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 546 } 547 } 548 549 static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev, 550 uint64_t **mods, 551 uint64_t *size, 552 uint64_t *capacity) 553 { 554 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 555 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 556 557 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 558 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 559 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 560 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 561 AMD_FMT_MOD_SET(PACKERS, pkrs) | 562 AMD_FMT_MOD_SET(DCC, 1) | 563 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 564 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 565 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 566 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 567 568 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 569 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 570 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 571 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 572 AMD_FMT_MOD_SET(PACKERS, pkrs) | 573 AMD_FMT_MOD_SET(DCC, 1) | 574 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 575 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 576 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 577 578 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 579 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 580 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 581 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 582 AMD_FMT_MOD_SET(PACKERS, pkrs) | 583 AMD_FMT_MOD_SET(DCC, 1) | 584 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 585 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 586 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 587 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 588 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 589 590 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 591 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 592 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 593 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 594 AMD_FMT_MOD_SET(PACKERS, pkrs) | 595 AMD_FMT_MOD_SET(DCC, 1) | 596 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 597 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 598 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 599 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 600 601 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 602 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 603 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 604 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 605 AMD_FMT_MOD_SET(PACKERS, pkrs)); 606 607 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 608 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 609 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 610 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 611 AMD_FMT_MOD_SET(PACKERS, pkrs)); 612 613 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 614 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 615 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 616 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 617 618 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 619 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 620 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 621 } 622 623 static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev, 624 uint64_t **mods, uint64_t *size, uint64_t *capacity) 625 { 626 int num_pipes = 0; 627 int pipe_xor_bits = 0; 628 int num_pkrs = 0; 629 int pkrs = 0; 630 u32 gb_addr_config; 631 u8 i = 0; 632 unsigned int swizzle_r_x; 633 uint64_t modifier_r_x; 634 uint64_t modifier_dcc_best; 635 uint64_t modifier_dcc_4k; 636 637 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 638 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 639 */ 640 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 641 ASSERT(gb_addr_config != 0); 642 643 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 644 pkrs = ilog2(num_pkrs); 645 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 646 pipe_xor_bits = ilog2(num_pipes); 647 648 for (i = 0; i < 2; i++) { 649 /* Insert the best one first. */ 650 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 651 if (num_pipes > 16) 652 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 653 else 654 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 655 656 modifier_r_x = AMD_FMT_MOD | 657 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 658 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 659 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 660 AMD_FMT_MOD_SET(PACKERS, pkrs); 661 662 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 663 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 664 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 665 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 666 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 667 668 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 669 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 670 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 671 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 672 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 673 674 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best); 675 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k); 676 677 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 678 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 679 680 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x); 681 } 682 683 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 684 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 685 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 686 } 687 688 static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, 689 uint64_t **mods, uint64_t *size, uint64_t *capacity) 690 { 691 uint64_t mod_64K_2D = AMD_FMT_MOD | 692 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | 693 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D); 694 695 /* 64K without DCC */ 696 amdgpu_dm_plane_add_modifier(mods, size, capacity, mod_64K_2D); 697 amdgpu_dm_plane_add_modifier(mods, size, capacity, DRM_FORMAT_MOD_LINEAR); 698 } 699 700 static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 701 { 702 uint64_t size = 0, capacity = 128; 703 *mods = NULL; 704 705 /* We have not hooked up any pre-GFX9 modifiers. */ 706 if (adev->family < AMDGPU_FAMILY_AI) 707 return 0; 708 709 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 710 711 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 712 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 713 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 714 return *mods ? 0 : -ENOMEM; 715 } 716 717 switch (adev->family) { 718 case AMDGPU_FAMILY_AI: 719 case AMDGPU_FAMILY_RV: 720 amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity); 721 break; 722 case AMDGPU_FAMILY_NV: 723 case AMDGPU_FAMILY_VGH: 724 case AMDGPU_FAMILY_YC: 725 case AMDGPU_FAMILY_GC_10_3_6: 726 case AMDGPU_FAMILY_GC_10_3_7: 727 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 728 amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity); 729 else 730 amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity); 731 break; 732 case AMDGPU_FAMILY_GC_11_0_0: 733 case AMDGPU_FAMILY_GC_11_0_1: 734 case AMDGPU_FAMILY_GC_11_5_0: 735 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); 736 break; 737 case AMDGPU_FAMILY_GC_12_0_0: 738 amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity); 739 break; 740 } 741 742 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 743 744 /* INVALID marks the end of the list. */ 745 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 746 747 if (!*mods) 748 return -ENOMEM; 749 750 return 0; 751 } 752 753 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, 754 const struct dc_plane_cap *plane_cap, 755 uint32_t *formats, int max_formats) 756 { 757 int i, num_formats = 0; 758 759 /* 760 * TODO: Query support for each group of formats directly from 761 * DC plane caps. This will require adding more formats to the 762 * caps list. 763 */ 764 765 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 766 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 767 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 768 if (num_formats >= max_formats) 769 break; 770 771 formats[num_formats++] = rgb_formats[i]; 772 } 773 774 if (plane_cap && plane_cap->pixel_format_support.nv12) 775 formats[num_formats++] = DRM_FORMAT_NV12; 776 if (plane_cap && plane_cap->pixel_format_support.p010) 777 formats[num_formats++] = DRM_FORMAT_P010; 778 if (plane_cap && plane_cap->pixel_format_support.fp16) { 779 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 780 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 781 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 782 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 783 } 784 } else { 785 switch (plane->type) { 786 case DRM_PLANE_TYPE_OVERLAY: 787 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 788 if (num_formats >= max_formats) 789 break; 790 791 formats[num_formats++] = overlay_formats[i]; 792 } 793 break; 794 795 case DRM_PLANE_TYPE_CURSOR: 796 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 797 if (num_formats >= max_formats) 798 break; 799 800 formats[num_formats++] = cursor_formats[i]; 801 } 802 break; 803 804 default: 805 break; 806 } 807 } 808 809 return num_formats; 810 } 811 812 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 813 const struct amdgpu_framebuffer *afb, 814 const enum surface_pixel_format format, 815 const enum dc_rotation_angle rotation, 816 const uint64_t tiling_flags, 817 union dc_tiling_info *tiling_info, 818 struct plane_size *plane_size, 819 struct dc_plane_dcc_param *dcc, 820 struct dc_plane_address *address, 821 bool tmz_surface, 822 bool force_disable_dcc) 823 { 824 const struct drm_framebuffer *fb = &afb->base; 825 int ret; 826 827 memset(tiling_info, 0, sizeof(*tiling_info)); 828 memset(plane_size, 0, sizeof(*plane_size)); 829 memset(dcc, 0, sizeof(*dcc)); 830 memset(address, 0, sizeof(*address)); 831 832 address->tmz_surface = tmz_surface; 833 834 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 835 uint64_t addr = afb->address + fb->offsets[0]; 836 837 plane_size->surface_size.x = 0; 838 plane_size->surface_size.y = 0; 839 plane_size->surface_size.width = fb->width; 840 plane_size->surface_size.height = fb->height; 841 plane_size->surface_pitch = 842 fb->pitches[0] / fb->format->cpp[0]; 843 844 address->type = PLN_ADDR_TYPE_GRAPHICS; 845 address->grph.addr.low_part = lower_32_bits(addr); 846 address->grph.addr.high_part = upper_32_bits(addr); 847 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 848 uint64_t luma_addr = afb->address + fb->offsets[0]; 849 uint64_t chroma_addr = afb->address + fb->offsets[1]; 850 851 plane_size->surface_size.x = 0; 852 plane_size->surface_size.y = 0; 853 plane_size->surface_size.width = fb->width; 854 plane_size->surface_size.height = fb->height; 855 plane_size->surface_pitch = 856 fb->pitches[0] / fb->format->cpp[0]; 857 858 plane_size->chroma_size.x = 0; 859 plane_size->chroma_size.y = 0; 860 /* TODO: set these based on surface format */ 861 plane_size->chroma_size.width = fb->width / 2; 862 plane_size->chroma_size.height = fb->height / 2; 863 864 plane_size->chroma_pitch = 865 fb->pitches[1] / fb->format->cpp[1]; 866 867 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 868 address->video_progressive.luma_addr.low_part = 869 lower_32_bits(luma_addr); 870 address->video_progressive.luma_addr.high_part = 871 upper_32_bits(luma_addr); 872 address->video_progressive.chroma_addr.low_part = 873 lower_32_bits(chroma_addr); 874 address->video_progressive.chroma_addr.high_part = 875 upper_32_bits(chroma_addr); 876 } 877 878 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 879 ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, 880 rotation, plane_size, 881 tiling_info, dcc, 882 address, 883 force_disable_dcc); 884 if (ret) 885 return ret; 886 } else if (adev->family >= AMDGPU_FAMILY_AI) { 887 ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 888 rotation, plane_size, 889 tiling_info, dcc, 890 address, 891 force_disable_dcc); 892 if (ret) 893 return ret; 894 } else { 895 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 896 } 897 898 return 0; 899 } 900 901 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, 902 struct drm_plane_state *new_state) 903 { 904 struct amdgpu_framebuffer *afb; 905 struct drm_gem_object *obj; 906 struct amdgpu_device *adev; 907 struct amdgpu_bo *rbo; 908 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 909 uint32_t domain; 910 int r; 911 912 if (!new_state->fb) { 913 DRM_DEBUG_KMS("No FB bound\n"); 914 return 0; 915 } 916 917 afb = to_amdgpu_framebuffer(new_state->fb); 918 obj = new_state->fb->obj[0]; 919 rbo = gem_to_amdgpu_bo(obj); 920 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 921 922 r = amdgpu_bo_reserve(rbo, true); 923 if (r) { 924 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 925 return r; 926 } 927 928 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 929 if (r) { 930 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 931 goto error_unlock; 932 } 933 934 if (plane->type != DRM_PLANE_TYPE_CURSOR) 935 domain = amdgpu_display_supported_domains(adev, rbo->flags); 936 else 937 domain = AMDGPU_GEM_DOMAIN_VRAM; 938 939 r = amdgpu_bo_pin(rbo, domain); 940 if (unlikely(r != 0)) { 941 if (r != -ERESTARTSYS) 942 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 943 goto error_unlock; 944 } 945 946 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 947 if (unlikely(r != 0)) { 948 DRM_ERROR("%p bind failed\n", rbo); 949 goto error_unpin; 950 } 951 952 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 953 if (unlikely(r != 0)) 954 goto error_unpin; 955 956 amdgpu_bo_unreserve(rbo); 957 958 afb->address = amdgpu_bo_gpu_offset(rbo); 959 960 amdgpu_bo_ref(rbo); 961 962 /** 963 * We don't do surface updates on planes that have been newly created, 964 * but we also don't have the afb->address during atomic check. 965 * 966 * Fill in buffer attributes depending on the address here, but only on 967 * newly created planes since they're not being used by DC yet and this 968 * won't modify global state. 969 */ 970 dm_plane_state_old = to_dm_plane_state(plane->state); 971 dm_plane_state_new = to_dm_plane_state(new_state); 972 973 if (dm_plane_state_new->dc_state && 974 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 975 struct dc_plane_state *plane_state = 976 dm_plane_state_new->dc_state; 977 bool force_disable_dcc = !plane_state->dcc.enable; 978 979 amdgpu_dm_plane_fill_plane_buffer_attributes( 980 adev, afb, plane_state->format, plane_state->rotation, 981 afb->tiling_flags, 982 &plane_state->tiling_info, &plane_state->plane_size, 983 &plane_state->dcc, &plane_state->address, 984 afb->tmz_surface, force_disable_dcc); 985 } 986 987 return 0; 988 989 error_unpin: 990 amdgpu_bo_unpin(rbo); 991 992 error_unlock: 993 amdgpu_bo_unreserve(rbo); 994 return r; 995 } 996 997 static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, 998 struct drm_plane_state *old_state) 999 { 1000 struct amdgpu_bo *rbo; 1001 int r; 1002 1003 if (!old_state->fb) 1004 return; 1005 1006 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 1007 r = amdgpu_bo_reserve(rbo, false); 1008 if (unlikely(r)) { 1009 DRM_ERROR("failed to reserve rbo before unpin\n"); 1010 return; 1011 } 1012 1013 amdgpu_bo_unpin(rbo); 1014 amdgpu_bo_unreserve(rbo); 1015 amdgpu_bo_unref(&rbo); 1016 } 1017 1018 static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, 1019 struct drm_framebuffer *fb, 1020 int *min_downscale, int *max_upscale) 1021 { 1022 struct amdgpu_device *adev = drm_to_adev(dev); 1023 struct dc *dc = adev->dm.dc; 1024 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 1025 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 1026 1027 switch (fb->format->format) { 1028 case DRM_FORMAT_P010: 1029 case DRM_FORMAT_NV12: 1030 case DRM_FORMAT_NV21: 1031 *max_upscale = plane_cap->max_upscale_factor.nv12; 1032 *min_downscale = plane_cap->max_downscale_factor.nv12; 1033 break; 1034 1035 case DRM_FORMAT_XRGB16161616F: 1036 case DRM_FORMAT_ARGB16161616F: 1037 case DRM_FORMAT_XBGR16161616F: 1038 case DRM_FORMAT_ABGR16161616F: 1039 *max_upscale = plane_cap->max_upscale_factor.fp16; 1040 *min_downscale = plane_cap->max_downscale_factor.fp16; 1041 break; 1042 1043 default: 1044 *max_upscale = plane_cap->max_upscale_factor.argb8888; 1045 *min_downscale = plane_cap->max_downscale_factor.argb8888; 1046 break; 1047 } 1048 1049 /* 1050 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 1051 * scaling factor of 1.0 == 1000 units. 1052 */ 1053 if (*max_upscale == 1) 1054 *max_upscale = 1000; 1055 1056 if (*min_downscale == 1) 1057 *min_downscale = 1000; 1058 } 1059 1060 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 1061 struct drm_crtc_state *new_crtc_state) 1062 { 1063 struct drm_framebuffer *fb = state->fb; 1064 int min_downscale, max_upscale; 1065 int min_scale = 0; 1066 int max_scale = INT_MAX; 1067 1068 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1069 if (fb && state->crtc) { 1070 /* Validate viewport to cover the case when only the position changes */ 1071 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1072 int viewport_width = state->crtc_w; 1073 int viewport_height = state->crtc_h; 1074 1075 if (state->crtc_x < 0) 1076 viewport_width += state->crtc_x; 1077 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1078 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1079 1080 if (state->crtc_y < 0) 1081 viewport_height += state->crtc_y; 1082 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1083 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1084 1085 if (viewport_width < 0 || viewport_height < 0) { 1086 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1087 return -EINVAL; 1088 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1089 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1090 return -EINVAL; 1091 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1092 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1093 return -EINVAL; 1094 } 1095 1096 } 1097 1098 /* Get min/max allowed scaling factors from plane caps. */ 1099 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1100 &min_downscale, &max_upscale); 1101 /* 1102 * Convert to drm convention: 16.16 fixed point, instead of dc's 1103 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1104 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1105 */ 1106 min_scale = (1000 << 16) / max_upscale; 1107 max_scale = (1000 << 16) / min_downscale; 1108 } 1109 1110 return drm_atomic_helper_check_plane_state( 1111 state, new_crtc_state, min_scale, max_scale, true, true); 1112 } 1113 1114 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1115 const struct drm_plane_state *state, 1116 struct dc_scaling_info *scaling_info) 1117 { 1118 int scale_w, scale_h, min_downscale, max_upscale; 1119 1120 memset(scaling_info, 0, sizeof(*scaling_info)); 1121 1122 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1123 scaling_info->src_rect.x = state->src_x >> 16; 1124 scaling_info->src_rect.y = state->src_y >> 16; 1125 1126 /* 1127 * For reasons we don't (yet) fully understand a non-zero 1128 * src_y coordinate into an NV12 buffer can cause a 1129 * system hang on DCN1x. 1130 * To avoid hangs (and maybe be overly cautious) 1131 * let's reject both non-zero src_x and src_y. 1132 * 1133 * We currently know of only one use-case to reproduce a 1134 * scenario with non-zero src_x and src_y for NV12, which 1135 * is to gesture the YouTube Android app into full screen 1136 * on ChromeOS. 1137 */ 1138 if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1139 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && 1140 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1141 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1142 return -EINVAL; 1143 1144 scaling_info->src_rect.width = state->src_w >> 16; 1145 if (scaling_info->src_rect.width == 0) 1146 return -EINVAL; 1147 1148 scaling_info->src_rect.height = state->src_h >> 16; 1149 if (scaling_info->src_rect.height == 0) 1150 return -EINVAL; 1151 1152 scaling_info->dst_rect.x = state->crtc_x; 1153 scaling_info->dst_rect.y = state->crtc_y; 1154 1155 if (state->crtc_w == 0) 1156 return -EINVAL; 1157 1158 scaling_info->dst_rect.width = state->crtc_w; 1159 1160 if (state->crtc_h == 0) 1161 return -EINVAL; 1162 1163 scaling_info->dst_rect.height = state->crtc_h; 1164 1165 /* DRM doesn't specify clipping on destination output. */ 1166 scaling_info->clip_rect = scaling_info->dst_rect; 1167 1168 /* Validate scaling per-format with DC plane caps */ 1169 if (state->plane && state->plane->dev && state->fb) { 1170 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1171 &min_downscale, &max_upscale); 1172 } else { 1173 min_downscale = 250; 1174 max_upscale = 16000; 1175 } 1176 1177 scale_w = scaling_info->dst_rect.width * 1000 / 1178 scaling_info->src_rect.width; 1179 1180 if (scale_w < min_downscale || scale_w > max_upscale) 1181 return -EINVAL; 1182 1183 scale_h = scaling_info->dst_rect.height * 1000 / 1184 scaling_info->src_rect.height; 1185 1186 if (scale_h < min_downscale || scale_h > max_upscale) 1187 return -EINVAL; 1188 1189 /* 1190 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1191 * assume reasonable defaults based on the format. 1192 */ 1193 1194 return 0; 1195 } 1196 1197 static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, 1198 struct drm_atomic_state *state) 1199 { 1200 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1201 plane); 1202 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1203 struct dc *dc = adev->dm.dc; 1204 struct dm_plane_state *dm_plane_state; 1205 struct dc_scaling_info scaling_info; 1206 struct drm_crtc_state *new_crtc_state; 1207 int ret; 1208 1209 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1210 1211 dm_plane_state = to_dm_plane_state(new_plane_state); 1212 1213 if (!dm_plane_state->dc_state) 1214 return 0; 1215 1216 new_crtc_state = 1217 drm_atomic_get_new_crtc_state(state, 1218 new_plane_state->crtc); 1219 if (!new_crtc_state) 1220 return -EINVAL; 1221 1222 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1223 if (ret) 1224 return ret; 1225 1226 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1227 if (ret) 1228 return ret; 1229 1230 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1231 return 0; 1232 1233 return -EINVAL; 1234 } 1235 1236 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, 1237 struct drm_atomic_state *state) 1238 { 1239 struct drm_crtc_state *new_crtc_state; 1240 struct drm_plane_state *new_plane_state; 1241 struct dm_crtc_state *dm_new_crtc_state; 1242 1243 /* Only support async updates on cursor planes. */ 1244 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1245 return -EINVAL; 1246 1247 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 1248 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 1249 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1250 /* Reject overlay cursors for now*/ 1251 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 1252 return -EINVAL; 1253 1254 return 0; 1255 } 1256 1257 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1258 struct dc_cursor_position *position) 1259 { 1260 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1261 int x, y; 1262 int xorigin = 0, yorigin = 0; 1263 1264 if (!crtc || !plane->state->fb) 1265 return 0; 1266 1267 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1268 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1269 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1270 __func__, 1271 plane->state->crtc_w, 1272 plane->state->crtc_h); 1273 return -EINVAL; 1274 } 1275 1276 x = plane->state->crtc_x; 1277 y = plane->state->crtc_y; 1278 1279 if (x <= -amdgpu_crtc->max_cursor_width || 1280 y <= -amdgpu_crtc->max_cursor_height) 1281 return 0; 1282 1283 if (x < 0) { 1284 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1285 x = 0; 1286 } 1287 if (y < 0) { 1288 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1289 y = 0; 1290 } 1291 position->enable = true; 1292 position->translate_by_source = true; 1293 position->x = x; 1294 position->y = y; 1295 position->x_hotspot = xorigin; 1296 position->y_hotspot = yorigin; 1297 1298 return 0; 1299 } 1300 1301 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1302 struct drm_plane_state *old_plane_state) 1303 { 1304 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1305 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1306 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1307 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1309 uint64_t address = afb ? afb->address : 0; 1310 struct dc_cursor_position position = {0}; 1311 struct dc_cursor_attributes attributes; 1312 int ret; 1313 1314 if (!plane->state->fb && !old_plane_state->fb) 1315 return; 1316 1317 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 1318 amdgpu_crtc->crtc_id, plane->state->crtc_w, 1319 plane->state->crtc_h); 1320 1321 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 1322 if (ret) 1323 return; 1324 1325 if (!position.enable) { 1326 /* turn off cursor */ 1327 if (crtc_state && crtc_state->stream) { 1328 mutex_lock(&adev->dm.dc_lock); 1329 dc_stream_program_cursor_position(crtc_state->stream, 1330 &position); 1331 mutex_unlock(&adev->dm.dc_lock); 1332 } 1333 return; 1334 } 1335 1336 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1337 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1338 1339 memset(&attributes, 0, sizeof(attributes)); 1340 attributes.address.high_part = upper_32_bits(address); 1341 attributes.address.low_part = lower_32_bits(address); 1342 attributes.width = plane->state->crtc_w; 1343 attributes.height = plane->state->crtc_h; 1344 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1345 attributes.rotation_angle = 0; 1346 attributes.attribute_flags.value = 0; 1347 1348 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 1349 * legacy gamma setup. 1350 */ 1351 if (crtc_state->cm_is_degamma_srgb && 1352 adev->dm.dc->caps.color.dpp.gamma_corr) 1353 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 1354 1355 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1356 1357 if (crtc_state->stream) { 1358 mutex_lock(&adev->dm.dc_lock); 1359 if (!dc_stream_program_cursor_attributes(crtc_state->stream, 1360 &attributes)) 1361 DRM_ERROR("DC failed to set cursor attributes\n"); 1362 1363 if (!dc_stream_program_cursor_position(crtc_state->stream, 1364 &position)) 1365 DRM_ERROR("DC failed to set cursor position\n"); 1366 mutex_unlock(&adev->dm.dc_lock); 1367 } 1368 } 1369 1370 static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, 1371 struct drm_atomic_state *state) 1372 { 1373 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1374 plane); 1375 struct drm_plane_state *old_state = 1376 drm_atomic_get_old_plane_state(state, plane); 1377 1378 trace_amdgpu_dm_atomic_update_cursor(new_state); 1379 1380 swap(plane->state->fb, new_state->fb); 1381 1382 plane->state->src_x = new_state->src_x; 1383 plane->state->src_y = new_state->src_y; 1384 plane->state->src_w = new_state->src_w; 1385 plane->state->src_h = new_state->src_h; 1386 plane->state->crtc_x = new_state->crtc_x; 1387 plane->state->crtc_y = new_state->crtc_y; 1388 plane->state->crtc_w = new_state->crtc_w; 1389 plane->state->crtc_h = new_state->crtc_h; 1390 1391 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1392 } 1393 1394 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1395 .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, 1396 .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, 1397 .atomic_check = amdgpu_dm_plane_atomic_check, 1398 .atomic_async_check = amdgpu_dm_plane_atomic_async_check, 1399 .atomic_async_update = amdgpu_dm_plane_atomic_async_update 1400 }; 1401 1402 static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) 1403 { 1404 struct dm_plane_state *amdgpu_state = NULL; 1405 1406 if (plane->state) 1407 plane->funcs->atomic_destroy_state(plane, plane->state); 1408 1409 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1410 WARN_ON(amdgpu_state == NULL); 1411 1412 if (!amdgpu_state) 1413 return; 1414 1415 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1416 amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1417 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; 1418 amdgpu_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1419 amdgpu_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1420 } 1421 1422 static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane) 1423 { 1424 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1425 1426 old_dm_plane_state = to_dm_plane_state(plane->state); 1427 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1428 if (!dm_plane_state) 1429 return NULL; 1430 1431 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1432 1433 if (old_dm_plane_state->dc_state) { 1434 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1435 dc_plane_state_retain(dm_plane_state->dc_state); 1436 } 1437 1438 if (old_dm_plane_state->degamma_lut) 1439 dm_plane_state->degamma_lut = 1440 drm_property_blob_get(old_dm_plane_state->degamma_lut); 1441 if (old_dm_plane_state->ctm) 1442 dm_plane_state->ctm = 1443 drm_property_blob_get(old_dm_plane_state->ctm); 1444 if (old_dm_plane_state->shaper_lut) 1445 dm_plane_state->shaper_lut = 1446 drm_property_blob_get(old_dm_plane_state->shaper_lut); 1447 if (old_dm_plane_state->lut3d) 1448 dm_plane_state->lut3d = 1449 drm_property_blob_get(old_dm_plane_state->lut3d); 1450 if (old_dm_plane_state->blend_lut) 1451 dm_plane_state->blend_lut = 1452 drm_property_blob_get(old_dm_plane_state->blend_lut); 1453 1454 dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf; 1455 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult; 1456 dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf; 1457 dm_plane_state->blend_tf = old_dm_plane_state->blend_tf; 1458 1459 return &dm_plane_state->base; 1460 } 1461 1462 static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, 1463 uint32_t format, 1464 uint64_t modifier) 1465 { 1466 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1467 const struct drm_format_info *info = drm_format_info(format); 1468 int i; 1469 1470 if (!info) 1471 return false; 1472 1473 /* 1474 * We always have to allow these modifiers: 1475 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1476 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1477 */ 1478 if (modifier == DRM_FORMAT_MOD_LINEAR || 1479 modifier == DRM_FORMAT_MOD_INVALID) { 1480 return true; 1481 } 1482 1483 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1484 for (i = 0; i < plane->modifier_count; i++) { 1485 if (modifier == plane->modifiers[i]) 1486 break; 1487 } 1488 if (i == plane->modifier_count) 1489 return false; 1490 1491 /* GFX12 doesn't have these limitations. */ 1492 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11) { 1493 enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3; 1494 1495 /* 1496 * For D swizzle the canonical modifier depends on the bpp, so check 1497 * it here. 1498 */ 1499 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1500 adev->family >= AMDGPU_FAMILY_NV) { 1501 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1502 return false; 1503 } 1504 1505 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1506 info->cpp[0] < 8) 1507 return false; 1508 1509 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) { 1510 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1511 if (info->cpp[0] != 4) 1512 return false; 1513 /* We support multi-planar formats, but not when combined with 1514 * additional DCC metadata planes. 1515 */ 1516 if (info->num_planes > 1) 1517 return false; 1518 } 1519 } 1520 1521 return true; 1522 } 1523 1524 static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, 1525 struct drm_plane_state *state) 1526 { 1527 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1528 1529 if (dm_plane_state->degamma_lut) 1530 drm_property_blob_put(dm_plane_state->degamma_lut); 1531 if (dm_plane_state->ctm) 1532 drm_property_blob_put(dm_plane_state->ctm); 1533 if (dm_plane_state->lut3d) 1534 drm_property_blob_put(dm_plane_state->lut3d); 1535 if (dm_plane_state->shaper_lut) 1536 drm_property_blob_put(dm_plane_state->shaper_lut); 1537 if (dm_plane_state->blend_lut) 1538 drm_property_blob_put(dm_plane_state->blend_lut); 1539 1540 if (dm_plane_state->dc_state) 1541 dc_plane_state_release(dm_plane_state->dc_state); 1542 1543 drm_atomic_helper_plane_destroy_state(plane, state); 1544 } 1545 1546 #ifdef AMD_PRIVATE_COLOR 1547 static void 1548 dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, 1549 struct drm_plane *plane) 1550 { 1551 struct amdgpu_mode_info mode_info = dm->adev->mode_info; 1552 struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp; 1553 1554 /* Check HW color pipeline capabilities on DPP block (pre-blending) 1555 * before exposing related properties. 1556 */ 1557 if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) { 1558 drm_object_attach_property(&plane->base, 1559 mode_info.plane_degamma_lut_property, 1560 0); 1561 drm_object_attach_property(&plane->base, 1562 mode_info.plane_degamma_lut_size_property, 1563 MAX_COLOR_LUT_ENTRIES); 1564 drm_object_attach_property(&plane->base, 1565 dm->adev->mode_info.plane_degamma_tf_property, 1566 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1567 } 1568 /* HDR MULT is always available */ 1569 drm_object_attach_property(&plane->base, 1570 dm->adev->mode_info.plane_hdr_mult_property, 1571 AMDGPU_HDR_MULT_DEFAULT); 1572 1573 /* Only enable plane CTM if both DPP and MPC gamut remap is available. */ 1574 if (dm->dc->caps.color.mpc.gamut_remap) 1575 drm_object_attach_property(&plane->base, 1576 dm->adev->mode_info.plane_ctm_property, 0); 1577 1578 if (dpp_color_caps.hw_3d_lut) { 1579 drm_object_attach_property(&plane->base, 1580 mode_info.plane_shaper_lut_property, 0); 1581 drm_object_attach_property(&plane->base, 1582 mode_info.plane_shaper_lut_size_property, 1583 MAX_COLOR_LUT_ENTRIES); 1584 drm_object_attach_property(&plane->base, 1585 mode_info.plane_shaper_tf_property, 1586 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1587 drm_object_attach_property(&plane->base, 1588 mode_info.plane_lut3d_property, 0); 1589 drm_object_attach_property(&plane->base, 1590 mode_info.plane_lut3d_size_property, 1591 MAX_COLOR_3DLUT_SIZE); 1592 } 1593 1594 if (dpp_color_caps.ogam_ram) { 1595 drm_object_attach_property(&plane->base, 1596 mode_info.plane_blend_lut_property, 0); 1597 drm_object_attach_property(&plane->base, 1598 mode_info.plane_blend_lut_size_property, 1599 MAX_COLOR_LUT_ENTRIES); 1600 drm_object_attach_property(&plane->base, 1601 mode_info.plane_blend_tf_property, 1602 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1603 } 1604 } 1605 1606 static int 1607 dm_atomic_plane_set_property(struct drm_plane *plane, 1608 struct drm_plane_state *state, 1609 struct drm_property *property, 1610 uint64_t val) 1611 { 1612 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1613 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1614 bool replaced = false; 1615 int ret; 1616 1617 if (property == adev->mode_info.plane_degamma_lut_property) { 1618 ret = drm_property_replace_blob_from_id(plane->dev, 1619 &dm_plane_state->degamma_lut, 1620 val, -1, 1621 sizeof(struct drm_color_lut), 1622 &replaced); 1623 dm_plane_state->base.color_mgmt_changed |= replaced; 1624 return ret; 1625 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1626 if (dm_plane_state->degamma_tf != val) { 1627 dm_plane_state->degamma_tf = val; 1628 dm_plane_state->base.color_mgmt_changed = 1; 1629 } 1630 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1631 if (dm_plane_state->hdr_mult != val) { 1632 dm_plane_state->hdr_mult = val; 1633 dm_plane_state->base.color_mgmt_changed = 1; 1634 } 1635 } else if (property == adev->mode_info.plane_ctm_property) { 1636 ret = drm_property_replace_blob_from_id(plane->dev, 1637 &dm_plane_state->ctm, 1638 val, 1639 sizeof(struct drm_color_ctm_3x4), -1, 1640 &replaced); 1641 dm_plane_state->base.color_mgmt_changed |= replaced; 1642 return ret; 1643 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1644 ret = drm_property_replace_blob_from_id(plane->dev, 1645 &dm_plane_state->shaper_lut, 1646 val, -1, 1647 sizeof(struct drm_color_lut), 1648 &replaced); 1649 dm_plane_state->base.color_mgmt_changed |= replaced; 1650 return ret; 1651 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1652 if (dm_plane_state->shaper_tf != val) { 1653 dm_plane_state->shaper_tf = val; 1654 dm_plane_state->base.color_mgmt_changed = 1; 1655 } 1656 } else if (property == adev->mode_info.plane_lut3d_property) { 1657 ret = drm_property_replace_blob_from_id(plane->dev, 1658 &dm_plane_state->lut3d, 1659 val, -1, 1660 sizeof(struct drm_color_lut), 1661 &replaced); 1662 dm_plane_state->base.color_mgmt_changed |= replaced; 1663 return ret; 1664 } else if (property == adev->mode_info.plane_blend_lut_property) { 1665 ret = drm_property_replace_blob_from_id(plane->dev, 1666 &dm_plane_state->blend_lut, 1667 val, -1, 1668 sizeof(struct drm_color_lut), 1669 &replaced); 1670 dm_plane_state->base.color_mgmt_changed |= replaced; 1671 return ret; 1672 } else if (property == adev->mode_info.plane_blend_tf_property) { 1673 if (dm_plane_state->blend_tf != val) { 1674 dm_plane_state->blend_tf = val; 1675 dm_plane_state->base.color_mgmt_changed = 1; 1676 } 1677 } else { 1678 drm_dbg_atomic(plane->dev, 1679 "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", 1680 plane->base.id, plane->name, 1681 property->base.id, property->name); 1682 return -EINVAL; 1683 } 1684 1685 return 0; 1686 } 1687 1688 static int 1689 dm_atomic_plane_get_property(struct drm_plane *plane, 1690 const struct drm_plane_state *state, 1691 struct drm_property *property, 1692 uint64_t *val) 1693 { 1694 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1695 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1696 1697 if (property == adev->mode_info.plane_degamma_lut_property) { 1698 *val = (dm_plane_state->degamma_lut) ? 1699 dm_plane_state->degamma_lut->base.id : 0; 1700 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1701 *val = dm_plane_state->degamma_tf; 1702 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1703 *val = dm_plane_state->hdr_mult; 1704 } else if (property == adev->mode_info.plane_ctm_property) { 1705 *val = (dm_plane_state->ctm) ? 1706 dm_plane_state->ctm->base.id : 0; 1707 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1708 *val = (dm_plane_state->shaper_lut) ? 1709 dm_plane_state->shaper_lut->base.id : 0; 1710 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1711 *val = dm_plane_state->shaper_tf; 1712 } else if (property == adev->mode_info.plane_lut3d_property) { 1713 *val = (dm_plane_state->lut3d) ? 1714 dm_plane_state->lut3d->base.id : 0; 1715 } else if (property == adev->mode_info.plane_blend_lut_property) { 1716 *val = (dm_plane_state->blend_lut) ? 1717 dm_plane_state->blend_lut->base.id : 0; 1718 } else if (property == adev->mode_info.plane_blend_tf_property) { 1719 *val = dm_plane_state->blend_tf; 1720 1721 } else { 1722 return -EINVAL; 1723 } 1724 1725 return 0; 1726 } 1727 #endif 1728 1729 static const struct drm_plane_funcs dm_plane_funcs = { 1730 .update_plane = drm_atomic_helper_update_plane, 1731 .disable_plane = drm_atomic_helper_disable_plane, 1732 .destroy = drm_plane_helper_destroy, 1733 .reset = amdgpu_dm_plane_drm_plane_reset, 1734 .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, 1735 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, 1736 .format_mod_supported = amdgpu_dm_plane_format_mod_supported, 1737 #ifdef AMD_PRIVATE_COLOR 1738 .atomic_set_property = dm_atomic_plane_set_property, 1739 .atomic_get_property = dm_atomic_plane_get_property, 1740 #endif 1741 }; 1742 1743 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1744 struct drm_plane *plane, 1745 unsigned long possible_crtcs, 1746 const struct dc_plane_cap *plane_cap) 1747 { 1748 uint32_t formats[32]; 1749 int num_formats; 1750 int res = -EPERM; 1751 unsigned int supported_rotations; 1752 uint64_t *modifiers = NULL; 1753 unsigned int primary_zpos = dm->dc->caps.max_slave_planes; 1754 1755 num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, 1756 ARRAY_SIZE(formats)); 1757 1758 res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); 1759 if (res) 1760 return res; 1761 1762 if (modifiers == NULL) 1763 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1764 1765 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1766 &dm_plane_funcs, formats, num_formats, 1767 modifiers, plane->type, NULL); 1768 kfree(modifiers); 1769 if (res) 1770 return res; 1771 1772 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1773 plane_cap && plane_cap->per_pixel_alpha) { 1774 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1775 BIT(DRM_MODE_BLEND_PREMULTI) | 1776 BIT(DRM_MODE_BLEND_COVERAGE); 1777 1778 drm_plane_create_alpha_property(plane); 1779 drm_plane_create_blend_mode_property(plane, blend_caps); 1780 } 1781 1782 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1783 /* 1784 * Allow OVERLAY planes to be used as underlays by assigning an 1785 * immutable zpos = # of OVERLAY planes to the PRIMARY plane. 1786 */ 1787 drm_plane_create_zpos_immutable_property(plane, primary_zpos); 1788 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1789 /* 1790 * OVERLAY planes can be below or above the PRIMARY, but cannot 1791 * be above the CURSOR plane. 1792 */ 1793 unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane); 1794 1795 drm_plane_create_zpos_property(plane, zpos, 0, 254); 1796 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1797 drm_plane_create_zpos_immutable_property(plane, 255); 1798 } 1799 1800 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1801 plane_cap && 1802 (plane_cap->pixel_format_support.nv12 || 1803 plane_cap->pixel_format_support.p010)) { 1804 /* This only affects YUV formats. */ 1805 drm_plane_create_color_properties( 1806 plane, 1807 BIT(DRM_COLOR_YCBCR_BT601) | 1808 BIT(DRM_COLOR_YCBCR_BT709) | 1809 BIT(DRM_COLOR_YCBCR_BT2020), 1810 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1811 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1812 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1813 } 1814 1815 supported_rotations = 1816 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1817 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1818 1819 if (dm->adev->asic_type >= CHIP_BONAIRE && 1820 plane->type != DRM_PLANE_TYPE_CURSOR) 1821 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1822 supported_rotations); 1823 1824 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) > IP_VERSION(3, 0, 1) && 1825 plane->type != DRM_PLANE_TYPE_CURSOR) 1826 drm_plane_enable_fb_damage_clips(plane); 1827 1828 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1829 1830 #ifdef AMD_PRIVATE_COLOR 1831 dm_atomic_plane_attach_color_mgmt_properties(dm, plane); 1832 #endif 1833 /* Create (reset) the plane state */ 1834 if (plane->funcs->reset) 1835 plane->funcs->reset(plane); 1836 1837 return 0; 1838 } 1839 1840 bool amdgpu_dm_plane_is_video_format(uint32_t format) 1841 { 1842 int i; 1843 1844 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1845 if (format == video_formats[i]) 1846 return true; 1847 1848 return false; 1849 } 1850 1851