1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_blend.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_fourcc.h> 32 33 #include "amdgpu.h" 34 #include "dal_asic_id.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_dm_trace.h" 37 #include "amdgpu_dm_plane.h" 38 #include "gc/gc_11_0_0_offset.h" 39 #include "gc/gc_11_0_0_sh_mask.h" 40 41 /* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47 static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62 }; 63 64 static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74 }; 75 76 static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80 }; 81 82 static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84 }; 85 86 enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91 }; 92 93 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94 { 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96 } 97 98 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101 { 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 108 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 109 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 110 static const uint32_t alpha_formats[] = { 111 DRM_FORMAT_ARGB8888, 112 DRM_FORMAT_RGBA8888, 113 DRM_FORMAT_ABGR8888, 114 DRM_FORMAT_ARGB2101010, 115 DRM_FORMAT_ABGR2101010, 116 DRM_FORMAT_ARGB16161616, 117 DRM_FORMAT_ABGR16161616, 118 DRM_FORMAT_ARGB16161616F, 119 }; 120 uint32_t format = plane_state->fb->format->format; 121 unsigned int i; 122 123 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 124 if (format == alpha_formats[i]) { 125 *per_pixel_alpha = true; 126 break; 127 } 128 } 129 130 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 131 *pre_multiplied_alpha = false; 132 } 133 134 if (plane_state->alpha < 0xffff) { 135 *global_alpha = true; 136 *global_alpha_value = plane_state->alpha >> 8; 137 } 138 } 139 140 static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 141 { 142 if (!*mods) 143 return; 144 145 if (*cap - *size < 1) { 146 uint64_t new_cap = *cap * 2; 147 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 148 149 if (!new_mods) { 150 kfree(*mods); 151 *mods = NULL; 152 return; 153 } 154 155 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 156 kfree(*mods); 157 *mods = new_mods; 158 *cap = new_cap; 159 } 160 161 (*mods)[*size] = mod; 162 *size += 1; 163 } 164 165 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) 166 { 167 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 168 } 169 170 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) 171 { 172 if (modifier == DRM_FORMAT_MOD_LINEAR) 173 return 0; 174 175 return AMD_FMT_MOD_GET(TILE, modifier); 176 } 177 178 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 179 uint64_t tiling_flags) 180 { 181 /* Fill GFX8 params */ 182 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 183 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 184 185 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 186 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 187 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 188 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 189 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 190 191 /* XXX fix me for VI */ 192 tiling_info->gfx8.num_banks = num_banks; 193 tiling_info->gfx8.array_mode = 194 DC_ARRAY_2D_TILED_THIN1; 195 tiling_info->gfx8.tile_split = tile_split; 196 tiling_info->gfx8.bank_width = bankw; 197 tiling_info->gfx8.bank_height = bankh; 198 tiling_info->gfx8.tile_aspect = mtaspect; 199 tiling_info->gfx8.tile_mode = 200 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 201 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 202 == DC_ARRAY_1D_TILED_THIN1) { 203 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 204 } 205 206 tiling_info->gfx8.pipe_config = 207 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 208 } 209 210 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 211 union dc_tiling_info *tiling_info) 212 { 213 /* Fill GFX9 params */ 214 tiling_info->gfx9.num_pipes = 215 adev->gfx.config.gb_addr_config_fields.num_pipes; 216 tiling_info->gfx9.num_banks = 217 adev->gfx.config.gb_addr_config_fields.num_banks; 218 tiling_info->gfx9.pipe_interleave = 219 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 220 tiling_info->gfx9.num_shader_engines = 221 adev->gfx.config.gb_addr_config_fields.num_se; 222 tiling_info->gfx9.max_compressed_frags = 223 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 224 tiling_info->gfx9.num_rb_per_se = 225 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 226 tiling_info->gfx9.shaderEnable = 1; 227 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 228 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 229 } 230 231 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 232 union dc_tiling_info *tiling_info, 233 uint64_t modifier) 234 { 235 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 236 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 237 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 238 unsigned int pipes_log2; 239 240 pipes_log2 = min(5u, mod_pipe_xor_bits); 241 242 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 243 244 if (!IS_AMD_FMT_MOD(modifier)) 245 return; 246 247 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 248 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 249 250 if (adev->family >= AMDGPU_FAMILY_NV) { 251 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 252 } else { 253 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 254 255 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 256 } 257 } 258 259 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, 260 const enum surface_pixel_format format, 261 const enum dc_rotation_angle rotation, 262 const union dc_tiling_info *tiling_info, 263 const struct dc_plane_dcc_param *dcc, 264 const struct dc_plane_address *address, 265 const struct plane_size *plane_size) 266 { 267 struct dc *dc = adev->dm.dc; 268 struct dc_dcc_surface_param input; 269 struct dc_surface_dcc_cap output; 270 271 memset(&input, 0, sizeof(input)); 272 memset(&output, 0, sizeof(output)); 273 274 if (!dcc->enable) 275 return 0; 276 277 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 278 !dc->cap_funcs.get_dcc_compression_cap) 279 return -EINVAL; 280 281 input.format = format; 282 input.surface_size.width = plane_size->surface_size.width; 283 input.surface_size.height = plane_size->surface_size.height; 284 input.swizzle_mode = tiling_info->gfx9.swizzle; 285 286 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 287 input.scan = SCAN_DIRECTION_HORIZONTAL; 288 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 289 input.scan = SCAN_DIRECTION_VERTICAL; 290 291 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 292 return -EINVAL; 293 294 if (!output.capable) 295 return -EINVAL; 296 297 if (dcc->independent_64b_blks == 0 && 298 output.grph.rgb.independent_64b_blks != 0) 299 return -EINVAL; 300 301 return 0; 302 } 303 304 static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 305 const struct amdgpu_framebuffer *afb, 306 const enum surface_pixel_format format, 307 const enum dc_rotation_angle rotation, 308 const struct plane_size *plane_size, 309 union dc_tiling_info *tiling_info, 310 struct dc_plane_dcc_param *dcc, 311 struct dc_plane_address *address, 312 const bool force_disable_dcc) 313 { 314 const uint64_t modifier = afb->base.modifier; 315 int ret = 0; 316 317 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 318 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 319 320 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 321 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 322 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 323 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 324 325 dcc->enable = 1; 326 dcc->meta_pitch = afb->base.pitches[1]; 327 dcc->independent_64b_blks = independent_64b_blks; 328 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 329 if (independent_64b_blks && independent_128b_blks) 330 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 331 else if (independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_128b; 333 else if (independent_64b_blks && !independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_64b; 335 else 336 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 337 } else { 338 if (independent_64b_blks) 339 dcc->dcc_ind_blk = hubp_ind_block_64b; 340 else 341 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 342 } 343 344 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 345 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 346 } 347 348 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 349 if (ret) 350 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 351 352 return ret; 353 } 354 355 static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, 356 const struct amdgpu_framebuffer *afb, 357 const enum surface_pixel_format format, 358 const enum dc_rotation_angle rotation, 359 const struct plane_size *plane_size, 360 union dc_tiling_info *tiling_info, 361 struct dc_plane_dcc_param *dcc, 362 struct dc_plane_address *address, 363 const bool force_disable_dcc) 364 { 365 const uint64_t modifier = afb->base.modifier; 366 int ret = 0; 367 368 /* TODO: Most of this function shouldn't be needed on GFX12. */ 369 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 370 371 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 372 373 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 374 int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); 375 376 dcc->enable = 1; 377 dcc->independent_64b_blks = max_compressed_block == 0; 378 379 if (max_compressed_block == 0) 380 dcc->dcc_ind_blk = hubp_ind_block_64b; 381 else if (max_compressed_block == 1) 382 dcc->dcc_ind_blk = hubp_ind_block_128b; 383 else 384 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 385 } 386 387 /* TODO: This seems wrong because there is no DCC plane on GFX12. */ 388 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 389 if (ret) 390 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 391 392 return ret; 393 } 394 395 static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev, 396 uint64_t **mods, 397 uint64_t *size, 398 uint64_t *capacity) 399 { 400 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 401 402 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 403 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 404 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 405 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 406 AMD_FMT_MOD_SET(DCC, 1) | 407 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 408 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 409 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 410 411 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 412 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 413 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 414 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 415 AMD_FMT_MOD_SET(DCC, 1) | 416 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 417 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 418 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 419 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 420 421 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 422 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 423 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 424 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 425 426 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 427 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 428 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 429 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 430 431 432 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 433 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 434 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 435 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 436 437 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 438 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 439 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 440 } 441 442 static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev, 443 uint64_t **mods, 444 uint64_t *size, 445 uint64_t *capacity) 446 { 447 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 448 int pipe_xor_bits = min(8, pipes + 449 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 450 int bank_xor_bits = min(8 - pipe_xor_bits, 451 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 452 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 453 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 454 455 456 if (adev->family == AMDGPU_FAMILY_RV) { 457 /* Raven2 and later */ 458 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 459 460 /* 461 * No _D DCC swizzles yet because we only allow 32bpp, which 462 * doesn't support _D on DCN 463 */ 464 465 if (has_constant_encode) { 466 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 467 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 468 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 469 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 470 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 471 AMD_FMT_MOD_SET(DCC, 1) | 472 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 473 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 474 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 475 } 476 477 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 478 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 479 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 480 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 481 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 482 AMD_FMT_MOD_SET(DCC, 1) | 483 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 484 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 485 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 486 487 if (has_constant_encode) { 488 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 489 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 490 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 491 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 492 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 493 AMD_FMT_MOD_SET(DCC, 1) | 494 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 495 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 496 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 497 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 498 AMD_FMT_MOD_SET(RB, rb) | 499 AMD_FMT_MOD_SET(PIPE, pipes)); 500 } 501 502 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 503 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 504 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 505 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 506 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 507 AMD_FMT_MOD_SET(DCC, 1) | 508 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 509 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 510 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 511 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 512 AMD_FMT_MOD_SET(RB, rb) | 513 AMD_FMT_MOD_SET(PIPE, pipes)); 514 } 515 516 /* 517 * Only supported for 64bpp on Raven, will be filtered on format in 518 * amdgpu_dm_plane_format_mod_supported. 519 */ 520 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 521 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 522 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 523 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 524 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 525 526 if (adev->family == AMDGPU_FAMILY_RV) { 527 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 528 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 529 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 530 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 531 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 532 } 533 534 /* 535 * Only supported for 64bpp on Raven, will be filtered on format in 536 * amdgpu_dm_plane_format_mod_supported. 537 */ 538 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 539 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 540 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 541 542 if (adev->family == AMDGPU_FAMILY_RV) { 543 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 544 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 545 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 546 } 547 } 548 549 static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev, 550 uint64_t **mods, 551 uint64_t *size, 552 uint64_t *capacity) 553 { 554 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 555 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 556 557 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 558 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 559 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 560 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 561 AMD_FMT_MOD_SET(PACKERS, pkrs) | 562 AMD_FMT_MOD_SET(DCC, 1) | 563 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 564 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 565 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 566 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 567 568 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 569 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 570 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 571 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 572 AMD_FMT_MOD_SET(PACKERS, pkrs) | 573 AMD_FMT_MOD_SET(DCC, 1) | 574 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 575 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 576 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 577 578 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 579 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 580 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 581 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 582 AMD_FMT_MOD_SET(PACKERS, pkrs) | 583 AMD_FMT_MOD_SET(DCC, 1) | 584 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 585 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 586 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 587 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 588 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 589 590 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 591 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 592 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 593 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 594 AMD_FMT_MOD_SET(PACKERS, pkrs) | 595 AMD_FMT_MOD_SET(DCC, 1) | 596 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 597 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 598 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 599 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 600 601 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 602 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 603 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 604 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 605 AMD_FMT_MOD_SET(PACKERS, pkrs)); 606 607 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 608 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 609 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 610 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 611 AMD_FMT_MOD_SET(PACKERS, pkrs)); 612 613 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 614 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 615 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 616 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 617 618 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 619 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 620 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 621 } 622 623 static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev, 624 uint64_t **mods, uint64_t *size, uint64_t *capacity) 625 { 626 int num_pipes = 0; 627 int pipe_xor_bits = 0; 628 int num_pkrs = 0; 629 int pkrs = 0; 630 u32 gb_addr_config; 631 u8 i = 0; 632 unsigned int swizzle_r_x; 633 uint64_t modifier_r_x; 634 uint64_t modifier_dcc_best; 635 uint64_t modifier_dcc_4k; 636 637 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 638 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 639 */ 640 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 641 ASSERT(gb_addr_config != 0); 642 643 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 644 pkrs = ilog2(num_pkrs); 645 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 646 pipe_xor_bits = ilog2(num_pipes); 647 648 for (i = 0; i < 2; i++) { 649 /* Insert the best one first. */ 650 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 651 if (num_pipes > 16) 652 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 653 else 654 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 655 656 modifier_r_x = AMD_FMT_MOD | 657 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 658 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 659 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 660 AMD_FMT_MOD_SET(PACKERS, pkrs); 661 662 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 663 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 664 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 665 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 666 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 667 668 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 669 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 670 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 671 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 672 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 673 674 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best); 675 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k); 676 677 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 678 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 679 680 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x); 681 } 682 683 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 684 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 685 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 686 } 687 688 static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, 689 uint64_t **mods, uint64_t *size, uint64_t *capacity) 690 { 691 uint64_t ver = AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12); 692 693 /* Without DCC: */ 694 amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256K_2D)); 695 amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D)); 696 amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D)); 697 amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D)); 698 amdgpu_dm_plane_add_modifier(mods, size, capacity, DRM_FORMAT_MOD_LINEAR); 699 } 700 701 static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 702 { 703 uint64_t size = 0, capacity = 128; 704 *mods = NULL; 705 706 /* We have not hooked up any pre-GFX9 modifiers. */ 707 if (adev->family < AMDGPU_FAMILY_AI) 708 return 0; 709 710 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 711 712 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 713 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 714 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 715 return *mods ? 0 : -ENOMEM; 716 } 717 718 switch (adev->family) { 719 case AMDGPU_FAMILY_AI: 720 case AMDGPU_FAMILY_RV: 721 amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity); 722 break; 723 case AMDGPU_FAMILY_NV: 724 case AMDGPU_FAMILY_VGH: 725 case AMDGPU_FAMILY_YC: 726 case AMDGPU_FAMILY_GC_10_3_6: 727 case AMDGPU_FAMILY_GC_10_3_7: 728 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 729 amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity); 730 else 731 amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity); 732 break; 733 case AMDGPU_FAMILY_GC_11_0_0: 734 case AMDGPU_FAMILY_GC_11_0_1: 735 case AMDGPU_FAMILY_GC_11_5_0: 736 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); 737 break; 738 case AMDGPU_FAMILY_GC_12_0_0: 739 amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity); 740 break; 741 } 742 743 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 744 745 /* INVALID marks the end of the list. */ 746 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 747 748 if (!*mods) 749 return -ENOMEM; 750 751 return 0; 752 } 753 754 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, 755 const struct dc_plane_cap *plane_cap, 756 uint32_t *formats, int max_formats) 757 { 758 int i, num_formats = 0; 759 760 /* 761 * TODO: Query support for each group of formats directly from 762 * DC plane caps. This will require adding more formats to the 763 * caps list. 764 */ 765 766 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 767 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 768 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 769 if (num_formats >= max_formats) 770 break; 771 772 formats[num_formats++] = rgb_formats[i]; 773 } 774 775 if (plane_cap && plane_cap->pixel_format_support.nv12) 776 formats[num_formats++] = DRM_FORMAT_NV12; 777 if (plane_cap && plane_cap->pixel_format_support.p010) 778 formats[num_formats++] = DRM_FORMAT_P010; 779 if (plane_cap && plane_cap->pixel_format_support.fp16) { 780 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 781 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 782 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 783 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 784 } 785 } else { 786 switch (plane->type) { 787 case DRM_PLANE_TYPE_OVERLAY: 788 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 789 if (num_formats >= max_formats) 790 break; 791 792 formats[num_formats++] = overlay_formats[i]; 793 } 794 break; 795 796 case DRM_PLANE_TYPE_CURSOR: 797 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 798 if (num_formats >= max_formats) 799 break; 800 801 formats[num_formats++] = cursor_formats[i]; 802 } 803 break; 804 805 default: 806 break; 807 } 808 } 809 810 return num_formats; 811 } 812 813 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 814 const struct amdgpu_framebuffer *afb, 815 const enum surface_pixel_format format, 816 const enum dc_rotation_angle rotation, 817 const uint64_t tiling_flags, 818 union dc_tiling_info *tiling_info, 819 struct plane_size *plane_size, 820 struct dc_plane_dcc_param *dcc, 821 struct dc_plane_address *address, 822 bool tmz_surface, 823 bool force_disable_dcc) 824 { 825 const struct drm_framebuffer *fb = &afb->base; 826 int ret; 827 828 memset(tiling_info, 0, sizeof(*tiling_info)); 829 memset(plane_size, 0, sizeof(*plane_size)); 830 memset(dcc, 0, sizeof(*dcc)); 831 memset(address, 0, sizeof(*address)); 832 833 address->tmz_surface = tmz_surface; 834 835 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 836 uint64_t addr = afb->address + fb->offsets[0]; 837 838 plane_size->surface_size.x = 0; 839 plane_size->surface_size.y = 0; 840 plane_size->surface_size.width = fb->width; 841 plane_size->surface_size.height = fb->height; 842 plane_size->surface_pitch = 843 fb->pitches[0] / fb->format->cpp[0]; 844 845 address->type = PLN_ADDR_TYPE_GRAPHICS; 846 address->grph.addr.low_part = lower_32_bits(addr); 847 address->grph.addr.high_part = upper_32_bits(addr); 848 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 849 uint64_t luma_addr = afb->address + fb->offsets[0]; 850 uint64_t chroma_addr = afb->address + fb->offsets[1]; 851 852 plane_size->surface_size.x = 0; 853 plane_size->surface_size.y = 0; 854 plane_size->surface_size.width = fb->width; 855 plane_size->surface_size.height = fb->height; 856 plane_size->surface_pitch = 857 fb->pitches[0] / fb->format->cpp[0]; 858 859 plane_size->chroma_size.x = 0; 860 plane_size->chroma_size.y = 0; 861 /* TODO: set these based on surface format */ 862 plane_size->chroma_size.width = fb->width / 2; 863 plane_size->chroma_size.height = fb->height / 2; 864 865 plane_size->chroma_pitch = 866 fb->pitches[1] / fb->format->cpp[1]; 867 868 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 869 address->video_progressive.luma_addr.low_part = 870 lower_32_bits(luma_addr); 871 address->video_progressive.luma_addr.high_part = 872 upper_32_bits(luma_addr); 873 address->video_progressive.chroma_addr.low_part = 874 lower_32_bits(chroma_addr); 875 address->video_progressive.chroma_addr.high_part = 876 upper_32_bits(chroma_addr); 877 } 878 879 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 880 ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, 881 rotation, plane_size, 882 tiling_info, dcc, 883 address, 884 force_disable_dcc); 885 if (ret) 886 return ret; 887 } else if (adev->family >= AMDGPU_FAMILY_AI) { 888 ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 889 rotation, plane_size, 890 tiling_info, dcc, 891 address, 892 force_disable_dcc); 893 if (ret) 894 return ret; 895 } else { 896 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 897 } 898 899 return 0; 900 } 901 902 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, 903 struct drm_plane_state *new_state) 904 { 905 struct amdgpu_framebuffer *afb; 906 struct drm_gem_object *obj; 907 struct amdgpu_device *adev; 908 struct amdgpu_bo *rbo; 909 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 910 uint32_t domain; 911 int r; 912 913 if (!new_state->fb) { 914 DRM_DEBUG_KMS("No FB bound\n"); 915 return 0; 916 } 917 918 afb = to_amdgpu_framebuffer(new_state->fb); 919 obj = new_state->fb->obj[0]; 920 rbo = gem_to_amdgpu_bo(obj); 921 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 922 923 r = amdgpu_bo_reserve(rbo, true); 924 if (r) { 925 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 926 return r; 927 } 928 929 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 930 if (r) { 931 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 932 goto error_unlock; 933 } 934 935 if (plane->type != DRM_PLANE_TYPE_CURSOR) 936 domain = amdgpu_display_supported_domains(adev, rbo->flags); 937 else 938 domain = AMDGPU_GEM_DOMAIN_VRAM; 939 940 r = amdgpu_bo_pin(rbo, domain); 941 if (unlikely(r != 0)) { 942 if (r != -ERESTARTSYS) 943 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 944 goto error_unlock; 945 } 946 947 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 948 if (unlikely(r != 0)) { 949 DRM_ERROR("%p bind failed\n", rbo); 950 goto error_unpin; 951 } 952 953 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 954 if (unlikely(r != 0)) 955 goto error_unpin; 956 957 amdgpu_bo_unreserve(rbo); 958 959 afb->address = amdgpu_bo_gpu_offset(rbo); 960 961 amdgpu_bo_ref(rbo); 962 963 /** 964 * We don't do surface updates on planes that have been newly created, 965 * but we also don't have the afb->address during atomic check. 966 * 967 * Fill in buffer attributes depending on the address here, but only on 968 * newly created planes since they're not being used by DC yet and this 969 * won't modify global state. 970 */ 971 dm_plane_state_old = to_dm_plane_state(plane->state); 972 dm_plane_state_new = to_dm_plane_state(new_state); 973 974 if (dm_plane_state_new->dc_state && 975 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 976 struct dc_plane_state *plane_state = 977 dm_plane_state_new->dc_state; 978 bool force_disable_dcc = !plane_state->dcc.enable; 979 980 amdgpu_dm_plane_fill_plane_buffer_attributes( 981 adev, afb, plane_state->format, plane_state->rotation, 982 afb->tiling_flags, 983 &plane_state->tiling_info, &plane_state->plane_size, 984 &plane_state->dcc, &plane_state->address, 985 afb->tmz_surface, force_disable_dcc); 986 } 987 988 return 0; 989 990 error_unpin: 991 amdgpu_bo_unpin(rbo); 992 993 error_unlock: 994 amdgpu_bo_unreserve(rbo); 995 return r; 996 } 997 998 static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, 999 struct drm_plane_state *old_state) 1000 { 1001 struct amdgpu_bo *rbo; 1002 int r; 1003 1004 if (!old_state->fb) 1005 return; 1006 1007 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 1008 r = amdgpu_bo_reserve(rbo, false); 1009 if (unlikely(r)) { 1010 DRM_ERROR("failed to reserve rbo before unpin\n"); 1011 return; 1012 } 1013 1014 amdgpu_bo_unpin(rbo); 1015 amdgpu_bo_unreserve(rbo); 1016 amdgpu_bo_unref(&rbo); 1017 } 1018 1019 static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, 1020 struct drm_framebuffer *fb, 1021 int *min_downscale, int *max_upscale) 1022 { 1023 struct amdgpu_device *adev = drm_to_adev(dev); 1024 struct dc *dc = adev->dm.dc; 1025 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 1026 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 1027 1028 switch (fb->format->format) { 1029 case DRM_FORMAT_P010: 1030 case DRM_FORMAT_NV12: 1031 case DRM_FORMAT_NV21: 1032 *max_upscale = plane_cap->max_upscale_factor.nv12; 1033 *min_downscale = plane_cap->max_downscale_factor.nv12; 1034 break; 1035 1036 case DRM_FORMAT_XRGB16161616F: 1037 case DRM_FORMAT_ARGB16161616F: 1038 case DRM_FORMAT_XBGR16161616F: 1039 case DRM_FORMAT_ABGR16161616F: 1040 *max_upscale = plane_cap->max_upscale_factor.fp16; 1041 *min_downscale = plane_cap->max_downscale_factor.fp16; 1042 break; 1043 1044 default: 1045 *max_upscale = plane_cap->max_upscale_factor.argb8888; 1046 *min_downscale = plane_cap->max_downscale_factor.argb8888; 1047 break; 1048 } 1049 1050 /* 1051 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 1052 * scaling factor of 1.0 == 1000 units. 1053 */ 1054 if (*max_upscale == 1) 1055 *max_upscale = 1000; 1056 1057 if (*min_downscale == 1) 1058 *min_downscale = 1000; 1059 } 1060 1061 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 1062 struct drm_crtc_state *new_crtc_state) 1063 { 1064 struct drm_framebuffer *fb = state->fb; 1065 int min_downscale, max_upscale; 1066 int min_scale = 0; 1067 int max_scale = INT_MAX; 1068 1069 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1070 if (fb && state->crtc) { 1071 /* Validate viewport to cover the case when only the position changes */ 1072 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1073 int viewport_width = state->crtc_w; 1074 int viewport_height = state->crtc_h; 1075 1076 if (state->crtc_x < 0) 1077 viewport_width += state->crtc_x; 1078 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1079 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1080 1081 if (state->crtc_y < 0) 1082 viewport_height += state->crtc_y; 1083 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1084 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1085 1086 if (viewport_width < 0 || viewport_height < 0) { 1087 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1088 return -EINVAL; 1089 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1090 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1091 return -EINVAL; 1092 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1093 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1094 return -EINVAL; 1095 } 1096 1097 } 1098 1099 /* Get min/max allowed scaling factors from plane caps. */ 1100 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1101 &min_downscale, &max_upscale); 1102 /* 1103 * Convert to drm convention: 16.16 fixed point, instead of dc's 1104 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1105 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1106 */ 1107 min_scale = (1000 << 16) / max_upscale; 1108 max_scale = (1000 << 16) / min_downscale; 1109 } 1110 1111 return drm_atomic_helper_check_plane_state( 1112 state, new_crtc_state, min_scale, max_scale, true, true); 1113 } 1114 1115 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1116 const struct drm_plane_state *state, 1117 struct dc_scaling_info *scaling_info) 1118 { 1119 int scale_w, scale_h, min_downscale, max_upscale; 1120 1121 memset(scaling_info, 0, sizeof(*scaling_info)); 1122 1123 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1124 scaling_info->src_rect.x = state->src_x >> 16; 1125 scaling_info->src_rect.y = state->src_y >> 16; 1126 1127 /* 1128 * For reasons we don't (yet) fully understand a non-zero 1129 * src_y coordinate into an NV12 buffer can cause a 1130 * system hang on DCN1x. 1131 * To avoid hangs (and maybe be overly cautious) 1132 * let's reject both non-zero src_x and src_y. 1133 * 1134 * We currently know of only one use-case to reproduce a 1135 * scenario with non-zero src_x and src_y for NV12, which 1136 * is to gesture the YouTube Android app into full screen 1137 * on ChromeOS. 1138 */ 1139 if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1140 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && 1141 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1142 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1143 return -EINVAL; 1144 1145 scaling_info->src_rect.width = state->src_w >> 16; 1146 if (scaling_info->src_rect.width == 0) 1147 return -EINVAL; 1148 1149 scaling_info->src_rect.height = state->src_h >> 16; 1150 if (scaling_info->src_rect.height == 0) 1151 return -EINVAL; 1152 1153 scaling_info->dst_rect.x = state->crtc_x; 1154 scaling_info->dst_rect.y = state->crtc_y; 1155 1156 if (state->crtc_w == 0) 1157 return -EINVAL; 1158 1159 scaling_info->dst_rect.width = state->crtc_w; 1160 1161 if (state->crtc_h == 0) 1162 return -EINVAL; 1163 1164 scaling_info->dst_rect.height = state->crtc_h; 1165 1166 /* DRM doesn't specify clipping on destination output. */ 1167 scaling_info->clip_rect = scaling_info->dst_rect; 1168 1169 /* Validate scaling per-format with DC plane caps */ 1170 if (state->plane && state->plane->dev && state->fb) { 1171 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1172 &min_downscale, &max_upscale); 1173 } else { 1174 min_downscale = 250; 1175 max_upscale = 16000; 1176 } 1177 1178 scale_w = scaling_info->dst_rect.width * 1000 / 1179 scaling_info->src_rect.width; 1180 1181 if (scale_w < min_downscale || scale_w > max_upscale) 1182 return -EINVAL; 1183 1184 scale_h = scaling_info->dst_rect.height * 1000 / 1185 scaling_info->src_rect.height; 1186 1187 if (scale_h < min_downscale || scale_h > max_upscale) 1188 return -EINVAL; 1189 1190 /* 1191 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1192 * assume reasonable defaults based on the format. 1193 */ 1194 1195 return 0; 1196 } 1197 1198 static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, 1199 struct drm_atomic_state *state) 1200 { 1201 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1202 plane); 1203 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1204 struct dc *dc = adev->dm.dc; 1205 struct dm_plane_state *dm_plane_state; 1206 struct dc_scaling_info scaling_info; 1207 struct drm_crtc_state *new_crtc_state; 1208 int ret; 1209 1210 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1211 1212 dm_plane_state = to_dm_plane_state(new_plane_state); 1213 1214 if (!dm_plane_state->dc_state) 1215 return 0; 1216 1217 new_crtc_state = 1218 drm_atomic_get_new_crtc_state(state, 1219 new_plane_state->crtc); 1220 if (!new_crtc_state) 1221 return -EINVAL; 1222 1223 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1224 if (ret) 1225 return ret; 1226 1227 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1228 if (ret) 1229 return ret; 1230 1231 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1232 return 0; 1233 1234 return -EINVAL; 1235 } 1236 1237 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, 1238 struct drm_atomic_state *state) 1239 { 1240 struct drm_crtc_state *new_crtc_state; 1241 struct drm_plane_state *new_plane_state; 1242 struct dm_crtc_state *dm_new_crtc_state; 1243 1244 /* Only support async updates on cursor planes. */ 1245 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1246 return -EINVAL; 1247 1248 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 1249 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 1250 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1251 /* Reject overlay cursors for now*/ 1252 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 1253 return -EINVAL; 1254 1255 return 0; 1256 } 1257 1258 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1259 struct dc_cursor_position *position) 1260 { 1261 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1262 int x, y; 1263 int xorigin = 0, yorigin = 0; 1264 1265 if (!crtc || !plane->state->fb) 1266 return 0; 1267 1268 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1269 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1270 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1271 __func__, 1272 plane->state->crtc_w, 1273 plane->state->crtc_h); 1274 return -EINVAL; 1275 } 1276 1277 x = plane->state->crtc_x; 1278 y = plane->state->crtc_y; 1279 1280 if (x <= -amdgpu_crtc->max_cursor_width || 1281 y <= -amdgpu_crtc->max_cursor_height) 1282 return 0; 1283 1284 if (x < 0) { 1285 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1286 x = 0; 1287 } 1288 if (y < 0) { 1289 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1290 y = 0; 1291 } 1292 position->enable = true; 1293 position->translate_by_source = true; 1294 position->x = x; 1295 position->y = y; 1296 position->x_hotspot = xorigin; 1297 position->y_hotspot = yorigin; 1298 1299 return 0; 1300 } 1301 1302 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1303 struct drm_plane_state *old_plane_state) 1304 { 1305 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1306 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1307 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1308 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1309 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1310 uint64_t address = afb ? afb->address : 0; 1311 struct dc_cursor_position position = {0}; 1312 struct dc_cursor_attributes attributes; 1313 int ret; 1314 1315 if (!plane->state->fb && !old_plane_state->fb) 1316 return; 1317 1318 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 1319 amdgpu_crtc->crtc_id, plane->state->crtc_w, 1320 plane->state->crtc_h); 1321 1322 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 1323 if (ret) 1324 return; 1325 1326 if (!position.enable) { 1327 /* turn off cursor */ 1328 if (crtc_state && crtc_state->stream) { 1329 mutex_lock(&adev->dm.dc_lock); 1330 dc_stream_program_cursor_position(crtc_state->stream, 1331 &position); 1332 mutex_unlock(&adev->dm.dc_lock); 1333 } 1334 return; 1335 } 1336 1337 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1338 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1339 1340 memset(&attributes, 0, sizeof(attributes)); 1341 attributes.address.high_part = upper_32_bits(address); 1342 attributes.address.low_part = lower_32_bits(address); 1343 attributes.width = plane->state->crtc_w; 1344 attributes.height = plane->state->crtc_h; 1345 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1346 attributes.rotation_angle = 0; 1347 attributes.attribute_flags.value = 0; 1348 1349 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 1350 * legacy gamma setup. 1351 */ 1352 if (crtc_state->cm_is_degamma_srgb && 1353 adev->dm.dc->caps.color.dpp.gamma_corr) 1354 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 1355 1356 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1357 1358 if (crtc_state->stream) { 1359 mutex_lock(&adev->dm.dc_lock); 1360 if (!dc_stream_program_cursor_attributes(crtc_state->stream, 1361 &attributes)) 1362 DRM_ERROR("DC failed to set cursor attributes\n"); 1363 1364 if (!dc_stream_program_cursor_position(crtc_state->stream, 1365 &position)) 1366 DRM_ERROR("DC failed to set cursor position\n"); 1367 mutex_unlock(&adev->dm.dc_lock); 1368 } 1369 } 1370 1371 static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, 1372 struct drm_atomic_state *state) 1373 { 1374 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1375 plane); 1376 struct drm_plane_state *old_state = 1377 drm_atomic_get_old_plane_state(state, plane); 1378 1379 trace_amdgpu_dm_atomic_update_cursor(new_state); 1380 1381 swap(plane->state->fb, new_state->fb); 1382 1383 plane->state->src_x = new_state->src_x; 1384 plane->state->src_y = new_state->src_y; 1385 plane->state->src_w = new_state->src_w; 1386 plane->state->src_h = new_state->src_h; 1387 plane->state->crtc_x = new_state->crtc_x; 1388 plane->state->crtc_y = new_state->crtc_y; 1389 plane->state->crtc_w = new_state->crtc_w; 1390 plane->state->crtc_h = new_state->crtc_h; 1391 1392 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1393 } 1394 1395 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1396 .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, 1397 .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, 1398 .atomic_check = amdgpu_dm_plane_atomic_check, 1399 .atomic_async_check = amdgpu_dm_plane_atomic_async_check, 1400 .atomic_async_update = amdgpu_dm_plane_atomic_async_update 1401 }; 1402 1403 static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) 1404 { 1405 struct dm_plane_state *amdgpu_state = NULL; 1406 1407 if (plane->state) 1408 plane->funcs->atomic_destroy_state(plane, plane->state); 1409 1410 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1411 WARN_ON(amdgpu_state == NULL); 1412 1413 if (!amdgpu_state) 1414 return; 1415 1416 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1417 amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1418 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; 1419 amdgpu_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1420 amdgpu_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1421 } 1422 1423 static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane) 1424 { 1425 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1426 1427 old_dm_plane_state = to_dm_plane_state(plane->state); 1428 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1429 if (!dm_plane_state) 1430 return NULL; 1431 1432 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1433 1434 if (old_dm_plane_state->dc_state) { 1435 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1436 dc_plane_state_retain(dm_plane_state->dc_state); 1437 } 1438 1439 if (old_dm_plane_state->degamma_lut) 1440 dm_plane_state->degamma_lut = 1441 drm_property_blob_get(old_dm_plane_state->degamma_lut); 1442 if (old_dm_plane_state->ctm) 1443 dm_plane_state->ctm = 1444 drm_property_blob_get(old_dm_plane_state->ctm); 1445 if (old_dm_plane_state->shaper_lut) 1446 dm_plane_state->shaper_lut = 1447 drm_property_blob_get(old_dm_plane_state->shaper_lut); 1448 if (old_dm_plane_state->lut3d) 1449 dm_plane_state->lut3d = 1450 drm_property_blob_get(old_dm_plane_state->lut3d); 1451 if (old_dm_plane_state->blend_lut) 1452 dm_plane_state->blend_lut = 1453 drm_property_blob_get(old_dm_plane_state->blend_lut); 1454 1455 dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf; 1456 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult; 1457 dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf; 1458 dm_plane_state->blend_tf = old_dm_plane_state->blend_tf; 1459 1460 return &dm_plane_state->base; 1461 } 1462 1463 static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, 1464 uint32_t format, 1465 uint64_t modifier) 1466 { 1467 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1468 const struct drm_format_info *info = drm_format_info(format); 1469 int i; 1470 1471 if (!info) 1472 return false; 1473 1474 /* 1475 * We always have to allow these modifiers: 1476 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1477 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1478 */ 1479 if (modifier == DRM_FORMAT_MOD_LINEAR || 1480 modifier == DRM_FORMAT_MOD_INVALID) { 1481 return true; 1482 } 1483 1484 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1485 for (i = 0; i < plane->modifier_count; i++) { 1486 if (modifier == plane->modifiers[i]) 1487 break; 1488 } 1489 if (i == plane->modifier_count) 1490 return false; 1491 1492 /* GFX12 doesn't have these limitations. */ 1493 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11) { 1494 enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3; 1495 1496 /* 1497 * For D swizzle the canonical modifier depends on the bpp, so check 1498 * it here. 1499 */ 1500 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1501 adev->family >= AMDGPU_FAMILY_NV) { 1502 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1503 return false; 1504 } 1505 1506 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1507 info->cpp[0] < 8) 1508 return false; 1509 1510 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) { 1511 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1512 if (info->cpp[0] != 4) 1513 return false; 1514 /* We support multi-planar formats, but not when combined with 1515 * additional DCC metadata planes. 1516 */ 1517 if (info->num_planes > 1) 1518 return false; 1519 } 1520 } 1521 1522 return true; 1523 } 1524 1525 static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, 1526 struct drm_plane_state *state) 1527 { 1528 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1529 1530 if (dm_plane_state->degamma_lut) 1531 drm_property_blob_put(dm_plane_state->degamma_lut); 1532 if (dm_plane_state->ctm) 1533 drm_property_blob_put(dm_plane_state->ctm); 1534 if (dm_plane_state->lut3d) 1535 drm_property_blob_put(dm_plane_state->lut3d); 1536 if (dm_plane_state->shaper_lut) 1537 drm_property_blob_put(dm_plane_state->shaper_lut); 1538 if (dm_plane_state->blend_lut) 1539 drm_property_blob_put(dm_plane_state->blend_lut); 1540 1541 if (dm_plane_state->dc_state) 1542 dc_plane_state_release(dm_plane_state->dc_state); 1543 1544 drm_atomic_helper_plane_destroy_state(plane, state); 1545 } 1546 1547 #ifdef AMD_PRIVATE_COLOR 1548 static void 1549 dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, 1550 struct drm_plane *plane) 1551 { 1552 struct amdgpu_mode_info mode_info = dm->adev->mode_info; 1553 struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp; 1554 1555 /* Check HW color pipeline capabilities on DPP block (pre-blending) 1556 * before exposing related properties. 1557 */ 1558 if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) { 1559 drm_object_attach_property(&plane->base, 1560 mode_info.plane_degamma_lut_property, 1561 0); 1562 drm_object_attach_property(&plane->base, 1563 mode_info.plane_degamma_lut_size_property, 1564 MAX_COLOR_LUT_ENTRIES); 1565 drm_object_attach_property(&plane->base, 1566 dm->adev->mode_info.plane_degamma_tf_property, 1567 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1568 } 1569 /* HDR MULT is always available */ 1570 drm_object_attach_property(&plane->base, 1571 dm->adev->mode_info.plane_hdr_mult_property, 1572 AMDGPU_HDR_MULT_DEFAULT); 1573 1574 /* Only enable plane CTM if both DPP and MPC gamut remap is available. */ 1575 if (dm->dc->caps.color.mpc.gamut_remap) 1576 drm_object_attach_property(&plane->base, 1577 dm->adev->mode_info.plane_ctm_property, 0); 1578 1579 if (dpp_color_caps.hw_3d_lut) { 1580 drm_object_attach_property(&plane->base, 1581 mode_info.plane_shaper_lut_property, 0); 1582 drm_object_attach_property(&plane->base, 1583 mode_info.plane_shaper_lut_size_property, 1584 MAX_COLOR_LUT_ENTRIES); 1585 drm_object_attach_property(&plane->base, 1586 mode_info.plane_shaper_tf_property, 1587 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1588 drm_object_attach_property(&plane->base, 1589 mode_info.plane_lut3d_property, 0); 1590 drm_object_attach_property(&plane->base, 1591 mode_info.plane_lut3d_size_property, 1592 MAX_COLOR_3DLUT_SIZE); 1593 } 1594 1595 if (dpp_color_caps.ogam_ram) { 1596 drm_object_attach_property(&plane->base, 1597 mode_info.plane_blend_lut_property, 0); 1598 drm_object_attach_property(&plane->base, 1599 mode_info.plane_blend_lut_size_property, 1600 MAX_COLOR_LUT_ENTRIES); 1601 drm_object_attach_property(&plane->base, 1602 mode_info.plane_blend_tf_property, 1603 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1604 } 1605 } 1606 1607 static int 1608 dm_atomic_plane_set_property(struct drm_plane *plane, 1609 struct drm_plane_state *state, 1610 struct drm_property *property, 1611 uint64_t val) 1612 { 1613 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1614 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1615 bool replaced = false; 1616 int ret; 1617 1618 if (property == adev->mode_info.plane_degamma_lut_property) { 1619 ret = drm_property_replace_blob_from_id(plane->dev, 1620 &dm_plane_state->degamma_lut, 1621 val, -1, 1622 sizeof(struct drm_color_lut), 1623 &replaced); 1624 dm_plane_state->base.color_mgmt_changed |= replaced; 1625 return ret; 1626 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1627 if (dm_plane_state->degamma_tf != val) { 1628 dm_plane_state->degamma_tf = val; 1629 dm_plane_state->base.color_mgmt_changed = 1; 1630 } 1631 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1632 if (dm_plane_state->hdr_mult != val) { 1633 dm_plane_state->hdr_mult = val; 1634 dm_plane_state->base.color_mgmt_changed = 1; 1635 } 1636 } else if (property == adev->mode_info.plane_ctm_property) { 1637 ret = drm_property_replace_blob_from_id(plane->dev, 1638 &dm_plane_state->ctm, 1639 val, 1640 sizeof(struct drm_color_ctm_3x4), -1, 1641 &replaced); 1642 dm_plane_state->base.color_mgmt_changed |= replaced; 1643 return ret; 1644 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1645 ret = drm_property_replace_blob_from_id(plane->dev, 1646 &dm_plane_state->shaper_lut, 1647 val, -1, 1648 sizeof(struct drm_color_lut), 1649 &replaced); 1650 dm_plane_state->base.color_mgmt_changed |= replaced; 1651 return ret; 1652 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1653 if (dm_plane_state->shaper_tf != val) { 1654 dm_plane_state->shaper_tf = val; 1655 dm_plane_state->base.color_mgmt_changed = 1; 1656 } 1657 } else if (property == adev->mode_info.plane_lut3d_property) { 1658 ret = drm_property_replace_blob_from_id(plane->dev, 1659 &dm_plane_state->lut3d, 1660 val, -1, 1661 sizeof(struct drm_color_lut), 1662 &replaced); 1663 dm_plane_state->base.color_mgmt_changed |= replaced; 1664 return ret; 1665 } else if (property == adev->mode_info.plane_blend_lut_property) { 1666 ret = drm_property_replace_blob_from_id(plane->dev, 1667 &dm_plane_state->blend_lut, 1668 val, -1, 1669 sizeof(struct drm_color_lut), 1670 &replaced); 1671 dm_plane_state->base.color_mgmt_changed |= replaced; 1672 return ret; 1673 } else if (property == adev->mode_info.plane_blend_tf_property) { 1674 if (dm_plane_state->blend_tf != val) { 1675 dm_plane_state->blend_tf = val; 1676 dm_plane_state->base.color_mgmt_changed = 1; 1677 } 1678 } else { 1679 drm_dbg_atomic(plane->dev, 1680 "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", 1681 plane->base.id, plane->name, 1682 property->base.id, property->name); 1683 return -EINVAL; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int 1690 dm_atomic_plane_get_property(struct drm_plane *plane, 1691 const struct drm_plane_state *state, 1692 struct drm_property *property, 1693 uint64_t *val) 1694 { 1695 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1696 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1697 1698 if (property == adev->mode_info.plane_degamma_lut_property) { 1699 *val = (dm_plane_state->degamma_lut) ? 1700 dm_plane_state->degamma_lut->base.id : 0; 1701 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1702 *val = dm_plane_state->degamma_tf; 1703 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1704 *val = dm_plane_state->hdr_mult; 1705 } else if (property == adev->mode_info.plane_ctm_property) { 1706 *val = (dm_plane_state->ctm) ? 1707 dm_plane_state->ctm->base.id : 0; 1708 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1709 *val = (dm_plane_state->shaper_lut) ? 1710 dm_plane_state->shaper_lut->base.id : 0; 1711 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1712 *val = dm_plane_state->shaper_tf; 1713 } else if (property == adev->mode_info.plane_lut3d_property) { 1714 *val = (dm_plane_state->lut3d) ? 1715 dm_plane_state->lut3d->base.id : 0; 1716 } else if (property == adev->mode_info.plane_blend_lut_property) { 1717 *val = (dm_plane_state->blend_lut) ? 1718 dm_plane_state->blend_lut->base.id : 0; 1719 } else if (property == adev->mode_info.plane_blend_tf_property) { 1720 *val = dm_plane_state->blend_tf; 1721 1722 } else { 1723 return -EINVAL; 1724 } 1725 1726 return 0; 1727 } 1728 #endif 1729 1730 static const struct drm_plane_funcs dm_plane_funcs = { 1731 .update_plane = drm_atomic_helper_update_plane, 1732 .disable_plane = drm_atomic_helper_disable_plane, 1733 .destroy = drm_plane_helper_destroy, 1734 .reset = amdgpu_dm_plane_drm_plane_reset, 1735 .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, 1736 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, 1737 .format_mod_supported = amdgpu_dm_plane_format_mod_supported, 1738 #ifdef AMD_PRIVATE_COLOR 1739 .atomic_set_property = dm_atomic_plane_set_property, 1740 .atomic_get_property = dm_atomic_plane_get_property, 1741 #endif 1742 }; 1743 1744 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1745 struct drm_plane *plane, 1746 unsigned long possible_crtcs, 1747 const struct dc_plane_cap *plane_cap) 1748 { 1749 uint32_t formats[32]; 1750 int num_formats; 1751 int res = -EPERM; 1752 unsigned int supported_rotations; 1753 uint64_t *modifiers = NULL; 1754 unsigned int primary_zpos = dm->dc->caps.max_slave_planes; 1755 1756 num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, 1757 ARRAY_SIZE(formats)); 1758 1759 res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); 1760 if (res) 1761 return res; 1762 1763 if (modifiers == NULL) 1764 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1765 1766 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1767 &dm_plane_funcs, formats, num_formats, 1768 modifiers, plane->type, NULL); 1769 kfree(modifiers); 1770 if (res) 1771 return res; 1772 1773 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1774 plane_cap && plane_cap->per_pixel_alpha) { 1775 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1776 BIT(DRM_MODE_BLEND_PREMULTI) | 1777 BIT(DRM_MODE_BLEND_COVERAGE); 1778 1779 drm_plane_create_alpha_property(plane); 1780 drm_plane_create_blend_mode_property(plane, blend_caps); 1781 } 1782 1783 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1784 /* 1785 * Allow OVERLAY planes to be used as underlays by assigning an 1786 * immutable zpos = # of OVERLAY planes to the PRIMARY plane. 1787 */ 1788 drm_plane_create_zpos_immutable_property(plane, primary_zpos); 1789 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1790 /* 1791 * OVERLAY planes can be below or above the PRIMARY, but cannot 1792 * be above the CURSOR plane. 1793 */ 1794 unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane); 1795 1796 drm_plane_create_zpos_property(plane, zpos, 0, 254); 1797 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1798 drm_plane_create_zpos_immutable_property(plane, 255); 1799 } 1800 1801 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1802 plane_cap && 1803 (plane_cap->pixel_format_support.nv12 || 1804 plane_cap->pixel_format_support.p010)) { 1805 /* This only affects YUV formats. */ 1806 drm_plane_create_color_properties( 1807 plane, 1808 BIT(DRM_COLOR_YCBCR_BT601) | 1809 BIT(DRM_COLOR_YCBCR_BT709) | 1810 BIT(DRM_COLOR_YCBCR_BT2020), 1811 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1812 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1813 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1814 } 1815 1816 supported_rotations = 1817 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1818 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1819 1820 if (dm->adev->asic_type >= CHIP_BONAIRE && 1821 plane->type != DRM_PLANE_TYPE_CURSOR) 1822 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1823 supported_rotations); 1824 1825 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) > IP_VERSION(3, 0, 1) && 1826 plane->type != DRM_PLANE_TYPE_CURSOR) 1827 drm_plane_enable_fb_damage_clips(plane); 1828 1829 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1830 1831 #ifdef AMD_PRIVATE_COLOR 1832 dm_atomic_plane_attach_color_mgmt_properties(dm, plane); 1833 #endif 1834 /* Create (reset) the plane state */ 1835 if (plane->funcs->reset) 1836 plane->funcs->reset(plane); 1837 1838 return 0; 1839 } 1840 1841 bool amdgpu_dm_plane_is_video_format(uint32_t format) 1842 { 1843 int i; 1844 1845 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1846 if (format == video_formats[i]) 1847 return true; 1848 1849 return false; 1850 } 1851 1852