1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_blend.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_fourcc.h> 32 33 #include "amdgpu.h" 34 #include "dal_asic_id.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_dm_trace.h" 37 #include "amdgpu_dm_plane.h" 38 #include "gc/gc_11_0_0_offset.h" 39 #include "gc/gc_11_0_0_sh_mask.h" 40 41 /* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47 static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62 }; 63 64 static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74 }; 75 76 static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80 }; 81 82 static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84 }; 85 86 enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91 }; 92 93 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94 { 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96 } 97 98 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101 { 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 108 return; 109 110 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 111 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 112 static const uint32_t alpha_formats[] = { 113 DRM_FORMAT_ARGB8888, 114 DRM_FORMAT_RGBA8888, 115 DRM_FORMAT_ABGR8888, 116 DRM_FORMAT_ARGB2101010, 117 DRM_FORMAT_ABGR2101010, 118 DRM_FORMAT_ARGB16161616, 119 DRM_FORMAT_ABGR16161616, 120 DRM_FORMAT_ARGB16161616F, 121 }; 122 uint32_t format = plane_state->fb->format->format; 123 unsigned int i; 124 125 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 126 if (format == alpha_formats[i]) { 127 *per_pixel_alpha = true; 128 break; 129 } 130 } 131 132 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 133 *pre_multiplied_alpha = false; 134 } 135 136 if (plane_state->alpha < 0xffff) { 137 *global_alpha = true; 138 *global_alpha_value = plane_state->alpha >> 8; 139 } 140 } 141 142 static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 143 { 144 if (!*mods) 145 return; 146 147 if (*cap - *size < 1) { 148 uint64_t new_cap = *cap * 2; 149 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 150 151 if (!new_mods) { 152 kfree(*mods); 153 *mods = NULL; 154 return; 155 } 156 157 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 158 kfree(*mods); 159 *mods = new_mods; 160 *cap = new_cap; 161 } 162 163 (*mods)[*size] = mod; 164 *size += 1; 165 } 166 167 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) 168 { 169 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 170 } 171 172 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) 173 { 174 if (modifier == DRM_FORMAT_MOD_LINEAR) 175 return 0; 176 177 return AMD_FMT_MOD_GET(TILE, modifier); 178 } 179 180 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 181 uint64_t tiling_flags) 182 { 183 /* Fill GFX8 params */ 184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 186 187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 192 193 /* XXX fix me for VI */ 194 tiling_info->gfx8.num_banks = num_banks; 195 tiling_info->gfx8.array_mode = 196 DC_ARRAY_2D_TILED_THIN1; 197 tiling_info->gfx8.tile_split = tile_split; 198 tiling_info->gfx8.bank_width = bankw; 199 tiling_info->gfx8.bank_height = bankh; 200 tiling_info->gfx8.tile_aspect = mtaspect; 201 tiling_info->gfx8.tile_mode = 202 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 204 == DC_ARRAY_1D_TILED_THIN1) { 205 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 206 } 207 208 tiling_info->gfx8.pipe_config = 209 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 210 } 211 212 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 213 union dc_tiling_info *tiling_info) 214 { 215 /* Fill GFX9 params */ 216 tiling_info->gfx9.num_pipes = 217 adev->gfx.config.gb_addr_config_fields.num_pipes; 218 tiling_info->gfx9.num_banks = 219 adev->gfx.config.gb_addr_config_fields.num_banks; 220 tiling_info->gfx9.pipe_interleave = 221 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 222 tiling_info->gfx9.num_shader_engines = 223 adev->gfx.config.gb_addr_config_fields.num_se; 224 tiling_info->gfx9.max_compressed_frags = 225 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 226 tiling_info->gfx9.num_rb_per_se = 227 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 228 tiling_info->gfx9.shaderEnable = 1; 229 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 230 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 231 } 232 233 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 234 union dc_tiling_info *tiling_info, 235 uint64_t modifier) 236 { 237 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 238 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 239 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 240 unsigned int pipes_log2; 241 242 pipes_log2 = min(5u, mod_pipe_xor_bits); 243 244 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); 245 246 if (!IS_AMD_FMT_MOD(modifier)) 247 return; 248 249 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 250 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 251 252 if (adev->family >= AMDGPU_FAMILY_NV) { 253 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 254 } else { 255 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 256 257 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 258 } 259 } 260 261 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, 262 const enum surface_pixel_format format, 263 const enum dc_rotation_angle rotation, 264 const union dc_tiling_info *tiling_info, 265 const struct dc_plane_dcc_param *dcc, 266 const struct dc_plane_address *address, 267 const struct plane_size *plane_size) 268 { 269 struct dc *dc = adev->dm.dc; 270 struct dc_dcc_surface_param input; 271 struct dc_surface_dcc_cap output; 272 273 memset(&input, 0, sizeof(input)); 274 memset(&output, 0, sizeof(output)); 275 276 if (!dcc->enable) 277 return 0; 278 279 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 280 !dc->cap_funcs.get_dcc_compression_cap) 281 return -EINVAL; 282 283 input.format = format; 284 input.surface_size.width = plane_size->surface_size.width; 285 input.surface_size.height = plane_size->surface_size.height; 286 input.swizzle_mode = tiling_info->gfx9.swizzle; 287 288 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 289 input.scan = SCAN_DIRECTION_HORIZONTAL; 290 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 291 input.scan = SCAN_DIRECTION_VERTICAL; 292 293 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 294 return -EINVAL; 295 296 if (!output.capable) 297 return -EINVAL; 298 299 if (dcc->independent_64b_blks == 0 && 300 output.grph.rgb.independent_64b_blks != 0) 301 return -EINVAL; 302 303 return 0; 304 } 305 306 static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 307 const struct amdgpu_framebuffer *afb, 308 const enum surface_pixel_format format, 309 const enum dc_rotation_angle rotation, 310 const struct plane_size *plane_size, 311 union dc_tiling_info *tiling_info, 312 struct dc_plane_dcc_param *dcc, 313 struct dc_plane_address *address, 314 const bool force_disable_dcc) 315 { 316 const uint64_t modifier = afb->base.modifier; 317 int ret = 0; 318 319 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 320 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); 321 322 if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) { 323 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 324 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 325 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 326 327 dcc->enable = 1; 328 dcc->meta_pitch = afb->base.pitches[1]; 329 dcc->independent_64b_blks = independent_64b_blks; 330 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 331 if (independent_64b_blks && independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 333 else if (independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_128b; 335 else if (independent_64b_blks && !independent_128b_blks) 336 dcc->dcc_ind_blk = hubp_ind_block_64b; 337 else 338 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 339 } else { 340 if (independent_64b_blks) 341 dcc->dcc_ind_blk = hubp_ind_block_64b; 342 else 343 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 344 } 345 346 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 347 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 348 } 349 350 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 351 if (ret) 352 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret); 353 354 return ret; 355 } 356 357 static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev, 358 uint64_t **mods, 359 uint64_t *size, 360 uint64_t *capacity) 361 { 362 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 363 364 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 365 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 366 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 367 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 368 AMD_FMT_MOD_SET(DCC, 1) | 369 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 370 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 371 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 372 373 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 374 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 375 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 376 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 377 AMD_FMT_MOD_SET(DCC, 1) | 378 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 379 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 380 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 381 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 382 383 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 384 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 385 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 386 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 387 388 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 389 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 390 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 391 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 392 393 394 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 395 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 396 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 397 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 398 399 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 400 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 401 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 402 } 403 404 static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev, 405 uint64_t **mods, 406 uint64_t *size, 407 uint64_t *capacity) 408 { 409 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 410 int pipe_xor_bits = min(8, pipes + 411 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 412 int bank_xor_bits = min(8 - pipe_xor_bits, 413 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 414 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 415 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 416 417 418 if (adev->family == AMDGPU_FAMILY_RV) { 419 /* Raven2 and later */ 420 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 421 422 /* 423 * No _D DCC swizzles yet because we only allow 32bpp, which 424 * doesn't support _D on DCN 425 */ 426 427 if (has_constant_encode) { 428 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 429 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 430 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 431 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 432 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 433 AMD_FMT_MOD_SET(DCC, 1) | 434 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 435 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 436 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 437 } 438 439 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 440 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 441 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 442 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 443 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 444 AMD_FMT_MOD_SET(DCC, 1) | 445 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 446 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 447 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 448 449 if (has_constant_encode) { 450 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 451 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 452 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 453 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 454 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 455 AMD_FMT_MOD_SET(DCC, 1) | 456 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 457 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 458 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 459 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 460 AMD_FMT_MOD_SET(RB, rb) | 461 AMD_FMT_MOD_SET(PIPE, pipes)); 462 } 463 464 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 465 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 466 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 467 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 468 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 469 AMD_FMT_MOD_SET(DCC, 1) | 470 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 471 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 472 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 473 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 474 AMD_FMT_MOD_SET(RB, rb) | 475 AMD_FMT_MOD_SET(PIPE, pipes)); 476 } 477 478 /* 479 * Only supported for 64bpp on Raven, will be filtered on format in 480 * amdgpu_dm_plane_format_mod_supported. 481 */ 482 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 483 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 484 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 485 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 486 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 487 488 if (adev->family == AMDGPU_FAMILY_RV) { 489 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 490 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 491 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 492 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 493 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 494 } 495 496 /* 497 * Only supported for 64bpp on Raven, will be filtered on format in 498 * amdgpu_dm_plane_format_mod_supported. 499 */ 500 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 501 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 502 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 503 504 if (adev->family == AMDGPU_FAMILY_RV) { 505 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 506 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 507 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 508 } 509 } 510 511 static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev, 512 uint64_t **mods, 513 uint64_t *size, 514 uint64_t *capacity) 515 { 516 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 517 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 518 519 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 520 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 521 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 522 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 523 AMD_FMT_MOD_SET(PACKERS, pkrs) | 524 AMD_FMT_MOD_SET(DCC, 1) | 525 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 526 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 527 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 528 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 529 530 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 531 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 532 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 533 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 534 AMD_FMT_MOD_SET(PACKERS, pkrs) | 535 AMD_FMT_MOD_SET(DCC, 1) | 536 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 537 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 538 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 539 540 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 541 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 542 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 543 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 544 AMD_FMT_MOD_SET(PACKERS, pkrs) | 545 AMD_FMT_MOD_SET(DCC, 1) | 546 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 547 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 548 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 549 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 550 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 551 552 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 553 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 554 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 555 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 556 AMD_FMT_MOD_SET(PACKERS, pkrs) | 557 AMD_FMT_MOD_SET(DCC, 1) | 558 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 559 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 560 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 561 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 562 563 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 564 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 565 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 566 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 567 AMD_FMT_MOD_SET(PACKERS, pkrs)); 568 569 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 570 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 571 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 572 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 573 AMD_FMT_MOD_SET(PACKERS, pkrs)); 574 575 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */ 576 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 577 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 578 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 579 580 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 581 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 582 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 583 } 584 585 static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev, 586 uint64_t **mods, uint64_t *size, uint64_t *capacity) 587 { 588 int num_pipes = 0; 589 int pipe_xor_bits = 0; 590 int num_pkrs = 0; 591 int pkrs = 0; 592 u32 gb_addr_config; 593 u8 i = 0; 594 unsigned int swizzle_r_x; 595 uint64_t modifier_r_x; 596 uint64_t modifier_dcc_best; 597 uint64_t modifier_dcc_4k; 598 599 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 600 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 601 */ 602 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 603 ASSERT(gb_addr_config != 0); 604 605 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 606 pkrs = ilog2(num_pkrs); 607 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 608 pipe_xor_bits = ilog2(num_pipes); 609 610 for (i = 0; i < 2; i++) { 611 /* Insert the best one first. */ 612 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 613 if (num_pipes > 16) 614 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 615 else 616 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 617 618 modifier_r_x = AMD_FMT_MOD | 619 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 620 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 621 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 622 AMD_FMT_MOD_SET(PACKERS, pkrs); 623 624 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 625 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 626 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 627 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 628 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 629 630 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 631 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 632 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 633 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 634 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 635 636 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best); 637 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k); 638 639 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 640 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 641 642 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x); 643 } 644 645 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD | 646 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 647 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 648 } 649 650 static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, 651 uint64_t **mods, uint64_t *size, uint64_t *capacity) 652 { 653 uint64_t mod_64K_2D = AMD_FMT_MOD | 654 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) | 655 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D); 656 657 /* 64K without DCC */ 658 amdgpu_dm_plane_add_modifier(mods, size, capacity, mod_64K_2D); 659 amdgpu_dm_plane_add_modifier(mods, size, capacity, DRM_FORMAT_MOD_LINEAR); 660 } 661 662 static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 663 { 664 uint64_t size = 0, capacity = 128; 665 *mods = NULL; 666 667 /* We have not hooked up any pre-GFX9 modifiers. */ 668 if (adev->family < AMDGPU_FAMILY_AI) 669 return 0; 670 671 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 672 673 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 674 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 675 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 676 return *mods ? 0 : -ENOMEM; 677 } 678 679 switch (adev->family) { 680 case AMDGPU_FAMILY_AI: 681 case AMDGPU_FAMILY_RV: 682 amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity); 683 break; 684 case AMDGPU_FAMILY_NV: 685 case AMDGPU_FAMILY_VGH: 686 case AMDGPU_FAMILY_YC: 687 case AMDGPU_FAMILY_GC_10_3_6: 688 case AMDGPU_FAMILY_GC_10_3_7: 689 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 690 amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity); 691 else 692 amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity); 693 break; 694 case AMDGPU_FAMILY_GC_11_0_0: 695 case AMDGPU_FAMILY_GC_11_0_1: 696 case AMDGPU_FAMILY_GC_11_5_0: 697 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); 698 break; 699 case AMDGPU_FAMILY_GC_12_0_0: 700 amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity); 701 break; 702 } 703 704 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 705 706 /* INVALID marks the end of the list. */ 707 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 708 709 if (!*mods) 710 return -ENOMEM; 711 712 return 0; 713 } 714 715 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, 716 const struct dc_plane_cap *plane_cap, 717 uint32_t *formats, int max_formats) 718 { 719 int i, num_formats = 0; 720 721 /* 722 * TODO: Query support for each group of formats directly from 723 * DC plane caps. This will require adding more formats to the 724 * caps list. 725 */ 726 727 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 728 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 729 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 730 if (num_formats >= max_formats) 731 break; 732 733 formats[num_formats++] = rgb_formats[i]; 734 } 735 736 if (plane_cap && plane_cap->pixel_format_support.nv12) 737 formats[num_formats++] = DRM_FORMAT_NV12; 738 if (plane_cap && plane_cap->pixel_format_support.p010) 739 formats[num_formats++] = DRM_FORMAT_P010; 740 if (plane_cap && plane_cap->pixel_format_support.fp16) { 741 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 742 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 743 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 744 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 745 } 746 } else { 747 switch (plane->type) { 748 case DRM_PLANE_TYPE_OVERLAY: 749 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 750 if (num_formats >= max_formats) 751 break; 752 753 formats[num_formats++] = overlay_formats[i]; 754 } 755 break; 756 757 case DRM_PLANE_TYPE_CURSOR: 758 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 759 if (num_formats >= max_formats) 760 break; 761 762 formats[num_formats++] = cursor_formats[i]; 763 } 764 break; 765 766 default: 767 break; 768 } 769 } 770 771 return num_formats; 772 } 773 774 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 775 const struct amdgpu_framebuffer *afb, 776 const enum surface_pixel_format format, 777 const enum dc_rotation_angle rotation, 778 const uint64_t tiling_flags, 779 union dc_tiling_info *tiling_info, 780 struct plane_size *plane_size, 781 struct dc_plane_dcc_param *dcc, 782 struct dc_plane_address *address, 783 bool tmz_surface, 784 bool force_disable_dcc) 785 { 786 const struct drm_framebuffer *fb = &afb->base; 787 int ret; 788 789 memset(tiling_info, 0, sizeof(*tiling_info)); 790 memset(plane_size, 0, sizeof(*plane_size)); 791 memset(dcc, 0, sizeof(*dcc)); 792 memset(address, 0, sizeof(*address)); 793 794 address->tmz_surface = tmz_surface; 795 796 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 797 uint64_t addr = afb->address + fb->offsets[0]; 798 799 plane_size->surface_size.x = 0; 800 plane_size->surface_size.y = 0; 801 plane_size->surface_size.width = fb->width; 802 plane_size->surface_size.height = fb->height; 803 plane_size->surface_pitch = 804 fb->pitches[0] / fb->format->cpp[0]; 805 806 address->type = PLN_ADDR_TYPE_GRAPHICS; 807 address->grph.addr.low_part = lower_32_bits(addr); 808 address->grph.addr.high_part = upper_32_bits(addr); 809 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 810 uint64_t luma_addr = afb->address + fb->offsets[0]; 811 uint64_t chroma_addr = afb->address + fb->offsets[1]; 812 813 plane_size->surface_size.x = 0; 814 plane_size->surface_size.y = 0; 815 plane_size->surface_size.width = fb->width; 816 plane_size->surface_size.height = fb->height; 817 plane_size->surface_pitch = 818 fb->pitches[0] / fb->format->cpp[0]; 819 820 plane_size->chroma_size.x = 0; 821 plane_size->chroma_size.y = 0; 822 /* TODO: set these based on surface format */ 823 plane_size->chroma_size.width = fb->width / 2; 824 plane_size->chroma_size.height = fb->height / 2; 825 826 plane_size->chroma_pitch = 827 fb->pitches[1] / fb->format->cpp[1]; 828 829 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 830 address->video_progressive.luma_addr.low_part = 831 lower_32_bits(luma_addr); 832 address->video_progressive.luma_addr.high_part = 833 upper_32_bits(luma_addr); 834 address->video_progressive.chroma_addr.low_part = 835 lower_32_bits(chroma_addr); 836 address->video_progressive.chroma_addr.high_part = 837 upper_32_bits(chroma_addr); 838 } 839 840 if (adev->family >= AMDGPU_FAMILY_AI) { 841 ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 842 rotation, plane_size, 843 tiling_info, dcc, 844 address, 845 force_disable_dcc); 846 if (ret) 847 return ret; 848 } else { 849 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 850 } 851 852 return 0; 853 } 854 855 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, 856 struct drm_plane_state *new_state) 857 { 858 struct amdgpu_framebuffer *afb; 859 struct drm_gem_object *obj; 860 struct amdgpu_device *adev; 861 struct amdgpu_bo *rbo; 862 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 863 uint32_t domain; 864 int r; 865 866 if (!new_state->fb) { 867 DRM_DEBUG_KMS("No FB bound\n"); 868 return 0; 869 } 870 871 afb = to_amdgpu_framebuffer(new_state->fb); 872 obj = new_state->fb->obj[0]; 873 rbo = gem_to_amdgpu_bo(obj); 874 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 875 876 r = amdgpu_bo_reserve(rbo, true); 877 if (r) { 878 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 879 return r; 880 } 881 882 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 883 if (r) { 884 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 885 goto error_unlock; 886 } 887 888 if (plane->type != DRM_PLANE_TYPE_CURSOR) 889 domain = amdgpu_display_supported_domains(adev, rbo->flags); 890 else 891 domain = AMDGPU_GEM_DOMAIN_VRAM; 892 893 r = amdgpu_bo_pin(rbo, domain); 894 if (unlikely(r != 0)) { 895 if (r != -ERESTARTSYS) 896 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 897 goto error_unlock; 898 } 899 900 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 901 if (unlikely(r != 0)) { 902 DRM_ERROR("%p bind failed\n", rbo); 903 goto error_unpin; 904 } 905 906 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 907 if (unlikely(r != 0)) 908 goto error_unpin; 909 910 amdgpu_bo_unreserve(rbo); 911 912 afb->address = amdgpu_bo_gpu_offset(rbo); 913 914 amdgpu_bo_ref(rbo); 915 916 /** 917 * We don't do surface updates on planes that have been newly created, 918 * but we also don't have the afb->address during atomic check. 919 * 920 * Fill in buffer attributes depending on the address here, but only on 921 * newly created planes since they're not being used by DC yet and this 922 * won't modify global state. 923 */ 924 dm_plane_state_old = to_dm_plane_state(plane->state); 925 dm_plane_state_new = to_dm_plane_state(new_state); 926 927 if (dm_plane_state_new->dc_state && 928 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 929 struct dc_plane_state *plane_state = 930 dm_plane_state_new->dc_state; 931 bool force_disable_dcc = !plane_state->dcc.enable; 932 933 amdgpu_dm_plane_fill_plane_buffer_attributes( 934 adev, afb, plane_state->format, plane_state->rotation, 935 afb->tiling_flags, 936 &plane_state->tiling_info, &plane_state->plane_size, 937 &plane_state->dcc, &plane_state->address, 938 afb->tmz_surface, force_disable_dcc); 939 } 940 941 return 0; 942 943 error_unpin: 944 amdgpu_bo_unpin(rbo); 945 946 error_unlock: 947 amdgpu_bo_unreserve(rbo); 948 return r; 949 } 950 951 static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, 952 struct drm_plane_state *old_state) 953 { 954 struct amdgpu_bo *rbo; 955 int r; 956 957 if (!old_state->fb) 958 return; 959 960 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 961 r = amdgpu_bo_reserve(rbo, false); 962 if (unlikely(r)) { 963 DRM_ERROR("failed to reserve rbo before unpin\n"); 964 return; 965 } 966 967 amdgpu_bo_unpin(rbo); 968 amdgpu_bo_unreserve(rbo); 969 amdgpu_bo_unref(&rbo); 970 } 971 972 static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, 973 struct drm_framebuffer *fb, 974 int *min_downscale, int *max_upscale) 975 { 976 struct amdgpu_device *adev = drm_to_adev(dev); 977 struct dc *dc = adev->dm.dc; 978 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 979 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 980 981 switch (fb->format->format) { 982 case DRM_FORMAT_P010: 983 case DRM_FORMAT_NV12: 984 case DRM_FORMAT_NV21: 985 *max_upscale = plane_cap->max_upscale_factor.nv12; 986 *min_downscale = plane_cap->max_downscale_factor.nv12; 987 break; 988 989 case DRM_FORMAT_XRGB16161616F: 990 case DRM_FORMAT_ARGB16161616F: 991 case DRM_FORMAT_XBGR16161616F: 992 case DRM_FORMAT_ABGR16161616F: 993 *max_upscale = plane_cap->max_upscale_factor.fp16; 994 *min_downscale = plane_cap->max_downscale_factor.fp16; 995 break; 996 997 default: 998 *max_upscale = plane_cap->max_upscale_factor.argb8888; 999 *min_downscale = plane_cap->max_downscale_factor.argb8888; 1000 break; 1001 } 1002 1003 /* 1004 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 1005 * scaling factor of 1.0 == 1000 units. 1006 */ 1007 if (*max_upscale == 1) 1008 *max_upscale = 1000; 1009 1010 if (*min_downscale == 1) 1011 *min_downscale = 1000; 1012 } 1013 1014 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 1015 struct drm_crtc_state *new_crtc_state) 1016 { 1017 struct drm_framebuffer *fb = state->fb; 1018 int min_downscale, max_upscale; 1019 int min_scale = 0; 1020 int max_scale = INT_MAX; 1021 1022 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1023 if (fb && state->crtc) { 1024 /* Validate viewport to cover the case when only the position changes */ 1025 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1026 int viewport_width = state->crtc_w; 1027 int viewport_height = state->crtc_h; 1028 1029 if (state->crtc_x < 0) 1030 viewport_width += state->crtc_x; 1031 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1032 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1033 1034 if (state->crtc_y < 0) 1035 viewport_height += state->crtc_y; 1036 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1037 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1038 1039 if (viewport_width < 0 || viewport_height < 0) { 1040 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1041 return -EINVAL; 1042 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1043 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1044 return -EINVAL; 1045 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1046 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1047 return -EINVAL; 1048 } 1049 1050 } 1051 1052 /* Get min/max allowed scaling factors from plane caps. */ 1053 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1054 &min_downscale, &max_upscale); 1055 /* 1056 * Convert to drm convention: 16.16 fixed point, instead of dc's 1057 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1058 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1059 */ 1060 min_scale = (1000 << 16) / max_upscale; 1061 max_scale = (1000 << 16) / min_downscale; 1062 } 1063 1064 return drm_atomic_helper_check_plane_state( 1065 state, new_crtc_state, min_scale, max_scale, true, true); 1066 } 1067 1068 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1069 const struct drm_plane_state *state, 1070 struct dc_scaling_info *scaling_info) 1071 { 1072 int scale_w, scale_h, min_downscale, max_upscale; 1073 1074 memset(scaling_info, 0, sizeof(*scaling_info)); 1075 1076 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1077 scaling_info->src_rect.x = state->src_x >> 16; 1078 scaling_info->src_rect.y = state->src_y >> 16; 1079 1080 /* 1081 * For reasons we don't (yet) fully understand a non-zero 1082 * src_y coordinate into an NV12 buffer can cause a 1083 * system hang on DCN1x. 1084 * To avoid hangs (and maybe be overly cautious) 1085 * let's reject both non-zero src_x and src_y. 1086 * 1087 * We currently know of only one use-case to reproduce a 1088 * scenario with non-zero src_x and src_y for NV12, which 1089 * is to gesture the YouTube Android app into full screen 1090 * on ChromeOS. 1091 */ 1092 if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1093 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && 1094 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1095 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1096 return -EINVAL; 1097 1098 scaling_info->src_rect.width = state->src_w >> 16; 1099 if (scaling_info->src_rect.width == 0) 1100 return -EINVAL; 1101 1102 scaling_info->src_rect.height = state->src_h >> 16; 1103 if (scaling_info->src_rect.height == 0) 1104 return -EINVAL; 1105 1106 scaling_info->dst_rect.x = state->crtc_x; 1107 scaling_info->dst_rect.y = state->crtc_y; 1108 1109 if (state->crtc_w == 0) 1110 return -EINVAL; 1111 1112 scaling_info->dst_rect.width = state->crtc_w; 1113 1114 if (state->crtc_h == 0) 1115 return -EINVAL; 1116 1117 scaling_info->dst_rect.height = state->crtc_h; 1118 1119 /* DRM doesn't specify clipping on destination output. */ 1120 scaling_info->clip_rect = scaling_info->dst_rect; 1121 1122 /* Validate scaling per-format with DC plane caps */ 1123 if (state->plane && state->plane->dev && state->fb) { 1124 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1125 &min_downscale, &max_upscale); 1126 } else { 1127 min_downscale = 250; 1128 max_upscale = 16000; 1129 } 1130 1131 scale_w = scaling_info->dst_rect.width * 1000 / 1132 scaling_info->src_rect.width; 1133 1134 if (scale_w < min_downscale || scale_w > max_upscale) 1135 return -EINVAL; 1136 1137 scale_h = scaling_info->dst_rect.height * 1000 / 1138 scaling_info->src_rect.height; 1139 1140 if (scale_h < min_downscale || scale_h > max_upscale) 1141 return -EINVAL; 1142 1143 /* 1144 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1145 * assume reasonable defaults based on the format. 1146 */ 1147 1148 return 0; 1149 } 1150 1151 static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, 1152 struct drm_atomic_state *state) 1153 { 1154 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1155 plane); 1156 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1157 struct dc *dc = adev->dm.dc; 1158 struct dm_plane_state *dm_plane_state; 1159 struct dc_scaling_info scaling_info; 1160 struct drm_crtc_state *new_crtc_state; 1161 int ret; 1162 1163 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1164 1165 dm_plane_state = to_dm_plane_state(new_plane_state); 1166 1167 if (!dm_plane_state->dc_state) 1168 return 0; 1169 1170 new_crtc_state = 1171 drm_atomic_get_new_crtc_state(state, 1172 new_plane_state->crtc); 1173 if (!new_crtc_state) 1174 return -EINVAL; 1175 1176 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1177 if (ret) 1178 return ret; 1179 1180 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1181 if (ret) 1182 return ret; 1183 1184 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1185 return 0; 1186 1187 return -EINVAL; 1188 } 1189 1190 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, 1191 struct drm_atomic_state *state) 1192 { 1193 /* Only support async updates on cursor planes. */ 1194 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1195 return -EINVAL; 1196 1197 return 0; 1198 } 1199 1200 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1201 struct dc_cursor_position *position) 1202 { 1203 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1204 int x, y; 1205 int xorigin = 0, yorigin = 0; 1206 1207 if (!crtc || !plane->state->fb) 1208 return 0; 1209 1210 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1211 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1212 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1213 __func__, 1214 plane->state->crtc_w, 1215 plane->state->crtc_h); 1216 return -EINVAL; 1217 } 1218 1219 x = plane->state->crtc_x; 1220 y = plane->state->crtc_y; 1221 1222 if (x <= -amdgpu_crtc->max_cursor_width || 1223 y <= -amdgpu_crtc->max_cursor_height) 1224 return 0; 1225 1226 if (x < 0) { 1227 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1228 x = 0; 1229 } 1230 if (y < 0) { 1231 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1232 y = 0; 1233 } 1234 position->enable = true; 1235 position->translate_by_source = true; 1236 position->x = x; 1237 position->y = y; 1238 position->x_hotspot = xorigin; 1239 position->y_hotspot = yorigin; 1240 1241 return 0; 1242 } 1243 1244 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1245 struct drm_plane_state *old_plane_state) 1246 { 1247 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1248 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1249 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1250 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1251 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1252 uint64_t address = afb ? afb->address : 0; 1253 struct dc_cursor_position position = {0}; 1254 struct dc_cursor_attributes attributes; 1255 int ret; 1256 1257 if (!plane->state->fb && !old_plane_state->fb) 1258 return; 1259 1260 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 1261 amdgpu_crtc->crtc_id, plane->state->crtc_w, 1262 plane->state->crtc_h); 1263 1264 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 1265 if (ret) 1266 return; 1267 1268 if (!position.enable) { 1269 /* turn off cursor */ 1270 if (crtc_state && crtc_state->stream) { 1271 mutex_lock(&adev->dm.dc_lock); 1272 dc_stream_program_cursor_position(crtc_state->stream, 1273 &position); 1274 mutex_unlock(&adev->dm.dc_lock); 1275 } 1276 return; 1277 } 1278 1279 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1280 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1281 1282 memset(&attributes, 0, sizeof(attributes)); 1283 attributes.address.high_part = upper_32_bits(address); 1284 attributes.address.low_part = lower_32_bits(address); 1285 attributes.width = plane->state->crtc_w; 1286 attributes.height = plane->state->crtc_h; 1287 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1288 attributes.rotation_angle = 0; 1289 attributes.attribute_flags.value = 0; 1290 1291 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 1292 * legacy gamma setup. 1293 */ 1294 if (crtc_state->cm_is_degamma_srgb && 1295 adev->dm.dc->caps.color.dpp.gamma_corr) 1296 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 1297 1298 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1299 1300 if (crtc_state->stream) { 1301 mutex_lock(&adev->dm.dc_lock); 1302 if (!dc_stream_program_cursor_attributes(crtc_state->stream, 1303 &attributes)) 1304 DRM_ERROR("DC failed to set cursor attributes\n"); 1305 1306 if (!dc_stream_program_cursor_position(crtc_state->stream, 1307 &position)) 1308 DRM_ERROR("DC failed to set cursor position\n"); 1309 mutex_unlock(&adev->dm.dc_lock); 1310 } 1311 } 1312 1313 static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, 1314 struct drm_atomic_state *state) 1315 { 1316 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1317 plane); 1318 struct drm_plane_state *old_state = 1319 drm_atomic_get_old_plane_state(state, plane); 1320 1321 trace_amdgpu_dm_atomic_update_cursor(new_state); 1322 1323 swap(plane->state->fb, new_state->fb); 1324 1325 plane->state->src_x = new_state->src_x; 1326 plane->state->src_y = new_state->src_y; 1327 plane->state->src_w = new_state->src_w; 1328 plane->state->src_h = new_state->src_h; 1329 plane->state->crtc_x = new_state->crtc_x; 1330 plane->state->crtc_y = new_state->crtc_y; 1331 plane->state->crtc_w = new_state->crtc_w; 1332 plane->state->crtc_h = new_state->crtc_h; 1333 1334 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1335 } 1336 1337 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1338 .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, 1339 .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, 1340 .atomic_check = amdgpu_dm_plane_atomic_check, 1341 .atomic_async_check = amdgpu_dm_plane_atomic_async_check, 1342 .atomic_async_update = amdgpu_dm_plane_atomic_async_update 1343 }; 1344 1345 static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) 1346 { 1347 struct dm_plane_state *amdgpu_state = NULL; 1348 1349 if (plane->state) 1350 plane->funcs->atomic_destroy_state(plane, plane->state); 1351 1352 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1353 WARN_ON(amdgpu_state == NULL); 1354 1355 if (!amdgpu_state) 1356 return; 1357 1358 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1359 amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1360 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT; 1361 amdgpu_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1362 amdgpu_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; 1363 } 1364 1365 static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane) 1366 { 1367 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1368 1369 old_dm_plane_state = to_dm_plane_state(plane->state); 1370 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1371 if (!dm_plane_state) 1372 return NULL; 1373 1374 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1375 1376 if (old_dm_plane_state->dc_state) { 1377 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1378 dc_plane_state_retain(dm_plane_state->dc_state); 1379 } 1380 1381 if (old_dm_plane_state->degamma_lut) 1382 dm_plane_state->degamma_lut = 1383 drm_property_blob_get(old_dm_plane_state->degamma_lut); 1384 if (old_dm_plane_state->ctm) 1385 dm_plane_state->ctm = 1386 drm_property_blob_get(old_dm_plane_state->ctm); 1387 if (old_dm_plane_state->shaper_lut) 1388 dm_plane_state->shaper_lut = 1389 drm_property_blob_get(old_dm_plane_state->shaper_lut); 1390 if (old_dm_plane_state->lut3d) 1391 dm_plane_state->lut3d = 1392 drm_property_blob_get(old_dm_plane_state->lut3d); 1393 if (old_dm_plane_state->blend_lut) 1394 dm_plane_state->blend_lut = 1395 drm_property_blob_get(old_dm_plane_state->blend_lut); 1396 1397 dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf; 1398 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult; 1399 dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf; 1400 dm_plane_state->blend_tf = old_dm_plane_state->blend_tf; 1401 1402 return &dm_plane_state->base; 1403 } 1404 1405 static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, 1406 uint32_t format, 1407 uint64_t modifier) 1408 { 1409 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1410 const struct drm_format_info *info = drm_format_info(format); 1411 int i; 1412 1413 enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3; 1414 1415 if (!info) 1416 return false; 1417 1418 /* 1419 * We always have to allow these modifiers: 1420 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1421 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1422 */ 1423 if (modifier == DRM_FORMAT_MOD_LINEAR || 1424 modifier == DRM_FORMAT_MOD_INVALID) { 1425 return true; 1426 } 1427 1428 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1429 for (i = 0; i < plane->modifier_count; i++) { 1430 if (modifier == plane->modifiers[i]) 1431 break; 1432 } 1433 if (i == plane->modifier_count) 1434 return false; 1435 1436 /* 1437 * For D swizzle the canonical modifier depends on the bpp, so check 1438 * it here. 1439 */ 1440 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1441 adev->family >= AMDGPU_FAMILY_NV) { 1442 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1443 return false; 1444 } 1445 1446 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1447 info->cpp[0] < 8) 1448 return false; 1449 1450 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) { 1451 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1452 if (info->cpp[0] != 4) 1453 return false; 1454 /* We support multi-planar formats, but not when combined with 1455 * additional DCC metadata planes. 1456 */ 1457 if (info->num_planes > 1) 1458 return false; 1459 } 1460 1461 return true; 1462 } 1463 1464 static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, 1465 struct drm_plane_state *state) 1466 { 1467 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1468 1469 if (dm_plane_state->degamma_lut) 1470 drm_property_blob_put(dm_plane_state->degamma_lut); 1471 if (dm_plane_state->ctm) 1472 drm_property_blob_put(dm_plane_state->ctm); 1473 if (dm_plane_state->lut3d) 1474 drm_property_blob_put(dm_plane_state->lut3d); 1475 if (dm_plane_state->shaper_lut) 1476 drm_property_blob_put(dm_plane_state->shaper_lut); 1477 if (dm_plane_state->blend_lut) 1478 drm_property_blob_put(dm_plane_state->blend_lut); 1479 1480 if (dm_plane_state->dc_state) 1481 dc_plane_state_release(dm_plane_state->dc_state); 1482 1483 drm_atomic_helper_plane_destroy_state(plane, state); 1484 } 1485 1486 #ifdef AMD_PRIVATE_COLOR 1487 static void 1488 dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, 1489 struct drm_plane *plane) 1490 { 1491 struct amdgpu_mode_info mode_info = dm->adev->mode_info; 1492 struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp; 1493 1494 /* Check HW color pipeline capabilities on DPP block (pre-blending) 1495 * before exposing related properties. 1496 */ 1497 if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) { 1498 drm_object_attach_property(&plane->base, 1499 mode_info.plane_degamma_lut_property, 1500 0); 1501 drm_object_attach_property(&plane->base, 1502 mode_info.plane_degamma_lut_size_property, 1503 MAX_COLOR_LUT_ENTRIES); 1504 drm_object_attach_property(&plane->base, 1505 dm->adev->mode_info.plane_degamma_tf_property, 1506 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1507 } 1508 /* HDR MULT is always available */ 1509 drm_object_attach_property(&plane->base, 1510 dm->adev->mode_info.plane_hdr_mult_property, 1511 AMDGPU_HDR_MULT_DEFAULT); 1512 1513 /* Only enable plane CTM if both DPP and MPC gamut remap is available. */ 1514 if (dm->dc->caps.color.mpc.gamut_remap) 1515 drm_object_attach_property(&plane->base, 1516 dm->adev->mode_info.plane_ctm_property, 0); 1517 1518 if (dpp_color_caps.hw_3d_lut) { 1519 drm_object_attach_property(&plane->base, 1520 mode_info.plane_shaper_lut_property, 0); 1521 drm_object_attach_property(&plane->base, 1522 mode_info.plane_shaper_lut_size_property, 1523 MAX_COLOR_LUT_ENTRIES); 1524 drm_object_attach_property(&plane->base, 1525 mode_info.plane_shaper_tf_property, 1526 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1527 drm_object_attach_property(&plane->base, 1528 mode_info.plane_lut3d_property, 0); 1529 drm_object_attach_property(&plane->base, 1530 mode_info.plane_lut3d_size_property, 1531 MAX_COLOR_3DLUT_SIZE); 1532 } 1533 1534 if (dpp_color_caps.ogam_ram) { 1535 drm_object_attach_property(&plane->base, 1536 mode_info.plane_blend_lut_property, 0); 1537 drm_object_attach_property(&plane->base, 1538 mode_info.plane_blend_lut_size_property, 1539 MAX_COLOR_LUT_ENTRIES); 1540 drm_object_attach_property(&plane->base, 1541 mode_info.plane_blend_tf_property, 1542 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 1543 } 1544 } 1545 1546 static int 1547 dm_atomic_plane_set_property(struct drm_plane *plane, 1548 struct drm_plane_state *state, 1549 struct drm_property *property, 1550 uint64_t val) 1551 { 1552 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1553 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1554 bool replaced = false; 1555 int ret; 1556 1557 if (property == adev->mode_info.plane_degamma_lut_property) { 1558 ret = drm_property_replace_blob_from_id(plane->dev, 1559 &dm_plane_state->degamma_lut, 1560 val, -1, 1561 sizeof(struct drm_color_lut), 1562 &replaced); 1563 dm_plane_state->base.color_mgmt_changed |= replaced; 1564 return ret; 1565 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1566 if (dm_plane_state->degamma_tf != val) { 1567 dm_plane_state->degamma_tf = val; 1568 dm_plane_state->base.color_mgmt_changed = 1; 1569 } 1570 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1571 if (dm_plane_state->hdr_mult != val) { 1572 dm_plane_state->hdr_mult = val; 1573 dm_plane_state->base.color_mgmt_changed = 1; 1574 } 1575 } else if (property == adev->mode_info.plane_ctm_property) { 1576 ret = drm_property_replace_blob_from_id(plane->dev, 1577 &dm_plane_state->ctm, 1578 val, 1579 sizeof(struct drm_color_ctm_3x4), -1, 1580 &replaced); 1581 dm_plane_state->base.color_mgmt_changed |= replaced; 1582 return ret; 1583 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1584 ret = drm_property_replace_blob_from_id(plane->dev, 1585 &dm_plane_state->shaper_lut, 1586 val, -1, 1587 sizeof(struct drm_color_lut), 1588 &replaced); 1589 dm_plane_state->base.color_mgmt_changed |= replaced; 1590 return ret; 1591 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1592 if (dm_plane_state->shaper_tf != val) { 1593 dm_plane_state->shaper_tf = val; 1594 dm_plane_state->base.color_mgmt_changed = 1; 1595 } 1596 } else if (property == adev->mode_info.plane_lut3d_property) { 1597 ret = drm_property_replace_blob_from_id(plane->dev, 1598 &dm_plane_state->lut3d, 1599 val, -1, 1600 sizeof(struct drm_color_lut), 1601 &replaced); 1602 dm_plane_state->base.color_mgmt_changed |= replaced; 1603 return ret; 1604 } else if (property == adev->mode_info.plane_blend_lut_property) { 1605 ret = drm_property_replace_blob_from_id(plane->dev, 1606 &dm_plane_state->blend_lut, 1607 val, -1, 1608 sizeof(struct drm_color_lut), 1609 &replaced); 1610 dm_plane_state->base.color_mgmt_changed |= replaced; 1611 return ret; 1612 } else if (property == adev->mode_info.plane_blend_tf_property) { 1613 if (dm_plane_state->blend_tf != val) { 1614 dm_plane_state->blend_tf = val; 1615 dm_plane_state->base.color_mgmt_changed = 1; 1616 } 1617 } else { 1618 drm_dbg_atomic(plane->dev, 1619 "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", 1620 plane->base.id, plane->name, 1621 property->base.id, property->name); 1622 return -EINVAL; 1623 } 1624 1625 return 0; 1626 } 1627 1628 static int 1629 dm_atomic_plane_get_property(struct drm_plane *plane, 1630 const struct drm_plane_state *state, 1631 struct drm_property *property, 1632 uint64_t *val) 1633 { 1634 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1635 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1636 1637 if (property == adev->mode_info.plane_degamma_lut_property) { 1638 *val = (dm_plane_state->degamma_lut) ? 1639 dm_plane_state->degamma_lut->base.id : 0; 1640 } else if (property == adev->mode_info.plane_degamma_tf_property) { 1641 *val = dm_plane_state->degamma_tf; 1642 } else if (property == adev->mode_info.plane_hdr_mult_property) { 1643 *val = dm_plane_state->hdr_mult; 1644 } else if (property == adev->mode_info.plane_ctm_property) { 1645 *val = (dm_plane_state->ctm) ? 1646 dm_plane_state->ctm->base.id : 0; 1647 } else if (property == adev->mode_info.plane_shaper_lut_property) { 1648 *val = (dm_plane_state->shaper_lut) ? 1649 dm_plane_state->shaper_lut->base.id : 0; 1650 } else if (property == adev->mode_info.plane_shaper_tf_property) { 1651 *val = dm_plane_state->shaper_tf; 1652 } else if (property == adev->mode_info.plane_lut3d_property) { 1653 *val = (dm_plane_state->lut3d) ? 1654 dm_plane_state->lut3d->base.id : 0; 1655 } else if (property == adev->mode_info.plane_blend_lut_property) { 1656 *val = (dm_plane_state->blend_lut) ? 1657 dm_plane_state->blend_lut->base.id : 0; 1658 } else if (property == adev->mode_info.plane_blend_tf_property) { 1659 *val = dm_plane_state->blend_tf; 1660 1661 } else { 1662 return -EINVAL; 1663 } 1664 1665 return 0; 1666 } 1667 #endif 1668 1669 static const struct drm_plane_funcs dm_plane_funcs = { 1670 .update_plane = drm_atomic_helper_update_plane, 1671 .disable_plane = drm_atomic_helper_disable_plane, 1672 .destroy = drm_plane_helper_destroy, 1673 .reset = amdgpu_dm_plane_drm_plane_reset, 1674 .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, 1675 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, 1676 .format_mod_supported = amdgpu_dm_plane_format_mod_supported, 1677 #ifdef AMD_PRIVATE_COLOR 1678 .atomic_set_property = dm_atomic_plane_set_property, 1679 .atomic_get_property = dm_atomic_plane_get_property, 1680 #endif 1681 }; 1682 1683 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1684 struct drm_plane *plane, 1685 unsigned long possible_crtcs, 1686 const struct dc_plane_cap *plane_cap) 1687 { 1688 uint32_t formats[32]; 1689 int num_formats; 1690 int res = -EPERM; 1691 unsigned int supported_rotations; 1692 uint64_t *modifiers = NULL; 1693 1694 num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, 1695 ARRAY_SIZE(formats)); 1696 1697 res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); 1698 if (res) 1699 return res; 1700 1701 if (modifiers == NULL) 1702 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1703 1704 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1705 &dm_plane_funcs, formats, num_formats, 1706 modifiers, plane->type, NULL); 1707 kfree(modifiers); 1708 if (res) 1709 return res; 1710 1711 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1712 plane_cap && plane_cap->per_pixel_alpha) { 1713 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1714 BIT(DRM_MODE_BLEND_PREMULTI) | 1715 BIT(DRM_MODE_BLEND_COVERAGE); 1716 1717 drm_plane_create_alpha_property(plane); 1718 drm_plane_create_blend_mode_property(plane, blend_caps); 1719 } 1720 1721 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1722 drm_plane_create_zpos_immutable_property(plane, 0); 1723 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1724 unsigned int zpos = 1 + drm_plane_index(plane); 1725 drm_plane_create_zpos_property(plane, zpos, 1, 254); 1726 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1727 drm_plane_create_zpos_immutable_property(plane, 255); 1728 } 1729 1730 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1731 plane_cap && 1732 (plane_cap->pixel_format_support.nv12 || 1733 plane_cap->pixel_format_support.p010)) { 1734 /* This only affects YUV formats. */ 1735 drm_plane_create_color_properties( 1736 plane, 1737 BIT(DRM_COLOR_YCBCR_BT601) | 1738 BIT(DRM_COLOR_YCBCR_BT709) | 1739 BIT(DRM_COLOR_YCBCR_BT2020), 1740 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1741 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1742 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1743 } 1744 1745 supported_rotations = 1746 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1747 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1748 1749 if (dm->adev->asic_type >= CHIP_BONAIRE && 1750 plane->type != DRM_PLANE_TYPE_CURSOR) 1751 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1752 supported_rotations); 1753 1754 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) > IP_VERSION(3, 0, 1) && 1755 plane->type != DRM_PLANE_TYPE_CURSOR) 1756 drm_plane_enable_fb_damage_clips(plane); 1757 1758 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1759 1760 #ifdef AMD_PRIVATE_COLOR 1761 dm_atomic_plane_attach_color_mgmt_properties(dm, plane); 1762 #endif 1763 /* Create (reset) the plane state */ 1764 if (plane->funcs->reset) 1765 plane->funcs->reset(plane); 1766 1767 return 0; 1768 } 1769 1770 bool amdgpu_dm_plane_is_video_format(uint32_t format) 1771 { 1772 int i; 1773 1774 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1775 if (format == video_formats[i]) 1776 return true; 1777 1778 return false; 1779 } 1780 1781