1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_blend.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_fourcc.h> 32 33 #include "amdgpu.h" 34 #include "dal_asic_id.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_dm_trace.h" 37 #include "amdgpu_dm_plane.h" 38 #include "gc/gc_11_0_0_offset.h" 39 #include "gc/gc_11_0_0_sh_mask.h" 40 41 /* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47 static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62 }; 63 64 static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74 }; 75 76 static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80 }; 81 82 static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84 }; 85 86 enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91 }; 92 93 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94 { 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96 } 97 98 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101 { 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 108 return; 109 110 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 111 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 112 static const uint32_t alpha_formats[] = { 113 DRM_FORMAT_ARGB8888, 114 DRM_FORMAT_RGBA8888, 115 DRM_FORMAT_ABGR8888, 116 DRM_FORMAT_ARGB2101010, 117 DRM_FORMAT_ABGR2101010, 118 DRM_FORMAT_ARGB16161616, 119 DRM_FORMAT_ABGR16161616, 120 DRM_FORMAT_ARGB16161616F, 121 }; 122 uint32_t format = plane_state->fb->format->format; 123 unsigned int i; 124 125 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 126 if (format == alpha_formats[i]) { 127 *per_pixel_alpha = true; 128 break; 129 } 130 } 131 132 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 133 *pre_multiplied_alpha = false; 134 } 135 136 if (plane_state->alpha < 0xffff) { 137 *global_alpha = true; 138 *global_alpha_value = plane_state->alpha >> 8; 139 } 140 } 141 142 static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 143 { 144 if (!*mods) 145 return; 146 147 if (*cap - *size < 1) { 148 uint64_t new_cap = *cap * 2; 149 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 150 151 if (!new_mods) { 152 kfree(*mods); 153 *mods = NULL; 154 return; 155 } 156 157 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 158 kfree(*mods); 159 *mods = new_mods; 160 *cap = new_cap; 161 } 162 163 (*mods)[*size] = mod; 164 *size += 1; 165 } 166 167 static bool modifier_has_dcc(uint64_t modifier) 168 { 169 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 170 } 171 172 static unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier) 173 { 174 if (modifier == DRM_FORMAT_MOD_LINEAR) 175 return 0; 176 177 return AMD_FMT_MOD_GET(TILE, modifier); 178 } 179 180 static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 181 uint64_t tiling_flags) 182 { 183 /* Fill GFX8 params */ 184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 186 187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 192 193 /* XXX fix me for VI */ 194 tiling_info->gfx8.num_banks = num_banks; 195 tiling_info->gfx8.array_mode = 196 DC_ARRAY_2D_TILED_THIN1; 197 tiling_info->gfx8.tile_split = tile_split; 198 tiling_info->gfx8.bank_width = bankw; 199 tiling_info->gfx8.bank_height = bankh; 200 tiling_info->gfx8.tile_aspect = mtaspect; 201 tiling_info->gfx8.tile_mode = 202 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 204 == DC_ARRAY_1D_TILED_THIN1) { 205 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 206 } 207 208 tiling_info->gfx8.pipe_config = 209 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 210 } 211 212 static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 213 union dc_tiling_info *tiling_info) 214 { 215 /* Fill GFX9 params */ 216 tiling_info->gfx9.num_pipes = 217 adev->gfx.config.gb_addr_config_fields.num_pipes; 218 tiling_info->gfx9.num_banks = 219 adev->gfx.config.gb_addr_config_fields.num_banks; 220 tiling_info->gfx9.pipe_interleave = 221 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 222 tiling_info->gfx9.num_shader_engines = 223 adev->gfx.config.gb_addr_config_fields.num_se; 224 tiling_info->gfx9.max_compressed_frags = 225 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 226 tiling_info->gfx9.num_rb_per_se = 227 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 228 tiling_info->gfx9.shaderEnable = 1; 229 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 230 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 231 } 232 233 static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 234 union dc_tiling_info *tiling_info, 235 uint64_t modifier) 236 { 237 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 238 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 239 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 240 unsigned int pipes_log2; 241 242 pipes_log2 = min(5u, mod_pipe_xor_bits); 243 244 fill_gfx9_tiling_info_from_device(adev, tiling_info); 245 246 if (!IS_AMD_FMT_MOD(modifier)) 247 return; 248 249 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 250 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 251 252 if (adev->family >= AMDGPU_FAMILY_NV) { 253 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 254 } else { 255 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 256 257 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 258 } 259 } 260 261 static int validate_dcc(struct amdgpu_device *adev, 262 const enum surface_pixel_format format, 263 const enum dc_rotation_angle rotation, 264 const union dc_tiling_info *tiling_info, 265 const struct dc_plane_dcc_param *dcc, 266 const struct dc_plane_address *address, 267 const struct plane_size *plane_size) 268 { 269 struct dc *dc = adev->dm.dc; 270 struct dc_dcc_surface_param input; 271 struct dc_surface_dcc_cap output; 272 273 memset(&input, 0, sizeof(input)); 274 memset(&output, 0, sizeof(output)); 275 276 if (!dcc->enable) 277 return 0; 278 279 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 280 !dc->cap_funcs.get_dcc_compression_cap) 281 return -EINVAL; 282 283 input.format = format; 284 input.surface_size.width = plane_size->surface_size.width; 285 input.surface_size.height = plane_size->surface_size.height; 286 input.swizzle_mode = tiling_info->gfx9.swizzle; 287 288 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 289 input.scan = SCAN_DIRECTION_HORIZONTAL; 290 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 291 input.scan = SCAN_DIRECTION_VERTICAL; 292 293 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 294 return -EINVAL; 295 296 if (!output.capable) 297 return -EINVAL; 298 299 if (dcc->independent_64b_blks == 0 && 300 output.grph.rgb.independent_64b_blks != 0) 301 return -EINVAL; 302 303 return 0; 304 } 305 306 static int fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 307 const struct amdgpu_framebuffer *afb, 308 const enum surface_pixel_format format, 309 const enum dc_rotation_angle rotation, 310 const struct plane_size *plane_size, 311 union dc_tiling_info *tiling_info, 312 struct dc_plane_dcc_param *dcc, 313 struct dc_plane_address *address, 314 const bool force_disable_dcc) 315 { 316 const uint64_t modifier = afb->base.modifier; 317 int ret = 0; 318 319 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 320 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier); 321 322 if (modifier_has_dcc(modifier) && !force_disable_dcc) { 323 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 324 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 325 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 326 327 dcc->enable = 1; 328 dcc->meta_pitch = afb->base.pitches[1]; 329 dcc->independent_64b_blks = independent_64b_blks; 330 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 331 if (independent_64b_blks && independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 333 else if (independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_128b; 335 else if (independent_64b_blks && !independent_128b_blks) 336 dcc->dcc_ind_blk = hubp_ind_block_64b; 337 else 338 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 339 } else { 340 if (independent_64b_blks) 341 dcc->dcc_ind_blk = hubp_ind_block_64b; 342 else 343 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 344 } 345 346 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 347 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 348 } 349 350 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 351 if (ret) 352 drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret); 353 354 return ret; 355 } 356 357 static void add_gfx10_1_modifiers(const struct amdgpu_device *adev, 358 uint64_t **mods, uint64_t *size, uint64_t *capacity) 359 { 360 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 361 362 add_modifier(mods, size, capacity, AMD_FMT_MOD | 363 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 364 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 365 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 366 AMD_FMT_MOD_SET(DCC, 1) | 367 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 368 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 369 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 370 371 add_modifier(mods, size, capacity, AMD_FMT_MOD | 372 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 373 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 374 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 375 AMD_FMT_MOD_SET(DCC, 1) | 376 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 377 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 378 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 379 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 380 381 add_modifier(mods, size, capacity, AMD_FMT_MOD | 382 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 383 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 384 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 385 386 add_modifier(mods, size, capacity, AMD_FMT_MOD | 387 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 388 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 389 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 390 391 392 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 393 add_modifier(mods, size, capacity, AMD_FMT_MOD | 394 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 395 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 396 397 add_modifier(mods, size, capacity, AMD_FMT_MOD | 398 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 399 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 400 } 401 402 static void add_gfx9_modifiers(const struct amdgpu_device *adev, 403 uint64_t **mods, uint64_t *size, uint64_t *capacity) 404 { 405 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 406 int pipe_xor_bits = min(8, pipes + 407 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 408 int bank_xor_bits = min(8 - pipe_xor_bits, 409 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 410 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 411 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 412 413 414 if (adev->family == AMDGPU_FAMILY_RV) { 415 /* Raven2 and later */ 416 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 417 418 /* 419 * No _D DCC swizzles yet because we only allow 32bpp, which 420 * doesn't support _D on DCN 421 */ 422 423 if (has_constant_encode) { 424 add_modifier(mods, size, capacity, AMD_FMT_MOD | 425 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 426 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 427 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 428 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 429 AMD_FMT_MOD_SET(DCC, 1) | 430 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 431 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 432 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 433 } 434 435 add_modifier(mods, size, capacity, AMD_FMT_MOD | 436 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 437 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 438 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 439 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 440 AMD_FMT_MOD_SET(DCC, 1) | 441 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 442 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 443 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 444 445 if (has_constant_encode) { 446 add_modifier(mods, size, capacity, AMD_FMT_MOD | 447 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 448 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 449 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 450 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 451 AMD_FMT_MOD_SET(DCC, 1) | 452 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 453 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 454 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 455 456 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 457 AMD_FMT_MOD_SET(RB, rb) | 458 AMD_FMT_MOD_SET(PIPE, pipes)); 459 } 460 461 add_modifier(mods, size, capacity, AMD_FMT_MOD | 462 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 463 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 464 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 465 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 466 AMD_FMT_MOD_SET(DCC, 1) | 467 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 468 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 469 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 470 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 471 AMD_FMT_MOD_SET(RB, rb) | 472 AMD_FMT_MOD_SET(PIPE, pipes)); 473 } 474 475 /* 476 * Only supported for 64bpp on Raven, will be filtered on format in 477 * dm_plane_format_mod_supported. 478 */ 479 add_modifier(mods, size, capacity, AMD_FMT_MOD | 480 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 481 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 482 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 483 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 484 485 if (adev->family == AMDGPU_FAMILY_RV) { 486 add_modifier(mods, size, capacity, AMD_FMT_MOD | 487 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 488 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 489 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 490 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 491 } 492 493 /* 494 * Only supported for 64bpp on Raven, will be filtered on format in 495 * dm_plane_format_mod_supported. 496 */ 497 add_modifier(mods, size, capacity, AMD_FMT_MOD | 498 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 499 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 500 501 if (adev->family == AMDGPU_FAMILY_RV) { 502 add_modifier(mods, size, capacity, AMD_FMT_MOD | 503 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 504 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 505 } 506 } 507 508 static void add_gfx10_3_modifiers(const struct amdgpu_device *adev, 509 uint64_t **mods, uint64_t *size, uint64_t *capacity) 510 { 511 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 512 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 513 514 add_modifier(mods, size, capacity, AMD_FMT_MOD | 515 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 516 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 517 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 518 AMD_FMT_MOD_SET(PACKERS, pkrs) | 519 AMD_FMT_MOD_SET(DCC, 1) | 520 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 521 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 522 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 523 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 524 525 add_modifier(mods, size, capacity, AMD_FMT_MOD | 526 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 527 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 528 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 529 AMD_FMT_MOD_SET(PACKERS, pkrs) | 530 AMD_FMT_MOD_SET(DCC, 1) | 531 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 532 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 533 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 534 535 add_modifier(mods, size, capacity, AMD_FMT_MOD | 536 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 537 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 538 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 539 AMD_FMT_MOD_SET(PACKERS, pkrs) | 540 AMD_FMT_MOD_SET(DCC, 1) | 541 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 542 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 543 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 544 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 545 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 546 547 add_modifier(mods, size, capacity, AMD_FMT_MOD | 548 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 549 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 550 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 551 AMD_FMT_MOD_SET(PACKERS, pkrs) | 552 AMD_FMT_MOD_SET(DCC, 1) | 553 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 554 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 555 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 556 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 557 558 add_modifier(mods, size, capacity, AMD_FMT_MOD | 559 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 560 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 561 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 562 AMD_FMT_MOD_SET(PACKERS, pkrs)); 563 564 add_modifier(mods, size, capacity, AMD_FMT_MOD | 565 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 566 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 567 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 568 AMD_FMT_MOD_SET(PACKERS, pkrs)); 569 570 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 571 add_modifier(mods, size, capacity, AMD_FMT_MOD | 572 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 573 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 574 575 add_modifier(mods, size, capacity, AMD_FMT_MOD | 576 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 577 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 578 } 579 580 static void add_gfx11_modifiers(struct amdgpu_device *adev, 581 uint64_t **mods, uint64_t *size, uint64_t *capacity) 582 { 583 int num_pipes = 0; 584 int pipe_xor_bits = 0; 585 int num_pkrs = 0; 586 int pkrs = 0; 587 u32 gb_addr_config; 588 u8 i = 0; 589 unsigned int swizzle_r_x; 590 uint64_t modifier_r_x; 591 uint64_t modifier_dcc_best; 592 uint64_t modifier_dcc_4k; 593 594 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 595 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 596 */ 597 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 598 ASSERT(gb_addr_config != 0); 599 600 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 601 pkrs = ilog2(num_pkrs); 602 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 603 pipe_xor_bits = ilog2(num_pipes); 604 605 for (i = 0; i < 2; i++) { 606 /* Insert the best one first. */ 607 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 608 if (num_pipes > 16) 609 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 610 else 611 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 612 613 modifier_r_x = AMD_FMT_MOD | 614 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 615 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 616 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 617 AMD_FMT_MOD_SET(PACKERS, pkrs); 618 619 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 620 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 621 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 622 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 623 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 624 625 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 626 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 627 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 628 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 629 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 630 631 add_modifier(mods, size, capacity, modifier_dcc_best); 632 add_modifier(mods, size, capacity, modifier_dcc_4k); 633 634 add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 635 add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 636 637 add_modifier(mods, size, capacity, modifier_r_x); 638 } 639 640 add_modifier(mods, size, capacity, AMD_FMT_MOD | 641 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 642 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 643 } 644 645 static int get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 646 { 647 uint64_t size = 0, capacity = 128; 648 *mods = NULL; 649 650 /* We have not hooked up any pre-GFX9 modifiers. */ 651 if (adev->family < AMDGPU_FAMILY_AI) 652 return 0; 653 654 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 655 656 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 657 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 658 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 659 return *mods ? 0 : -ENOMEM; 660 } 661 662 switch (adev->family) { 663 case AMDGPU_FAMILY_AI: 664 case AMDGPU_FAMILY_RV: 665 add_gfx9_modifiers(adev, mods, &size, &capacity); 666 break; 667 case AMDGPU_FAMILY_NV: 668 case AMDGPU_FAMILY_VGH: 669 case AMDGPU_FAMILY_YC: 670 case AMDGPU_FAMILY_GC_10_3_6: 671 case AMDGPU_FAMILY_GC_10_3_7: 672 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 673 add_gfx10_3_modifiers(adev, mods, &size, &capacity); 674 else 675 add_gfx10_1_modifiers(adev, mods, &size, &capacity); 676 break; 677 case AMDGPU_FAMILY_GC_11_0_0: 678 case AMDGPU_FAMILY_GC_11_0_1: 679 case AMDGPU_FAMILY_GC_11_5_0: 680 add_gfx11_modifiers(adev, mods, &size, &capacity); 681 break; 682 } 683 684 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 685 686 /* INVALID marks the end of the list. */ 687 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 688 689 if (!*mods) 690 return -ENOMEM; 691 692 return 0; 693 } 694 695 static int get_plane_formats(const struct drm_plane *plane, 696 const struct dc_plane_cap *plane_cap, 697 uint32_t *formats, int max_formats) 698 { 699 int i, num_formats = 0; 700 701 /* 702 * TODO: Query support for each group of formats directly from 703 * DC plane caps. This will require adding more formats to the 704 * caps list. 705 */ 706 707 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 708 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 709 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 710 if (num_formats >= max_formats) 711 break; 712 713 formats[num_formats++] = rgb_formats[i]; 714 } 715 716 if (plane_cap && plane_cap->pixel_format_support.nv12) 717 formats[num_formats++] = DRM_FORMAT_NV12; 718 if (plane_cap && plane_cap->pixel_format_support.p010) 719 formats[num_formats++] = DRM_FORMAT_P010; 720 if (plane_cap && plane_cap->pixel_format_support.fp16) { 721 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 722 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 723 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 724 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 725 } 726 } else { 727 switch (plane->type) { 728 case DRM_PLANE_TYPE_OVERLAY: 729 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 730 if (num_formats >= max_formats) 731 break; 732 733 formats[num_formats++] = overlay_formats[i]; 734 } 735 break; 736 737 case DRM_PLANE_TYPE_CURSOR: 738 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 739 if (num_formats >= max_formats) 740 break; 741 742 formats[num_formats++] = cursor_formats[i]; 743 } 744 break; 745 746 default: 747 break; 748 } 749 } 750 751 return num_formats; 752 } 753 754 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 755 const struct amdgpu_framebuffer *afb, 756 const enum surface_pixel_format format, 757 const enum dc_rotation_angle rotation, 758 const uint64_t tiling_flags, 759 union dc_tiling_info *tiling_info, 760 struct plane_size *plane_size, 761 struct dc_plane_dcc_param *dcc, 762 struct dc_plane_address *address, 763 bool tmz_surface, 764 bool force_disable_dcc) 765 { 766 const struct drm_framebuffer *fb = &afb->base; 767 int ret; 768 769 memset(tiling_info, 0, sizeof(*tiling_info)); 770 memset(plane_size, 0, sizeof(*plane_size)); 771 memset(dcc, 0, sizeof(*dcc)); 772 memset(address, 0, sizeof(*address)); 773 774 address->tmz_surface = tmz_surface; 775 776 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 777 uint64_t addr = afb->address + fb->offsets[0]; 778 779 plane_size->surface_size.x = 0; 780 plane_size->surface_size.y = 0; 781 plane_size->surface_size.width = fb->width; 782 plane_size->surface_size.height = fb->height; 783 plane_size->surface_pitch = 784 fb->pitches[0] / fb->format->cpp[0]; 785 786 address->type = PLN_ADDR_TYPE_GRAPHICS; 787 address->grph.addr.low_part = lower_32_bits(addr); 788 address->grph.addr.high_part = upper_32_bits(addr); 789 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 790 uint64_t luma_addr = afb->address + fb->offsets[0]; 791 uint64_t chroma_addr = afb->address + fb->offsets[1]; 792 793 plane_size->surface_size.x = 0; 794 plane_size->surface_size.y = 0; 795 plane_size->surface_size.width = fb->width; 796 plane_size->surface_size.height = fb->height; 797 plane_size->surface_pitch = 798 fb->pitches[0] / fb->format->cpp[0]; 799 800 plane_size->chroma_size.x = 0; 801 plane_size->chroma_size.y = 0; 802 /* TODO: set these based on surface format */ 803 plane_size->chroma_size.width = fb->width / 2; 804 plane_size->chroma_size.height = fb->height / 2; 805 806 plane_size->chroma_pitch = 807 fb->pitches[1] / fb->format->cpp[1]; 808 809 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 810 address->video_progressive.luma_addr.low_part = 811 lower_32_bits(luma_addr); 812 address->video_progressive.luma_addr.high_part = 813 upper_32_bits(luma_addr); 814 address->video_progressive.chroma_addr.low_part = 815 lower_32_bits(chroma_addr); 816 address->video_progressive.chroma_addr.high_part = 817 upper_32_bits(chroma_addr); 818 } 819 820 if (adev->family >= AMDGPU_FAMILY_AI) { 821 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 822 rotation, plane_size, 823 tiling_info, dcc, 824 address, 825 force_disable_dcc); 826 if (ret) 827 return ret; 828 } else { 829 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 830 } 831 832 return 0; 833 } 834 835 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 836 struct drm_plane_state *new_state) 837 { 838 struct amdgpu_framebuffer *afb; 839 struct drm_gem_object *obj; 840 struct amdgpu_device *adev; 841 struct amdgpu_bo *rbo; 842 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 843 uint32_t domain; 844 int r; 845 846 if (!new_state->fb) { 847 DRM_DEBUG_KMS("No FB bound\n"); 848 return 0; 849 } 850 851 afb = to_amdgpu_framebuffer(new_state->fb); 852 obj = new_state->fb->obj[0]; 853 rbo = gem_to_amdgpu_bo(obj); 854 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 855 856 r = amdgpu_bo_reserve(rbo, true); 857 if (r) { 858 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 859 return r; 860 } 861 862 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 863 if (r) { 864 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 865 goto error_unlock; 866 } 867 868 if (plane->type != DRM_PLANE_TYPE_CURSOR) 869 domain = amdgpu_display_supported_domains(adev, rbo->flags); 870 else 871 domain = AMDGPU_GEM_DOMAIN_VRAM; 872 873 r = amdgpu_bo_pin(rbo, domain); 874 if (unlikely(r != 0)) { 875 if (r != -ERESTARTSYS) 876 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 877 goto error_unlock; 878 } 879 880 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 881 if (unlikely(r != 0)) { 882 DRM_ERROR("%p bind failed\n", rbo); 883 goto error_unpin; 884 } 885 886 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 887 if (unlikely(r != 0)) 888 goto error_unpin; 889 890 amdgpu_bo_unreserve(rbo); 891 892 afb->address = amdgpu_bo_gpu_offset(rbo); 893 894 amdgpu_bo_ref(rbo); 895 896 /** 897 * We don't do surface updates on planes that have been newly created, 898 * but we also don't have the afb->address during atomic check. 899 * 900 * Fill in buffer attributes depending on the address here, but only on 901 * newly created planes since they're not being used by DC yet and this 902 * won't modify global state. 903 */ 904 dm_plane_state_old = to_dm_plane_state(plane->state); 905 dm_plane_state_new = to_dm_plane_state(new_state); 906 907 if (dm_plane_state_new->dc_state && 908 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 909 struct dc_plane_state *plane_state = 910 dm_plane_state_new->dc_state; 911 bool force_disable_dcc = !plane_state->dcc.enable; 912 913 amdgpu_dm_plane_fill_plane_buffer_attributes( 914 adev, afb, plane_state->format, plane_state->rotation, 915 afb->tiling_flags, 916 &plane_state->tiling_info, &plane_state->plane_size, 917 &plane_state->dcc, &plane_state->address, 918 afb->tmz_surface, force_disable_dcc); 919 } 920 921 return 0; 922 923 error_unpin: 924 amdgpu_bo_unpin(rbo); 925 926 error_unlock: 927 amdgpu_bo_unreserve(rbo); 928 return r; 929 } 930 931 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 932 struct drm_plane_state *old_state) 933 { 934 struct amdgpu_bo *rbo; 935 int r; 936 937 if (!old_state->fb) 938 return; 939 940 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 941 r = amdgpu_bo_reserve(rbo, false); 942 if (unlikely(r)) { 943 DRM_ERROR("failed to reserve rbo before unpin\n"); 944 return; 945 } 946 947 amdgpu_bo_unpin(rbo); 948 amdgpu_bo_unreserve(rbo); 949 amdgpu_bo_unref(&rbo); 950 } 951 952 static void get_min_max_dc_plane_scaling(struct drm_device *dev, 953 struct drm_framebuffer *fb, 954 int *min_downscale, int *max_upscale) 955 { 956 struct amdgpu_device *adev = drm_to_adev(dev); 957 struct dc *dc = adev->dm.dc; 958 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 959 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 960 961 switch (fb->format->format) { 962 case DRM_FORMAT_P010: 963 case DRM_FORMAT_NV12: 964 case DRM_FORMAT_NV21: 965 *max_upscale = plane_cap->max_upscale_factor.nv12; 966 *min_downscale = plane_cap->max_downscale_factor.nv12; 967 break; 968 969 case DRM_FORMAT_XRGB16161616F: 970 case DRM_FORMAT_ARGB16161616F: 971 case DRM_FORMAT_XBGR16161616F: 972 case DRM_FORMAT_ABGR16161616F: 973 *max_upscale = plane_cap->max_upscale_factor.fp16; 974 *min_downscale = plane_cap->max_downscale_factor.fp16; 975 break; 976 977 default: 978 *max_upscale = plane_cap->max_upscale_factor.argb8888; 979 *min_downscale = plane_cap->max_downscale_factor.argb8888; 980 break; 981 } 982 983 /* 984 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 985 * scaling factor of 1.0 == 1000 units. 986 */ 987 if (*max_upscale == 1) 988 *max_upscale = 1000; 989 990 if (*min_downscale == 1) 991 *min_downscale = 1000; 992 } 993 994 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 995 struct drm_crtc_state *new_crtc_state) 996 { 997 struct drm_framebuffer *fb = state->fb; 998 int min_downscale, max_upscale; 999 int min_scale = 0; 1000 int max_scale = INT_MAX; 1001 1002 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1003 if (fb && state->crtc) { 1004 /* Validate viewport to cover the case when only the position changes */ 1005 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1006 int viewport_width = state->crtc_w; 1007 int viewport_height = state->crtc_h; 1008 1009 if (state->crtc_x < 0) 1010 viewport_width += state->crtc_x; 1011 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1012 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1013 1014 if (state->crtc_y < 0) 1015 viewport_height += state->crtc_y; 1016 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1017 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1018 1019 if (viewport_width < 0 || viewport_height < 0) { 1020 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1021 return -EINVAL; 1022 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1023 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1024 return -EINVAL; 1025 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1026 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1027 return -EINVAL; 1028 } 1029 1030 } 1031 1032 /* Get min/max allowed scaling factors from plane caps. */ 1033 get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1034 &min_downscale, &max_upscale); 1035 /* 1036 * Convert to drm convention: 16.16 fixed point, instead of dc's 1037 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1038 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1039 */ 1040 min_scale = (1000 << 16) / max_upscale; 1041 max_scale = (1000 << 16) / min_downscale; 1042 } 1043 1044 return drm_atomic_helper_check_plane_state( 1045 state, new_crtc_state, min_scale, max_scale, true, true); 1046 } 1047 1048 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1049 const struct drm_plane_state *state, 1050 struct dc_scaling_info *scaling_info) 1051 { 1052 int scale_w, scale_h, min_downscale, max_upscale; 1053 1054 memset(scaling_info, 0, sizeof(*scaling_info)); 1055 1056 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1057 scaling_info->src_rect.x = state->src_x >> 16; 1058 scaling_info->src_rect.y = state->src_y >> 16; 1059 1060 /* 1061 * For reasons we don't (yet) fully understand a non-zero 1062 * src_y coordinate into an NV12 buffer can cause a 1063 * system hang on DCN1x. 1064 * To avoid hangs (and maybe be overly cautious) 1065 * let's reject both non-zero src_x and src_y. 1066 * 1067 * We currently know of only one use-case to reproduce a 1068 * scenario with non-zero src_x and src_y for NV12, which 1069 * is to gesture the YouTube Android app into full screen 1070 * on ChromeOS. 1071 */ 1072 if (((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1073 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) && 1074 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1075 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1076 return -EINVAL; 1077 1078 scaling_info->src_rect.width = state->src_w >> 16; 1079 if (scaling_info->src_rect.width == 0) 1080 return -EINVAL; 1081 1082 scaling_info->src_rect.height = state->src_h >> 16; 1083 if (scaling_info->src_rect.height == 0) 1084 return -EINVAL; 1085 1086 scaling_info->dst_rect.x = state->crtc_x; 1087 scaling_info->dst_rect.y = state->crtc_y; 1088 1089 if (state->crtc_w == 0) 1090 return -EINVAL; 1091 1092 scaling_info->dst_rect.width = state->crtc_w; 1093 1094 if (state->crtc_h == 0) 1095 return -EINVAL; 1096 1097 scaling_info->dst_rect.height = state->crtc_h; 1098 1099 /* DRM doesn't specify clipping on destination output. */ 1100 scaling_info->clip_rect = scaling_info->dst_rect; 1101 1102 /* Validate scaling per-format with DC plane caps */ 1103 if (state->plane && state->plane->dev && state->fb) { 1104 get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1105 &min_downscale, &max_upscale); 1106 } else { 1107 min_downscale = 250; 1108 max_upscale = 16000; 1109 } 1110 1111 scale_w = scaling_info->dst_rect.width * 1000 / 1112 scaling_info->src_rect.width; 1113 1114 if (scale_w < min_downscale || scale_w > max_upscale) 1115 return -EINVAL; 1116 1117 scale_h = scaling_info->dst_rect.height * 1000 / 1118 scaling_info->src_rect.height; 1119 1120 if (scale_h < min_downscale || scale_h > max_upscale) 1121 return -EINVAL; 1122 1123 /* 1124 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1125 * assume reasonable defaults based on the format. 1126 */ 1127 1128 return 0; 1129 } 1130 1131 static int dm_plane_atomic_check(struct drm_plane *plane, 1132 struct drm_atomic_state *state) 1133 { 1134 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1135 plane); 1136 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1137 struct dc *dc = adev->dm.dc; 1138 struct dm_plane_state *dm_plane_state; 1139 struct dc_scaling_info scaling_info; 1140 struct drm_crtc_state *new_crtc_state; 1141 int ret; 1142 1143 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1144 1145 dm_plane_state = to_dm_plane_state(new_plane_state); 1146 1147 if (!dm_plane_state->dc_state) 1148 return 0; 1149 1150 new_crtc_state = 1151 drm_atomic_get_new_crtc_state(state, 1152 new_plane_state->crtc); 1153 if (!new_crtc_state) 1154 return -EINVAL; 1155 1156 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1157 if (ret) 1158 return ret; 1159 1160 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1161 if (ret) 1162 return ret; 1163 1164 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1165 return 0; 1166 1167 return -EINVAL; 1168 } 1169 1170 static int dm_plane_atomic_async_check(struct drm_plane *plane, 1171 struct drm_atomic_state *state) 1172 { 1173 /* Only support async updates on cursor planes. */ 1174 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1175 return -EINVAL; 1176 1177 return 0; 1178 } 1179 1180 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1181 struct dc_cursor_position *position) 1182 { 1183 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1184 int x, y; 1185 int xorigin = 0, yorigin = 0; 1186 1187 if (!crtc || !plane->state->fb) 1188 return 0; 1189 1190 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1191 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1192 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1193 __func__, 1194 plane->state->crtc_w, 1195 plane->state->crtc_h); 1196 return -EINVAL; 1197 } 1198 1199 x = plane->state->crtc_x; 1200 y = plane->state->crtc_y; 1201 1202 if (x <= -amdgpu_crtc->max_cursor_width || 1203 y <= -amdgpu_crtc->max_cursor_height) 1204 return 0; 1205 1206 if (x < 0) { 1207 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1208 x = 0; 1209 } 1210 if (y < 0) { 1211 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1212 y = 0; 1213 } 1214 position->enable = true; 1215 position->translate_by_source = true; 1216 position->x = x; 1217 position->y = y; 1218 position->x_hotspot = xorigin; 1219 position->y_hotspot = yorigin; 1220 1221 return 0; 1222 } 1223 1224 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1225 struct drm_plane_state *old_plane_state) 1226 { 1227 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1228 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1229 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1230 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1231 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1232 uint64_t address = afb ? afb->address : 0; 1233 struct dc_cursor_position position = {0}; 1234 struct dc_cursor_attributes attributes; 1235 int ret; 1236 1237 if (!plane->state->fb && !old_plane_state->fb) 1238 return; 1239 1240 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n", 1241 __func__, 1242 amdgpu_crtc->crtc_id, 1243 plane->state->crtc_w, 1244 plane->state->crtc_h); 1245 1246 ret = get_cursor_position(plane, crtc, &position); 1247 if (ret) 1248 return; 1249 1250 if (!position.enable) { 1251 /* turn off cursor */ 1252 if (crtc_state && crtc_state->stream) { 1253 mutex_lock(&adev->dm.dc_lock); 1254 dc_stream_set_cursor_position(crtc_state->stream, 1255 &position); 1256 mutex_unlock(&adev->dm.dc_lock); 1257 } 1258 return; 1259 } 1260 1261 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1262 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1263 1264 memset(&attributes, 0, sizeof(attributes)); 1265 attributes.address.high_part = upper_32_bits(address); 1266 attributes.address.low_part = lower_32_bits(address); 1267 attributes.width = plane->state->crtc_w; 1268 attributes.height = plane->state->crtc_h; 1269 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1270 attributes.rotation_angle = 0; 1271 attributes.attribute_flags.value = 0; 1272 1273 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1274 1275 if (crtc_state->stream) { 1276 mutex_lock(&adev->dm.dc_lock); 1277 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 1278 &attributes)) 1279 DRM_ERROR("DC failed to set cursor attributes\n"); 1280 1281 if (!dc_stream_set_cursor_position(crtc_state->stream, 1282 &position)) 1283 DRM_ERROR("DC failed to set cursor position\n"); 1284 mutex_unlock(&adev->dm.dc_lock); 1285 } 1286 } 1287 1288 static void dm_plane_atomic_async_update(struct drm_plane *plane, 1289 struct drm_atomic_state *state) 1290 { 1291 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1292 plane); 1293 struct drm_plane_state *old_state = 1294 drm_atomic_get_old_plane_state(state, plane); 1295 1296 trace_amdgpu_dm_atomic_update_cursor(new_state); 1297 1298 swap(plane->state->fb, new_state->fb); 1299 1300 plane->state->src_x = new_state->src_x; 1301 plane->state->src_y = new_state->src_y; 1302 plane->state->src_w = new_state->src_w; 1303 plane->state->src_h = new_state->src_h; 1304 plane->state->crtc_x = new_state->crtc_x; 1305 plane->state->crtc_y = new_state->crtc_y; 1306 plane->state->crtc_w = new_state->crtc_w; 1307 plane->state->crtc_h = new_state->crtc_h; 1308 1309 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1310 } 1311 1312 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1313 .prepare_fb = dm_plane_helper_prepare_fb, 1314 .cleanup_fb = dm_plane_helper_cleanup_fb, 1315 .atomic_check = dm_plane_atomic_check, 1316 .atomic_async_check = dm_plane_atomic_async_check, 1317 .atomic_async_update = dm_plane_atomic_async_update 1318 }; 1319 1320 static void dm_drm_plane_reset(struct drm_plane *plane) 1321 { 1322 struct dm_plane_state *amdgpu_state = NULL; 1323 1324 if (plane->state) 1325 plane->funcs->atomic_destroy_state(plane, plane->state); 1326 1327 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1328 WARN_ON(amdgpu_state == NULL); 1329 1330 if (amdgpu_state) 1331 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1332 } 1333 1334 static struct drm_plane_state * 1335 dm_drm_plane_duplicate_state(struct drm_plane *plane) 1336 { 1337 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1338 1339 old_dm_plane_state = to_dm_plane_state(plane->state); 1340 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1341 if (!dm_plane_state) 1342 return NULL; 1343 1344 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1345 1346 if (old_dm_plane_state->dc_state) { 1347 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1348 dc_plane_state_retain(dm_plane_state->dc_state); 1349 } 1350 1351 return &dm_plane_state->base; 1352 } 1353 1354 static bool dm_plane_format_mod_supported(struct drm_plane *plane, 1355 uint32_t format, 1356 uint64_t modifier) 1357 { 1358 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1359 const struct drm_format_info *info = drm_format_info(format); 1360 int i; 1361 1362 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; 1363 1364 if (!info) 1365 return false; 1366 1367 /* 1368 * We always have to allow these modifiers: 1369 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1370 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1371 */ 1372 if (modifier == DRM_FORMAT_MOD_LINEAR || 1373 modifier == DRM_FORMAT_MOD_INVALID) { 1374 return true; 1375 } 1376 1377 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1378 for (i = 0; i < plane->modifier_count; i++) { 1379 if (modifier == plane->modifiers[i]) 1380 break; 1381 } 1382 if (i == plane->modifier_count) 1383 return false; 1384 1385 /* 1386 * For D swizzle the canonical modifier depends on the bpp, so check 1387 * it here. 1388 */ 1389 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1390 adev->family >= AMDGPU_FAMILY_NV) { 1391 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1392 return false; 1393 } 1394 1395 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1396 info->cpp[0] < 8) 1397 return false; 1398 1399 if (modifier_has_dcc(modifier)) { 1400 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1401 if (info->cpp[0] != 4) 1402 return false; 1403 /* We support multi-planar formats, but not when combined with 1404 * additional DCC metadata planes. 1405 */ 1406 if (info->num_planes > 1) 1407 return false; 1408 } 1409 1410 return true; 1411 } 1412 1413 static void dm_drm_plane_destroy_state(struct drm_plane *plane, 1414 struct drm_plane_state *state) 1415 { 1416 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1417 1418 if (dm_plane_state->dc_state) 1419 dc_plane_state_release(dm_plane_state->dc_state); 1420 1421 drm_atomic_helper_plane_destroy_state(plane, state); 1422 } 1423 1424 static const struct drm_plane_funcs dm_plane_funcs = { 1425 .update_plane = drm_atomic_helper_update_plane, 1426 .disable_plane = drm_atomic_helper_disable_plane, 1427 .destroy = drm_plane_helper_destroy, 1428 .reset = dm_drm_plane_reset, 1429 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 1430 .atomic_destroy_state = dm_drm_plane_destroy_state, 1431 .format_mod_supported = dm_plane_format_mod_supported, 1432 }; 1433 1434 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1435 struct drm_plane *plane, 1436 unsigned long possible_crtcs, 1437 const struct dc_plane_cap *plane_cap) 1438 { 1439 uint32_t formats[32]; 1440 int num_formats; 1441 int res = -EPERM; 1442 unsigned int supported_rotations; 1443 uint64_t *modifiers = NULL; 1444 1445 num_formats = get_plane_formats(plane, plane_cap, formats, 1446 ARRAY_SIZE(formats)); 1447 1448 res = get_plane_modifiers(dm->adev, plane->type, &modifiers); 1449 if (res) 1450 return res; 1451 1452 if (modifiers == NULL) 1453 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1454 1455 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1456 &dm_plane_funcs, formats, num_formats, 1457 modifiers, plane->type, NULL); 1458 kfree(modifiers); 1459 if (res) 1460 return res; 1461 1462 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1463 plane_cap && plane_cap->per_pixel_alpha) { 1464 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1465 BIT(DRM_MODE_BLEND_PREMULTI) | 1466 BIT(DRM_MODE_BLEND_COVERAGE); 1467 1468 drm_plane_create_alpha_property(plane); 1469 drm_plane_create_blend_mode_property(plane, blend_caps); 1470 } 1471 1472 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1473 drm_plane_create_zpos_immutable_property(plane, 0); 1474 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1475 unsigned int zpos = 1 + drm_plane_index(plane); 1476 drm_plane_create_zpos_property(plane, zpos, 1, 254); 1477 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1478 drm_plane_create_zpos_immutable_property(plane, 255); 1479 } 1480 1481 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1482 plane_cap && 1483 (plane_cap->pixel_format_support.nv12 || 1484 plane_cap->pixel_format_support.p010)) { 1485 /* This only affects YUV formats. */ 1486 drm_plane_create_color_properties( 1487 plane, 1488 BIT(DRM_COLOR_YCBCR_BT601) | 1489 BIT(DRM_COLOR_YCBCR_BT709) | 1490 BIT(DRM_COLOR_YCBCR_BT2020), 1491 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1492 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1493 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1494 } 1495 1496 supported_rotations = 1497 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1498 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1499 1500 if (dm->adev->asic_type >= CHIP_BONAIRE && 1501 plane->type != DRM_PLANE_TYPE_CURSOR) 1502 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1503 supported_rotations); 1504 1505 if (dm->adev->ip_versions[DCE_HWIP][0] > IP_VERSION(3, 0, 1) && 1506 plane->type != DRM_PLANE_TYPE_CURSOR) 1507 drm_plane_enable_fb_damage_clips(plane); 1508 1509 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1510 1511 /* Create (reset) the plane state */ 1512 if (plane->funcs->reset) 1513 plane->funcs->reset(plane); 1514 1515 return 0; 1516 } 1517 1518 bool is_video_format(uint32_t format) 1519 { 1520 int i; 1521 1522 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1523 if (format == video_formats[i]) 1524 return true; 1525 1526 return false; 1527 } 1528 1529