1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_hdcp.h" 27 #include "amdgpu.h" 28 #include "amdgpu_dm.h" 29 #include "dm_helpers.h" 30 #include <drm/display/drm_hdcp_helper.h> 31 #include "hdcp_psp.h" 32 33 /* 34 * If the SRM version being loaded is less than or equal to the 35 * currently loaded SRM, psp will return 0xFFFF as the version 36 */ 37 #define PSP_SRM_VERSION_MAX 0xFFFF 38 39 static bool 40 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 41 { 42 struct dc_link *link = handle; 43 struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} }; 44 struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, 45 link->dc->caps.i2c_speed_in_khz}; 46 47 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 48 } 49 50 static bool 51 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size) 52 { 53 struct dc_link *link = handle; 54 55 struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, 56 {false, address, size, data} }; 57 struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, 58 link->dc->caps.i2c_speed_in_khz}; 59 60 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 61 } 62 63 static bool 64 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 65 { 66 struct dc_link *link = handle; 67 68 return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size); 69 } 70 71 static bool 72 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size) 73 { 74 struct dc_link *link = handle; 75 76 return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size); 77 } 78 79 static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size) 80 { 81 struct ta_hdcp_shared_memory *hdcp_cmd; 82 83 if (!psp->hdcp_context.context.initialized) { 84 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); 85 return NULL; 86 } 87 88 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; 89 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); 90 91 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM; 92 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); 93 94 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS) 95 return NULL; 96 97 *srm_version = hdcp_cmd->out_msg.hdcp_get_srm.srm_version; 98 *srm_size = hdcp_cmd->out_msg.hdcp_get_srm.srm_buf_size; 99 100 return hdcp_cmd->out_msg.hdcp_get_srm.srm_buf; 101 } 102 103 static int psp_set_srm(struct psp_context *psp, 104 u8 *srm, uint32_t srm_size, uint32_t *srm_version) 105 { 106 struct ta_hdcp_shared_memory *hdcp_cmd; 107 108 if (!psp->hdcp_context.context.initialized) { 109 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); 110 return -EINVAL; 111 } 112 113 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; 114 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); 115 116 memcpy(hdcp_cmd->in_msg.hdcp_set_srm.srm_buf, srm, srm_size); 117 hdcp_cmd->in_msg.hdcp_set_srm.srm_buf_size = srm_size; 118 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_SET_SRM; 119 120 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); 121 122 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS || 123 hdcp_cmd->out_msg.hdcp_set_srm.valid_signature != 1 || 124 hdcp_cmd->out_msg.hdcp_set_srm.srm_version == PSP_SRM_VERSION_MAX) 125 return -EINVAL; 126 127 *srm_version = hdcp_cmd->out_msg.hdcp_set_srm.srm_version; 128 return 0; 129 } 130 131 static void process_output(struct hdcp_workqueue *hdcp_work) 132 { 133 struct mod_hdcp_output output = hdcp_work->output; 134 135 if (output.callback_stop) 136 cancel_delayed_work(&hdcp_work->callback_dwork); 137 138 if (output.callback_needed) 139 schedule_delayed_work(&hdcp_work->callback_dwork, 140 msecs_to_jiffies(output.callback_delay)); 141 142 if (output.watchdog_timer_stop) 143 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 144 145 if (output.watchdog_timer_needed) 146 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork, 147 msecs_to_jiffies(output.watchdog_timer_delay)); 148 149 schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0)); 150 } 151 152 static void link_lock(struct hdcp_workqueue *work, bool lock) 153 { 154 int i = 0; 155 156 for (i = 0; i < work->max_link; i++) { 157 if (lock) 158 mutex_lock(&work[i].mutex); 159 else 160 mutex_unlock(&work[i].mutex); 161 } 162 } 163 164 void hdcp_update_display(struct hdcp_workqueue *hdcp_work, 165 unsigned int link_index, 166 struct amdgpu_dm_connector *aconnector, 167 u8 content_type, 168 bool enable_encryption) 169 { 170 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 171 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 172 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 173 struct mod_hdcp_display_query query; 174 unsigned int conn_index = aconnector->base.index; 175 176 mutex_lock(&hdcp_w->mutex); 177 hdcp_w->aconnector[conn_index] = aconnector; 178 179 query.display = NULL; 180 mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query); 181 182 if (query.display) { 183 memcpy(display, query.display, sizeof(struct mod_hdcp_display)); 184 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 185 186 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; 187 188 if (enable_encryption) { 189 /* Explicitly set the saved SRM as sysfs call will be after 190 * we already enabled hdcp (s3 resume case) 191 */ 192 if (hdcp_work->srm_size > 0) 193 psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm, 194 hdcp_work->srm_size, 195 &hdcp_work->srm_version); 196 197 display->adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE; 198 if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { 199 hdcp_w->link.adjust.hdcp1.disable = 0; 200 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; 201 } else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) { 202 hdcp_w->link.adjust.hdcp1.disable = 1; 203 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; 204 } 205 206 schedule_delayed_work(&hdcp_w->property_validate_dwork, 207 msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); 208 } else { 209 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; 210 hdcp_w->encryption_status[conn_index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 211 cancel_delayed_work(&hdcp_w->property_validate_dwork); 212 } 213 214 display->state = MOD_HDCP_DISPLAY_ACTIVE; 215 } 216 217 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); 218 219 process_output(hdcp_w); 220 mutex_unlock(&hdcp_w->mutex); 221 } 222 223 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, 224 unsigned int link_index, 225 struct amdgpu_dm_connector *aconnector) 226 { 227 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 228 struct drm_connector_state *conn_state = aconnector->base.state; 229 unsigned int conn_index = aconnector->base.index; 230 231 mutex_lock(&hdcp_w->mutex); 232 hdcp_w->aconnector[conn_index] = aconnector; 233 234 /* the removal of display will invoke auth reset -> hdcp destroy and 235 * we'd expect the Content Protection (CP) property changed back to 236 * DESIRED if at the time ENABLED. CP property change should occur 237 * before the element removed from linked list. 238 */ 239 if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 240 conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 241 242 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", 243 aconnector->base.index, conn_state->hdcp_content_type, 244 aconnector->base.dpms); 245 } 246 247 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 248 249 process_output(hdcp_w); 250 mutex_unlock(&hdcp_w->mutex); 251 } 252 253 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 254 { 255 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 256 unsigned int conn_index; 257 258 mutex_lock(&hdcp_w->mutex); 259 260 mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); 261 262 cancel_delayed_work(&hdcp_w->property_validate_dwork); 263 264 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { 265 hdcp_w->encryption_status[conn_index] = 266 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 267 } 268 269 process_output(hdcp_w); 270 271 mutex_unlock(&hdcp_w->mutex); 272 } 273 274 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 275 { 276 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 277 278 schedule_work(&hdcp_w->cpirq_work); 279 } 280 281 static void event_callback(struct work_struct *work) 282 { 283 struct hdcp_workqueue *hdcp_work; 284 285 hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue, 286 callback_dwork); 287 288 mutex_lock(&hdcp_work->mutex); 289 290 cancel_delayed_work(&hdcp_work->callback_dwork); 291 292 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK, 293 &hdcp_work->output); 294 295 process_output(hdcp_work); 296 297 mutex_unlock(&hdcp_work->mutex); 298 } 299 300 static void event_property_update(struct work_struct *work) 301 { 302 struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, 303 property_update_work); 304 struct amdgpu_dm_connector *aconnector = NULL; 305 struct drm_device *dev; 306 long ret; 307 unsigned int conn_index; 308 struct drm_connector *connector; 309 struct drm_connector_state *conn_state; 310 311 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { 312 aconnector = hdcp_work->aconnector[conn_index]; 313 314 if (!aconnector) 315 continue; 316 317 connector = &aconnector->base; 318 319 /* check if display connected */ 320 if (connector->status != connector_status_connected) 321 continue; 322 323 conn_state = aconnector->base.state; 324 325 if (!conn_state) 326 continue; 327 328 dev = connector->dev; 329 330 if (!dev) 331 continue; 332 333 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 334 mutex_lock(&hdcp_work->mutex); 335 336 if (conn_state->commit) { 337 ret = wait_for_completion_interruptible_timeout(&conn_state->commit->hw_done, 338 10 * HZ); 339 if (ret == 0) { 340 DRM_ERROR("HDCP state unknown! Setting it to DESIRED\n"); 341 hdcp_work->encryption_status[conn_index] = 342 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 343 } 344 } 345 if (hdcp_work->encryption_status[conn_index] != 346 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { 347 if (conn_state->hdcp_content_type == 348 DRM_MODE_HDCP_CONTENT_TYPE0 && 349 hdcp_work->encryption_status[conn_index] <= 350 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) { 351 DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_ENABLED\n"); 352 drm_hdcp_update_content_protection(connector, 353 DRM_MODE_CONTENT_PROTECTION_ENABLED); 354 } else if (conn_state->hdcp_content_type == 355 DRM_MODE_HDCP_CONTENT_TYPE1 && 356 hdcp_work->encryption_status[conn_index] == 357 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) { 358 drm_hdcp_update_content_protection(connector, 359 DRM_MODE_CONTENT_PROTECTION_ENABLED); 360 } 361 } else { 362 DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); 363 drm_hdcp_update_content_protection(connector, 364 DRM_MODE_CONTENT_PROTECTION_DESIRED); 365 } 366 mutex_unlock(&hdcp_work->mutex); 367 drm_modeset_unlock(&dev->mode_config.connection_mutex); 368 } 369 } 370 371 static void event_property_validate(struct work_struct *work) 372 { 373 struct hdcp_workqueue *hdcp_work = 374 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork); 375 struct mod_hdcp_display_query query; 376 struct amdgpu_dm_connector *aconnector; 377 unsigned int conn_index; 378 379 mutex_lock(&hdcp_work->mutex); 380 381 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; 382 conn_index++) { 383 aconnector = hdcp_work->aconnector[conn_index]; 384 385 if (!aconnector) 386 continue; 387 388 /* check if display connected */ 389 if (aconnector->base.status != connector_status_connected) 390 continue; 391 392 if (!aconnector->base.state) 393 continue; 394 395 query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 396 mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, 397 &query); 398 399 DRM_DEBUG_DRIVER("[HDCP_DM] disp %d, connector->CP %u, (query, work): (%d, %d)\n", 400 aconnector->base.index, 401 aconnector->base.state->content_protection, 402 query.encryption_status, 403 hdcp_work->encryption_status[conn_index]); 404 405 if (query.encryption_status != 406 hdcp_work->encryption_status[conn_index]) { 407 DRM_DEBUG_DRIVER("[HDCP_DM] encryption_status change from %x to %x\n", 408 hdcp_work->encryption_status[conn_index], 409 query.encryption_status); 410 411 hdcp_work->encryption_status[conn_index] = 412 query.encryption_status; 413 414 DRM_DEBUG_DRIVER("[HDCP_DM] trigger property_update_work\n"); 415 416 schedule_work(&hdcp_work->property_update_work); 417 } 418 } 419 420 mutex_unlock(&hdcp_work->mutex); 421 } 422 423 static void event_watchdog_timer(struct work_struct *work) 424 { 425 struct hdcp_workqueue *hdcp_work; 426 427 hdcp_work = container_of(to_delayed_work(work), 428 struct hdcp_workqueue, 429 watchdog_timer_dwork); 430 431 mutex_lock(&hdcp_work->mutex); 432 433 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 434 435 mod_hdcp_process_event(&hdcp_work->hdcp, 436 MOD_HDCP_EVENT_WATCHDOG_TIMEOUT, 437 &hdcp_work->output); 438 439 process_output(hdcp_work); 440 441 mutex_unlock(&hdcp_work->mutex); 442 } 443 444 static void event_cpirq(struct work_struct *work) 445 { 446 struct hdcp_workqueue *hdcp_work; 447 448 hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work); 449 450 mutex_lock(&hdcp_work->mutex); 451 452 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output); 453 454 process_output(hdcp_work); 455 456 mutex_unlock(&hdcp_work->mutex); 457 } 458 459 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work) 460 { 461 int i = 0; 462 463 for (i = 0; i < hdcp_work->max_link; i++) { 464 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork); 465 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); 466 } 467 468 sysfs_remove_bin_file(kobj, &hdcp_work[0].attr); 469 kfree(hdcp_work->srm); 470 kfree(hdcp_work->srm_temp); 471 kfree(hdcp_work); 472 } 473 474 static bool enable_assr(void *handle, struct dc_link *link) 475 { 476 struct hdcp_workqueue *hdcp_work = handle; 477 struct mod_hdcp hdcp = hdcp_work->hdcp; 478 struct psp_context *psp = hdcp.config.psp.handle; 479 struct ta_dtm_shared_memory *dtm_cmd; 480 bool res = true; 481 482 if (!psp->dtm_context.context.initialized) { 483 DRM_INFO("Failed to enable ASSR, DTM TA is not initialized."); 484 return false; 485 } 486 487 dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf; 488 489 mutex_lock(&psp->dtm_context.mutex); 490 memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); 491 492 dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE; 493 dtm_cmd->dtm_in_message.topology_assr_enable.display_topology_dig_be_index = 494 link->link_enc_hw_inst; 495 dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; 496 497 psp_dtm_invoke(psp, dtm_cmd->cmd_id); 498 499 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { 500 DRM_INFO("Failed to enable ASSR"); 501 res = false; 502 } 503 504 mutex_unlock(&psp->dtm_context.mutex); 505 506 return res; 507 } 508 509 static void update_config(void *handle, struct cp_psp_stream_config *config) 510 { 511 struct hdcp_workqueue *hdcp_work = handle; 512 struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx; 513 int link_index = aconnector->dc_link->link_index; 514 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 515 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 516 struct drm_connector_state *conn_state; 517 struct dc_sink *sink = NULL; 518 bool link_is_hdcp14 = false; 519 520 if (config->dpms_off) { 521 hdcp_remove_display(hdcp_work, link_index, aconnector); 522 return; 523 } 524 525 memset(display, 0, sizeof(*display)); 526 memset(link, 0, sizeof(*link)); 527 528 display->index = aconnector->base.index; 529 display->state = MOD_HDCP_DISPLAY_ACTIVE; 530 531 if (aconnector->dc_sink) 532 sink = aconnector->dc_sink; 533 else if (aconnector->dc_em_sink) 534 sink = aconnector->dc_em_sink; 535 536 if (sink) 537 link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal); 538 539 display->controller = CONTROLLER_ID_D0 + config->otg_inst; 540 display->dig_fe = config->dig_fe; 541 link->dig_be = config->dig_be; 542 link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; 543 display->stream_enc_idx = config->stream_enc_idx; 544 link->link_enc_idx = config->link_enc_idx; 545 link->dio_output_id = config->dio_output_idx; 546 link->phy_idx = config->phy_idx; 547 548 if (sink) 549 link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); 550 link->hdcp_supported_informational = link_is_hdcp14; 551 link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; 552 link->dp.assr_enabled = config->assr_enabled; 553 link->dp.mst_enabled = config->mst_enabled; 554 link->dp.dp2_enabled = config->dp2_enabled; 555 link->dp.usb4_enabled = config->usb4_enabled; 556 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; 557 link->adjust.auth_delay = 2; 558 link->adjust.hdcp1.disable = 0; 559 conn_state = aconnector->base.state; 560 561 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, 562 (!!aconnector->base.state) ? 563 aconnector->base.state->content_protection : -1, 564 (!!aconnector->base.state) ? 565 aconnector->base.state->hdcp_content_type : -1); 566 567 if (conn_state) 568 hdcp_update_display(hdcp_work, link_index, aconnector, 569 conn_state->hdcp_content_type, false); 570 } 571 572 /** 573 * DOC: Add sysfs interface for set/get srm 574 * 575 * NOTE: From the usermodes prospective you only need to call write *ONCE*, the kernel 576 * will automatically call once or twice depending on the size 577 * 578 * call: "cat file > /sys/class/drm/card0/device/hdcp_srm" from usermode no matter what the size is 579 * 580 * The kernel can only send PAGE_SIZE at once and since MAX_SRM_FILE(5120) > PAGE_SIZE(4096), 581 * srm_data_write can be called multiple times. 582 * 583 * sysfs interface doesn't tell us the size we will get so we are sending partial SRMs to psp and on 584 * the last call we will send the full SRM. PSP will fail on every call before the last. 585 * 586 * This means we don't know if the SRM is good until the last call. And because of this 587 * limitation we cannot throw errors early as it will stop the kernel from writing to sysfs 588 * 589 * Example 1: 590 * Good SRM size = 5096 591 * first call to write 4096 -> PSP fails 592 * Second call to write 1000 -> PSP Pass -> SRM is set 593 * 594 * Example 2: 595 * Bad SRM size = 4096 596 * first call to write 4096 -> PSP fails (This is the same as above, but we don't know if this 597 * is the last call) 598 * 599 * Solution?: 600 * 1: Parse the SRM? -> It is signed so we don't know the EOF 601 * 2: We can have another sysfs that passes the size before calling set. -> simpler solution 602 * below 603 * 604 * Easy Solution: 605 * Always call get after Set to verify if set was successful. 606 * +----------------------+ 607 * | Why it works: | 608 * +----------------------+ 609 * PSP will only update its srm if its older than the one we are trying to load. 610 * Always do set first than get. 611 * -if we try to "1. SET" a older version PSP will reject it and we can "2. GET" the newer 612 * version and save it 613 * 614 * -if we try to "1. SET" a newer version PSP will accept it and we can "2. GET" the 615 * same(newer) version back and save it 616 * 617 * -if we try to "1. SET" a newer version and PSP rejects it. That means the format is 618 * incorrect/corrupted and we should correct our SRM by getting it from PSP 619 */ 620 static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, 621 struct bin_attribute *bin_attr, char *buffer, 622 loff_t pos, size_t count) 623 { 624 struct hdcp_workqueue *work; 625 u32 srm_version = 0; 626 627 work = container_of(bin_attr, struct hdcp_workqueue, attr); 628 link_lock(work, true); 629 630 memcpy(work->srm_temp + pos, buffer, count); 631 632 if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) { 633 DRM_DEBUG_DRIVER("HDCP SRM SET version 0x%X", srm_version); 634 memcpy(work->srm, work->srm_temp, pos + count); 635 work->srm_size = pos + count; 636 work->srm_version = srm_version; 637 } 638 639 link_lock(work, false); 640 641 return count; 642 } 643 644 static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, 645 struct bin_attribute *bin_attr, char *buffer, 646 loff_t pos, size_t count) 647 { 648 struct hdcp_workqueue *work; 649 u8 *srm = NULL; 650 u32 srm_version; 651 u32 srm_size; 652 size_t ret = count; 653 654 work = container_of(bin_attr, struct hdcp_workqueue, attr); 655 656 link_lock(work, true); 657 658 srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size); 659 660 if (!srm) { 661 ret = -EINVAL; 662 goto ret; 663 } 664 665 if (pos >= srm_size) 666 ret = 0; 667 668 if (srm_size - pos < count) { 669 memcpy(buffer, srm + pos, srm_size - pos); 670 ret = srm_size - pos; 671 goto ret; 672 } 673 674 memcpy(buffer, srm + pos, count); 675 676 ret: 677 link_lock(work, false); 678 return ret; 679 } 680 681 /* From the hdcp spec (5.Renewability) SRM needs to be stored in a non-volatile memory. 682 * 683 * For example, 684 * if Application "A" sets the SRM (ver 2) and we reboot/suspend and later when Application "B" 685 * needs to use HDCP, the version in PSP should be SRM(ver 2). So SRM should be persistent 686 * across boot/reboots/suspend/resume/shutdown 687 * 688 * Currently when the system goes down (suspend/shutdown) the SRM is cleared from PSP. For HDCP 689 * we need to make the SRM persistent. 690 * 691 * -PSP owns the checking of SRM but doesn't have the ability to store it in a non-volatile memory. 692 * -The kernel cannot write to the file systems. 693 * -So we need usermode to do this for us, which is why an interface for usermode is needed 694 * 695 * 696 * 697 * Usermode can read/write to/from PSP using the sysfs interface 698 * For example: 699 * to save SRM from PSP to storage : cat /sys/class/drm/card0/device/hdcp_srm > srmfile 700 * to load from storage to PSP: cat srmfile > /sys/class/drm/card0/device/hdcp_srm 701 */ 702 static const struct bin_attribute data_attr = { 703 .attr = {.name = "hdcp_srm", .mode = 0664}, 704 .size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */ 705 .write = srm_data_write, 706 .read = srm_data_read, 707 }; 708 709 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, 710 struct cp_psp *cp_psp, struct dc *dc) 711 { 712 int max_caps = dc->caps.max_links; 713 struct hdcp_workqueue *hdcp_work; 714 int i = 0; 715 716 hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL); 717 if (ZERO_OR_NULL_PTR(hdcp_work)) 718 return NULL; 719 720 hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, 721 sizeof(*hdcp_work->srm), GFP_KERNEL); 722 723 if (!hdcp_work->srm) 724 goto fail_alloc_context; 725 726 hdcp_work->srm_temp = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, 727 sizeof(*hdcp_work->srm_temp), GFP_KERNEL); 728 729 if (!hdcp_work->srm_temp) 730 goto fail_alloc_context; 731 732 hdcp_work->max_link = max_caps; 733 734 for (i = 0; i < max_caps; i++) { 735 mutex_init(&hdcp_work[i].mutex); 736 737 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq); 738 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update); 739 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback); 740 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer); 741 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); 742 743 hdcp_work[i].hdcp.config.psp.handle = &adev->psp; 744 if (dc->ctx->dce_version == DCN_VERSION_3_1 || 745 dc->ctx->dce_version == DCN_VERSION_3_14 || 746 dc->ctx->dce_version == DCN_VERSION_3_15 || 747 dc->ctx->dce_version == DCN_VERSION_3_16) 748 hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1; 749 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); 750 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; 751 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c; 752 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd; 753 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd; 754 755 memset(hdcp_work[i].aconnector, 0, 756 sizeof(struct amdgpu_dm_connector *) * 757 AMDGPU_DM_MAX_DISPLAY_INDEX); 758 memset(hdcp_work[i].encryption_status, 0, 759 sizeof(enum mod_hdcp_encryption_status) * 760 AMDGPU_DM_MAX_DISPLAY_INDEX); 761 } 762 763 cp_psp->funcs.update_stream_config = update_config; 764 cp_psp->funcs.enable_assr = enable_assr; 765 cp_psp->handle = hdcp_work; 766 767 /* File created at /sys/class/drm/card0/device/hdcp_srm*/ 768 hdcp_work[0].attr = data_attr; 769 sysfs_bin_attr_init(&hdcp_work[0].attr); 770 771 if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr)) 772 DRM_WARN("Failed to create device file hdcp_srm"); 773 774 return hdcp_work; 775 776 fail_alloc_context: 777 kfree(hdcp_work->srm); 778 kfree(hdcp_work->srm_temp); 779 kfree(hdcp_work); 780 781 return NULL; 782 } 783 784