1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_hdcp.h" 27 #include "amdgpu.h" 28 #include "amdgpu_dm.h" 29 #include "dm_helpers.h" 30 #include <drm/drm_hdcp.h> 31 32 static bool 33 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 34 { 35 36 struct dc_link *link = handle; 37 struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} }; 38 struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; 39 40 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 41 } 42 43 static bool 44 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size) 45 { 46 struct dc_link *link = handle; 47 48 struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} }; 49 struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; 50 51 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 52 } 53 54 static bool 55 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 56 { 57 struct dc_link *link = handle; 58 59 return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size); 60 } 61 62 static bool 63 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size) 64 { 65 struct dc_link *link = handle; 66 67 return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size); 68 } 69 70 static void process_output(struct hdcp_workqueue *hdcp_work) 71 { 72 struct mod_hdcp_output output = hdcp_work->output; 73 74 if (output.callback_stop) 75 cancel_delayed_work(&hdcp_work->callback_dwork); 76 77 if (output.callback_needed) 78 schedule_delayed_work(&hdcp_work->callback_dwork, 79 msecs_to_jiffies(output.callback_delay)); 80 81 if (output.watchdog_timer_stop) 82 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 83 84 if (output.watchdog_timer_needed) 85 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork, 86 msecs_to_jiffies(output.watchdog_timer_delay)); 87 88 schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0)); 89 } 90 91 void hdcp_update_display(struct hdcp_workqueue *hdcp_work, 92 unsigned int link_index, 93 struct amdgpu_dm_connector *aconnector, 94 uint8_t content_type, 95 bool enable_encryption) 96 { 97 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 98 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 99 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 100 struct mod_hdcp_display_query query; 101 102 mutex_lock(&hdcp_w->mutex); 103 hdcp_w->aconnector = aconnector; 104 105 query.display = NULL; 106 mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query); 107 108 if (query.display != NULL) { 109 memcpy(display, query.display, sizeof(struct mod_hdcp_display)); 110 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 111 112 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; 113 114 if (enable_encryption) { 115 display->adjust.disable = 0; 116 if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) 117 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; 118 else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) 119 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; 120 121 schedule_delayed_work(&hdcp_w->property_validate_dwork, 122 msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); 123 } else { 124 display->adjust.disable = 1; 125 hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 126 cancel_delayed_work(&hdcp_w->property_validate_dwork); 127 } 128 129 display->state = MOD_HDCP_DISPLAY_ACTIVE; 130 } 131 132 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); 133 134 process_output(hdcp_w); 135 mutex_unlock(&hdcp_w->mutex); 136 } 137 138 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 139 { 140 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 141 142 mutex_lock(&hdcp_w->mutex); 143 144 mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); 145 146 cancel_delayed_work(&hdcp_w->property_validate_dwork); 147 hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 148 149 process_output(hdcp_w); 150 151 mutex_unlock(&hdcp_w->mutex); 152 } 153 154 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 155 { 156 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 157 158 schedule_work(&hdcp_w->cpirq_work); 159 } 160 161 162 163 164 static void event_callback(struct work_struct *work) 165 { 166 struct hdcp_workqueue *hdcp_work; 167 168 hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue, 169 callback_dwork); 170 171 mutex_lock(&hdcp_work->mutex); 172 173 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 174 175 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK, 176 &hdcp_work->output); 177 178 process_output(hdcp_work); 179 180 mutex_unlock(&hdcp_work->mutex); 181 182 183 } 184 static void event_property_update(struct work_struct *work) 185 { 186 187 struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work); 188 struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector; 189 struct drm_device *dev = hdcp_work->aconnector->base.dev; 190 long ret; 191 192 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 193 mutex_lock(&hdcp_work->mutex); 194 195 196 if (aconnector->base.state->commit) { 197 ret = wait_for_completion_interruptible_timeout(&aconnector->base.state->commit->hw_done, 10 * HZ); 198 199 if (ret == 0) { 200 DRM_ERROR("HDCP state unknown! Setting it to DESIRED"); 201 hdcp_work->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 202 } 203 } 204 205 if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { 206 if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 && 207 hdcp_work->encryption_status <= MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) 208 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); 209 else if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE1 && 210 hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) 211 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); 212 } else { 213 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED); 214 } 215 216 217 mutex_unlock(&hdcp_work->mutex); 218 drm_modeset_unlock(&dev->mode_config.connection_mutex); 219 } 220 221 static void event_property_validate(struct work_struct *work) 222 { 223 struct hdcp_workqueue *hdcp_work = 224 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork); 225 struct mod_hdcp_display_query query; 226 struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector; 227 228 if (!aconnector) 229 return; 230 231 mutex_lock(&hdcp_work->mutex); 232 233 query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 234 mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &query); 235 236 if (query.encryption_status != hdcp_work->encryption_status) { 237 hdcp_work->encryption_status = query.encryption_status; 238 schedule_work(&hdcp_work->property_update_work); 239 } 240 241 mutex_unlock(&hdcp_work->mutex); 242 } 243 244 static void event_watchdog_timer(struct work_struct *work) 245 { 246 struct hdcp_workqueue *hdcp_work; 247 248 hdcp_work = container_of(to_delayed_work(work), 249 struct hdcp_workqueue, 250 watchdog_timer_dwork); 251 252 mutex_lock(&hdcp_work->mutex); 253 254 mod_hdcp_process_event(&hdcp_work->hdcp, 255 MOD_HDCP_EVENT_WATCHDOG_TIMEOUT, 256 &hdcp_work->output); 257 258 process_output(hdcp_work); 259 260 mutex_unlock(&hdcp_work->mutex); 261 262 } 263 264 static void event_cpirq(struct work_struct *work) 265 { 266 struct hdcp_workqueue *hdcp_work; 267 268 hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work); 269 270 mutex_lock(&hdcp_work->mutex); 271 272 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output); 273 274 process_output(hdcp_work); 275 276 mutex_unlock(&hdcp_work->mutex); 277 278 } 279 280 281 void hdcp_destroy(struct hdcp_workqueue *hdcp_work) 282 { 283 int i = 0; 284 285 for (i = 0; i < hdcp_work->max_link; i++) { 286 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork); 287 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); 288 } 289 290 kfree(hdcp_work); 291 292 } 293 294 static void update_config(void *handle, struct cp_psp_stream_config *config) 295 { 296 struct hdcp_workqueue *hdcp_work = handle; 297 struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx; 298 int link_index = aconnector->dc_link->link_index; 299 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 300 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 301 302 memset(display, 0, sizeof(*display)); 303 memset(link, 0, sizeof(*link)); 304 305 display->index = aconnector->base.index; 306 display->state = MOD_HDCP_DISPLAY_ACTIVE; 307 308 if (aconnector->dc_sink != NULL) 309 link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal); 310 311 display->controller = CONTROLLER_ID_D0 + config->otg_inst; 312 display->dig_fe = config->stream_enc_inst; 313 link->dig_be = config->link_enc_inst; 314 link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; 315 link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; 316 display->adjust.disable = 1; 317 link->adjust.auth_delay = 2; 318 319 hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false); 320 } 321 322 struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc) 323 { 324 325 int max_caps = dc->caps.max_links; 326 struct hdcp_workqueue *hdcp_work = kzalloc(max_caps*sizeof(*hdcp_work), GFP_KERNEL); 327 int i = 0; 328 329 if (hdcp_work == NULL) 330 goto fail_alloc_context; 331 332 hdcp_work->max_link = max_caps; 333 334 for (i = 0; i < max_caps; i++) { 335 336 mutex_init(&hdcp_work[i].mutex); 337 338 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq); 339 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update); 340 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback); 341 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer); 342 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); 343 344 hdcp_work[i].hdcp.config.psp.handle = psp_context; 345 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); 346 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; 347 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c; 348 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd; 349 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd; 350 } 351 352 cp_psp->funcs.update_stream_config = update_config; 353 cp_psp->handle = hdcp_work; 354 355 return hdcp_work; 356 357 fail_alloc_context: 358 kfree(hdcp_work); 359 360 return NULL; 361 362 363 364 } 365 366 367 368