1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_hdcp.h" 27 #include "amdgpu.h" 28 #include "amdgpu_dm.h" 29 #include "dm_helpers.h" 30 #include <drm/display/drm_hdcp_helper.h> 31 #include "hdcp_psp.h" 32 33 /* 34 * If the SRM version being loaded is less than or equal to the 35 * currently loaded SRM, psp will return 0xFFFF as the version 36 */ 37 #define PSP_SRM_VERSION_MAX 0xFFFF 38 39 static bool 40 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 41 { 42 struct dc_link *link = handle; 43 struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} }; 44 struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, 45 link->dc->caps.i2c_speed_in_khz}; 46 47 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 48 } 49 50 static bool 51 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size) 52 { 53 struct dc_link *link = handle; 54 55 struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, 56 {false, address, size, data} }; 57 struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, 58 link->dc->caps.i2c_speed_in_khz}; 59 60 return dm_helpers_submit_i2c(link->ctx, link, &cmd); 61 } 62 63 static bool 64 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size) 65 { 66 struct dc_link *link = handle; 67 68 return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size); 69 } 70 71 static bool 72 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size) 73 { 74 struct dc_link *link = handle; 75 76 return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size); 77 } 78 79 static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size) 80 { 81 struct ta_hdcp_shared_memory *hdcp_cmd; 82 83 if (!psp->hdcp_context.context.initialized) { 84 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); 85 return NULL; 86 } 87 88 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; 89 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); 90 91 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM; 92 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); 93 94 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS) 95 return NULL; 96 97 *srm_version = hdcp_cmd->out_msg.hdcp_get_srm.srm_version; 98 *srm_size = hdcp_cmd->out_msg.hdcp_get_srm.srm_buf_size; 99 100 return hdcp_cmd->out_msg.hdcp_get_srm.srm_buf; 101 } 102 103 static int psp_set_srm(struct psp_context *psp, 104 u8 *srm, uint32_t srm_size, uint32_t *srm_version) 105 { 106 struct ta_hdcp_shared_memory *hdcp_cmd; 107 108 if (!psp->hdcp_context.context.initialized) { 109 DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); 110 return -EINVAL; 111 } 112 113 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; 114 memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); 115 116 memcpy(hdcp_cmd->in_msg.hdcp_set_srm.srm_buf, srm, srm_size); 117 hdcp_cmd->in_msg.hdcp_set_srm.srm_buf_size = srm_size; 118 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_SET_SRM; 119 120 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); 121 122 if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS || 123 hdcp_cmd->out_msg.hdcp_set_srm.valid_signature != 1 || 124 hdcp_cmd->out_msg.hdcp_set_srm.srm_version == PSP_SRM_VERSION_MAX) 125 return -EINVAL; 126 127 *srm_version = hdcp_cmd->out_msg.hdcp_set_srm.srm_version; 128 return 0; 129 } 130 131 static void process_output(struct hdcp_workqueue *hdcp_work) 132 { 133 struct mod_hdcp_output output = hdcp_work->output; 134 135 if (output.callback_stop) 136 cancel_delayed_work(&hdcp_work->callback_dwork); 137 138 if (output.callback_needed) 139 schedule_delayed_work(&hdcp_work->callback_dwork, 140 msecs_to_jiffies(output.callback_delay)); 141 142 if (output.watchdog_timer_stop) 143 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 144 145 if (output.watchdog_timer_needed) 146 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork, 147 msecs_to_jiffies(output.watchdog_timer_delay)); 148 149 schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0)); 150 } 151 152 static void link_lock(struct hdcp_workqueue *work, bool lock) 153 { 154 int i = 0; 155 156 for (i = 0; i < work->max_link; i++) { 157 if (lock) 158 mutex_lock(&work[i].mutex); 159 else 160 mutex_unlock(&work[i].mutex); 161 } 162 } 163 164 void hdcp_update_display(struct hdcp_workqueue *hdcp_work, 165 unsigned int link_index, 166 struct amdgpu_dm_connector *aconnector, 167 u8 content_type, 168 bool enable_encryption) 169 { 170 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 171 struct mod_hdcp_link_adjustment link_adjust; 172 struct mod_hdcp_display_adjustment display_adjust; 173 unsigned int conn_index = aconnector->base.index; 174 175 guard(mutex)(&hdcp_w->mutex); 176 hdcp_w->aconnector[conn_index] = aconnector; 177 178 memset(&link_adjust, 0, sizeof(link_adjust)); 179 memset(&display_adjust, 0, sizeof(display_adjust)); 180 181 if (enable_encryption) { 182 /* Explicitly set the saved SRM as sysfs call will be after we already enabled hdcp 183 * (s3 resume case) 184 */ 185 if (hdcp_work->srm_size > 0) 186 psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm, 187 hdcp_work->srm_size, 188 &hdcp_work->srm_version); 189 190 display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE; 191 192 link_adjust.auth_delay = 2; 193 194 if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { 195 link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; 196 } else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) { 197 link_adjust.hdcp1.disable = 1; 198 link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; 199 } 200 201 schedule_delayed_work(&hdcp_w->property_validate_dwork, 202 msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); 203 } else { 204 display_adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; 205 hdcp_w->encryption_status[conn_index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 206 cancel_delayed_work(&hdcp_w->property_validate_dwork); 207 } 208 209 mod_hdcp_update_display(&hdcp_w->hdcp, conn_index, &link_adjust, &display_adjust, &hdcp_w->output); 210 211 process_output(hdcp_w); 212 } 213 214 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, 215 unsigned int link_index, 216 struct amdgpu_dm_connector *aconnector) 217 { 218 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 219 struct drm_connector_state *conn_state = aconnector->base.state; 220 unsigned int conn_index = aconnector->base.index; 221 222 guard(mutex)(&hdcp_w->mutex); 223 hdcp_w->aconnector[conn_index] = aconnector; 224 225 /* the removal of display will invoke auth reset -> hdcp destroy and 226 * we'd expect the Content Protection (CP) property changed back to 227 * DESIRED if at the time ENABLED. CP property change should occur 228 * before the element removed from linked list. 229 */ 230 if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 231 conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 232 233 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", 234 aconnector->base.index, conn_state->hdcp_content_type, 235 aconnector->base.dpms); 236 } 237 238 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 239 240 process_output(hdcp_w); 241 } 242 243 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 244 { 245 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 246 unsigned int conn_index; 247 248 guard(mutex)(&hdcp_w->mutex); 249 250 mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); 251 252 cancel_delayed_work(&hdcp_w->property_validate_dwork); 253 254 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { 255 hdcp_w->encryption_status[conn_index] = 256 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 257 } 258 259 process_output(hdcp_w); 260 } 261 262 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index) 263 { 264 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 265 266 schedule_work(&hdcp_w->cpirq_work); 267 } 268 269 static void event_callback(struct work_struct *work) 270 { 271 struct hdcp_workqueue *hdcp_work; 272 273 hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue, 274 callback_dwork); 275 276 guard(mutex)(&hdcp_work->mutex); 277 278 cancel_delayed_work(&hdcp_work->callback_dwork); 279 280 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK, 281 &hdcp_work->output); 282 283 process_output(hdcp_work); 284 } 285 286 static void event_property_update(struct work_struct *work) 287 { 288 struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, 289 property_update_work); 290 struct amdgpu_dm_connector *aconnector = NULL; 291 struct drm_device *dev; 292 long ret; 293 unsigned int conn_index; 294 struct drm_connector *connector; 295 struct drm_connector_state *conn_state; 296 297 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { 298 aconnector = hdcp_work->aconnector[conn_index]; 299 300 if (!aconnector) 301 continue; 302 303 connector = &aconnector->base; 304 305 /* check if display connected */ 306 if (connector->status != connector_status_connected) 307 continue; 308 309 conn_state = aconnector->base.state; 310 311 if (!conn_state) 312 continue; 313 314 dev = connector->dev; 315 316 if (!dev) 317 continue; 318 319 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 320 guard(mutex)(&hdcp_work->mutex); 321 322 if (conn_state->commit) { 323 ret = wait_for_completion_interruptible_timeout(&conn_state->commit->hw_done, 324 10 * HZ); 325 if (ret == 0) { 326 DRM_ERROR("HDCP state unknown! Setting it to DESIRED\n"); 327 hdcp_work->encryption_status[conn_index] = 328 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 329 } 330 } 331 if (hdcp_work->encryption_status[conn_index] != 332 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { 333 if (conn_state->hdcp_content_type == 334 DRM_MODE_HDCP_CONTENT_TYPE0 && 335 hdcp_work->encryption_status[conn_index] <= 336 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) { 337 DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_ENABLED\n"); 338 drm_hdcp_update_content_protection(connector, 339 DRM_MODE_CONTENT_PROTECTION_ENABLED); 340 } else if (conn_state->hdcp_content_type == 341 DRM_MODE_HDCP_CONTENT_TYPE1 && 342 hdcp_work->encryption_status[conn_index] == 343 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) { 344 drm_hdcp_update_content_protection(connector, 345 DRM_MODE_CONTENT_PROTECTION_ENABLED); 346 } 347 } else { 348 DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); 349 drm_hdcp_update_content_protection(connector, 350 DRM_MODE_CONTENT_PROTECTION_DESIRED); 351 } 352 drm_modeset_unlock(&dev->mode_config.connection_mutex); 353 } 354 } 355 356 static void event_property_validate(struct work_struct *work) 357 { 358 struct hdcp_workqueue *hdcp_work = 359 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork); 360 struct mod_hdcp_display_query query; 361 struct amdgpu_dm_connector *aconnector; 362 unsigned int conn_index; 363 364 guard(mutex)(&hdcp_work->mutex); 365 366 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; 367 conn_index++) { 368 aconnector = hdcp_work->aconnector[conn_index]; 369 370 if (!aconnector) 371 continue; 372 373 /* check if display connected */ 374 if (aconnector->base.status != connector_status_connected) 375 continue; 376 377 if (!aconnector->base.state) 378 continue; 379 380 query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 381 mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, 382 &query); 383 384 DRM_DEBUG_DRIVER("[HDCP_DM] disp %d, connector->CP %u, (query, work): (%d, %d)\n", 385 aconnector->base.index, 386 aconnector->base.state->content_protection, 387 query.encryption_status, 388 hdcp_work->encryption_status[conn_index]); 389 390 if (query.encryption_status != 391 hdcp_work->encryption_status[conn_index]) { 392 DRM_DEBUG_DRIVER("[HDCP_DM] encryption_status change from %x to %x\n", 393 hdcp_work->encryption_status[conn_index], 394 query.encryption_status); 395 396 hdcp_work->encryption_status[conn_index] = 397 query.encryption_status; 398 399 DRM_DEBUG_DRIVER("[HDCP_DM] trigger property_update_work\n"); 400 401 schedule_work(&hdcp_work->property_update_work); 402 } 403 } 404 } 405 406 static void event_watchdog_timer(struct work_struct *work) 407 { 408 struct hdcp_workqueue *hdcp_work; 409 410 hdcp_work = container_of(to_delayed_work(work), 411 struct hdcp_workqueue, 412 watchdog_timer_dwork); 413 414 guard(mutex)(&hdcp_work->mutex); 415 416 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); 417 418 mod_hdcp_process_event(&hdcp_work->hdcp, 419 MOD_HDCP_EVENT_WATCHDOG_TIMEOUT, 420 &hdcp_work->output); 421 422 process_output(hdcp_work); 423 } 424 425 static void event_cpirq(struct work_struct *work) 426 { 427 struct hdcp_workqueue *hdcp_work; 428 429 hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work); 430 431 guard(mutex)(&hdcp_work->mutex); 432 433 mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output); 434 435 process_output(hdcp_work); 436 } 437 438 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work) 439 { 440 int i = 0; 441 442 for (i = 0; i < hdcp_work->max_link; i++) { 443 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork); 444 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); 445 cancel_delayed_work_sync(&hdcp_work[i].property_validate_dwork); 446 } 447 448 sysfs_remove_bin_file(kobj, &hdcp_work[0].attr); 449 kfree(hdcp_work->srm); 450 kfree(hdcp_work->srm_temp); 451 kfree(hdcp_work); 452 } 453 454 static bool enable_assr(void *handle, struct dc_link *link) 455 { 456 struct hdcp_workqueue *hdcp_work = handle; 457 struct mod_hdcp hdcp = hdcp_work->hdcp; 458 struct psp_context *psp = hdcp.config.psp.handle; 459 struct ta_dtm_shared_memory *dtm_cmd; 460 461 if (!psp->dtm_context.context.initialized) { 462 DRM_INFO("Failed to enable ASSR, DTM TA is not initialized."); 463 return false; 464 } 465 466 dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf; 467 468 guard(mutex)(&psp->dtm_context.mutex); 469 memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); 470 471 dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE; 472 dtm_cmd->dtm_in_message.topology_assr_enable.display_topology_dig_be_index = 473 link->link_enc_hw_inst; 474 dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; 475 476 psp_dtm_invoke(psp, dtm_cmd->cmd_id); 477 478 if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { 479 DRM_INFO("Failed to enable ASSR"); 480 return false; 481 } 482 483 return true; 484 } 485 486 static void update_config(void *handle, struct cp_psp_stream_config *config) 487 { 488 struct hdcp_workqueue *hdcp_work = handle; 489 struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx; 490 int link_index = aconnector->dc_link->link_index; 491 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 492 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 493 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 494 struct dc_sink *sink = NULL; 495 bool link_is_hdcp14 = false; 496 497 if (config->dpms_off) { 498 hdcp_remove_display(hdcp_work, link_index, aconnector); 499 return; 500 } 501 502 memset(display, 0, sizeof(*display)); 503 memset(link, 0, sizeof(*link)); 504 505 display->index = aconnector->base.index; 506 display->state = MOD_HDCP_DISPLAY_ACTIVE; 507 508 if (aconnector->dc_sink) 509 sink = aconnector->dc_sink; 510 else if (aconnector->dc_em_sink) 511 sink = aconnector->dc_em_sink; 512 513 if (sink) 514 link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal); 515 516 display->controller = CONTROLLER_ID_D0 + config->otg_inst; 517 display->dig_fe = config->dig_fe; 518 link->dig_be = config->dig_be; 519 link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; 520 display->stream_enc_idx = config->stream_enc_idx; 521 link->link_enc_idx = config->link_enc_idx; 522 link->dio_output_id = config->dio_output_idx; 523 link->phy_idx = config->phy_idx; 524 525 if (sink) 526 link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); 527 link->hdcp_supported_informational = link_is_hdcp14; 528 link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; 529 link->dp.assr_enabled = config->assr_enabled; 530 link->dp.mst_enabled = config->mst_enabled; 531 link->dp.dp2_enabled = config->dp2_enabled; 532 link->dp.usb4_enabled = config->usb4_enabled; 533 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; 534 link->adjust.auth_delay = 2; 535 link->adjust.hdcp1.disable = 0; 536 hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 537 538 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, 539 (!!aconnector->base.state) ? 540 aconnector->base.state->content_protection : -1, 541 (!!aconnector->base.state) ? 542 aconnector->base.state->hdcp_content_type : -1); 543 544 guard(mutex)(&hdcp_w->mutex); 545 546 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); 547 548 process_output(hdcp_w); 549 } 550 551 /** 552 * DOC: Add sysfs interface for set/get srm 553 * 554 * NOTE: From the usermodes prospective you only need to call write *ONCE*, the kernel 555 * will automatically call once or twice depending on the size 556 * 557 * call: "cat file > /sys/class/drm/card0/device/hdcp_srm" from usermode no matter what the size is 558 * 559 * The kernel can only send PAGE_SIZE at once and since MAX_SRM_FILE(5120) > PAGE_SIZE(4096), 560 * srm_data_write can be called multiple times. 561 * 562 * sysfs interface doesn't tell us the size we will get so we are sending partial SRMs to psp and on 563 * the last call we will send the full SRM. PSP will fail on every call before the last. 564 * 565 * This means we don't know if the SRM is good until the last call. And because of this 566 * limitation we cannot throw errors early as it will stop the kernel from writing to sysfs 567 * 568 * Example 1: 569 * Good SRM size = 5096 570 * first call to write 4096 -> PSP fails 571 * Second call to write 1000 -> PSP Pass -> SRM is set 572 * 573 * Example 2: 574 * Bad SRM size = 4096 575 * first call to write 4096 -> PSP fails (This is the same as above, but we don't know if this 576 * is the last call) 577 * 578 * Solution?: 579 * 1: Parse the SRM? -> It is signed so we don't know the EOF 580 * 2: We can have another sysfs that passes the size before calling set. -> simpler solution 581 * below 582 * 583 * Easy Solution: 584 * Always call get after Set to verify if set was successful. 585 * +----------------------+ 586 * | Why it works: | 587 * +----------------------+ 588 * PSP will only update its srm if its older than the one we are trying to load. 589 * Always do set first than get. 590 * -if we try to "1. SET" a older version PSP will reject it and we can "2. GET" the newer 591 * version and save it 592 * 593 * -if we try to "1. SET" a newer version PSP will accept it and we can "2. GET" the 594 * same(newer) version back and save it 595 * 596 * -if we try to "1. SET" a newer version and PSP rejects it. That means the format is 597 * incorrect/corrupted and we should correct our SRM by getting it from PSP 598 */ 599 static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, 600 const struct bin_attribute *bin_attr, char *buffer, 601 loff_t pos, size_t count) 602 { 603 struct hdcp_workqueue *work; 604 u32 srm_version = 0; 605 606 work = container_of(bin_attr, struct hdcp_workqueue, attr); 607 link_lock(work, true); 608 609 memcpy(work->srm_temp + pos, buffer, count); 610 611 if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) { 612 DRM_DEBUG_DRIVER("HDCP SRM SET version 0x%X", srm_version); 613 memcpy(work->srm, work->srm_temp, pos + count); 614 work->srm_size = pos + count; 615 work->srm_version = srm_version; 616 } 617 618 link_lock(work, false); 619 620 return count; 621 } 622 623 static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, 624 const struct bin_attribute *bin_attr, char *buffer, 625 loff_t pos, size_t count) 626 { 627 struct hdcp_workqueue *work; 628 u8 *srm = NULL; 629 u32 srm_version; 630 u32 srm_size; 631 size_t ret = count; 632 633 work = container_of(bin_attr, struct hdcp_workqueue, attr); 634 635 link_lock(work, true); 636 637 srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size); 638 639 if (!srm) { 640 ret = -EINVAL; 641 goto ret; 642 } 643 644 if (pos >= srm_size) 645 ret = 0; 646 647 if (srm_size - pos < count) { 648 memcpy(buffer, srm + pos, srm_size - pos); 649 ret = srm_size - pos; 650 goto ret; 651 } 652 653 memcpy(buffer, srm + pos, count); 654 655 ret: 656 link_lock(work, false); 657 return ret; 658 } 659 660 /* From the hdcp spec (5.Renewability) SRM needs to be stored in a non-volatile memory. 661 * 662 * For example, 663 * if Application "A" sets the SRM (ver 2) and we reboot/suspend and later when Application "B" 664 * needs to use HDCP, the version in PSP should be SRM(ver 2). So SRM should be persistent 665 * across boot/reboots/suspend/resume/shutdown 666 * 667 * Currently when the system goes down (suspend/shutdown) the SRM is cleared from PSP. For HDCP 668 * we need to make the SRM persistent. 669 * 670 * -PSP owns the checking of SRM but doesn't have the ability to store it in a non-volatile memory. 671 * -The kernel cannot write to the file systems. 672 * -So we need usermode to do this for us, which is why an interface for usermode is needed 673 * 674 * 675 * 676 * Usermode can read/write to/from PSP using the sysfs interface 677 * For example: 678 * to save SRM from PSP to storage : cat /sys/class/drm/card0/device/hdcp_srm > srmfile 679 * to load from storage to PSP: cat srmfile > /sys/class/drm/card0/device/hdcp_srm 680 */ 681 static const struct bin_attribute data_attr = { 682 .attr = {.name = "hdcp_srm", .mode = 0664}, 683 .size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */ 684 .write_new = srm_data_write, 685 .read_new = srm_data_read, 686 }; 687 688 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, 689 struct cp_psp *cp_psp, struct dc *dc) 690 { 691 int max_caps = dc->caps.max_links; 692 struct hdcp_workqueue *hdcp_work; 693 int i = 0; 694 695 hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL); 696 if (ZERO_OR_NULL_PTR(hdcp_work)) 697 return NULL; 698 699 hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, 700 sizeof(*hdcp_work->srm), GFP_KERNEL); 701 702 if (!hdcp_work->srm) 703 goto fail_alloc_context; 704 705 hdcp_work->srm_temp = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, 706 sizeof(*hdcp_work->srm_temp), GFP_KERNEL); 707 708 if (!hdcp_work->srm_temp) 709 goto fail_alloc_context; 710 711 hdcp_work->max_link = max_caps; 712 713 for (i = 0; i < max_caps; i++) { 714 mutex_init(&hdcp_work[i].mutex); 715 716 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq); 717 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update); 718 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback); 719 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer); 720 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); 721 722 hdcp_work[i].hdcp.config.psp.handle = &adev->psp; 723 if (dc->ctx->dce_version == DCN_VERSION_3_1 || 724 dc->ctx->dce_version == DCN_VERSION_3_14 || 725 dc->ctx->dce_version == DCN_VERSION_3_15 || 726 dc->ctx->dce_version == DCN_VERSION_3_5 || 727 dc->ctx->dce_version == DCN_VERSION_3_51 || 728 dc->ctx->dce_version == DCN_VERSION_3_6 || 729 dc->ctx->dce_version == DCN_VERSION_3_16) 730 hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1; 731 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); 732 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; 733 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c; 734 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd; 735 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd; 736 737 memset(hdcp_work[i].aconnector, 0, 738 sizeof(struct amdgpu_dm_connector *) * 739 AMDGPU_DM_MAX_DISPLAY_INDEX); 740 memset(hdcp_work[i].encryption_status, 0, 741 sizeof(enum mod_hdcp_encryption_status) * 742 AMDGPU_DM_MAX_DISPLAY_INDEX); 743 } 744 745 cp_psp->funcs.update_stream_config = update_config; 746 cp_psp->funcs.enable_assr = enable_assr; 747 cp_psp->handle = hdcp_work; 748 749 /* File created at /sys/class/drm/card0/device/hdcp_srm*/ 750 hdcp_work[0].attr = data_attr; 751 sysfs_bin_attr_init(&hdcp_work[0].attr); 752 753 if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr)) 754 DRM_WARN("Failed to create device file hdcp_srm"); 755 756 return hdcp_work; 757 758 fail_alloc_context: 759 kfree(hdcp_work->srm); 760 kfree(hdcp_work->srm_temp); 761 kfree(hdcp_work); 762 763 return NULL; 764 } 765 766