1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "link/protocols/link_dp_capability.h" 40 41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42 #include "amdgpu_dm_psr.h" 43 #endif 44 45 struct dmub_debugfs_trace_header { 46 uint32_t entry_count; 47 uint32_t reserved[3]; 48 }; 49 50 struct dmub_debugfs_trace_entry { 51 uint32_t trace_code; 52 uint32_t tick_count; 53 uint32_t param0; 54 uint32_t param1; 55 }; 56 57 static const char *const mst_progress_status[] = { 58 "probe", 59 "remote_edid", 60 "allocate_new_payload", 61 "clear_allocated_payload", 62 }; 63 64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 65 * 66 * Function takes in attributes passed to debugfs write entry 67 * and writes into param array. 68 * The user passes max_param_num to identify maximum number of 69 * parameters that could be parsed. 70 * 71 */ 72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 73 long *param, const char __user *buf, 74 int max_param_num, 75 uint8_t *param_nums) 76 { 77 char *wr_buf_ptr = NULL; 78 uint32_t wr_buf_count = 0; 79 int r; 80 char *sub_str = NULL; 81 const char delimiter[3] = {' ', '\n', '\0'}; 82 uint8_t param_index = 0; 83 84 *param_nums = 0; 85 86 wr_buf_ptr = wr_buf; 87 88 /* r is bytes not be copied */ 89 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 90 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 91 return -EFAULT; 92 } 93 94 /* check number of parameters. isspace could not differ space and \n */ 95 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 96 /* skip space*/ 97 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 98 wr_buf_ptr++; 99 wr_buf_count++; 100 } 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 105 /* skip non-space*/ 106 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 107 wr_buf_ptr++; 108 wr_buf_count++; 109 } 110 111 (*param_nums)++; 112 113 if (wr_buf_count == wr_buf_size) 114 break; 115 } 116 117 if (*param_nums > max_param_num) 118 *param_nums = max_param_num; 119 120 wr_buf_ptr = wr_buf; /* reset buf pointer */ 121 wr_buf_count = 0; /* number of char already checked */ 122 123 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 124 wr_buf_ptr++; 125 wr_buf_count++; 126 } 127 128 while (param_index < *param_nums) { 129 /* after strsep, wr_buf_ptr will be moved to after space */ 130 sub_str = strsep(&wr_buf_ptr, delimiter); 131 132 r = kstrtol(sub_str, 16, &(param[param_index])); 133 134 if (r) 135 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 136 137 param_index++; 138 } 139 140 return 0; 141 } 142 143 /* function description 144 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 145 * 146 * valid lane count value: 1, 2, 4 147 * valid link rate value: 148 * 06h = 1.62Gbps per lane 149 * 0Ah = 2.7Gbps per lane 150 * 0Ch = 3.24Gbps per lane 151 * 14h = 5.4Gbps per lane 152 * 1Eh = 8.1Gbps per lane 153 * 154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * --- to get dp configuration 157 * 158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 159 * 160 * It will list current, verified, reported, preferred dp configuration. 161 * current -- for current video mode 162 * verified --- maximum configuration which pass link training 163 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 164 * preferred --- user force settings 165 * 166 * --- set (or force) dp configuration 167 * 168 * echo <lane_count> <link_rate> > link_settings 169 * 170 * for example, to force to 2 lane, 2.7GHz, 171 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 172 * 173 * spread_spectrum could not be changed dynamically. 174 * 175 * in case invalid lane count, link rate are force, no hw programming will be 176 * done. please check link settings after force operation to see if HW get 177 * programming. 178 * 179 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 180 * 181 * check current and preferred settings. 182 * 183 */ 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 185 size_t size, loff_t *pos) 186 { 187 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 188 struct dc_link *link = connector->dc_link; 189 char *rd_buf = NULL; 190 char *rd_buf_ptr = NULL; 191 const uint32_t rd_buf_size = 100; 192 uint32_t result = 0; 193 uint8_t str_len = 0; 194 int r; 195 196 if (*pos & 3 || size & 3) 197 return -EINVAL; 198 199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 200 if (!rd_buf) 201 return 0; 202 203 rd_buf_ptr = rd_buf; 204 205 str_len = strlen("Current: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 207 link->cur_link_settings.lane_count, 208 link->cur_link_settings.link_rate, 209 link->cur_link_settings.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Verified: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 214 link->verified_link_cap.lane_count, 215 link->verified_link_cap.link_rate, 216 link->verified_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Reported: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 221 link->reported_link_cap.lane_count, 222 link->reported_link_cap.link_rate, 223 link->reported_link_cap.link_spread); 224 rd_buf_ptr += str_len; 225 226 str_len = strlen("Preferred: %d 0x%x %d "); 227 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 228 link->preferred_link_setting.lane_count, 229 link->preferred_link_setting.link_rate, 230 link->preferred_link_setting.link_spread); 231 232 while (size) { 233 if (*pos >= rd_buf_size) 234 break; 235 236 r = put_user(*(rd_buf + result), buf); 237 if (r) { 238 kfree(rd_buf); 239 return r; /* r = -EFAULT */ 240 } 241 242 buf += 1; 243 size -= 1; 244 *pos += 1; 245 result += 1; 246 } 247 248 kfree(rd_buf); 249 return result; 250 } 251 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 253 size_t size, loff_t *pos) 254 { 255 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 256 struct dc_link *link = connector->dc_link; 257 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 258 struct dc *dc = (struct dc *)link->dc; 259 struct dc_link_settings prefer_link_settings; 260 char *wr_buf = NULL; 261 const uint32_t wr_buf_size = 40; 262 /* 0: lane_count; 1: link_rate */ 263 int max_param_num = 2; 264 uint8_t param_nums = 0; 265 long param[2]; 266 bool valid_input = true; 267 268 if (size == 0) 269 return -EINVAL; 270 271 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 272 if (!wr_buf) 273 return -ENOSPC; 274 275 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 276 (long *)param, buf, 277 max_param_num, 278 ¶m_nums)) { 279 kfree(wr_buf); 280 return -EINVAL; 281 } 282 283 if (param_nums <= 0) { 284 kfree(wr_buf); 285 DRM_DEBUG_DRIVER("user data not be read\n"); 286 return -EINVAL; 287 } 288 289 switch (param[0]) { 290 case LANE_COUNT_ONE: 291 case LANE_COUNT_TWO: 292 case LANE_COUNT_FOUR: 293 break; 294 default: 295 valid_input = false; 296 break; 297 } 298 299 switch (param[1]) { 300 case LINK_RATE_LOW: 301 case LINK_RATE_HIGH: 302 case LINK_RATE_RBR2: 303 case LINK_RATE_HIGH2: 304 case LINK_RATE_HIGH3: 305 case LINK_RATE_UHBR10: 306 case LINK_RATE_UHBR13_5: 307 case LINK_RATE_UHBR20: 308 break; 309 default: 310 valid_input = false; 311 break; 312 } 313 314 if (!valid_input) { 315 kfree(wr_buf); 316 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 317 mutex_lock(&adev->dm.dc_lock); 318 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 319 mutex_unlock(&adev->dm.dc_lock); 320 return size; 321 } 322 323 /* save user force lane_count, link_rate to preferred settings 324 * spread spectrum will not be changed 325 */ 326 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 327 prefer_link_settings.use_link_rate_set = false; 328 prefer_link_settings.lane_count = param[0]; 329 prefer_link_settings.link_rate = param[1]; 330 331 mutex_lock(&adev->dm.dc_lock); 332 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 333 mutex_unlock(&adev->dm.dc_lock); 334 335 kfree(wr_buf); 336 return size; 337 } 338 339 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 340 * post-cursor2 (defined by VESA DP specification) 341 * 342 * valid values 343 * voltage swing: 0,1,2,3 344 * pre-emphasis : 0,1,2,3 345 * post cursor2 : 0,1,2,3 346 * 347 * 348 * how to use this debugfs 349 * 350 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 351 * 352 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 353 * 354 * To figure out which DP-x is the display for DP to be check, 355 * cd DP-x 356 * ls -ll 357 * There should be debugfs file, like link_settings, phy_settings. 358 * cat link_settings 359 * from lane_count, link_rate to figure which DP-x is for display to be worked 360 * on 361 * 362 * To get current DP PHY settings, 363 * cat phy_settings 364 * 365 * To change DP PHY settings, 366 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 367 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 368 * 0, 369 * echo 2 3 0 > phy_settings 370 * 371 * To check if change be applied, get current phy settings by 372 * cat phy_settings 373 * 374 * In case invalid values are set by user, like 375 * echo 1 4 0 > phy_settings 376 * 377 * HW will NOT be programmed by these settings. 378 * cat phy_settings will show the previous valid settings. 379 */ 380 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 381 size_t size, loff_t *pos) 382 { 383 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 384 struct dc_link *link = connector->dc_link; 385 char *rd_buf = NULL; 386 const uint32_t rd_buf_size = 20; 387 uint32_t result = 0; 388 int r; 389 390 if (*pos & 3 || size & 3) 391 return -EINVAL; 392 393 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 394 if (!rd_buf) 395 return -EINVAL; 396 397 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 398 link->cur_lane_setting[0].VOLTAGE_SWING, 399 link->cur_lane_setting[0].PRE_EMPHASIS, 400 link->cur_lane_setting[0].POST_CURSOR2); 401 402 while (size) { 403 if (*pos >= rd_buf_size) 404 break; 405 406 r = put_user((*(rd_buf + result)), buf); 407 if (r) { 408 kfree(rd_buf); 409 return r; /* r = -EFAULT */ 410 } 411 412 buf += 1; 413 size -= 1; 414 *pos += 1; 415 result += 1; 416 } 417 418 kfree(rd_buf); 419 return result; 420 } 421 422 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 423 { 424 struct drm_connector *connector = m->private; 425 struct amdgpu_dm_connector *aconnector = 426 to_amdgpu_dm_connector(connector); 427 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 428 429 if (connector->status != connector_status_connected) 430 return -ENODEV; 431 432 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 433 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 434 caps.phy_repeater_cnt); 435 436 seq_puts(m, "phy repeater mode: "); 437 438 switch (caps.mode) { 439 case DP_PHY_REPEATER_MODE_TRANSPARENT: 440 seq_puts(m, "transparent"); 441 break; 442 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 443 seq_puts(m, "non-transparent"); 444 break; 445 case 0x00: 446 seq_puts(m, "non lttpr"); 447 break; 448 default: 449 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 450 break; 451 } 452 453 seq_puts(m, "\n"); 454 return 0; 455 } 456 457 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 458 size_t size, loff_t *pos) 459 { 460 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 461 struct dc_link *link = connector->dc_link; 462 struct dc *dc = (struct dc *)link->dc; 463 char *wr_buf = NULL; 464 uint32_t wr_buf_size = 40; 465 long param[3]; 466 bool use_prefer_link_setting; 467 struct link_training_settings link_lane_settings; 468 int max_param_num = 3; 469 uint8_t param_nums = 0; 470 int r = 0; 471 472 473 if (size == 0) 474 return -EINVAL; 475 476 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 477 if (!wr_buf) 478 return -ENOSPC; 479 480 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 481 (long *)param, buf, 482 max_param_num, 483 ¶m_nums)) { 484 kfree(wr_buf); 485 return -EINVAL; 486 } 487 488 if (param_nums <= 0) { 489 kfree(wr_buf); 490 DRM_DEBUG_DRIVER("user data not be read\n"); 491 return -EINVAL; 492 } 493 494 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 495 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 496 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 497 kfree(wr_buf); 498 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 499 return size; 500 } 501 502 /* get link settings: lane count, link rate */ 503 use_prefer_link_setting = 504 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 505 (link->test_pattern_enabled)); 506 507 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 508 509 if (use_prefer_link_setting) { 510 link_lane_settings.link_settings.lane_count = 511 link->preferred_link_setting.lane_count; 512 link_lane_settings.link_settings.link_rate = 513 link->preferred_link_setting.link_rate; 514 link_lane_settings.link_settings.link_spread = 515 link->preferred_link_setting.link_spread; 516 } else { 517 link_lane_settings.link_settings.lane_count = 518 link->cur_link_settings.lane_count; 519 link_lane_settings.link_settings.link_rate = 520 link->cur_link_settings.link_rate; 521 link_lane_settings.link_settings.link_spread = 522 link->cur_link_settings.link_spread; 523 } 524 525 /* apply phy settings from user */ 526 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 527 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 528 (enum dc_voltage_swing) (param[0]); 529 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 530 (enum dc_pre_emphasis) (param[1]); 531 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 532 (enum dc_post_cursor2) (param[2]); 533 } 534 535 /* program ASIC registers and DPCD registers */ 536 dc_link_set_drive_settings(dc, &link_lane_settings, link); 537 538 kfree(wr_buf); 539 return size; 540 } 541 542 /* function description 543 * 544 * set PHY layer or Link layer test pattern 545 * PHY test pattern is used for PHY SI check. 546 * Link layer test will not affect PHY SI. 547 * 548 * Reset Test Pattern: 549 * 0 = DP_TEST_PATTERN_VIDEO_MODE 550 * 551 * PHY test pattern supported: 552 * 1 = DP_TEST_PATTERN_D102 553 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 554 * 3 = DP_TEST_PATTERN_PRBS7 555 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 556 * 5 = DP_TEST_PATTERN_CP2520_1 557 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 558 * 7 = DP_TEST_PATTERN_CP2520_3 559 * 560 * DP PHY Link Training Patterns 561 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 562 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 563 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 564 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 565 * 566 * DP Link Layer Test pattern 567 * c = DP_TEST_PATTERN_COLOR_SQUARES 568 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 569 * e = DP_TEST_PATTERN_VERTICAL_BARS 570 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 571 * 10= DP_TEST_PATTERN_COLOR_RAMP 572 * 573 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 574 * 575 * --- set test pattern 576 * echo <test pattern #> > test_pattern 577 * 578 * If test pattern # is not supported, NO HW programming will be done. 579 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 580 * for the user pattern. input 10 bytes data are separated by space 581 * 582 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 583 * 584 * --- reset test pattern 585 * echo 0 > test_pattern 586 * 587 * --- HPD detection is disabled when set PHY test pattern 588 * 589 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 590 * is disable. User could unplug DP display from DP connected and plug scope to 591 * check test pattern PHY SI. 592 * If there is need unplug scope and plug DP display back, do steps below: 593 * echo 0 > phy_test_pattern 594 * unplug scope 595 * plug DP display. 596 * 597 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 598 * driver could detect "unplug scope" and "plug DP display" 599 */ 600 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 601 size_t size, loff_t *pos) 602 { 603 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 604 struct dc_link *link = connector->dc_link; 605 char *wr_buf = NULL; 606 uint32_t wr_buf_size = 100; 607 long param[11] = {0x0}; 608 int max_param_num = 11; 609 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 610 bool disable_hpd = false; 611 bool valid_test_pattern = false; 612 uint8_t param_nums = 0; 613 /* init with default 80bit custom pattern */ 614 uint8_t custom_pattern[10] = { 615 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 616 0x1f, 0x7c, 0xf0, 0xc1, 0x07 617 }; 618 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 619 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 620 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 621 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 622 struct link_training_settings link_training_settings; 623 int i; 624 625 if (size == 0) 626 return -EINVAL; 627 628 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 629 if (!wr_buf) 630 return -ENOSPC; 631 632 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 633 (long *)param, buf, 634 max_param_num, 635 ¶m_nums)) { 636 kfree(wr_buf); 637 return -EINVAL; 638 } 639 640 if (param_nums <= 0) { 641 kfree(wr_buf); 642 DRM_DEBUG_DRIVER("user data not be read\n"); 643 return -EINVAL; 644 } 645 646 647 test_pattern = param[0]; 648 649 switch (test_pattern) { 650 case DP_TEST_PATTERN_VIDEO_MODE: 651 case DP_TEST_PATTERN_COLOR_SQUARES: 652 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 653 case DP_TEST_PATTERN_VERTICAL_BARS: 654 case DP_TEST_PATTERN_HORIZONTAL_BARS: 655 case DP_TEST_PATTERN_COLOR_RAMP: 656 valid_test_pattern = true; 657 break; 658 659 case DP_TEST_PATTERN_D102: 660 case DP_TEST_PATTERN_SYMBOL_ERROR: 661 case DP_TEST_PATTERN_PRBS7: 662 case DP_TEST_PATTERN_80BIT_CUSTOM: 663 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 664 case DP_TEST_PATTERN_TRAINING_PATTERN4: 665 disable_hpd = true; 666 valid_test_pattern = true; 667 break; 668 669 default: 670 valid_test_pattern = false; 671 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 672 break; 673 } 674 675 if (!valid_test_pattern) { 676 kfree(wr_buf); 677 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 678 return size; 679 } 680 681 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 682 for (i = 0; i < 10; i++) { 683 if ((uint8_t) param[i + 1] != 0x0) 684 break; 685 } 686 687 if (i < 10) { 688 /* not use default value */ 689 for (i = 0; i < 10; i++) 690 custom_pattern[i] = (uint8_t) param[i + 1]; 691 } 692 } 693 694 /* Usage: set DP physical test pattern using debugfs with normal DP 695 * panel. Then plug out DP panel and connect a scope to measure 696 * For normal video mode and test pattern generated from CRCT, 697 * they are visibile to user. So do not disable HPD. 698 * Video Mode is also set to clear the test pattern, so enable HPD 699 * because it might have been disabled after a test pattern was set. 700 * AUX depends on HPD * sequence dependent, do not move! 701 */ 702 if (!disable_hpd) 703 dc_link_enable_hpd(link); 704 705 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 706 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 707 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 708 709 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 710 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 711 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 712 713 link_training_settings.link_settings = cur_link_settings; 714 715 716 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 717 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 718 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 719 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 720 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 721 link_training_settings.link_settings = prefer_link_settings; 722 } 723 724 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 725 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 726 727 dc_link_set_test_pattern( 728 link, 729 test_pattern, 730 DP_TEST_PATTERN_COLOR_SPACE_RGB, 731 &link_training_settings, 732 custom_pattern, 733 10); 734 735 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 736 * Then plug out DP panel and connect a scope to measure DP PHY signal. 737 * Need disable interrupt to avoid SW driver disable DP output. This is 738 * done after the test pattern is set. 739 */ 740 if (valid_test_pattern && disable_hpd) 741 dc_link_disable_hpd(link); 742 743 kfree(wr_buf); 744 745 return size; 746 } 747 748 /* 749 * Returns the DMCUB tracebuffer contents. 750 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 751 */ 752 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 753 { 754 struct amdgpu_device *adev = m->private; 755 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 756 struct dmub_debugfs_trace_entry *entries; 757 uint8_t *tbuf_base; 758 uint32_t tbuf_size, max_entries, num_entries, i; 759 760 if (!fb_info) 761 return 0; 762 763 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 764 if (!tbuf_base) 765 return 0; 766 767 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 768 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 769 sizeof(struct dmub_debugfs_trace_entry); 770 771 num_entries = 772 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 773 774 num_entries = min(num_entries, max_entries); 775 776 entries = (struct dmub_debugfs_trace_entry 777 *)(tbuf_base + 778 sizeof(struct dmub_debugfs_trace_header)); 779 780 for (i = 0; i < num_entries; ++i) { 781 struct dmub_debugfs_trace_entry *entry = &entries[i]; 782 783 seq_printf(m, 784 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 785 entry->trace_code, entry->tick_count, entry->param0, 786 entry->param1); 787 } 788 789 return 0; 790 } 791 792 /* 793 * Returns the DMCUB firmware state contents. 794 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 795 */ 796 static int dmub_fw_state_show(struct seq_file *m, void *data) 797 { 798 struct amdgpu_device *adev = m->private; 799 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 800 uint8_t *state_base; 801 uint32_t state_size; 802 803 if (!fb_info) 804 return 0; 805 806 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 807 if (!state_base) 808 return 0; 809 810 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 811 812 return seq_write(m, state_base, state_size); 813 } 814 815 /* psr_capability_show() - show eDP panel PSR capability 816 * 817 * The read function: sink_psr_capability_show 818 * Shows if sink has PSR capability or not. 819 * If yes - the PSR version is appended 820 * 821 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 822 * 823 * Expected output: 824 * "Sink support: no\n" - if panel doesn't support PSR 825 * "Sink support: yes [0x01]\n" - if panel supports PSR1 826 * "Driver support: no\n" - if driver doesn't support PSR 827 * "Driver support: yes [0x01]\n" - if driver supports PSR1 828 */ 829 static int psr_capability_show(struct seq_file *m, void *data) 830 { 831 struct drm_connector *connector = m->private; 832 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 833 struct dc_link *link = aconnector->dc_link; 834 835 if (!link) 836 return -ENODEV; 837 838 if (link->type == dc_connection_none) 839 return -ENODEV; 840 841 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 842 return -ENODEV; 843 844 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 845 if (link->dpcd_caps.psr_info.psr_version) 846 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 847 seq_puts(m, "\n"); 848 849 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 850 if (link->psr_settings.psr_version) 851 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 852 seq_puts(m, "\n"); 853 854 return 0; 855 } 856 857 /* 858 * Returns the current bpc for the crtc. 859 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 860 */ 861 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 862 { 863 struct drm_crtc *crtc = m->private; 864 struct drm_device *dev = crtc->dev; 865 struct dm_crtc_state *dm_crtc_state = NULL; 866 int res = -ENODEV; 867 unsigned int bpc; 868 869 mutex_lock(&dev->mode_config.mutex); 870 drm_modeset_lock(&crtc->mutex, NULL); 871 if (crtc->state == NULL) 872 goto unlock; 873 874 dm_crtc_state = to_dm_crtc_state(crtc->state); 875 if (dm_crtc_state->stream == NULL) 876 goto unlock; 877 878 switch (dm_crtc_state->stream->timing.display_color_depth) { 879 case COLOR_DEPTH_666: 880 bpc = 6; 881 break; 882 case COLOR_DEPTH_888: 883 bpc = 8; 884 break; 885 case COLOR_DEPTH_101010: 886 bpc = 10; 887 break; 888 case COLOR_DEPTH_121212: 889 bpc = 12; 890 break; 891 case COLOR_DEPTH_161616: 892 bpc = 16; 893 break; 894 default: 895 goto unlock; 896 } 897 898 seq_printf(m, "Current: %u\n", bpc); 899 res = 0; 900 901 unlock: 902 drm_modeset_unlock(&crtc->mutex); 903 mutex_unlock(&dev->mode_config.mutex); 904 905 return res; 906 } 907 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 908 909 /* 910 * Example usage: 911 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 912 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 913 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 914 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 915 */ 916 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 917 size_t size, loff_t *pos) 918 { 919 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 920 char *wr_buf = NULL; 921 uint32_t wr_buf_size = 42; 922 int max_param_num = 1; 923 long param; 924 uint8_t param_nums = 0; 925 926 if (size == 0) 927 return -EINVAL; 928 929 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 930 931 if (!wr_buf) { 932 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 933 return -ENOSPC; 934 } 935 936 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 937 ¶m, buf, 938 max_param_num, 939 ¶m_nums)) { 940 kfree(wr_buf); 941 return -EINVAL; 942 } 943 944 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 945 946 kfree(wr_buf); 947 return 0; 948 } 949 950 #ifdef CONFIG_DRM_AMD_DC_HDCP 951 /* 952 * Returns the HDCP capability of the Display (1.4 for now). 953 * 954 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 955 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 956 * 957 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 958 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 959 */ 960 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 961 { 962 struct drm_connector *connector = m->private; 963 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 964 bool hdcp_cap, hdcp2_cap; 965 966 if (connector->status != connector_status_connected) 967 return -ENODEV; 968 969 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 970 971 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 972 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 973 974 975 if (hdcp_cap) 976 seq_printf(m, "%s ", "HDCP1.4"); 977 if (hdcp2_cap) 978 seq_printf(m, "%s ", "HDCP2.2"); 979 980 if (!hdcp_cap && !hdcp2_cap) 981 seq_printf(m, "%s ", "None"); 982 983 seq_puts(m, "\n"); 984 985 return 0; 986 } 987 #endif 988 989 /* 990 * Returns whether the connected display is internal and not hotpluggable. 991 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 992 */ 993 static int internal_display_show(struct seq_file *m, void *data) 994 { 995 struct drm_connector *connector = m->private; 996 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 997 struct dc_link *link = aconnector->dc_link; 998 999 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1000 1001 return 0; 1002 } 1003 1004 /* function description 1005 * 1006 * generic SDP message access for testing 1007 * 1008 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1009 * 1010 * SDP header 1011 * Hb0 : Secondary-Data Packet ID 1012 * Hb1 : Secondary-Data Packet type 1013 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1014 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1015 * 1016 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1017 */ 1018 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1019 size_t size, loff_t *pos) 1020 { 1021 int r; 1022 uint8_t data[36]; 1023 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1024 struct dm_crtc_state *acrtc_state; 1025 uint32_t write_size = 36; 1026 1027 if (connector->base.status != connector_status_connected) 1028 return -ENODEV; 1029 1030 if (size == 0) 1031 return 0; 1032 1033 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1034 1035 r = copy_from_user(data, buf, write_size); 1036 1037 write_size -= r; 1038 1039 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1040 1041 return write_size; 1042 } 1043 1044 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1045 size_t size, loff_t *pos) 1046 { 1047 int r; 1048 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1049 1050 if (size < sizeof(connector->debugfs_dpcd_address)) 1051 return -EINVAL; 1052 1053 r = copy_from_user(&connector->debugfs_dpcd_address, 1054 buf, sizeof(connector->debugfs_dpcd_address)); 1055 1056 return size - r; 1057 } 1058 1059 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1060 size_t size, loff_t *pos) 1061 { 1062 int r; 1063 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1064 1065 if (size < sizeof(connector->debugfs_dpcd_size)) 1066 return -EINVAL; 1067 1068 r = copy_from_user(&connector->debugfs_dpcd_size, 1069 buf, sizeof(connector->debugfs_dpcd_size)); 1070 1071 if (connector->debugfs_dpcd_size > 256) 1072 connector->debugfs_dpcd_size = 0; 1073 1074 return size - r; 1075 } 1076 1077 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1078 size_t size, loff_t *pos) 1079 { 1080 int r; 1081 char *data; 1082 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1083 struct dc_link *link = connector->dc_link; 1084 uint32_t write_size = connector->debugfs_dpcd_size; 1085 1086 if (!write_size || size < write_size) 1087 return -EINVAL; 1088 1089 data = kzalloc(write_size, GFP_KERNEL); 1090 if (!data) 1091 return 0; 1092 1093 r = copy_from_user(data, buf, write_size); 1094 1095 dm_helpers_dp_write_dpcd(link->ctx, link, 1096 connector->debugfs_dpcd_address, data, write_size - r); 1097 kfree(data); 1098 return write_size - r; 1099 } 1100 1101 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1102 size_t size, loff_t *pos) 1103 { 1104 int r; 1105 char *data; 1106 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1107 struct dc_link *link = connector->dc_link; 1108 uint32_t read_size = connector->debugfs_dpcd_size; 1109 1110 if (!read_size || size < read_size) 1111 return 0; 1112 1113 data = kzalloc(read_size, GFP_KERNEL); 1114 if (!data) 1115 return 0; 1116 1117 dm_helpers_dp_read_dpcd(link->ctx, link, 1118 connector->debugfs_dpcd_address, data, read_size); 1119 1120 r = copy_to_user(buf, data, read_size); 1121 1122 kfree(data); 1123 return read_size - r; 1124 } 1125 1126 /* function: Read link's DSC & FEC capabilities 1127 * 1128 * 1129 * Access it with the following command (you need to specify 1130 * connector like DP-1): 1131 * 1132 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1133 * 1134 */ 1135 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1136 { 1137 struct drm_connector *connector = m->private; 1138 struct drm_modeset_acquire_ctx ctx; 1139 struct drm_device *dev = connector->dev; 1140 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1141 int ret = 0; 1142 bool try_again = false; 1143 bool is_fec_supported = false; 1144 bool is_dsc_supported = false; 1145 struct dpcd_caps dpcd_caps; 1146 1147 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1148 do { 1149 try_again = false; 1150 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1151 if (ret) { 1152 if (ret == -EDEADLK) { 1153 ret = drm_modeset_backoff(&ctx); 1154 if (!ret) { 1155 try_again = true; 1156 continue; 1157 } 1158 } 1159 break; 1160 } 1161 if (connector->status != connector_status_connected) { 1162 ret = -ENODEV; 1163 break; 1164 } 1165 dpcd_caps = aconnector->dc_link->dpcd_caps; 1166 if (aconnector->mst_output_port) { 1167 /* aconnector sets dsc_aux during get_modes call 1168 * if MST connector has it means it can either 1169 * enable DSC on the sink device or on MST branch 1170 * its connected to. 1171 */ 1172 if (aconnector->dsc_aux) { 1173 is_fec_supported = true; 1174 is_dsc_supported = true; 1175 } 1176 } else { 1177 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1178 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1179 } 1180 } while (try_again); 1181 1182 drm_modeset_drop_locks(&ctx); 1183 drm_modeset_acquire_fini(&ctx); 1184 1185 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1186 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1187 1188 return ret; 1189 } 1190 1191 /* function: Trigger virtual HPD redetection on connector 1192 * 1193 * This function will perform link rediscovery, link disable 1194 * and enable, and dm connector state update. 1195 * 1196 * Retrigger HPD on an existing connector by echoing 1 into 1197 * its respectful "trigger_hotplug" debugfs entry: 1198 * 1199 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1200 * 1201 * This function can perform HPD unplug: 1202 * 1203 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1204 * 1205 */ 1206 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1207 size_t size, loff_t *pos) 1208 { 1209 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1210 struct drm_connector *connector = &aconnector->base; 1211 struct dc_link *link = NULL; 1212 struct drm_device *dev = connector->dev; 1213 struct amdgpu_device *adev = drm_to_adev(dev); 1214 enum dc_connection_type new_connection_type = dc_connection_none; 1215 char *wr_buf = NULL; 1216 uint32_t wr_buf_size = 42; 1217 int max_param_num = 1; 1218 long param[1] = {0}; 1219 uint8_t param_nums = 0; 1220 bool ret = false; 1221 1222 if (!aconnector || !aconnector->dc_link) 1223 return -EINVAL; 1224 1225 if (size == 0) 1226 return -EINVAL; 1227 1228 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1229 1230 if (!wr_buf) { 1231 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1232 return -ENOSPC; 1233 } 1234 1235 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1236 (long *)param, buf, 1237 max_param_num, 1238 ¶m_nums)) { 1239 kfree(wr_buf); 1240 return -EINVAL; 1241 } 1242 1243 kfree(wr_buf); 1244 1245 if (param_nums <= 0) { 1246 DRM_DEBUG_DRIVER("user data not be read\n"); 1247 return -EINVAL; 1248 } 1249 1250 mutex_lock(&aconnector->hpd_lock); 1251 1252 /* Don't support for mst end device*/ 1253 if (aconnector->mst_root) { 1254 mutex_unlock(&aconnector->hpd_lock); 1255 return -EINVAL; 1256 } 1257 1258 if (param[0] == 1) { 1259 1260 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1261 new_connection_type != dc_connection_none) 1262 goto unlock; 1263 1264 mutex_lock(&adev->dm.dc_lock); 1265 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1266 mutex_unlock(&adev->dm.dc_lock); 1267 1268 if (!ret) 1269 goto unlock; 1270 1271 amdgpu_dm_update_connector_after_detect(aconnector); 1272 1273 drm_modeset_lock_all(dev); 1274 dm_restore_drm_connector_state(dev, connector); 1275 drm_modeset_unlock_all(dev); 1276 1277 drm_kms_helper_connector_hotplug_event(connector); 1278 } else if (param[0] == 0) { 1279 if (!aconnector->dc_link) 1280 goto unlock; 1281 1282 link = aconnector->dc_link; 1283 1284 if (link->local_sink) { 1285 dc_sink_release(link->local_sink); 1286 link->local_sink = NULL; 1287 } 1288 1289 link->dpcd_sink_count = 0; 1290 link->type = dc_connection_none; 1291 link->dongle_max_pix_clk = 0; 1292 1293 amdgpu_dm_update_connector_after_detect(aconnector); 1294 1295 /* If the aconnector is the root node in mst topology */ 1296 if (aconnector->mst_mgr.mst_state == true) 1297 dc_link_reset_cur_dp_mst_topology(link); 1298 1299 drm_modeset_lock_all(dev); 1300 dm_restore_drm_connector_state(dev, connector); 1301 drm_modeset_unlock_all(dev); 1302 1303 drm_kms_helper_connector_hotplug_event(connector); 1304 } 1305 1306 unlock: 1307 mutex_unlock(&aconnector->hpd_lock); 1308 1309 return size; 1310 } 1311 1312 /* function: read DSC status on the connector 1313 * 1314 * The read function: dp_dsc_clock_en_read 1315 * returns current status of DSC clock on the connector. 1316 * The return is a boolean flag: 1 or 0. 1317 * 1318 * Access it with the following command (you need to specify 1319 * connector like DP-1): 1320 * 1321 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1322 * 1323 * Expected output: 1324 * 1 - means that DSC is currently enabled 1325 * 0 - means that DSC is disabled 1326 */ 1327 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1328 size_t size, loff_t *pos) 1329 { 1330 char *rd_buf = NULL; 1331 char *rd_buf_ptr = NULL; 1332 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1333 struct display_stream_compressor *dsc; 1334 struct dcn_dsc_state dsc_state = {0}; 1335 const uint32_t rd_buf_size = 10; 1336 struct pipe_ctx *pipe_ctx; 1337 ssize_t result = 0; 1338 int i, r, str_len = 30; 1339 1340 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1341 1342 if (!rd_buf) 1343 return -ENOMEM; 1344 1345 rd_buf_ptr = rd_buf; 1346 1347 for (i = 0; i < MAX_PIPES; i++) { 1348 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1349 if (pipe_ctx->stream && 1350 pipe_ctx->stream->link == aconnector->dc_link) 1351 break; 1352 } 1353 1354 dsc = pipe_ctx->stream_res.dsc; 1355 if (dsc) 1356 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1357 1358 snprintf(rd_buf_ptr, str_len, 1359 "%d\n", 1360 dsc_state.dsc_clock_en); 1361 rd_buf_ptr += str_len; 1362 1363 while (size) { 1364 if (*pos >= rd_buf_size) 1365 break; 1366 1367 r = put_user(*(rd_buf + result), buf); 1368 if (r) { 1369 kfree(rd_buf); 1370 return r; /* r = -EFAULT */ 1371 } 1372 1373 buf += 1; 1374 size -= 1; 1375 *pos += 1; 1376 result += 1; 1377 } 1378 1379 kfree(rd_buf); 1380 return result; 1381 } 1382 1383 /* function: write force DSC on the connector 1384 * 1385 * The write function: dp_dsc_clock_en_write 1386 * enables to force DSC on the connector. 1387 * User can write to either force enable or force disable DSC 1388 * on the next modeset or set it to driver default 1389 * 1390 * Accepted inputs: 1391 * 0 - default DSC enablement policy 1392 * 1 - force enable DSC on the connector 1393 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1394 * 1395 * Writing DSC settings is done with the following command: 1396 * - To force enable DSC (you need to specify 1397 * connector like DP-1): 1398 * 1399 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1400 * 1401 * - To return to default state set the flag to zero and 1402 * let driver deal with DSC automatically 1403 * (you need to specify connector like DP-1): 1404 * 1405 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1406 * 1407 */ 1408 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1409 size_t size, loff_t *pos) 1410 { 1411 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1412 struct drm_connector *connector = &aconnector->base; 1413 struct drm_device *dev = connector->dev; 1414 struct drm_crtc *crtc = NULL; 1415 struct dm_crtc_state *dm_crtc_state = NULL; 1416 struct pipe_ctx *pipe_ctx; 1417 int i; 1418 char *wr_buf = NULL; 1419 uint32_t wr_buf_size = 42; 1420 int max_param_num = 1; 1421 long param[1] = {0}; 1422 uint8_t param_nums = 0; 1423 1424 if (size == 0) 1425 return -EINVAL; 1426 1427 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1428 1429 if (!wr_buf) { 1430 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1431 return -ENOSPC; 1432 } 1433 1434 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1435 (long *)param, buf, 1436 max_param_num, 1437 ¶m_nums)) { 1438 kfree(wr_buf); 1439 return -EINVAL; 1440 } 1441 1442 if (param_nums <= 0) { 1443 DRM_DEBUG_DRIVER("user data not be read\n"); 1444 kfree(wr_buf); 1445 return -EINVAL; 1446 } 1447 1448 for (i = 0; i < MAX_PIPES; i++) { 1449 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1450 if (pipe_ctx->stream && 1451 pipe_ctx->stream->link == aconnector->dc_link) 1452 break; 1453 } 1454 1455 if (!pipe_ctx->stream) 1456 goto done; 1457 1458 // Get CRTC state 1459 mutex_lock(&dev->mode_config.mutex); 1460 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1461 1462 if (connector->state == NULL) 1463 goto unlock; 1464 1465 crtc = connector->state->crtc; 1466 if (crtc == NULL) 1467 goto unlock; 1468 1469 drm_modeset_lock(&crtc->mutex, NULL); 1470 if (crtc->state == NULL) 1471 goto unlock; 1472 1473 dm_crtc_state = to_dm_crtc_state(crtc->state); 1474 if (dm_crtc_state->stream == NULL) 1475 goto unlock; 1476 1477 if (param[0] == 1) 1478 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1479 else if (param[0] == 2) 1480 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1481 else 1482 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1483 1484 dm_crtc_state->dsc_force_changed = true; 1485 1486 unlock: 1487 if (crtc) 1488 drm_modeset_unlock(&crtc->mutex); 1489 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1490 mutex_unlock(&dev->mode_config.mutex); 1491 1492 done: 1493 kfree(wr_buf); 1494 return size; 1495 } 1496 1497 /* function: read DSC slice width parameter on the connector 1498 * 1499 * The read function: dp_dsc_slice_width_read 1500 * returns dsc slice width used in the current configuration 1501 * The return is an integer: 0 or other positive number 1502 * 1503 * Access the status with the following command: 1504 * 1505 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1506 * 1507 * 0 - means that DSC is disabled 1508 * 1509 * Any other number more than zero represents the 1510 * slice width currently used by DSC in pixels 1511 * 1512 */ 1513 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1514 size_t size, loff_t *pos) 1515 { 1516 char *rd_buf = NULL; 1517 char *rd_buf_ptr = NULL; 1518 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1519 struct display_stream_compressor *dsc; 1520 struct dcn_dsc_state dsc_state = {0}; 1521 const uint32_t rd_buf_size = 100; 1522 struct pipe_ctx *pipe_ctx; 1523 ssize_t result = 0; 1524 int i, r, str_len = 30; 1525 1526 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1527 1528 if (!rd_buf) 1529 return -ENOMEM; 1530 1531 rd_buf_ptr = rd_buf; 1532 1533 for (i = 0; i < MAX_PIPES; i++) { 1534 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1535 if (pipe_ctx->stream && 1536 pipe_ctx->stream->link == aconnector->dc_link) 1537 break; 1538 } 1539 1540 dsc = pipe_ctx->stream_res.dsc; 1541 if (dsc) 1542 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1543 1544 snprintf(rd_buf_ptr, str_len, 1545 "%d\n", 1546 dsc_state.dsc_slice_width); 1547 rd_buf_ptr += str_len; 1548 1549 while (size) { 1550 if (*pos >= rd_buf_size) 1551 break; 1552 1553 r = put_user(*(rd_buf + result), buf); 1554 if (r) { 1555 kfree(rd_buf); 1556 return r; /* r = -EFAULT */ 1557 } 1558 1559 buf += 1; 1560 size -= 1; 1561 *pos += 1; 1562 result += 1; 1563 } 1564 1565 kfree(rd_buf); 1566 return result; 1567 } 1568 1569 /* function: write DSC slice width parameter 1570 * 1571 * The write function: dp_dsc_slice_width_write 1572 * overwrites automatically generated DSC configuration 1573 * of slice width. 1574 * 1575 * The user has to write the slice width divisible by the 1576 * picture width. 1577 * 1578 * Also the user has to write width in hexidecimal 1579 * rather than in decimal. 1580 * 1581 * Writing DSC settings is done with the following command: 1582 * - To force overwrite slice width: (example sets to 1920 pixels) 1583 * 1584 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1585 * 1586 * - To stop overwriting and let driver find the optimal size, 1587 * set the width to zero: 1588 * 1589 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1590 * 1591 */ 1592 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1593 size_t size, loff_t *pos) 1594 { 1595 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1596 struct pipe_ctx *pipe_ctx; 1597 struct drm_connector *connector = &aconnector->base; 1598 struct drm_device *dev = connector->dev; 1599 struct drm_crtc *crtc = NULL; 1600 struct dm_crtc_state *dm_crtc_state = NULL; 1601 int i; 1602 char *wr_buf = NULL; 1603 uint32_t wr_buf_size = 42; 1604 int max_param_num = 1; 1605 long param[1] = {0}; 1606 uint8_t param_nums = 0; 1607 1608 if (size == 0) 1609 return -EINVAL; 1610 1611 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1612 1613 if (!wr_buf) { 1614 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1615 return -ENOSPC; 1616 } 1617 1618 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1619 (long *)param, buf, 1620 max_param_num, 1621 ¶m_nums)) { 1622 kfree(wr_buf); 1623 return -EINVAL; 1624 } 1625 1626 if (param_nums <= 0) { 1627 DRM_DEBUG_DRIVER("user data not be read\n"); 1628 kfree(wr_buf); 1629 return -EINVAL; 1630 } 1631 1632 for (i = 0; i < MAX_PIPES; i++) { 1633 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1634 if (pipe_ctx->stream && 1635 pipe_ctx->stream->link == aconnector->dc_link) 1636 break; 1637 } 1638 1639 if (!pipe_ctx->stream) 1640 goto done; 1641 1642 // Safely get CRTC state 1643 mutex_lock(&dev->mode_config.mutex); 1644 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1645 1646 if (connector->state == NULL) 1647 goto unlock; 1648 1649 crtc = connector->state->crtc; 1650 if (crtc == NULL) 1651 goto unlock; 1652 1653 drm_modeset_lock(&crtc->mutex, NULL); 1654 if (crtc->state == NULL) 1655 goto unlock; 1656 1657 dm_crtc_state = to_dm_crtc_state(crtc->state); 1658 if (dm_crtc_state->stream == NULL) 1659 goto unlock; 1660 1661 if (param[0] > 0) 1662 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1663 pipe_ctx->stream->timing.h_addressable, 1664 param[0]); 1665 else 1666 aconnector->dsc_settings.dsc_num_slices_h = 0; 1667 1668 dm_crtc_state->dsc_force_changed = true; 1669 1670 unlock: 1671 if (crtc) 1672 drm_modeset_unlock(&crtc->mutex); 1673 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1674 mutex_unlock(&dev->mode_config.mutex); 1675 1676 done: 1677 kfree(wr_buf); 1678 return size; 1679 } 1680 1681 /* function: read DSC slice height parameter on the connector 1682 * 1683 * The read function: dp_dsc_slice_height_read 1684 * returns dsc slice height used in the current configuration 1685 * The return is an integer: 0 or other positive number 1686 * 1687 * Access the status with the following command: 1688 * 1689 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1690 * 1691 * 0 - means that DSC is disabled 1692 * 1693 * Any other number more than zero represents the 1694 * slice height currently used by DSC in pixels 1695 * 1696 */ 1697 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1698 size_t size, loff_t *pos) 1699 { 1700 char *rd_buf = NULL; 1701 char *rd_buf_ptr = NULL; 1702 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1703 struct display_stream_compressor *dsc; 1704 struct dcn_dsc_state dsc_state = {0}; 1705 const uint32_t rd_buf_size = 100; 1706 struct pipe_ctx *pipe_ctx; 1707 ssize_t result = 0; 1708 int i, r, str_len = 30; 1709 1710 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1711 1712 if (!rd_buf) 1713 return -ENOMEM; 1714 1715 rd_buf_ptr = rd_buf; 1716 1717 for (i = 0; i < MAX_PIPES; i++) { 1718 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1719 if (pipe_ctx->stream && 1720 pipe_ctx->stream->link == aconnector->dc_link) 1721 break; 1722 } 1723 1724 dsc = pipe_ctx->stream_res.dsc; 1725 if (dsc) 1726 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1727 1728 snprintf(rd_buf_ptr, str_len, 1729 "%d\n", 1730 dsc_state.dsc_slice_height); 1731 rd_buf_ptr += str_len; 1732 1733 while (size) { 1734 if (*pos >= rd_buf_size) 1735 break; 1736 1737 r = put_user(*(rd_buf + result), buf); 1738 if (r) { 1739 kfree(rd_buf); 1740 return r; /* r = -EFAULT */ 1741 } 1742 1743 buf += 1; 1744 size -= 1; 1745 *pos += 1; 1746 result += 1; 1747 } 1748 1749 kfree(rd_buf); 1750 return result; 1751 } 1752 1753 /* function: write DSC slice height parameter 1754 * 1755 * The write function: dp_dsc_slice_height_write 1756 * overwrites automatically generated DSC configuration 1757 * of slice height. 1758 * 1759 * The user has to write the slice height divisible by the 1760 * picture height. 1761 * 1762 * Also the user has to write height in hexidecimal 1763 * rather than in decimal. 1764 * 1765 * Writing DSC settings is done with the following command: 1766 * - To force overwrite slice height (example sets to 128 pixels): 1767 * 1768 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1769 * 1770 * - To stop overwriting and let driver find the optimal size, 1771 * set the height to zero: 1772 * 1773 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1774 * 1775 */ 1776 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1777 size_t size, loff_t *pos) 1778 { 1779 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1780 struct drm_connector *connector = &aconnector->base; 1781 struct drm_device *dev = connector->dev; 1782 struct drm_crtc *crtc = NULL; 1783 struct dm_crtc_state *dm_crtc_state = NULL; 1784 struct pipe_ctx *pipe_ctx; 1785 int i; 1786 char *wr_buf = NULL; 1787 uint32_t wr_buf_size = 42; 1788 int max_param_num = 1; 1789 uint8_t param_nums = 0; 1790 long param[1] = {0}; 1791 1792 if (size == 0) 1793 return -EINVAL; 1794 1795 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1796 1797 if (!wr_buf) { 1798 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1799 return -ENOSPC; 1800 } 1801 1802 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1803 (long *)param, buf, 1804 max_param_num, 1805 ¶m_nums)) { 1806 kfree(wr_buf); 1807 return -EINVAL; 1808 } 1809 1810 if (param_nums <= 0) { 1811 DRM_DEBUG_DRIVER("user data not be read\n"); 1812 kfree(wr_buf); 1813 return -EINVAL; 1814 } 1815 1816 for (i = 0; i < MAX_PIPES; i++) { 1817 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1818 if (pipe_ctx->stream && 1819 pipe_ctx->stream->link == aconnector->dc_link) 1820 break; 1821 } 1822 1823 if (!pipe_ctx->stream) 1824 goto done; 1825 1826 // Get CRTC state 1827 mutex_lock(&dev->mode_config.mutex); 1828 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1829 1830 if (connector->state == NULL) 1831 goto unlock; 1832 1833 crtc = connector->state->crtc; 1834 if (crtc == NULL) 1835 goto unlock; 1836 1837 drm_modeset_lock(&crtc->mutex, NULL); 1838 if (crtc->state == NULL) 1839 goto unlock; 1840 1841 dm_crtc_state = to_dm_crtc_state(crtc->state); 1842 if (dm_crtc_state->stream == NULL) 1843 goto unlock; 1844 1845 if (param[0] > 0) 1846 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1847 pipe_ctx->stream->timing.v_addressable, 1848 param[0]); 1849 else 1850 aconnector->dsc_settings.dsc_num_slices_v = 0; 1851 1852 dm_crtc_state->dsc_force_changed = true; 1853 1854 unlock: 1855 if (crtc) 1856 drm_modeset_unlock(&crtc->mutex); 1857 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1858 mutex_unlock(&dev->mode_config.mutex); 1859 1860 done: 1861 kfree(wr_buf); 1862 return size; 1863 } 1864 1865 /* function: read DSC target rate on the connector in bits per pixel 1866 * 1867 * The read function: dp_dsc_bits_per_pixel_read 1868 * returns target rate of compression in bits per pixel 1869 * The return is an integer: 0 or other positive integer 1870 * 1871 * Access it with the following command: 1872 * 1873 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1874 * 1875 * 0 - means that DSC is disabled 1876 */ 1877 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1878 size_t size, loff_t *pos) 1879 { 1880 char *rd_buf = NULL; 1881 char *rd_buf_ptr = NULL; 1882 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1883 struct display_stream_compressor *dsc; 1884 struct dcn_dsc_state dsc_state = {0}; 1885 const uint32_t rd_buf_size = 100; 1886 struct pipe_ctx *pipe_ctx; 1887 ssize_t result = 0; 1888 int i, r, str_len = 30; 1889 1890 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1891 1892 if (!rd_buf) 1893 return -ENOMEM; 1894 1895 rd_buf_ptr = rd_buf; 1896 1897 for (i = 0; i < MAX_PIPES; i++) { 1898 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1899 if (pipe_ctx->stream && 1900 pipe_ctx->stream->link == aconnector->dc_link) 1901 break; 1902 } 1903 1904 dsc = pipe_ctx->stream_res.dsc; 1905 if (dsc) 1906 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1907 1908 snprintf(rd_buf_ptr, str_len, 1909 "%d\n", 1910 dsc_state.dsc_bits_per_pixel); 1911 rd_buf_ptr += str_len; 1912 1913 while (size) { 1914 if (*pos >= rd_buf_size) 1915 break; 1916 1917 r = put_user(*(rd_buf + result), buf); 1918 if (r) { 1919 kfree(rd_buf); 1920 return r; /* r = -EFAULT */ 1921 } 1922 1923 buf += 1; 1924 size -= 1; 1925 *pos += 1; 1926 result += 1; 1927 } 1928 1929 kfree(rd_buf); 1930 return result; 1931 } 1932 1933 /* function: write DSC target rate in bits per pixel 1934 * 1935 * The write function: dp_dsc_bits_per_pixel_write 1936 * overwrites automatically generated DSC configuration 1937 * of DSC target bit rate. 1938 * 1939 * Also the user has to write bpp in hexidecimal 1940 * rather than in decimal. 1941 * 1942 * Writing DSC settings is done with the following command: 1943 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1944 * 1945 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1946 * 1947 * - To stop overwriting and let driver find the optimal rate, 1948 * set the rate to zero: 1949 * 1950 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1951 * 1952 */ 1953 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1954 size_t size, loff_t *pos) 1955 { 1956 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1957 struct drm_connector *connector = &aconnector->base; 1958 struct drm_device *dev = connector->dev; 1959 struct drm_crtc *crtc = NULL; 1960 struct dm_crtc_state *dm_crtc_state = NULL; 1961 struct pipe_ctx *pipe_ctx; 1962 int i; 1963 char *wr_buf = NULL; 1964 uint32_t wr_buf_size = 42; 1965 int max_param_num = 1; 1966 uint8_t param_nums = 0; 1967 long param[1] = {0}; 1968 1969 if (size == 0) 1970 return -EINVAL; 1971 1972 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1973 1974 if (!wr_buf) { 1975 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1976 return -ENOSPC; 1977 } 1978 1979 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1980 (long *)param, buf, 1981 max_param_num, 1982 ¶m_nums)) { 1983 kfree(wr_buf); 1984 return -EINVAL; 1985 } 1986 1987 if (param_nums <= 0) { 1988 DRM_DEBUG_DRIVER("user data not be read\n"); 1989 kfree(wr_buf); 1990 return -EINVAL; 1991 } 1992 1993 for (i = 0; i < MAX_PIPES; i++) { 1994 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1995 if (pipe_ctx->stream && 1996 pipe_ctx->stream->link == aconnector->dc_link) 1997 break; 1998 } 1999 2000 if (!pipe_ctx->stream) 2001 goto done; 2002 2003 // Get CRTC state 2004 mutex_lock(&dev->mode_config.mutex); 2005 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2006 2007 if (connector->state == NULL) 2008 goto unlock; 2009 2010 crtc = connector->state->crtc; 2011 if (crtc == NULL) 2012 goto unlock; 2013 2014 drm_modeset_lock(&crtc->mutex, NULL); 2015 if (crtc->state == NULL) 2016 goto unlock; 2017 2018 dm_crtc_state = to_dm_crtc_state(crtc->state); 2019 if (dm_crtc_state->stream == NULL) 2020 goto unlock; 2021 2022 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2023 2024 dm_crtc_state->dsc_force_changed = true; 2025 2026 unlock: 2027 if (crtc) 2028 drm_modeset_unlock(&crtc->mutex); 2029 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2030 mutex_unlock(&dev->mode_config.mutex); 2031 2032 done: 2033 kfree(wr_buf); 2034 return size; 2035 } 2036 2037 /* function: read DSC picture width parameter on the connector 2038 * 2039 * The read function: dp_dsc_pic_width_read 2040 * returns dsc picture width used in the current configuration 2041 * It is the same as h_addressable of the current 2042 * display's timing 2043 * The return is an integer: 0 or other positive integer 2044 * If 0 then DSC is disabled. 2045 * 2046 * Access it with the following command: 2047 * 2048 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2049 * 2050 * 0 - means that DSC is disabled 2051 */ 2052 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2053 size_t size, loff_t *pos) 2054 { 2055 char *rd_buf = NULL; 2056 char *rd_buf_ptr = NULL; 2057 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2058 struct display_stream_compressor *dsc; 2059 struct dcn_dsc_state dsc_state = {0}; 2060 const uint32_t rd_buf_size = 100; 2061 struct pipe_ctx *pipe_ctx; 2062 ssize_t result = 0; 2063 int i, r, str_len = 30; 2064 2065 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2066 2067 if (!rd_buf) 2068 return -ENOMEM; 2069 2070 rd_buf_ptr = rd_buf; 2071 2072 for (i = 0; i < MAX_PIPES; i++) { 2073 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2074 if (pipe_ctx->stream && 2075 pipe_ctx->stream->link == aconnector->dc_link) 2076 break; 2077 } 2078 2079 dsc = pipe_ctx->stream_res.dsc; 2080 if (dsc) 2081 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2082 2083 snprintf(rd_buf_ptr, str_len, 2084 "%d\n", 2085 dsc_state.dsc_pic_width); 2086 rd_buf_ptr += str_len; 2087 2088 while (size) { 2089 if (*pos >= rd_buf_size) 2090 break; 2091 2092 r = put_user(*(rd_buf + result), buf); 2093 if (r) { 2094 kfree(rd_buf); 2095 return r; /* r = -EFAULT */ 2096 } 2097 2098 buf += 1; 2099 size -= 1; 2100 *pos += 1; 2101 result += 1; 2102 } 2103 2104 kfree(rd_buf); 2105 return result; 2106 } 2107 2108 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2109 size_t size, loff_t *pos) 2110 { 2111 char *rd_buf = NULL; 2112 char *rd_buf_ptr = NULL; 2113 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2114 struct display_stream_compressor *dsc; 2115 struct dcn_dsc_state dsc_state = {0}; 2116 const uint32_t rd_buf_size = 100; 2117 struct pipe_ctx *pipe_ctx; 2118 ssize_t result = 0; 2119 int i, r, str_len = 30; 2120 2121 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2122 2123 if (!rd_buf) 2124 return -ENOMEM; 2125 2126 rd_buf_ptr = rd_buf; 2127 2128 for (i = 0; i < MAX_PIPES; i++) { 2129 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2130 if (pipe_ctx->stream && 2131 pipe_ctx->stream->link == aconnector->dc_link) 2132 break; 2133 } 2134 2135 dsc = pipe_ctx->stream_res.dsc; 2136 if (dsc) 2137 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2138 2139 snprintf(rd_buf_ptr, str_len, 2140 "%d\n", 2141 dsc_state.dsc_pic_height); 2142 rd_buf_ptr += str_len; 2143 2144 while (size) { 2145 if (*pos >= rd_buf_size) 2146 break; 2147 2148 r = put_user(*(rd_buf + result), buf); 2149 if (r) { 2150 kfree(rd_buf); 2151 return r; /* r = -EFAULT */ 2152 } 2153 2154 buf += 1; 2155 size -= 1; 2156 *pos += 1; 2157 result += 1; 2158 } 2159 2160 kfree(rd_buf); 2161 return result; 2162 } 2163 2164 /* function: read DSC chunk size parameter on the connector 2165 * 2166 * The read function: dp_dsc_chunk_size_read 2167 * returns dsc chunk size set in the current configuration 2168 * The value is calculated automatically by DSC code 2169 * and depends on slice parameters and bpp target rate 2170 * The return is an integer: 0 or other positive integer 2171 * If 0 then DSC is disabled. 2172 * 2173 * Access it with the following command: 2174 * 2175 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2176 * 2177 * 0 - means that DSC is disabled 2178 */ 2179 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2180 size_t size, loff_t *pos) 2181 { 2182 char *rd_buf = NULL; 2183 char *rd_buf_ptr = NULL; 2184 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2185 struct display_stream_compressor *dsc; 2186 struct dcn_dsc_state dsc_state = {0}; 2187 const uint32_t rd_buf_size = 100; 2188 struct pipe_ctx *pipe_ctx; 2189 ssize_t result = 0; 2190 int i, r, str_len = 30; 2191 2192 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2193 2194 if (!rd_buf) 2195 return -ENOMEM; 2196 2197 rd_buf_ptr = rd_buf; 2198 2199 for (i = 0; i < MAX_PIPES; i++) { 2200 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2201 if (pipe_ctx->stream && 2202 pipe_ctx->stream->link == aconnector->dc_link) 2203 break; 2204 } 2205 2206 dsc = pipe_ctx->stream_res.dsc; 2207 if (dsc) 2208 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2209 2210 snprintf(rd_buf_ptr, str_len, 2211 "%d\n", 2212 dsc_state.dsc_chunk_size); 2213 rd_buf_ptr += str_len; 2214 2215 while (size) { 2216 if (*pos >= rd_buf_size) 2217 break; 2218 2219 r = put_user(*(rd_buf + result), buf); 2220 if (r) { 2221 kfree(rd_buf); 2222 return r; /* r = -EFAULT */ 2223 } 2224 2225 buf += 1; 2226 size -= 1; 2227 *pos += 1; 2228 result += 1; 2229 } 2230 2231 kfree(rd_buf); 2232 return result; 2233 } 2234 2235 /* function: read DSC slice bpg offset on the connector 2236 * 2237 * The read function: dp_dsc_slice_bpg_offset_read 2238 * returns dsc bpg slice offset set in the current configuration 2239 * The value is calculated automatically by DSC code 2240 * and depends on slice parameters and bpp target rate 2241 * The return is an integer: 0 or other positive integer 2242 * If 0 then DSC is disabled. 2243 * 2244 * Access it with the following command: 2245 * 2246 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2247 * 2248 * 0 - means that DSC is disabled 2249 */ 2250 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2251 size_t size, loff_t *pos) 2252 { 2253 char *rd_buf = NULL; 2254 char *rd_buf_ptr = NULL; 2255 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2256 struct display_stream_compressor *dsc; 2257 struct dcn_dsc_state dsc_state = {0}; 2258 const uint32_t rd_buf_size = 100; 2259 struct pipe_ctx *pipe_ctx; 2260 ssize_t result = 0; 2261 int i, r, str_len = 30; 2262 2263 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2264 2265 if (!rd_buf) 2266 return -ENOMEM; 2267 2268 rd_buf_ptr = rd_buf; 2269 2270 for (i = 0; i < MAX_PIPES; i++) { 2271 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2272 if (pipe_ctx->stream && 2273 pipe_ctx->stream->link == aconnector->dc_link) 2274 break; 2275 } 2276 2277 dsc = pipe_ctx->stream_res.dsc; 2278 if (dsc) 2279 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2280 2281 snprintf(rd_buf_ptr, str_len, 2282 "%d\n", 2283 dsc_state.dsc_slice_bpg_offset); 2284 rd_buf_ptr += str_len; 2285 2286 while (size) { 2287 if (*pos >= rd_buf_size) 2288 break; 2289 2290 r = put_user(*(rd_buf + result), buf); 2291 if (r) { 2292 kfree(rd_buf); 2293 return r; /* r = -EFAULT */ 2294 } 2295 2296 buf += 1; 2297 size -= 1; 2298 *pos += 1; 2299 result += 1; 2300 } 2301 2302 kfree(rd_buf); 2303 return result; 2304 } 2305 2306 2307 /* 2308 * function description: Read max_requested_bpc property from the connector 2309 * 2310 * Access it with the following command: 2311 * 2312 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2313 * 2314 */ 2315 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2316 size_t size, loff_t *pos) 2317 { 2318 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2319 struct drm_connector *connector = &aconnector->base; 2320 struct drm_device *dev = connector->dev; 2321 struct dm_connector_state *state; 2322 ssize_t result = 0; 2323 char *rd_buf = NULL; 2324 char *rd_buf_ptr = NULL; 2325 const uint32_t rd_buf_size = 10; 2326 int r; 2327 2328 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2329 2330 if (!rd_buf) 2331 return -ENOMEM; 2332 2333 mutex_lock(&dev->mode_config.mutex); 2334 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2335 2336 if (connector->state == NULL) 2337 goto unlock; 2338 2339 state = to_dm_connector_state(connector->state); 2340 2341 rd_buf_ptr = rd_buf; 2342 snprintf(rd_buf_ptr, rd_buf_size, 2343 "%u\n", 2344 state->base.max_requested_bpc); 2345 2346 while (size) { 2347 if (*pos >= rd_buf_size) 2348 break; 2349 2350 r = put_user(*(rd_buf + result), buf); 2351 if (r) { 2352 result = r; /* r = -EFAULT */ 2353 goto unlock; 2354 } 2355 buf += 1; 2356 size -= 1; 2357 *pos += 1; 2358 result += 1; 2359 } 2360 unlock: 2361 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2362 mutex_unlock(&dev->mode_config.mutex); 2363 kfree(rd_buf); 2364 return result; 2365 } 2366 2367 2368 /* 2369 * function description: Set max_requested_bpc property on the connector 2370 * 2371 * This function will not force the input BPC on connector, it will only 2372 * change the max value. This is equivalent to setting max_bpc through 2373 * xrandr. 2374 * 2375 * The BPC value written must be >= 6 and <= 16. Values outside of this 2376 * range will result in errors. 2377 * 2378 * BPC values: 2379 * 0x6 - 6 BPC 2380 * 0x8 - 8 BPC 2381 * 0xa - 10 BPC 2382 * 0xc - 12 BPC 2383 * 0x10 - 16 BPC 2384 * 2385 * Write the max_bpc in the following way: 2386 * 2387 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2388 * 2389 */ 2390 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2391 size_t size, loff_t *pos) 2392 { 2393 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2394 struct drm_connector *connector = &aconnector->base; 2395 struct dm_connector_state *state; 2396 struct drm_device *dev = connector->dev; 2397 char *wr_buf = NULL; 2398 uint32_t wr_buf_size = 42; 2399 int max_param_num = 1; 2400 long param[1] = {0}; 2401 uint8_t param_nums = 0; 2402 2403 if (size == 0) 2404 return -EINVAL; 2405 2406 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2407 2408 if (!wr_buf) { 2409 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2410 return -ENOSPC; 2411 } 2412 2413 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2414 (long *)param, buf, 2415 max_param_num, 2416 ¶m_nums)) { 2417 kfree(wr_buf); 2418 return -EINVAL; 2419 } 2420 2421 if (param_nums <= 0) { 2422 DRM_DEBUG_DRIVER("user data not be read\n"); 2423 kfree(wr_buf); 2424 return -EINVAL; 2425 } 2426 2427 if (param[0] < 6 || param[0] > 16) { 2428 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2429 kfree(wr_buf); 2430 return -EINVAL; 2431 } 2432 2433 mutex_lock(&dev->mode_config.mutex); 2434 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2435 2436 if (connector->state == NULL) 2437 goto unlock; 2438 2439 state = to_dm_connector_state(connector->state); 2440 state->base.max_requested_bpc = param[0]; 2441 unlock: 2442 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2443 mutex_unlock(&dev->mode_config.mutex); 2444 2445 kfree(wr_buf); 2446 return size; 2447 } 2448 2449 /* 2450 * Backlight at this moment. Read only. 2451 * As written to display, taking ABM and backlight lut into account. 2452 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2453 * 2454 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2455 */ 2456 static int current_backlight_show(struct seq_file *m, void *unused) 2457 { 2458 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2459 struct dc_link *link = aconnector->dc_link; 2460 unsigned int backlight; 2461 2462 backlight = dc_link_get_backlight_level(link); 2463 seq_printf(m, "0x%x\n", backlight); 2464 2465 return 0; 2466 } 2467 2468 /* 2469 * Backlight value that is being approached. Read only. 2470 * As written to display, taking ABM and backlight lut into account. 2471 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2472 * 2473 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2474 */ 2475 static int target_backlight_show(struct seq_file *m, void *unused) 2476 { 2477 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2478 struct dc_link *link = aconnector->dc_link; 2479 unsigned int backlight; 2480 2481 backlight = dc_link_get_target_backlight_pwm(link); 2482 seq_printf(m, "0x%x\n", backlight); 2483 2484 return 0; 2485 } 2486 2487 /* 2488 * function description: Determine if the connector is mst connector 2489 * 2490 * This function helps to determine whether a connector is a mst connector. 2491 * - "root" stands for the root connector of the topology 2492 * - "branch" stands for branch device of the topology 2493 * - "end" stands for leaf node connector of the topology 2494 * - "no" stands for the connector is not a device of a mst topology 2495 * Access it with the following command: 2496 * 2497 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2498 * 2499 */ 2500 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2501 { 2502 struct drm_connector *connector = m->private; 2503 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2504 struct drm_dp_mst_topology_mgr *mgr = NULL; 2505 struct drm_dp_mst_port *port = NULL; 2506 char *role = NULL; 2507 2508 mutex_lock(&aconnector->hpd_lock); 2509 2510 if (aconnector->mst_mgr.mst_state) { 2511 role = "root"; 2512 } else if (aconnector->mst_root && 2513 aconnector->mst_root->mst_mgr.mst_state) { 2514 2515 role = "end"; 2516 2517 mgr = &aconnector->mst_root->mst_mgr; 2518 port = aconnector->mst_output_port; 2519 2520 drm_modeset_lock(&mgr->base.lock, NULL); 2521 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2522 port->mcs) 2523 role = "branch"; 2524 drm_modeset_unlock(&mgr->base.lock); 2525 2526 } else { 2527 role = "no"; 2528 } 2529 2530 seq_printf(m, "%s\n", role); 2531 2532 mutex_unlock(&aconnector->hpd_lock); 2533 2534 return 0; 2535 } 2536 2537 /* 2538 * function description: Read out the mst progress status 2539 * 2540 * This function helps to determine the mst progress status of 2541 * a mst connector. 2542 * 2543 * Access it with the following command: 2544 * 2545 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2546 * 2547 */ 2548 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2549 { 2550 struct drm_connector *connector = m->private; 2551 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2552 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2553 int i; 2554 2555 mutex_lock(&aconnector->hpd_lock); 2556 mutex_lock(&adev->dm.dc_lock); 2557 2558 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2559 seq_puts(m, "disabled\n"); 2560 } else { 2561 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2562 seq_printf(m, "%s:%s\n", 2563 mst_progress_status[i], 2564 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2565 } 2566 2567 mutex_unlock(&adev->dm.dc_lock); 2568 mutex_unlock(&aconnector->hpd_lock); 2569 2570 return 0; 2571 } 2572 2573 /* 2574 * Reports whether the connected display is a USB4 DPIA tunneled display 2575 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2576 */ 2577 static int is_dpia_link_show(struct seq_file *m, void *data) 2578 { 2579 struct drm_connector *connector = m->private; 2580 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2581 struct dc_link *link = aconnector->dc_link; 2582 2583 if (connector->status != connector_status_connected) 2584 return -ENODEV; 2585 2586 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2587 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2588 2589 return 0; 2590 } 2591 2592 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2593 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2594 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2595 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2596 #ifdef CONFIG_DRM_AMD_DC_HDCP 2597 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2598 #endif 2599 DEFINE_SHOW_ATTRIBUTE(internal_display); 2600 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2601 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2602 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2603 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2604 2605 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2606 .owner = THIS_MODULE, 2607 .read = dp_dsc_clock_en_read, 2608 .write = dp_dsc_clock_en_write, 2609 .llseek = default_llseek 2610 }; 2611 2612 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2613 .owner = THIS_MODULE, 2614 .read = dp_dsc_slice_width_read, 2615 .write = dp_dsc_slice_width_write, 2616 .llseek = default_llseek 2617 }; 2618 2619 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2620 .owner = THIS_MODULE, 2621 .read = dp_dsc_slice_height_read, 2622 .write = dp_dsc_slice_height_write, 2623 .llseek = default_llseek 2624 }; 2625 2626 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2627 .owner = THIS_MODULE, 2628 .read = dp_dsc_bits_per_pixel_read, 2629 .write = dp_dsc_bits_per_pixel_write, 2630 .llseek = default_llseek 2631 }; 2632 2633 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2634 .owner = THIS_MODULE, 2635 .read = dp_dsc_pic_width_read, 2636 .llseek = default_llseek 2637 }; 2638 2639 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2640 .owner = THIS_MODULE, 2641 .read = dp_dsc_pic_height_read, 2642 .llseek = default_llseek 2643 }; 2644 2645 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2646 .owner = THIS_MODULE, 2647 .read = dp_dsc_chunk_size_read, 2648 .llseek = default_llseek 2649 }; 2650 2651 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2652 .owner = THIS_MODULE, 2653 .read = dp_dsc_slice_bpg_offset_read, 2654 .llseek = default_llseek 2655 }; 2656 2657 static const struct file_operations trigger_hotplug_debugfs_fops = { 2658 .owner = THIS_MODULE, 2659 .write = trigger_hotplug, 2660 .llseek = default_llseek 2661 }; 2662 2663 static const struct file_operations dp_link_settings_debugfs_fops = { 2664 .owner = THIS_MODULE, 2665 .read = dp_link_settings_read, 2666 .write = dp_link_settings_write, 2667 .llseek = default_llseek 2668 }; 2669 2670 static const struct file_operations dp_phy_settings_debugfs_fop = { 2671 .owner = THIS_MODULE, 2672 .read = dp_phy_settings_read, 2673 .write = dp_phy_settings_write, 2674 .llseek = default_llseek 2675 }; 2676 2677 static const struct file_operations dp_phy_test_pattern_fops = { 2678 .owner = THIS_MODULE, 2679 .write = dp_phy_test_pattern_debugfs_write, 2680 .llseek = default_llseek 2681 }; 2682 2683 static const struct file_operations sdp_message_fops = { 2684 .owner = THIS_MODULE, 2685 .write = dp_sdp_message_debugfs_write, 2686 .llseek = default_llseek 2687 }; 2688 2689 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2690 .owner = THIS_MODULE, 2691 .write = dp_dpcd_address_write, 2692 .llseek = default_llseek 2693 }; 2694 2695 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2696 .owner = THIS_MODULE, 2697 .write = dp_dpcd_size_write, 2698 .llseek = default_llseek 2699 }; 2700 2701 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2702 .owner = THIS_MODULE, 2703 .read = dp_dpcd_data_read, 2704 .write = dp_dpcd_data_write, 2705 .llseek = default_llseek 2706 }; 2707 2708 static const struct file_operations dp_max_bpc_debugfs_fops = { 2709 .owner = THIS_MODULE, 2710 .read = dp_max_bpc_read, 2711 .write = dp_max_bpc_write, 2712 .llseek = default_llseek 2713 }; 2714 2715 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2716 .owner = THIS_MODULE, 2717 .write = dp_dsc_passthrough_set, 2718 .llseek = default_llseek 2719 }; 2720 2721 static const struct { 2722 char *name; 2723 const struct file_operations *fops; 2724 } dp_debugfs_entries[] = { 2725 {"link_settings", &dp_link_settings_debugfs_fops}, 2726 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2727 {"lttpr_status", &dp_lttpr_status_fops}, 2728 {"test_pattern", &dp_phy_test_pattern_fops}, 2729 #ifdef CONFIG_DRM_AMD_DC_HDCP 2730 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2731 #endif 2732 {"sdp_message", &sdp_message_fops}, 2733 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2734 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2735 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2736 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2737 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2738 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2739 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2740 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2741 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2742 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2743 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2744 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2745 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2746 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2747 {"is_mst_connector", &dp_is_mst_connector_fops}, 2748 {"mst_progress_status", &dp_mst_progress_status_fops}, 2749 {"is_dpia_link", &is_dpia_link_fops} 2750 }; 2751 2752 #ifdef CONFIG_DRM_AMD_DC_HDCP 2753 static const struct { 2754 char *name; 2755 const struct file_operations *fops; 2756 } hdmi_debugfs_entries[] = { 2757 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2758 }; 2759 #endif 2760 /* 2761 * Force YUV420 output if available from the given mode 2762 */ 2763 static int force_yuv420_output_set(void *data, u64 val) 2764 { 2765 struct amdgpu_dm_connector *connector = data; 2766 2767 connector->force_yuv420_output = (bool)val; 2768 2769 return 0; 2770 } 2771 2772 /* 2773 * Check if YUV420 is forced when available from the given mode 2774 */ 2775 static int force_yuv420_output_get(void *data, u64 *val) 2776 { 2777 struct amdgpu_dm_connector *connector = data; 2778 2779 *val = connector->force_yuv420_output; 2780 2781 return 0; 2782 } 2783 2784 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2785 force_yuv420_output_set, "%llu\n"); 2786 2787 /* 2788 * Read PSR state 2789 */ 2790 static int psr_get(void *data, u64 *val) 2791 { 2792 struct amdgpu_dm_connector *connector = data; 2793 struct dc_link *link = connector->dc_link; 2794 enum dc_psr_state state = PSR_STATE0; 2795 2796 dc_link_get_psr_state(link, &state); 2797 2798 *val = state; 2799 2800 return 0; 2801 } 2802 2803 /* 2804 * Set dmcub trace event IRQ enable or disable. 2805 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2806 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2807 */ 2808 static int dmcub_trace_event_state_set(void *data, u64 val) 2809 { 2810 struct amdgpu_device *adev = data; 2811 2812 if (val == 1 || val == 0) { 2813 dc_dmub_trace_event_control(adev->dm.dc, val); 2814 adev->dm.dmcub_trace_event_en = (bool)val; 2815 } else 2816 return 0; 2817 2818 return 0; 2819 } 2820 2821 /* 2822 * The interface doesn't need get function, so it will return the 2823 * value of zero 2824 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2825 */ 2826 static int dmcub_trace_event_state_get(void *data, u64 *val) 2827 { 2828 struct amdgpu_device *adev = data; 2829 2830 *val = adev->dm.dmcub_trace_event_en; 2831 return 0; 2832 } 2833 2834 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2835 dmcub_trace_event_state_set, "%llu\n"); 2836 2837 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2838 2839 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2840 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2841 2842 static const struct { 2843 char *name; 2844 const struct file_operations *fops; 2845 } connector_debugfs_entries[] = { 2846 {"force_yuv420_output", &force_yuv420_output_fops}, 2847 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2848 {"internal_display", &internal_display_fops} 2849 }; 2850 2851 /* 2852 * Returns supported customized link rates by this eDP panel. 2853 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2854 */ 2855 static int edp_ilr_show(struct seq_file *m, void *unused) 2856 { 2857 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2858 struct dc_link *link = aconnector->dc_link; 2859 uint8_t supported_link_rates[16]; 2860 uint32_t link_rate_in_khz; 2861 uint32_t entry = 0; 2862 uint8_t dpcd_rev; 2863 2864 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2865 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2866 supported_link_rates, sizeof(supported_link_rates)); 2867 2868 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2869 2870 if (dpcd_rev >= DP_DPCD_REV_13 && 2871 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2872 2873 for (entry = 0; entry < 16; entry += 2) { 2874 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2875 supported_link_rates[entry]) * 200; 2876 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2877 } 2878 } else { 2879 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2880 } 2881 2882 return 0; 2883 } 2884 2885 /* 2886 * Set supported customized link rate to eDP panel. 2887 * 2888 * echo <lane_count> <link_rate option> > ilr_setting 2889 * 2890 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2891 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2892 * to set 4 lanes and 2.16 GHz 2893 */ 2894 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2895 size_t size, loff_t *pos) 2896 { 2897 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2898 struct dc_link *link = connector->dc_link; 2899 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2900 struct dc *dc = (struct dc *)link->dc; 2901 struct dc_link_settings prefer_link_settings; 2902 char *wr_buf = NULL; 2903 const uint32_t wr_buf_size = 40; 2904 /* 0: lane_count; 1: link_rate */ 2905 int max_param_num = 2; 2906 uint8_t param_nums = 0; 2907 long param[2]; 2908 bool valid_input = true; 2909 2910 if (size == 0) 2911 return -EINVAL; 2912 2913 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2914 if (!wr_buf) 2915 return -ENOMEM; 2916 2917 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2918 (long *)param, buf, 2919 max_param_num, 2920 ¶m_nums)) { 2921 kfree(wr_buf); 2922 return -EINVAL; 2923 } 2924 2925 if (param_nums <= 0) { 2926 kfree(wr_buf); 2927 return -EINVAL; 2928 } 2929 2930 switch (param[0]) { 2931 case LANE_COUNT_ONE: 2932 case LANE_COUNT_TWO: 2933 case LANE_COUNT_FOUR: 2934 break; 2935 default: 2936 valid_input = false; 2937 break; 2938 } 2939 2940 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2941 valid_input = false; 2942 2943 if (!valid_input) { 2944 kfree(wr_buf); 2945 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2946 prefer_link_settings.use_link_rate_set = false; 2947 mutex_lock(&adev->dm.dc_lock); 2948 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2949 mutex_unlock(&adev->dm.dc_lock); 2950 return size; 2951 } 2952 2953 /* save user force lane_count, link_rate to preferred settings 2954 * spread spectrum will not be changed 2955 */ 2956 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2957 prefer_link_settings.lane_count = param[0]; 2958 prefer_link_settings.use_link_rate_set = true; 2959 prefer_link_settings.link_rate_set = param[1]; 2960 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2961 2962 mutex_lock(&adev->dm.dc_lock); 2963 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2964 NULL, link, false); 2965 mutex_unlock(&adev->dm.dc_lock); 2966 2967 kfree(wr_buf); 2968 return size; 2969 } 2970 2971 static int edp_ilr_open(struct inode *inode, struct file *file) 2972 { 2973 return single_open(file, edp_ilr_show, inode->i_private); 2974 } 2975 2976 static const struct file_operations edp_ilr_debugfs_fops = { 2977 .owner = THIS_MODULE, 2978 .open = edp_ilr_open, 2979 .read = seq_read, 2980 .llseek = seq_lseek, 2981 .release = single_release, 2982 .write = edp_ilr_write 2983 }; 2984 2985 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2986 { 2987 int i; 2988 struct dentry *dir = connector->base.debugfs_entry; 2989 2990 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2991 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2992 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2993 debugfs_create_file(dp_debugfs_entries[i].name, 2994 0644, dir, connector, 2995 dp_debugfs_entries[i].fops); 2996 } 2997 } 2998 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2999 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3000 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3001 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3002 ¤t_backlight_fops); 3003 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3004 &target_backlight_fops); 3005 debugfs_create_file("ilr_setting", 0644, dir, connector, 3006 &edp_ilr_debugfs_fops); 3007 } 3008 3009 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3010 debugfs_create_file(connector_debugfs_entries[i].name, 3011 0644, dir, connector, 3012 connector_debugfs_entries[i].fops); 3013 } 3014 3015 connector->debugfs_dpcd_address = 0; 3016 connector->debugfs_dpcd_size = 0; 3017 3018 #ifdef CONFIG_DRM_AMD_DC_HDCP 3019 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3020 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3021 debugfs_create_file(hdmi_debugfs_entries[i].name, 3022 0644, dir, connector, 3023 hdmi_debugfs_entries[i].fops); 3024 } 3025 } 3026 #endif 3027 } 3028 3029 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3030 /* 3031 * Set crc window coordinate x start 3032 */ 3033 static int crc_win_x_start_set(void *data, u64 val) 3034 { 3035 struct drm_crtc *crtc = data; 3036 struct drm_device *drm_dev = crtc->dev; 3037 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3038 3039 spin_lock_irq(&drm_dev->event_lock); 3040 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3041 acrtc->dm_irq_params.window_param.update_win = false; 3042 spin_unlock_irq(&drm_dev->event_lock); 3043 3044 return 0; 3045 } 3046 3047 /* 3048 * Get crc window coordinate x start 3049 */ 3050 static int crc_win_x_start_get(void *data, u64 *val) 3051 { 3052 struct drm_crtc *crtc = data; 3053 struct drm_device *drm_dev = crtc->dev; 3054 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3055 3056 spin_lock_irq(&drm_dev->event_lock); 3057 *val = acrtc->dm_irq_params.window_param.x_start; 3058 spin_unlock_irq(&drm_dev->event_lock); 3059 3060 return 0; 3061 } 3062 3063 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3064 crc_win_x_start_set, "%llu\n"); 3065 3066 3067 /* 3068 * Set crc window coordinate y start 3069 */ 3070 static int crc_win_y_start_set(void *data, u64 val) 3071 { 3072 struct drm_crtc *crtc = data; 3073 struct drm_device *drm_dev = crtc->dev; 3074 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3075 3076 spin_lock_irq(&drm_dev->event_lock); 3077 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3078 acrtc->dm_irq_params.window_param.update_win = false; 3079 spin_unlock_irq(&drm_dev->event_lock); 3080 3081 return 0; 3082 } 3083 3084 /* 3085 * Get crc window coordinate y start 3086 */ 3087 static int crc_win_y_start_get(void *data, u64 *val) 3088 { 3089 struct drm_crtc *crtc = data; 3090 struct drm_device *drm_dev = crtc->dev; 3091 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3092 3093 spin_lock_irq(&drm_dev->event_lock); 3094 *val = acrtc->dm_irq_params.window_param.y_start; 3095 spin_unlock_irq(&drm_dev->event_lock); 3096 3097 return 0; 3098 } 3099 3100 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3101 crc_win_y_start_set, "%llu\n"); 3102 3103 /* 3104 * Set crc window coordinate x end 3105 */ 3106 static int crc_win_x_end_set(void *data, u64 val) 3107 { 3108 struct drm_crtc *crtc = data; 3109 struct drm_device *drm_dev = crtc->dev; 3110 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3111 3112 spin_lock_irq(&drm_dev->event_lock); 3113 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3114 acrtc->dm_irq_params.window_param.update_win = false; 3115 spin_unlock_irq(&drm_dev->event_lock); 3116 3117 return 0; 3118 } 3119 3120 /* 3121 * Get crc window coordinate x end 3122 */ 3123 static int crc_win_x_end_get(void *data, u64 *val) 3124 { 3125 struct drm_crtc *crtc = data; 3126 struct drm_device *drm_dev = crtc->dev; 3127 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3128 3129 spin_lock_irq(&drm_dev->event_lock); 3130 *val = acrtc->dm_irq_params.window_param.x_end; 3131 spin_unlock_irq(&drm_dev->event_lock); 3132 3133 return 0; 3134 } 3135 3136 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3137 crc_win_x_end_set, "%llu\n"); 3138 3139 /* 3140 * Set crc window coordinate y end 3141 */ 3142 static int crc_win_y_end_set(void *data, u64 val) 3143 { 3144 struct drm_crtc *crtc = data; 3145 struct drm_device *drm_dev = crtc->dev; 3146 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3147 3148 spin_lock_irq(&drm_dev->event_lock); 3149 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3150 acrtc->dm_irq_params.window_param.update_win = false; 3151 spin_unlock_irq(&drm_dev->event_lock); 3152 3153 return 0; 3154 } 3155 3156 /* 3157 * Get crc window coordinate y end 3158 */ 3159 static int crc_win_y_end_get(void *data, u64 *val) 3160 { 3161 struct drm_crtc *crtc = data; 3162 struct drm_device *drm_dev = crtc->dev; 3163 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3164 3165 spin_lock_irq(&drm_dev->event_lock); 3166 *val = acrtc->dm_irq_params.window_param.y_end; 3167 spin_unlock_irq(&drm_dev->event_lock); 3168 3169 return 0; 3170 } 3171 3172 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3173 crc_win_y_end_set, "%llu\n"); 3174 /* 3175 * Trigger to commit crc window 3176 */ 3177 static int crc_win_update_set(void *data, u64 val) 3178 { 3179 struct drm_crtc *crtc = data; 3180 struct amdgpu_crtc *acrtc; 3181 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3182 3183 if (val) { 3184 acrtc = to_amdgpu_crtc(crtc); 3185 mutex_lock(&adev->dm.dc_lock); 3186 /* PSR may write to OTG CRC window control register, 3187 * so close it before starting secure_display. 3188 */ 3189 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3190 3191 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3192 3193 acrtc->dm_irq_params.window_param.activated = true; 3194 acrtc->dm_irq_params.window_param.update_win = true; 3195 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3196 3197 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3198 mutex_unlock(&adev->dm.dc_lock); 3199 } 3200 3201 return 0; 3202 } 3203 3204 /* 3205 * Get crc window update flag 3206 */ 3207 static int crc_win_update_get(void *data, u64 *val) 3208 { 3209 *val = 0; 3210 return 0; 3211 } 3212 3213 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3214 crc_win_update_set, "%llu\n"); 3215 #endif 3216 void crtc_debugfs_init(struct drm_crtc *crtc) 3217 { 3218 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3219 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3220 3221 if (!dir) 3222 return; 3223 3224 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3225 &crc_win_x_start_fops); 3226 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3227 &crc_win_y_start_fops); 3228 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3229 &crc_win_x_end_fops); 3230 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3231 &crc_win_y_end_fops); 3232 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3233 &crc_win_update_fops); 3234 dput(dir); 3235 #endif 3236 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3237 crtc, &amdgpu_current_bpc_fops); 3238 } 3239 3240 /* 3241 * Writes DTN log state to the user supplied buffer. 3242 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3243 */ 3244 static ssize_t dtn_log_read( 3245 struct file *f, 3246 char __user *buf, 3247 size_t size, 3248 loff_t *pos) 3249 { 3250 struct amdgpu_device *adev = file_inode(f)->i_private; 3251 struct dc *dc = adev->dm.dc; 3252 struct dc_log_buffer_ctx log_ctx = { 0 }; 3253 ssize_t result = 0; 3254 3255 if (!buf || !size) 3256 return -EINVAL; 3257 3258 if (!dc->hwss.log_hw_state) 3259 return 0; 3260 3261 dc->hwss.log_hw_state(dc, &log_ctx); 3262 3263 if (*pos < log_ctx.pos) { 3264 size_t to_copy = log_ctx.pos - *pos; 3265 3266 to_copy = min(to_copy, size); 3267 3268 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3269 *pos += to_copy; 3270 result = to_copy; 3271 } 3272 } 3273 3274 kfree(log_ctx.buf); 3275 3276 return result; 3277 } 3278 3279 /* 3280 * Writes DTN log state to dmesg when triggered via a write. 3281 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3282 */ 3283 static ssize_t dtn_log_write( 3284 struct file *f, 3285 const char __user *buf, 3286 size_t size, 3287 loff_t *pos) 3288 { 3289 struct amdgpu_device *adev = file_inode(f)->i_private; 3290 struct dc *dc = adev->dm.dc; 3291 3292 /* Write triggers log output via dmesg. */ 3293 if (size == 0) 3294 return 0; 3295 3296 if (dc->hwss.log_hw_state) 3297 dc->hwss.log_hw_state(dc, NULL); 3298 3299 return size; 3300 } 3301 3302 static int mst_topo_show(struct seq_file *m, void *unused) 3303 { 3304 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3305 struct drm_device *dev = adev_to_drm(adev); 3306 struct drm_connector *connector; 3307 struct drm_connector_list_iter conn_iter; 3308 struct amdgpu_dm_connector *aconnector; 3309 3310 drm_connector_list_iter_begin(dev, &conn_iter); 3311 drm_for_each_connector_iter(connector, &conn_iter) { 3312 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3313 continue; 3314 3315 aconnector = to_amdgpu_dm_connector(connector); 3316 3317 /* Ensure we're only dumping the topology of a root mst node */ 3318 if (!aconnector->mst_mgr.mst_state) 3319 continue; 3320 3321 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3322 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3323 } 3324 drm_connector_list_iter_end(&conn_iter); 3325 3326 return 0; 3327 } 3328 3329 /* 3330 * Sets trigger hpd for MST topologies. 3331 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3332 * All topologies will be disconnected if val of 0 is set . 3333 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3334 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3335 */ 3336 static int trigger_hpd_mst_set(void *data, u64 val) 3337 { 3338 struct amdgpu_device *adev = data; 3339 struct drm_device *dev = adev_to_drm(adev); 3340 struct drm_connector_list_iter iter; 3341 struct amdgpu_dm_connector *aconnector; 3342 struct drm_connector *connector; 3343 struct dc_link *link = NULL; 3344 3345 if (val == 1) { 3346 drm_connector_list_iter_begin(dev, &iter); 3347 drm_for_each_connector_iter(connector, &iter) { 3348 aconnector = to_amdgpu_dm_connector(connector); 3349 if (aconnector->dc_link->type == dc_connection_mst_branch && 3350 aconnector->mst_mgr.aux) { 3351 mutex_lock(&adev->dm.dc_lock); 3352 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3353 mutex_unlock(&adev->dm.dc_lock); 3354 3355 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3356 } 3357 } 3358 } else if (val == 0) { 3359 drm_connector_list_iter_begin(dev, &iter); 3360 drm_for_each_connector_iter(connector, &iter) { 3361 aconnector = to_amdgpu_dm_connector(connector); 3362 if (!aconnector->dc_link) 3363 continue; 3364 3365 if (!aconnector->mst_root) 3366 continue; 3367 3368 link = aconnector->dc_link; 3369 dc_link_dp_receiver_power_ctrl(link, false); 3370 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3371 link->mst_stream_alloc_table.stream_count = 0; 3372 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3373 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3374 } 3375 } else { 3376 return 0; 3377 } 3378 drm_kms_helper_hotplug_event(dev); 3379 3380 return 0; 3381 } 3382 3383 /* 3384 * The interface doesn't need get function, so it will return the 3385 * value of zero 3386 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3387 */ 3388 static int trigger_hpd_mst_get(void *data, u64 *val) 3389 { 3390 *val = 0; 3391 return 0; 3392 } 3393 3394 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3395 trigger_hpd_mst_set, "%llu\n"); 3396 3397 3398 /* 3399 * Sets the force_timing_sync debug option from the given string. 3400 * All connected displays will be force synchronized immediately. 3401 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3402 */ 3403 static int force_timing_sync_set(void *data, u64 val) 3404 { 3405 struct amdgpu_device *adev = data; 3406 3407 adev->dm.force_timing_sync = (bool)val; 3408 3409 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3410 3411 return 0; 3412 } 3413 3414 /* 3415 * Gets the force_timing_sync debug option value into the given buffer. 3416 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3417 */ 3418 static int force_timing_sync_get(void *data, u64 *val) 3419 { 3420 struct amdgpu_device *adev = data; 3421 3422 *val = adev->dm.force_timing_sync; 3423 3424 return 0; 3425 } 3426 3427 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3428 force_timing_sync_set, "%llu\n"); 3429 3430 3431 /* 3432 * Disables all HPD and HPD RX interrupt handling in the 3433 * driver when set to 1. Default is 0. 3434 */ 3435 static int disable_hpd_set(void *data, u64 val) 3436 { 3437 struct amdgpu_device *adev = data; 3438 3439 adev->dm.disable_hpd_irq = (bool)val; 3440 3441 return 0; 3442 } 3443 3444 3445 /* 3446 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3447 * 0 otherwise. 3448 */ 3449 static int disable_hpd_get(void *data, u64 *val) 3450 { 3451 struct amdgpu_device *adev = data; 3452 3453 *val = adev->dm.disable_hpd_irq; 3454 3455 return 0; 3456 } 3457 3458 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3459 disable_hpd_set, "%llu\n"); 3460 3461 /* 3462 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3463 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3464 */ 3465 static int dp_force_sst_set(void *data, u64 val) 3466 { 3467 struct amdgpu_device *adev = data; 3468 3469 adev->dm.dc->debug.set_mst_en_for_sst = val; 3470 3471 return 0; 3472 } 3473 3474 static int dp_force_sst_get(void *data, u64 *val) 3475 { 3476 struct amdgpu_device *adev = data; 3477 3478 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3479 3480 return 0; 3481 } 3482 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3483 dp_force_sst_set, "%llu\n"); 3484 3485 /* 3486 * Force DP2 sequence without VESA certified cable. 3487 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3488 */ 3489 static int dp_ignore_cable_id_set(void *data, u64 val) 3490 { 3491 struct amdgpu_device *adev = data; 3492 3493 adev->dm.dc->debug.ignore_cable_id = val; 3494 3495 return 0; 3496 } 3497 3498 static int dp_ignore_cable_id_get(void *data, u64 *val) 3499 { 3500 struct amdgpu_device *adev = data; 3501 3502 *val = adev->dm.dc->debug.ignore_cable_id; 3503 3504 return 0; 3505 } 3506 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3507 dp_ignore_cable_id_set, "%llu\n"); 3508 3509 /* 3510 * Sets the DC visual confirm debug option from the given string. 3511 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3512 */ 3513 static int visual_confirm_set(void *data, u64 val) 3514 { 3515 struct amdgpu_device *adev = data; 3516 3517 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3518 3519 return 0; 3520 } 3521 3522 /* 3523 * Reads the DC visual confirm debug option value into the given buffer. 3524 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3525 */ 3526 static int visual_confirm_get(void *data, u64 *val) 3527 { 3528 struct amdgpu_device *adev = data; 3529 3530 *val = adev->dm.dc->debug.visual_confirm; 3531 3532 return 0; 3533 } 3534 3535 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3536 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3537 visual_confirm_set, "%llu\n"); 3538 3539 3540 /* 3541 * Sets the DC skip_detection_link_training debug option from the given string. 3542 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3543 */ 3544 static int skip_detection_link_training_set(void *data, u64 val) 3545 { 3546 struct amdgpu_device *adev = data; 3547 3548 if (val == 0) 3549 adev->dm.dc->debug.skip_detection_link_training = false; 3550 else 3551 adev->dm.dc->debug.skip_detection_link_training = true; 3552 3553 return 0; 3554 } 3555 3556 /* 3557 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3558 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3559 */ 3560 static int skip_detection_link_training_get(void *data, u64 *val) 3561 { 3562 struct amdgpu_device *adev = data; 3563 3564 *val = adev->dm.dc->debug.skip_detection_link_training; 3565 3566 return 0; 3567 } 3568 3569 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3570 skip_detection_link_training_get, 3571 skip_detection_link_training_set, "%llu\n"); 3572 3573 /* 3574 * Dumps the DCC_EN bit for each pipe. 3575 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3576 */ 3577 static ssize_t dcc_en_bits_read( 3578 struct file *f, 3579 char __user *buf, 3580 size_t size, 3581 loff_t *pos) 3582 { 3583 struct amdgpu_device *adev = file_inode(f)->i_private; 3584 struct dc *dc = adev->dm.dc; 3585 char *rd_buf = NULL; 3586 const uint32_t rd_buf_size = 32; 3587 uint32_t result = 0; 3588 int offset = 0; 3589 int num_pipes = dc->res_pool->pipe_count; 3590 int *dcc_en_bits; 3591 int i, r; 3592 3593 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3594 if (!dcc_en_bits) 3595 return -ENOMEM; 3596 3597 if (!dc->hwss.get_dcc_en_bits) { 3598 kfree(dcc_en_bits); 3599 return 0; 3600 } 3601 3602 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3603 3604 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3605 if (!rd_buf) { 3606 kfree(dcc_en_bits); 3607 return -ENOMEM; 3608 } 3609 3610 for (i = 0; i < num_pipes; i++) 3611 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3612 "%d ", dcc_en_bits[i]); 3613 rd_buf[strlen(rd_buf)] = '\n'; 3614 3615 kfree(dcc_en_bits); 3616 3617 while (size) { 3618 if (*pos >= rd_buf_size) 3619 break; 3620 r = put_user(*(rd_buf + result), buf); 3621 if (r) { 3622 kfree(rd_buf); 3623 return r; /* r = -EFAULT */ 3624 } 3625 buf += 1; 3626 size -= 1; 3627 *pos += 1; 3628 result += 1; 3629 } 3630 3631 kfree(rd_buf); 3632 return result; 3633 } 3634 3635 void dtn_debugfs_init(struct amdgpu_device *adev) 3636 { 3637 static const struct file_operations dtn_log_fops = { 3638 .owner = THIS_MODULE, 3639 .read = dtn_log_read, 3640 .write = dtn_log_write, 3641 .llseek = default_llseek 3642 }; 3643 static const struct file_operations dcc_en_bits_fops = { 3644 .owner = THIS_MODULE, 3645 .read = dcc_en_bits_read, 3646 .llseek = default_llseek 3647 }; 3648 3649 struct drm_minor *minor = adev_to_drm(adev)->primary; 3650 struct dentry *root = minor->debugfs_root; 3651 3652 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3653 adev, &mst_topo_fops); 3654 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3655 &dtn_log_fops); 3656 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3657 &dp_set_mst_en_for_sst_ops); 3658 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3659 &dp_ignore_cable_id_ops); 3660 3661 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3662 &visual_confirm_fops); 3663 3664 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3665 &skip_detection_link_training_fops); 3666 3667 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3668 adev, &dmub_tracebuffer_fops); 3669 3670 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3671 adev, &dmub_fw_state_fops); 3672 3673 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3674 adev, &force_timing_sync_ops); 3675 3676 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3677 adev, &dmcub_trace_event_state_fops); 3678 3679 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3680 adev, &trigger_hpd_mst_ops); 3681 3682 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3683 &dcc_en_bits_fops); 3684 3685 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3686 &disable_hpd_ops); 3687 3688 } 3689