1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 40 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 41 #include "amdgpu_dm_psr.h" 42 #endif 43 44 struct dmub_debugfs_trace_header { 45 uint32_t entry_count; 46 uint32_t reserved[3]; 47 }; 48 49 struct dmub_debugfs_trace_entry { 50 uint32_t trace_code; 51 uint32_t tick_count; 52 uint32_t param0; 53 uint32_t param1; 54 }; 55 56 static const char *const mst_progress_status[] = { 57 "probe", 58 "remote_edid", 59 "allocate_new_payload", 60 "clear_allocated_payload", 61 }; 62 63 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 64 * 65 * Function takes in attributes passed to debugfs write entry 66 * and writes into param array. 67 * The user passes max_param_num to identify maximum number of 68 * parameters that could be parsed. 69 * 70 */ 71 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 72 long *param, const char __user *buf, 73 int max_param_num, 74 uint8_t *param_nums) 75 { 76 char *wr_buf_ptr = NULL; 77 uint32_t wr_buf_count = 0; 78 int r; 79 char *sub_str = NULL; 80 const char delimiter[3] = {' ', '\n', '\0'}; 81 uint8_t param_index = 0; 82 83 *param_nums = 0; 84 85 wr_buf_ptr = wr_buf; 86 87 /* r is bytes not be copied */ 88 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 89 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 90 return -EFAULT; 91 } 92 93 /* check number of parameters. isspace could not differ space and \n */ 94 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 95 /* skip space*/ 96 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 97 wr_buf_ptr++; 98 wr_buf_count++; 99 } 100 101 if (wr_buf_count == wr_buf_size) 102 break; 103 104 /* skip non-space*/ 105 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 106 wr_buf_ptr++; 107 wr_buf_count++; 108 } 109 110 (*param_nums)++; 111 112 if (wr_buf_count == wr_buf_size) 113 break; 114 } 115 116 if (*param_nums > max_param_num) 117 *param_nums = max_param_num; 118 119 wr_buf_ptr = wr_buf; /* reset buf pointer */ 120 wr_buf_count = 0; /* number of char already checked */ 121 122 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 123 wr_buf_ptr++; 124 wr_buf_count++; 125 } 126 127 while (param_index < *param_nums) { 128 /* after strsep, wr_buf_ptr will be moved to after space */ 129 sub_str = strsep(&wr_buf_ptr, delimiter); 130 131 r = kstrtol(sub_str, 16, &(param[param_index])); 132 133 if (r) 134 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 135 136 param_index++; 137 } 138 139 return 0; 140 } 141 142 /* function description 143 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 144 * 145 * valid lane count value: 1, 2, 4 146 * valid link rate value: 147 * 06h = 1.62Gbps per lane 148 * 0Ah = 2.7Gbps per lane 149 * 0Ch = 3.24Gbps per lane 150 * 14h = 5.4Gbps per lane 151 * 1Eh = 8.1Gbps per lane 152 * 153 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 154 * 155 * --- to get dp configuration 156 * 157 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 158 * 159 * It will list current, verified, reported, preferred dp configuration. 160 * current -- for current video mode 161 * verified --- maximum configuration which pass link training 162 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 163 * preferred --- user force settings 164 * 165 * --- set (or force) dp configuration 166 * 167 * echo <lane_count> <link_rate> > link_settings 168 * 169 * for example, to force to 2 lane, 2.7GHz, 170 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 171 * 172 * spread_spectrum could not be changed dynamically. 173 * 174 * in case invalid lane count, link rate are force, no hw programming will be 175 * done. please check link settings after force operation to see if HW get 176 * programming. 177 * 178 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 179 * 180 * check current and preferred settings. 181 * 182 */ 183 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 184 size_t size, loff_t *pos) 185 { 186 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 187 struct dc_link *link = connector->dc_link; 188 char *rd_buf = NULL; 189 char *rd_buf_ptr = NULL; 190 const uint32_t rd_buf_size = 100; 191 uint32_t result = 0; 192 uint8_t str_len = 0; 193 int r; 194 195 if (*pos & 3 || size & 3) 196 return -EINVAL; 197 198 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 199 if (!rd_buf) 200 return 0; 201 202 rd_buf_ptr = rd_buf; 203 204 str_len = strlen("Current: %d 0x%x %d "); 205 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 206 link->cur_link_settings.lane_count, 207 link->cur_link_settings.link_rate, 208 link->cur_link_settings.link_spread); 209 rd_buf_ptr += str_len; 210 211 str_len = strlen("Verified: %d 0x%x %d "); 212 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 213 link->verified_link_cap.lane_count, 214 link->verified_link_cap.link_rate, 215 link->verified_link_cap.link_spread); 216 rd_buf_ptr += str_len; 217 218 str_len = strlen("Reported: %d 0x%x %d "); 219 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 220 link->reported_link_cap.lane_count, 221 link->reported_link_cap.link_rate, 222 link->reported_link_cap.link_spread); 223 rd_buf_ptr += str_len; 224 225 str_len = strlen("Preferred: %d 0x%x %d "); 226 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 227 link->preferred_link_setting.lane_count, 228 link->preferred_link_setting.link_rate, 229 link->preferred_link_setting.link_spread); 230 231 while (size) { 232 if (*pos >= rd_buf_size) 233 break; 234 235 r = put_user(*(rd_buf + result), buf); 236 if (r) { 237 kfree(rd_buf); 238 return r; /* r = -EFAULT */ 239 } 240 241 buf += 1; 242 size -= 1; 243 *pos += 1; 244 result += 1; 245 } 246 247 kfree(rd_buf); 248 return result; 249 } 250 251 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 252 size_t size, loff_t *pos) 253 { 254 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 255 struct dc_link *link = connector->dc_link; 256 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 257 struct dc *dc = (struct dc *)link->dc; 258 struct dc_link_settings prefer_link_settings; 259 char *wr_buf = NULL; 260 const uint32_t wr_buf_size = 40; 261 /* 0: lane_count; 1: link_rate */ 262 int max_param_num = 2; 263 uint8_t param_nums = 0; 264 long param[2]; 265 bool valid_input = true; 266 267 if (size == 0) 268 return -EINVAL; 269 270 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 271 if (!wr_buf) 272 return -ENOSPC; 273 274 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 275 (long *)param, buf, 276 max_param_num, 277 ¶m_nums)) { 278 kfree(wr_buf); 279 return -EINVAL; 280 } 281 282 if (param_nums <= 0) { 283 kfree(wr_buf); 284 DRM_DEBUG_DRIVER("user data not be read\n"); 285 return -EINVAL; 286 } 287 288 switch (param[0]) { 289 case LANE_COUNT_ONE: 290 case LANE_COUNT_TWO: 291 case LANE_COUNT_FOUR: 292 break; 293 default: 294 valid_input = false; 295 break; 296 } 297 298 switch (param[1]) { 299 case LINK_RATE_LOW: 300 case LINK_RATE_HIGH: 301 case LINK_RATE_RBR2: 302 case LINK_RATE_HIGH2: 303 case LINK_RATE_HIGH3: 304 case LINK_RATE_UHBR10: 305 case LINK_RATE_UHBR13_5: 306 case LINK_RATE_UHBR20: 307 break; 308 default: 309 valid_input = false; 310 break; 311 } 312 313 if (!valid_input) { 314 kfree(wr_buf); 315 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 316 mutex_lock(&adev->dm.dc_lock); 317 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 318 mutex_unlock(&adev->dm.dc_lock); 319 return size; 320 } 321 322 /* save user force lane_count, link_rate to preferred settings 323 * spread spectrum will not be changed 324 */ 325 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 326 prefer_link_settings.use_link_rate_set = false; 327 prefer_link_settings.lane_count = param[0]; 328 prefer_link_settings.link_rate = param[1]; 329 330 mutex_lock(&adev->dm.dc_lock); 331 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 332 mutex_unlock(&adev->dm.dc_lock); 333 334 kfree(wr_buf); 335 return size; 336 } 337 338 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 339 * post-cursor2 (defined by VESA DP specification) 340 * 341 * valid values 342 * voltage swing: 0,1,2,3 343 * pre-emphasis : 0,1,2,3 344 * post cursor2 : 0,1,2,3 345 * 346 * 347 * how to use this debugfs 348 * 349 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 350 * 351 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 352 * 353 * To figure out which DP-x is the display for DP to be check, 354 * cd DP-x 355 * ls -ll 356 * There should be debugfs file, like link_settings, phy_settings. 357 * cat link_settings 358 * from lane_count, link_rate to figure which DP-x is for display to be worked 359 * on 360 * 361 * To get current DP PHY settings, 362 * cat phy_settings 363 * 364 * To change DP PHY settings, 365 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 366 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 367 * 0, 368 * echo 2 3 0 > phy_settings 369 * 370 * To check if change be applied, get current phy settings by 371 * cat phy_settings 372 * 373 * In case invalid values are set by user, like 374 * echo 1 4 0 > phy_settings 375 * 376 * HW will NOT be programmed by these settings. 377 * cat phy_settings will show the previous valid settings. 378 */ 379 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 380 size_t size, loff_t *pos) 381 { 382 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 383 struct dc_link *link = connector->dc_link; 384 char *rd_buf = NULL; 385 const uint32_t rd_buf_size = 20; 386 uint32_t result = 0; 387 int r; 388 389 if (*pos & 3 || size & 3) 390 return -EINVAL; 391 392 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 393 if (!rd_buf) 394 return -EINVAL; 395 396 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 397 link->cur_lane_setting[0].VOLTAGE_SWING, 398 link->cur_lane_setting[0].PRE_EMPHASIS, 399 link->cur_lane_setting[0].POST_CURSOR2); 400 401 while (size) { 402 if (*pos >= rd_buf_size) 403 break; 404 405 r = put_user((*(rd_buf + result)), buf); 406 if (r) { 407 kfree(rd_buf); 408 return r; /* r = -EFAULT */ 409 } 410 411 buf += 1; 412 size -= 1; 413 *pos += 1; 414 result += 1; 415 } 416 417 kfree(rd_buf); 418 return result; 419 } 420 421 static int dp_lttpr_status_show(struct seq_file *m, void *d) 422 { 423 char *data; 424 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 425 struct dc_link *link = connector->dc_link; 426 uint32_t read_size = 1; 427 uint8_t repeater_count = 0; 428 429 data = kzalloc(read_size, GFP_KERNEL); 430 if (!data) 431 return 0; 432 433 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 434 435 switch ((uint8_t)*data) { 436 case 0x80: 437 repeater_count = 1; 438 break; 439 case 0x40: 440 repeater_count = 2; 441 break; 442 case 0x20: 443 repeater_count = 3; 444 break; 445 case 0x10: 446 repeater_count = 4; 447 break; 448 case 0x8: 449 repeater_count = 5; 450 break; 451 case 0x4: 452 repeater_count = 6; 453 break; 454 case 0x2: 455 repeater_count = 7; 456 break; 457 case 0x1: 458 repeater_count = 8; 459 break; 460 case 0x0: 461 repeater_count = 0; 462 break; 463 default: 464 repeater_count = (uint8_t)*data; 465 break; 466 } 467 468 seq_printf(m, "phy repeater count: %d\n", repeater_count); 469 470 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 471 472 if ((uint8_t)*data == 0x55) 473 seq_printf(m, "phy repeater mode: transparent\n"); 474 else if ((uint8_t)*data == 0xAA) 475 seq_printf(m, "phy repeater mode: non-transparent\n"); 476 else if ((uint8_t)*data == 0x00) 477 seq_printf(m, "phy repeater mode: non lttpr\n"); 478 else 479 seq_printf(m, "phy repeater mode: read error\n"); 480 481 kfree(data); 482 return 0; 483 } 484 485 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 486 size_t size, loff_t *pos) 487 { 488 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 489 struct dc_link *link = connector->dc_link; 490 struct dc *dc = (struct dc *)link->dc; 491 char *wr_buf = NULL; 492 uint32_t wr_buf_size = 40; 493 long param[3]; 494 bool use_prefer_link_setting; 495 struct link_training_settings link_lane_settings; 496 int max_param_num = 3; 497 uint8_t param_nums = 0; 498 int r = 0; 499 500 501 if (size == 0) 502 return -EINVAL; 503 504 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 505 if (!wr_buf) 506 return -ENOSPC; 507 508 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 509 (long *)param, buf, 510 max_param_num, 511 ¶m_nums)) { 512 kfree(wr_buf); 513 return -EINVAL; 514 } 515 516 if (param_nums <= 0) { 517 kfree(wr_buf); 518 DRM_DEBUG_DRIVER("user data not be read\n"); 519 return -EINVAL; 520 } 521 522 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 523 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 524 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 525 kfree(wr_buf); 526 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 527 return size; 528 } 529 530 /* get link settings: lane count, link rate */ 531 use_prefer_link_setting = 532 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 533 (link->test_pattern_enabled)); 534 535 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 536 537 if (use_prefer_link_setting) { 538 link_lane_settings.link_settings.lane_count = 539 link->preferred_link_setting.lane_count; 540 link_lane_settings.link_settings.link_rate = 541 link->preferred_link_setting.link_rate; 542 link_lane_settings.link_settings.link_spread = 543 link->preferred_link_setting.link_spread; 544 } else { 545 link_lane_settings.link_settings.lane_count = 546 link->cur_link_settings.lane_count; 547 link_lane_settings.link_settings.link_rate = 548 link->cur_link_settings.link_rate; 549 link_lane_settings.link_settings.link_spread = 550 link->cur_link_settings.link_spread; 551 } 552 553 /* apply phy settings from user */ 554 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 555 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 556 (enum dc_voltage_swing) (param[0]); 557 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 558 (enum dc_pre_emphasis) (param[1]); 559 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 560 (enum dc_post_cursor2) (param[2]); 561 } 562 563 /* program ASIC registers and DPCD registers */ 564 dc_link_set_drive_settings(dc, &link_lane_settings, link); 565 566 kfree(wr_buf); 567 return size; 568 } 569 570 /* function description 571 * 572 * set PHY layer or Link layer test pattern 573 * PHY test pattern is used for PHY SI check. 574 * Link layer test will not affect PHY SI. 575 * 576 * Reset Test Pattern: 577 * 0 = DP_TEST_PATTERN_VIDEO_MODE 578 * 579 * PHY test pattern supported: 580 * 1 = DP_TEST_PATTERN_D102 581 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 582 * 3 = DP_TEST_PATTERN_PRBS7 583 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 584 * 5 = DP_TEST_PATTERN_CP2520_1 585 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 586 * 7 = DP_TEST_PATTERN_CP2520_3 587 * 588 * DP PHY Link Training Patterns 589 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 590 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 591 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 592 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 593 * 594 * DP Link Layer Test pattern 595 * c = DP_TEST_PATTERN_COLOR_SQUARES 596 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 597 * e = DP_TEST_PATTERN_VERTICAL_BARS 598 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 599 * 10= DP_TEST_PATTERN_COLOR_RAMP 600 * 601 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 602 * 603 * --- set test pattern 604 * echo <test pattern #> > test_pattern 605 * 606 * If test pattern # is not supported, NO HW programming will be done. 607 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 608 * for the user pattern. input 10 bytes data are separated by space 609 * 610 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 611 * 612 * --- reset test pattern 613 * echo 0 > test_pattern 614 * 615 * --- HPD detection is disabled when set PHY test pattern 616 * 617 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 618 * is disable. User could unplug DP display from DP connected and plug scope to 619 * check test pattern PHY SI. 620 * If there is need unplug scope and plug DP display back, do steps below: 621 * echo 0 > phy_test_pattern 622 * unplug scope 623 * plug DP display. 624 * 625 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 626 * driver could detect "unplug scope" and "plug DP display" 627 */ 628 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 629 size_t size, loff_t *pos) 630 { 631 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 632 struct dc_link *link = connector->dc_link; 633 char *wr_buf = NULL; 634 uint32_t wr_buf_size = 100; 635 long param[11] = {0x0}; 636 int max_param_num = 11; 637 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 638 bool disable_hpd = false; 639 bool valid_test_pattern = false; 640 uint8_t param_nums = 0; 641 /* init with default 80bit custom pattern */ 642 uint8_t custom_pattern[10] = { 643 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 644 0x1f, 0x7c, 0xf0, 0xc1, 0x07 645 }; 646 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 647 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 648 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 649 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 650 struct link_training_settings link_training_settings; 651 int i; 652 653 if (size == 0) 654 return -EINVAL; 655 656 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 657 if (!wr_buf) 658 return -ENOSPC; 659 660 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 661 (long *)param, buf, 662 max_param_num, 663 ¶m_nums)) { 664 kfree(wr_buf); 665 return -EINVAL; 666 } 667 668 if (param_nums <= 0) { 669 kfree(wr_buf); 670 DRM_DEBUG_DRIVER("user data not be read\n"); 671 return -EINVAL; 672 } 673 674 675 test_pattern = param[0]; 676 677 switch (test_pattern) { 678 case DP_TEST_PATTERN_VIDEO_MODE: 679 case DP_TEST_PATTERN_COLOR_SQUARES: 680 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 681 case DP_TEST_PATTERN_VERTICAL_BARS: 682 case DP_TEST_PATTERN_HORIZONTAL_BARS: 683 case DP_TEST_PATTERN_COLOR_RAMP: 684 valid_test_pattern = true; 685 break; 686 687 case DP_TEST_PATTERN_D102: 688 case DP_TEST_PATTERN_SYMBOL_ERROR: 689 case DP_TEST_PATTERN_PRBS7: 690 case DP_TEST_PATTERN_80BIT_CUSTOM: 691 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 692 case DP_TEST_PATTERN_TRAINING_PATTERN4: 693 disable_hpd = true; 694 valid_test_pattern = true; 695 break; 696 697 default: 698 valid_test_pattern = false; 699 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 700 break; 701 } 702 703 if (!valid_test_pattern) { 704 kfree(wr_buf); 705 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 706 return size; 707 } 708 709 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 710 for (i = 0; i < 10; i++) { 711 if ((uint8_t) param[i + 1] != 0x0) 712 break; 713 } 714 715 if (i < 10) { 716 /* not use default value */ 717 for (i = 0; i < 10; i++) 718 custom_pattern[i] = (uint8_t) param[i + 1]; 719 } 720 } 721 722 /* Usage: set DP physical test pattern using debugfs with normal DP 723 * panel. Then plug out DP panel and connect a scope to measure 724 * For normal video mode and test pattern generated from CRCT, 725 * they are visibile to user. So do not disable HPD. 726 * Video Mode is also set to clear the test pattern, so enable HPD 727 * because it might have been disabled after a test pattern was set. 728 * AUX depends on HPD * sequence dependent, do not move! 729 */ 730 if (!disable_hpd) 731 dc_link_enable_hpd(link); 732 733 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 734 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 735 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 736 737 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 738 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 739 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 740 741 link_training_settings.link_settings = cur_link_settings; 742 743 744 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 745 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 746 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 747 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 748 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 749 link_training_settings.link_settings = prefer_link_settings; 750 } 751 752 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 753 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 754 755 dc_link_set_test_pattern( 756 link, 757 test_pattern, 758 DP_TEST_PATTERN_COLOR_SPACE_RGB, 759 &link_training_settings, 760 custom_pattern, 761 10); 762 763 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 764 * Then plug out DP panel and connect a scope to measure DP PHY signal. 765 * Need disable interrupt to avoid SW driver disable DP output. This is 766 * done after the test pattern is set. 767 */ 768 if (valid_test_pattern && disable_hpd) 769 dc_link_disable_hpd(link); 770 771 kfree(wr_buf); 772 773 return size; 774 } 775 776 /* 777 * Returns the DMCUB tracebuffer contents. 778 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 779 */ 780 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 781 { 782 struct amdgpu_device *adev = m->private; 783 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 784 struct dmub_debugfs_trace_entry *entries; 785 uint8_t *tbuf_base; 786 uint32_t tbuf_size, max_entries, num_entries, i; 787 788 if (!fb_info) 789 return 0; 790 791 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 792 if (!tbuf_base) 793 return 0; 794 795 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 796 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 797 sizeof(struct dmub_debugfs_trace_entry); 798 799 num_entries = 800 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 801 802 num_entries = min(num_entries, max_entries); 803 804 entries = (struct dmub_debugfs_trace_entry 805 *)(tbuf_base + 806 sizeof(struct dmub_debugfs_trace_header)); 807 808 for (i = 0; i < num_entries; ++i) { 809 struct dmub_debugfs_trace_entry *entry = &entries[i]; 810 811 seq_printf(m, 812 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 813 entry->trace_code, entry->tick_count, entry->param0, 814 entry->param1); 815 } 816 817 return 0; 818 } 819 820 /* 821 * Returns the DMCUB firmware state contents. 822 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 823 */ 824 static int dmub_fw_state_show(struct seq_file *m, void *data) 825 { 826 struct amdgpu_device *adev = m->private; 827 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 828 uint8_t *state_base; 829 uint32_t state_size; 830 831 if (!fb_info) 832 return 0; 833 834 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 835 if (!state_base) 836 return 0; 837 838 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 839 840 return seq_write(m, state_base, state_size); 841 } 842 843 /* psr_capability_show() - show eDP panel PSR capability 844 * 845 * The read function: sink_psr_capability_show 846 * Shows if sink has PSR capability or not. 847 * If yes - the PSR version is appended 848 * 849 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 850 * 851 * Expected output: 852 * "Sink support: no\n" - if panel doesn't support PSR 853 * "Sink support: yes [0x01]\n" - if panel supports PSR1 854 * "Driver support: no\n" - if driver doesn't support PSR 855 * "Driver support: yes [0x01]\n" - if driver supports PSR1 856 */ 857 static int psr_capability_show(struct seq_file *m, void *data) 858 { 859 struct drm_connector *connector = m->private; 860 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 861 struct dc_link *link = aconnector->dc_link; 862 863 if (!link) 864 return -ENODEV; 865 866 if (link->type == dc_connection_none) 867 return -ENODEV; 868 869 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 870 return -ENODEV; 871 872 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 873 if (link->dpcd_caps.psr_info.psr_version) 874 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 875 seq_puts(m, "\n"); 876 877 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 878 if (link->psr_settings.psr_version) 879 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 880 seq_puts(m, "\n"); 881 882 return 0; 883 } 884 885 /* 886 * Returns the current bpc for the crtc. 887 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 888 */ 889 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 890 { 891 struct drm_crtc *crtc = m->private; 892 struct drm_device *dev = crtc->dev; 893 struct dm_crtc_state *dm_crtc_state = NULL; 894 int res = -ENODEV; 895 unsigned int bpc; 896 897 mutex_lock(&dev->mode_config.mutex); 898 drm_modeset_lock(&crtc->mutex, NULL); 899 if (crtc->state == NULL) 900 goto unlock; 901 902 dm_crtc_state = to_dm_crtc_state(crtc->state); 903 if (dm_crtc_state->stream == NULL) 904 goto unlock; 905 906 switch (dm_crtc_state->stream->timing.display_color_depth) { 907 case COLOR_DEPTH_666: 908 bpc = 6; 909 break; 910 case COLOR_DEPTH_888: 911 bpc = 8; 912 break; 913 case COLOR_DEPTH_101010: 914 bpc = 10; 915 break; 916 case COLOR_DEPTH_121212: 917 bpc = 12; 918 break; 919 case COLOR_DEPTH_161616: 920 bpc = 16; 921 break; 922 default: 923 goto unlock; 924 } 925 926 seq_printf(m, "Current: %u\n", bpc); 927 res = 0; 928 929 unlock: 930 drm_modeset_unlock(&crtc->mutex); 931 mutex_unlock(&dev->mode_config.mutex); 932 933 return res; 934 } 935 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 936 937 /* 938 * Example usage: 939 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 940 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 941 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 942 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 943 */ 944 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 945 size_t size, loff_t *pos) 946 { 947 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 948 char *wr_buf = NULL; 949 uint32_t wr_buf_size = 42; 950 int max_param_num = 1; 951 long param; 952 uint8_t param_nums = 0; 953 954 if (size == 0) 955 return -EINVAL; 956 957 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 958 959 if (!wr_buf) { 960 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 961 return -ENOSPC; 962 } 963 964 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 965 ¶m, buf, 966 max_param_num, 967 ¶m_nums)) { 968 kfree(wr_buf); 969 return -EINVAL; 970 } 971 972 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 973 974 kfree(wr_buf); 975 return 0; 976 } 977 978 #ifdef CONFIG_DRM_AMD_DC_HDCP 979 /* 980 * Returns the HDCP capability of the Display (1.4 for now). 981 * 982 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 983 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 984 * 985 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 986 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 987 */ 988 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 989 { 990 struct drm_connector *connector = m->private; 991 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 992 bool hdcp_cap, hdcp2_cap; 993 994 if (connector->status != connector_status_connected) 995 return -ENODEV; 996 997 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 998 999 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1000 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1001 1002 1003 if (hdcp_cap) 1004 seq_printf(m, "%s ", "HDCP1.4"); 1005 if (hdcp2_cap) 1006 seq_printf(m, "%s ", "HDCP2.2"); 1007 1008 if (!hdcp_cap && !hdcp2_cap) 1009 seq_printf(m, "%s ", "None"); 1010 1011 seq_puts(m, "\n"); 1012 1013 return 0; 1014 } 1015 #endif 1016 1017 /* 1018 * Returns whether the connected display is internal and not hotpluggable. 1019 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1020 */ 1021 static int internal_display_show(struct seq_file *m, void *data) 1022 { 1023 struct drm_connector *connector = m->private; 1024 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1025 struct dc_link *link = aconnector->dc_link; 1026 1027 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1028 1029 return 0; 1030 } 1031 1032 /* function description 1033 * 1034 * generic SDP message access for testing 1035 * 1036 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1037 * 1038 * SDP header 1039 * Hb0 : Secondary-Data Packet ID 1040 * Hb1 : Secondary-Data Packet type 1041 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1042 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1043 * 1044 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1045 */ 1046 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1047 size_t size, loff_t *pos) 1048 { 1049 int r; 1050 uint8_t data[36]; 1051 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1052 struct dm_crtc_state *acrtc_state; 1053 uint32_t write_size = 36; 1054 1055 if (connector->base.status != connector_status_connected) 1056 return -ENODEV; 1057 1058 if (size == 0) 1059 return 0; 1060 1061 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1062 1063 r = copy_from_user(data, buf, write_size); 1064 1065 write_size -= r; 1066 1067 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1068 1069 return write_size; 1070 } 1071 1072 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1073 size_t size, loff_t *pos) 1074 { 1075 int r; 1076 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1077 1078 if (size < sizeof(connector->debugfs_dpcd_address)) 1079 return -EINVAL; 1080 1081 r = copy_from_user(&connector->debugfs_dpcd_address, 1082 buf, sizeof(connector->debugfs_dpcd_address)); 1083 1084 return size - r; 1085 } 1086 1087 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1088 size_t size, loff_t *pos) 1089 { 1090 int r; 1091 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1092 1093 if (size < sizeof(connector->debugfs_dpcd_size)) 1094 return -EINVAL; 1095 1096 r = copy_from_user(&connector->debugfs_dpcd_size, 1097 buf, sizeof(connector->debugfs_dpcd_size)); 1098 1099 if (connector->debugfs_dpcd_size > 256) 1100 connector->debugfs_dpcd_size = 0; 1101 1102 return size - r; 1103 } 1104 1105 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1106 size_t size, loff_t *pos) 1107 { 1108 int r; 1109 char *data; 1110 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1111 struct dc_link *link = connector->dc_link; 1112 uint32_t write_size = connector->debugfs_dpcd_size; 1113 1114 if (!write_size || size < write_size) 1115 return -EINVAL; 1116 1117 data = kzalloc(write_size, GFP_KERNEL); 1118 if (!data) 1119 return 0; 1120 1121 r = copy_from_user(data, buf, write_size); 1122 1123 dm_helpers_dp_write_dpcd(link->ctx, link, 1124 connector->debugfs_dpcd_address, data, write_size - r); 1125 kfree(data); 1126 return write_size - r; 1127 } 1128 1129 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1130 size_t size, loff_t *pos) 1131 { 1132 int r; 1133 char *data; 1134 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1135 struct dc_link *link = connector->dc_link; 1136 uint32_t read_size = connector->debugfs_dpcd_size; 1137 1138 if (!read_size || size < read_size) 1139 return 0; 1140 1141 data = kzalloc(read_size, GFP_KERNEL); 1142 if (!data) 1143 return 0; 1144 1145 dm_helpers_dp_read_dpcd(link->ctx, link, 1146 connector->debugfs_dpcd_address, data, read_size); 1147 1148 r = copy_to_user(buf, data, read_size); 1149 1150 kfree(data); 1151 return read_size - r; 1152 } 1153 1154 /* function: Read link's DSC & FEC capabilities 1155 * 1156 * 1157 * Access it with the following command (you need to specify 1158 * connector like DP-1): 1159 * 1160 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1161 * 1162 */ 1163 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1164 { 1165 struct drm_connector *connector = m->private; 1166 struct drm_modeset_acquire_ctx ctx; 1167 struct drm_device *dev = connector->dev; 1168 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1169 int ret = 0; 1170 bool try_again = false; 1171 bool is_fec_supported = false; 1172 bool is_dsc_supported = false; 1173 struct dpcd_caps dpcd_caps; 1174 1175 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1176 do { 1177 try_again = false; 1178 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1179 if (ret) { 1180 if (ret == -EDEADLK) { 1181 ret = drm_modeset_backoff(&ctx); 1182 if (!ret) { 1183 try_again = true; 1184 continue; 1185 } 1186 } 1187 break; 1188 } 1189 if (connector->status != connector_status_connected) { 1190 ret = -ENODEV; 1191 break; 1192 } 1193 dpcd_caps = aconnector->dc_link->dpcd_caps; 1194 if (aconnector->mst_output_port) { 1195 /* aconnector sets dsc_aux during get_modes call 1196 * if MST connector has it means it can either 1197 * enable DSC on the sink device or on MST branch 1198 * its connected to. 1199 */ 1200 if (aconnector->dsc_aux) { 1201 is_fec_supported = true; 1202 is_dsc_supported = true; 1203 } 1204 } else { 1205 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1206 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1207 } 1208 } while (try_again); 1209 1210 drm_modeset_drop_locks(&ctx); 1211 drm_modeset_acquire_fini(&ctx); 1212 1213 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1214 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1215 1216 return ret; 1217 } 1218 1219 /* function: Trigger virtual HPD redetection on connector 1220 * 1221 * This function will perform link rediscovery, link disable 1222 * and enable, and dm connector state update. 1223 * 1224 * Retrigger HPD on an existing connector by echoing 1 into 1225 * its respectful "trigger_hotplug" debugfs entry: 1226 * 1227 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1228 * 1229 * This function can perform HPD unplug: 1230 * 1231 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1232 * 1233 */ 1234 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1235 size_t size, loff_t *pos) 1236 { 1237 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1238 struct drm_connector *connector = &aconnector->base; 1239 struct dc_link *link = NULL; 1240 struct drm_device *dev = connector->dev; 1241 struct amdgpu_device *adev = drm_to_adev(dev); 1242 enum dc_connection_type new_connection_type = dc_connection_none; 1243 char *wr_buf = NULL; 1244 uint32_t wr_buf_size = 42; 1245 int max_param_num = 1; 1246 long param[1] = {0}; 1247 uint8_t param_nums = 0; 1248 bool ret = false; 1249 1250 if (!aconnector || !aconnector->dc_link) 1251 return -EINVAL; 1252 1253 if (size == 0) 1254 return -EINVAL; 1255 1256 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1257 1258 if (!wr_buf) { 1259 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1260 return -ENOSPC; 1261 } 1262 1263 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1264 (long *)param, buf, 1265 max_param_num, 1266 ¶m_nums)) { 1267 kfree(wr_buf); 1268 return -EINVAL; 1269 } 1270 1271 kfree(wr_buf); 1272 1273 if (param_nums <= 0) { 1274 DRM_DEBUG_DRIVER("user data not be read\n"); 1275 return -EINVAL; 1276 } 1277 1278 mutex_lock(&aconnector->hpd_lock); 1279 1280 /* Don't support for mst end device*/ 1281 if (aconnector->mst_root) { 1282 mutex_unlock(&aconnector->hpd_lock); 1283 return -EINVAL; 1284 } 1285 1286 if (param[0] == 1) { 1287 1288 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1289 new_connection_type != dc_connection_none) 1290 goto unlock; 1291 1292 mutex_lock(&adev->dm.dc_lock); 1293 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1294 mutex_unlock(&adev->dm.dc_lock); 1295 1296 if (!ret) 1297 goto unlock; 1298 1299 amdgpu_dm_update_connector_after_detect(aconnector); 1300 1301 drm_modeset_lock_all(dev); 1302 dm_restore_drm_connector_state(dev, connector); 1303 drm_modeset_unlock_all(dev); 1304 1305 drm_kms_helper_connector_hotplug_event(connector); 1306 } else if (param[0] == 0) { 1307 if (!aconnector->dc_link) 1308 goto unlock; 1309 1310 link = aconnector->dc_link; 1311 1312 if (link->local_sink) { 1313 dc_sink_release(link->local_sink); 1314 link->local_sink = NULL; 1315 } 1316 1317 link->dpcd_sink_count = 0; 1318 link->type = dc_connection_none; 1319 link->dongle_max_pix_clk = 0; 1320 1321 amdgpu_dm_update_connector_after_detect(aconnector); 1322 1323 /* If the aconnector is the root node in mst topology */ 1324 if (aconnector->mst_mgr.mst_state == true) 1325 reset_cur_dp_mst_topology(link); 1326 1327 drm_modeset_lock_all(dev); 1328 dm_restore_drm_connector_state(dev, connector); 1329 drm_modeset_unlock_all(dev); 1330 1331 drm_kms_helper_connector_hotplug_event(connector); 1332 } 1333 1334 unlock: 1335 mutex_unlock(&aconnector->hpd_lock); 1336 1337 return size; 1338 } 1339 1340 /* function: read DSC status on the connector 1341 * 1342 * The read function: dp_dsc_clock_en_read 1343 * returns current status of DSC clock on the connector. 1344 * The return is a boolean flag: 1 or 0. 1345 * 1346 * Access it with the following command (you need to specify 1347 * connector like DP-1): 1348 * 1349 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1350 * 1351 * Expected output: 1352 * 1 - means that DSC is currently enabled 1353 * 0 - means that DSC is disabled 1354 */ 1355 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1356 size_t size, loff_t *pos) 1357 { 1358 char *rd_buf = NULL; 1359 char *rd_buf_ptr = NULL; 1360 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1361 struct display_stream_compressor *dsc; 1362 struct dcn_dsc_state dsc_state = {0}; 1363 const uint32_t rd_buf_size = 10; 1364 struct pipe_ctx *pipe_ctx; 1365 ssize_t result = 0; 1366 int i, r, str_len = 30; 1367 1368 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1369 1370 if (!rd_buf) 1371 return -ENOMEM; 1372 1373 rd_buf_ptr = rd_buf; 1374 1375 for (i = 0; i < MAX_PIPES; i++) { 1376 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1377 if (pipe_ctx->stream && 1378 pipe_ctx->stream->link == aconnector->dc_link) 1379 break; 1380 } 1381 1382 dsc = pipe_ctx->stream_res.dsc; 1383 if (dsc) 1384 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1385 1386 snprintf(rd_buf_ptr, str_len, 1387 "%d\n", 1388 dsc_state.dsc_clock_en); 1389 rd_buf_ptr += str_len; 1390 1391 while (size) { 1392 if (*pos >= rd_buf_size) 1393 break; 1394 1395 r = put_user(*(rd_buf + result), buf); 1396 if (r) { 1397 kfree(rd_buf); 1398 return r; /* r = -EFAULT */ 1399 } 1400 1401 buf += 1; 1402 size -= 1; 1403 *pos += 1; 1404 result += 1; 1405 } 1406 1407 kfree(rd_buf); 1408 return result; 1409 } 1410 1411 /* function: write force DSC on the connector 1412 * 1413 * The write function: dp_dsc_clock_en_write 1414 * enables to force DSC on the connector. 1415 * User can write to either force enable or force disable DSC 1416 * on the next modeset or set it to driver default 1417 * 1418 * Accepted inputs: 1419 * 0 - default DSC enablement policy 1420 * 1 - force enable DSC on the connector 1421 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1422 * 1423 * Writing DSC settings is done with the following command: 1424 * - To force enable DSC (you need to specify 1425 * connector like DP-1): 1426 * 1427 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1428 * 1429 * - To return to default state set the flag to zero and 1430 * let driver deal with DSC automatically 1431 * (you need to specify connector like DP-1): 1432 * 1433 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1434 * 1435 */ 1436 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1437 size_t size, loff_t *pos) 1438 { 1439 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1440 struct drm_connector *connector = &aconnector->base; 1441 struct drm_device *dev = connector->dev; 1442 struct drm_crtc *crtc = NULL; 1443 struct dm_crtc_state *dm_crtc_state = NULL; 1444 struct pipe_ctx *pipe_ctx; 1445 int i; 1446 char *wr_buf = NULL; 1447 uint32_t wr_buf_size = 42; 1448 int max_param_num = 1; 1449 long param[1] = {0}; 1450 uint8_t param_nums = 0; 1451 1452 if (size == 0) 1453 return -EINVAL; 1454 1455 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1456 1457 if (!wr_buf) { 1458 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1459 return -ENOSPC; 1460 } 1461 1462 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1463 (long *)param, buf, 1464 max_param_num, 1465 ¶m_nums)) { 1466 kfree(wr_buf); 1467 return -EINVAL; 1468 } 1469 1470 if (param_nums <= 0) { 1471 DRM_DEBUG_DRIVER("user data not be read\n"); 1472 kfree(wr_buf); 1473 return -EINVAL; 1474 } 1475 1476 for (i = 0; i < MAX_PIPES; i++) { 1477 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1478 if (pipe_ctx->stream && 1479 pipe_ctx->stream->link == aconnector->dc_link) 1480 break; 1481 } 1482 1483 if (!pipe_ctx->stream) 1484 goto done; 1485 1486 // Get CRTC state 1487 mutex_lock(&dev->mode_config.mutex); 1488 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1489 1490 if (connector->state == NULL) 1491 goto unlock; 1492 1493 crtc = connector->state->crtc; 1494 if (crtc == NULL) 1495 goto unlock; 1496 1497 drm_modeset_lock(&crtc->mutex, NULL); 1498 if (crtc->state == NULL) 1499 goto unlock; 1500 1501 dm_crtc_state = to_dm_crtc_state(crtc->state); 1502 if (dm_crtc_state->stream == NULL) 1503 goto unlock; 1504 1505 if (param[0] == 1) 1506 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1507 else if (param[0] == 2) 1508 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1509 else 1510 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1511 1512 dm_crtc_state->dsc_force_changed = true; 1513 1514 unlock: 1515 if (crtc) 1516 drm_modeset_unlock(&crtc->mutex); 1517 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1518 mutex_unlock(&dev->mode_config.mutex); 1519 1520 done: 1521 kfree(wr_buf); 1522 return size; 1523 } 1524 1525 /* function: read DSC slice width parameter on the connector 1526 * 1527 * The read function: dp_dsc_slice_width_read 1528 * returns dsc slice width used in the current configuration 1529 * The return is an integer: 0 or other positive number 1530 * 1531 * Access the status with the following command: 1532 * 1533 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1534 * 1535 * 0 - means that DSC is disabled 1536 * 1537 * Any other number more than zero represents the 1538 * slice width currently used by DSC in pixels 1539 * 1540 */ 1541 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1542 size_t size, loff_t *pos) 1543 { 1544 char *rd_buf = NULL; 1545 char *rd_buf_ptr = NULL; 1546 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1547 struct display_stream_compressor *dsc; 1548 struct dcn_dsc_state dsc_state = {0}; 1549 const uint32_t rd_buf_size = 100; 1550 struct pipe_ctx *pipe_ctx; 1551 ssize_t result = 0; 1552 int i, r, str_len = 30; 1553 1554 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1555 1556 if (!rd_buf) 1557 return -ENOMEM; 1558 1559 rd_buf_ptr = rd_buf; 1560 1561 for (i = 0; i < MAX_PIPES; i++) { 1562 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1563 if (pipe_ctx->stream && 1564 pipe_ctx->stream->link == aconnector->dc_link) 1565 break; 1566 } 1567 1568 dsc = pipe_ctx->stream_res.dsc; 1569 if (dsc) 1570 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1571 1572 snprintf(rd_buf_ptr, str_len, 1573 "%d\n", 1574 dsc_state.dsc_slice_width); 1575 rd_buf_ptr += str_len; 1576 1577 while (size) { 1578 if (*pos >= rd_buf_size) 1579 break; 1580 1581 r = put_user(*(rd_buf + result), buf); 1582 if (r) { 1583 kfree(rd_buf); 1584 return r; /* r = -EFAULT */ 1585 } 1586 1587 buf += 1; 1588 size -= 1; 1589 *pos += 1; 1590 result += 1; 1591 } 1592 1593 kfree(rd_buf); 1594 return result; 1595 } 1596 1597 /* function: write DSC slice width parameter 1598 * 1599 * The write function: dp_dsc_slice_width_write 1600 * overwrites automatically generated DSC configuration 1601 * of slice width. 1602 * 1603 * The user has to write the slice width divisible by the 1604 * picture width. 1605 * 1606 * Also the user has to write width in hexidecimal 1607 * rather than in decimal. 1608 * 1609 * Writing DSC settings is done with the following command: 1610 * - To force overwrite slice width: (example sets to 1920 pixels) 1611 * 1612 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1613 * 1614 * - To stop overwriting and let driver find the optimal size, 1615 * set the width to zero: 1616 * 1617 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1618 * 1619 */ 1620 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1621 size_t size, loff_t *pos) 1622 { 1623 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1624 struct pipe_ctx *pipe_ctx; 1625 struct drm_connector *connector = &aconnector->base; 1626 struct drm_device *dev = connector->dev; 1627 struct drm_crtc *crtc = NULL; 1628 struct dm_crtc_state *dm_crtc_state = NULL; 1629 int i; 1630 char *wr_buf = NULL; 1631 uint32_t wr_buf_size = 42; 1632 int max_param_num = 1; 1633 long param[1] = {0}; 1634 uint8_t param_nums = 0; 1635 1636 if (size == 0) 1637 return -EINVAL; 1638 1639 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1640 1641 if (!wr_buf) { 1642 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1643 return -ENOSPC; 1644 } 1645 1646 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1647 (long *)param, buf, 1648 max_param_num, 1649 ¶m_nums)) { 1650 kfree(wr_buf); 1651 return -EINVAL; 1652 } 1653 1654 if (param_nums <= 0) { 1655 DRM_DEBUG_DRIVER("user data not be read\n"); 1656 kfree(wr_buf); 1657 return -EINVAL; 1658 } 1659 1660 for (i = 0; i < MAX_PIPES; i++) { 1661 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1662 if (pipe_ctx->stream && 1663 pipe_ctx->stream->link == aconnector->dc_link) 1664 break; 1665 } 1666 1667 if (!pipe_ctx->stream) 1668 goto done; 1669 1670 // Safely get CRTC state 1671 mutex_lock(&dev->mode_config.mutex); 1672 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1673 1674 if (connector->state == NULL) 1675 goto unlock; 1676 1677 crtc = connector->state->crtc; 1678 if (crtc == NULL) 1679 goto unlock; 1680 1681 drm_modeset_lock(&crtc->mutex, NULL); 1682 if (crtc->state == NULL) 1683 goto unlock; 1684 1685 dm_crtc_state = to_dm_crtc_state(crtc->state); 1686 if (dm_crtc_state->stream == NULL) 1687 goto unlock; 1688 1689 if (param[0] > 0) 1690 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1691 pipe_ctx->stream->timing.h_addressable, 1692 param[0]); 1693 else 1694 aconnector->dsc_settings.dsc_num_slices_h = 0; 1695 1696 dm_crtc_state->dsc_force_changed = true; 1697 1698 unlock: 1699 if (crtc) 1700 drm_modeset_unlock(&crtc->mutex); 1701 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1702 mutex_unlock(&dev->mode_config.mutex); 1703 1704 done: 1705 kfree(wr_buf); 1706 return size; 1707 } 1708 1709 /* function: read DSC slice height parameter on the connector 1710 * 1711 * The read function: dp_dsc_slice_height_read 1712 * returns dsc slice height used in the current configuration 1713 * The return is an integer: 0 or other positive number 1714 * 1715 * Access the status with the following command: 1716 * 1717 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1718 * 1719 * 0 - means that DSC is disabled 1720 * 1721 * Any other number more than zero represents the 1722 * slice height currently used by DSC in pixels 1723 * 1724 */ 1725 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1726 size_t size, loff_t *pos) 1727 { 1728 char *rd_buf = NULL; 1729 char *rd_buf_ptr = NULL; 1730 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1731 struct display_stream_compressor *dsc; 1732 struct dcn_dsc_state dsc_state = {0}; 1733 const uint32_t rd_buf_size = 100; 1734 struct pipe_ctx *pipe_ctx; 1735 ssize_t result = 0; 1736 int i, r, str_len = 30; 1737 1738 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1739 1740 if (!rd_buf) 1741 return -ENOMEM; 1742 1743 rd_buf_ptr = rd_buf; 1744 1745 for (i = 0; i < MAX_PIPES; i++) { 1746 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1747 if (pipe_ctx->stream && 1748 pipe_ctx->stream->link == aconnector->dc_link) 1749 break; 1750 } 1751 1752 dsc = pipe_ctx->stream_res.dsc; 1753 if (dsc) 1754 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1755 1756 snprintf(rd_buf_ptr, str_len, 1757 "%d\n", 1758 dsc_state.dsc_slice_height); 1759 rd_buf_ptr += str_len; 1760 1761 while (size) { 1762 if (*pos >= rd_buf_size) 1763 break; 1764 1765 r = put_user(*(rd_buf + result), buf); 1766 if (r) { 1767 kfree(rd_buf); 1768 return r; /* r = -EFAULT */ 1769 } 1770 1771 buf += 1; 1772 size -= 1; 1773 *pos += 1; 1774 result += 1; 1775 } 1776 1777 kfree(rd_buf); 1778 return result; 1779 } 1780 1781 /* function: write DSC slice height parameter 1782 * 1783 * The write function: dp_dsc_slice_height_write 1784 * overwrites automatically generated DSC configuration 1785 * of slice height. 1786 * 1787 * The user has to write the slice height divisible by the 1788 * picture height. 1789 * 1790 * Also the user has to write height in hexidecimal 1791 * rather than in decimal. 1792 * 1793 * Writing DSC settings is done with the following command: 1794 * - To force overwrite slice height (example sets to 128 pixels): 1795 * 1796 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1797 * 1798 * - To stop overwriting and let driver find the optimal size, 1799 * set the height to zero: 1800 * 1801 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1802 * 1803 */ 1804 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1805 size_t size, loff_t *pos) 1806 { 1807 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1808 struct drm_connector *connector = &aconnector->base; 1809 struct drm_device *dev = connector->dev; 1810 struct drm_crtc *crtc = NULL; 1811 struct dm_crtc_state *dm_crtc_state = NULL; 1812 struct pipe_ctx *pipe_ctx; 1813 int i; 1814 char *wr_buf = NULL; 1815 uint32_t wr_buf_size = 42; 1816 int max_param_num = 1; 1817 uint8_t param_nums = 0; 1818 long param[1] = {0}; 1819 1820 if (size == 0) 1821 return -EINVAL; 1822 1823 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1824 1825 if (!wr_buf) { 1826 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1827 return -ENOSPC; 1828 } 1829 1830 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1831 (long *)param, buf, 1832 max_param_num, 1833 ¶m_nums)) { 1834 kfree(wr_buf); 1835 return -EINVAL; 1836 } 1837 1838 if (param_nums <= 0) { 1839 DRM_DEBUG_DRIVER("user data not be read\n"); 1840 kfree(wr_buf); 1841 return -EINVAL; 1842 } 1843 1844 for (i = 0; i < MAX_PIPES; i++) { 1845 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1846 if (pipe_ctx->stream && 1847 pipe_ctx->stream->link == aconnector->dc_link) 1848 break; 1849 } 1850 1851 if (!pipe_ctx->stream) 1852 goto done; 1853 1854 // Get CRTC state 1855 mutex_lock(&dev->mode_config.mutex); 1856 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1857 1858 if (connector->state == NULL) 1859 goto unlock; 1860 1861 crtc = connector->state->crtc; 1862 if (crtc == NULL) 1863 goto unlock; 1864 1865 drm_modeset_lock(&crtc->mutex, NULL); 1866 if (crtc->state == NULL) 1867 goto unlock; 1868 1869 dm_crtc_state = to_dm_crtc_state(crtc->state); 1870 if (dm_crtc_state->stream == NULL) 1871 goto unlock; 1872 1873 if (param[0] > 0) 1874 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1875 pipe_ctx->stream->timing.v_addressable, 1876 param[0]); 1877 else 1878 aconnector->dsc_settings.dsc_num_slices_v = 0; 1879 1880 dm_crtc_state->dsc_force_changed = true; 1881 1882 unlock: 1883 if (crtc) 1884 drm_modeset_unlock(&crtc->mutex); 1885 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1886 mutex_unlock(&dev->mode_config.mutex); 1887 1888 done: 1889 kfree(wr_buf); 1890 return size; 1891 } 1892 1893 /* function: read DSC target rate on the connector in bits per pixel 1894 * 1895 * The read function: dp_dsc_bits_per_pixel_read 1896 * returns target rate of compression in bits per pixel 1897 * The return is an integer: 0 or other positive integer 1898 * 1899 * Access it with the following command: 1900 * 1901 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1902 * 1903 * 0 - means that DSC is disabled 1904 */ 1905 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1906 size_t size, loff_t *pos) 1907 { 1908 char *rd_buf = NULL; 1909 char *rd_buf_ptr = NULL; 1910 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1911 struct display_stream_compressor *dsc; 1912 struct dcn_dsc_state dsc_state = {0}; 1913 const uint32_t rd_buf_size = 100; 1914 struct pipe_ctx *pipe_ctx; 1915 ssize_t result = 0; 1916 int i, r, str_len = 30; 1917 1918 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1919 1920 if (!rd_buf) 1921 return -ENOMEM; 1922 1923 rd_buf_ptr = rd_buf; 1924 1925 for (i = 0; i < MAX_PIPES; i++) { 1926 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1927 if (pipe_ctx->stream && 1928 pipe_ctx->stream->link == aconnector->dc_link) 1929 break; 1930 } 1931 1932 dsc = pipe_ctx->stream_res.dsc; 1933 if (dsc) 1934 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1935 1936 snprintf(rd_buf_ptr, str_len, 1937 "%d\n", 1938 dsc_state.dsc_bits_per_pixel); 1939 rd_buf_ptr += str_len; 1940 1941 while (size) { 1942 if (*pos >= rd_buf_size) 1943 break; 1944 1945 r = put_user(*(rd_buf + result), buf); 1946 if (r) { 1947 kfree(rd_buf); 1948 return r; /* r = -EFAULT */ 1949 } 1950 1951 buf += 1; 1952 size -= 1; 1953 *pos += 1; 1954 result += 1; 1955 } 1956 1957 kfree(rd_buf); 1958 return result; 1959 } 1960 1961 /* function: write DSC target rate in bits per pixel 1962 * 1963 * The write function: dp_dsc_bits_per_pixel_write 1964 * overwrites automatically generated DSC configuration 1965 * of DSC target bit rate. 1966 * 1967 * Also the user has to write bpp in hexidecimal 1968 * rather than in decimal. 1969 * 1970 * Writing DSC settings is done with the following command: 1971 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1972 * 1973 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1974 * 1975 * - To stop overwriting and let driver find the optimal rate, 1976 * set the rate to zero: 1977 * 1978 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1979 * 1980 */ 1981 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1982 size_t size, loff_t *pos) 1983 { 1984 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1985 struct drm_connector *connector = &aconnector->base; 1986 struct drm_device *dev = connector->dev; 1987 struct drm_crtc *crtc = NULL; 1988 struct dm_crtc_state *dm_crtc_state = NULL; 1989 struct pipe_ctx *pipe_ctx; 1990 int i; 1991 char *wr_buf = NULL; 1992 uint32_t wr_buf_size = 42; 1993 int max_param_num = 1; 1994 uint8_t param_nums = 0; 1995 long param[1] = {0}; 1996 1997 if (size == 0) 1998 return -EINVAL; 1999 2000 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2001 2002 if (!wr_buf) { 2003 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2004 return -ENOSPC; 2005 } 2006 2007 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2008 (long *)param, buf, 2009 max_param_num, 2010 ¶m_nums)) { 2011 kfree(wr_buf); 2012 return -EINVAL; 2013 } 2014 2015 if (param_nums <= 0) { 2016 DRM_DEBUG_DRIVER("user data not be read\n"); 2017 kfree(wr_buf); 2018 return -EINVAL; 2019 } 2020 2021 for (i = 0; i < MAX_PIPES; i++) { 2022 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2023 if (pipe_ctx->stream && 2024 pipe_ctx->stream->link == aconnector->dc_link) 2025 break; 2026 } 2027 2028 if (!pipe_ctx->stream) 2029 goto done; 2030 2031 // Get CRTC state 2032 mutex_lock(&dev->mode_config.mutex); 2033 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2034 2035 if (connector->state == NULL) 2036 goto unlock; 2037 2038 crtc = connector->state->crtc; 2039 if (crtc == NULL) 2040 goto unlock; 2041 2042 drm_modeset_lock(&crtc->mutex, NULL); 2043 if (crtc->state == NULL) 2044 goto unlock; 2045 2046 dm_crtc_state = to_dm_crtc_state(crtc->state); 2047 if (dm_crtc_state->stream == NULL) 2048 goto unlock; 2049 2050 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2051 2052 dm_crtc_state->dsc_force_changed = true; 2053 2054 unlock: 2055 if (crtc) 2056 drm_modeset_unlock(&crtc->mutex); 2057 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2058 mutex_unlock(&dev->mode_config.mutex); 2059 2060 done: 2061 kfree(wr_buf); 2062 return size; 2063 } 2064 2065 /* function: read DSC picture width parameter on the connector 2066 * 2067 * The read function: dp_dsc_pic_width_read 2068 * returns dsc picture width used in the current configuration 2069 * It is the same as h_addressable of the current 2070 * display's timing 2071 * The return is an integer: 0 or other positive integer 2072 * If 0 then DSC is disabled. 2073 * 2074 * Access it with the following command: 2075 * 2076 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2077 * 2078 * 0 - means that DSC is disabled 2079 */ 2080 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2081 size_t size, loff_t *pos) 2082 { 2083 char *rd_buf = NULL; 2084 char *rd_buf_ptr = NULL; 2085 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2086 struct display_stream_compressor *dsc; 2087 struct dcn_dsc_state dsc_state = {0}; 2088 const uint32_t rd_buf_size = 100; 2089 struct pipe_ctx *pipe_ctx; 2090 ssize_t result = 0; 2091 int i, r, str_len = 30; 2092 2093 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2094 2095 if (!rd_buf) 2096 return -ENOMEM; 2097 2098 rd_buf_ptr = rd_buf; 2099 2100 for (i = 0; i < MAX_PIPES; i++) { 2101 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2102 if (pipe_ctx->stream && 2103 pipe_ctx->stream->link == aconnector->dc_link) 2104 break; 2105 } 2106 2107 dsc = pipe_ctx->stream_res.dsc; 2108 if (dsc) 2109 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2110 2111 snprintf(rd_buf_ptr, str_len, 2112 "%d\n", 2113 dsc_state.dsc_pic_width); 2114 rd_buf_ptr += str_len; 2115 2116 while (size) { 2117 if (*pos >= rd_buf_size) 2118 break; 2119 2120 r = put_user(*(rd_buf + result), buf); 2121 if (r) { 2122 kfree(rd_buf); 2123 return r; /* r = -EFAULT */ 2124 } 2125 2126 buf += 1; 2127 size -= 1; 2128 *pos += 1; 2129 result += 1; 2130 } 2131 2132 kfree(rd_buf); 2133 return result; 2134 } 2135 2136 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2137 size_t size, loff_t *pos) 2138 { 2139 char *rd_buf = NULL; 2140 char *rd_buf_ptr = NULL; 2141 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2142 struct display_stream_compressor *dsc; 2143 struct dcn_dsc_state dsc_state = {0}; 2144 const uint32_t rd_buf_size = 100; 2145 struct pipe_ctx *pipe_ctx; 2146 ssize_t result = 0; 2147 int i, r, str_len = 30; 2148 2149 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2150 2151 if (!rd_buf) 2152 return -ENOMEM; 2153 2154 rd_buf_ptr = rd_buf; 2155 2156 for (i = 0; i < MAX_PIPES; i++) { 2157 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2158 if (pipe_ctx->stream && 2159 pipe_ctx->stream->link == aconnector->dc_link) 2160 break; 2161 } 2162 2163 dsc = pipe_ctx->stream_res.dsc; 2164 if (dsc) 2165 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2166 2167 snprintf(rd_buf_ptr, str_len, 2168 "%d\n", 2169 dsc_state.dsc_pic_height); 2170 rd_buf_ptr += str_len; 2171 2172 while (size) { 2173 if (*pos >= rd_buf_size) 2174 break; 2175 2176 r = put_user(*(rd_buf + result), buf); 2177 if (r) { 2178 kfree(rd_buf); 2179 return r; /* r = -EFAULT */ 2180 } 2181 2182 buf += 1; 2183 size -= 1; 2184 *pos += 1; 2185 result += 1; 2186 } 2187 2188 kfree(rd_buf); 2189 return result; 2190 } 2191 2192 /* function: read DSC chunk size parameter on the connector 2193 * 2194 * The read function: dp_dsc_chunk_size_read 2195 * returns dsc chunk size set in the current configuration 2196 * The value is calculated automatically by DSC code 2197 * and depends on slice parameters and bpp target rate 2198 * The return is an integer: 0 or other positive integer 2199 * If 0 then DSC is disabled. 2200 * 2201 * Access it with the following command: 2202 * 2203 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2204 * 2205 * 0 - means that DSC is disabled 2206 */ 2207 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2208 size_t size, loff_t *pos) 2209 { 2210 char *rd_buf = NULL; 2211 char *rd_buf_ptr = NULL; 2212 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2213 struct display_stream_compressor *dsc; 2214 struct dcn_dsc_state dsc_state = {0}; 2215 const uint32_t rd_buf_size = 100; 2216 struct pipe_ctx *pipe_ctx; 2217 ssize_t result = 0; 2218 int i, r, str_len = 30; 2219 2220 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2221 2222 if (!rd_buf) 2223 return -ENOMEM; 2224 2225 rd_buf_ptr = rd_buf; 2226 2227 for (i = 0; i < MAX_PIPES; i++) { 2228 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2229 if (pipe_ctx->stream && 2230 pipe_ctx->stream->link == aconnector->dc_link) 2231 break; 2232 } 2233 2234 dsc = pipe_ctx->stream_res.dsc; 2235 if (dsc) 2236 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2237 2238 snprintf(rd_buf_ptr, str_len, 2239 "%d\n", 2240 dsc_state.dsc_chunk_size); 2241 rd_buf_ptr += str_len; 2242 2243 while (size) { 2244 if (*pos >= rd_buf_size) 2245 break; 2246 2247 r = put_user(*(rd_buf + result), buf); 2248 if (r) { 2249 kfree(rd_buf); 2250 return r; /* r = -EFAULT */ 2251 } 2252 2253 buf += 1; 2254 size -= 1; 2255 *pos += 1; 2256 result += 1; 2257 } 2258 2259 kfree(rd_buf); 2260 return result; 2261 } 2262 2263 /* function: read DSC slice bpg offset on the connector 2264 * 2265 * The read function: dp_dsc_slice_bpg_offset_read 2266 * returns dsc bpg slice offset set in the current configuration 2267 * The value is calculated automatically by DSC code 2268 * and depends on slice parameters and bpp target rate 2269 * The return is an integer: 0 or other positive integer 2270 * If 0 then DSC is disabled. 2271 * 2272 * Access it with the following command: 2273 * 2274 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2275 * 2276 * 0 - means that DSC is disabled 2277 */ 2278 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2279 size_t size, loff_t *pos) 2280 { 2281 char *rd_buf = NULL; 2282 char *rd_buf_ptr = NULL; 2283 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2284 struct display_stream_compressor *dsc; 2285 struct dcn_dsc_state dsc_state = {0}; 2286 const uint32_t rd_buf_size = 100; 2287 struct pipe_ctx *pipe_ctx; 2288 ssize_t result = 0; 2289 int i, r, str_len = 30; 2290 2291 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2292 2293 if (!rd_buf) 2294 return -ENOMEM; 2295 2296 rd_buf_ptr = rd_buf; 2297 2298 for (i = 0; i < MAX_PIPES; i++) { 2299 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2300 if (pipe_ctx->stream && 2301 pipe_ctx->stream->link == aconnector->dc_link) 2302 break; 2303 } 2304 2305 dsc = pipe_ctx->stream_res.dsc; 2306 if (dsc) 2307 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2308 2309 snprintf(rd_buf_ptr, str_len, 2310 "%d\n", 2311 dsc_state.dsc_slice_bpg_offset); 2312 rd_buf_ptr += str_len; 2313 2314 while (size) { 2315 if (*pos >= rd_buf_size) 2316 break; 2317 2318 r = put_user(*(rd_buf + result), buf); 2319 if (r) { 2320 kfree(rd_buf); 2321 return r; /* r = -EFAULT */ 2322 } 2323 2324 buf += 1; 2325 size -= 1; 2326 *pos += 1; 2327 result += 1; 2328 } 2329 2330 kfree(rd_buf); 2331 return result; 2332 } 2333 2334 2335 /* 2336 * function description: Read max_requested_bpc property from the connector 2337 * 2338 * Access it with the following command: 2339 * 2340 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2341 * 2342 */ 2343 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2344 size_t size, loff_t *pos) 2345 { 2346 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2347 struct drm_connector *connector = &aconnector->base; 2348 struct drm_device *dev = connector->dev; 2349 struct dm_connector_state *state; 2350 ssize_t result = 0; 2351 char *rd_buf = NULL; 2352 char *rd_buf_ptr = NULL; 2353 const uint32_t rd_buf_size = 10; 2354 int r; 2355 2356 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2357 2358 if (!rd_buf) 2359 return -ENOMEM; 2360 2361 mutex_lock(&dev->mode_config.mutex); 2362 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2363 2364 if (connector->state == NULL) 2365 goto unlock; 2366 2367 state = to_dm_connector_state(connector->state); 2368 2369 rd_buf_ptr = rd_buf; 2370 snprintf(rd_buf_ptr, rd_buf_size, 2371 "%u\n", 2372 state->base.max_requested_bpc); 2373 2374 while (size) { 2375 if (*pos >= rd_buf_size) 2376 break; 2377 2378 r = put_user(*(rd_buf + result), buf); 2379 if (r) { 2380 result = r; /* r = -EFAULT */ 2381 goto unlock; 2382 } 2383 buf += 1; 2384 size -= 1; 2385 *pos += 1; 2386 result += 1; 2387 } 2388 unlock: 2389 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2390 mutex_unlock(&dev->mode_config.mutex); 2391 kfree(rd_buf); 2392 return result; 2393 } 2394 2395 2396 /* 2397 * function description: Set max_requested_bpc property on the connector 2398 * 2399 * This function will not force the input BPC on connector, it will only 2400 * change the max value. This is equivalent to setting max_bpc through 2401 * xrandr. 2402 * 2403 * The BPC value written must be >= 6 and <= 16. Values outside of this 2404 * range will result in errors. 2405 * 2406 * BPC values: 2407 * 0x6 - 6 BPC 2408 * 0x8 - 8 BPC 2409 * 0xa - 10 BPC 2410 * 0xc - 12 BPC 2411 * 0x10 - 16 BPC 2412 * 2413 * Write the max_bpc in the following way: 2414 * 2415 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2416 * 2417 */ 2418 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2419 size_t size, loff_t *pos) 2420 { 2421 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2422 struct drm_connector *connector = &aconnector->base; 2423 struct dm_connector_state *state; 2424 struct drm_device *dev = connector->dev; 2425 char *wr_buf = NULL; 2426 uint32_t wr_buf_size = 42; 2427 int max_param_num = 1; 2428 long param[1] = {0}; 2429 uint8_t param_nums = 0; 2430 2431 if (size == 0) 2432 return -EINVAL; 2433 2434 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2435 2436 if (!wr_buf) { 2437 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2438 return -ENOSPC; 2439 } 2440 2441 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2442 (long *)param, buf, 2443 max_param_num, 2444 ¶m_nums)) { 2445 kfree(wr_buf); 2446 return -EINVAL; 2447 } 2448 2449 if (param_nums <= 0) { 2450 DRM_DEBUG_DRIVER("user data not be read\n"); 2451 kfree(wr_buf); 2452 return -EINVAL; 2453 } 2454 2455 if (param[0] < 6 || param[0] > 16) { 2456 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2457 kfree(wr_buf); 2458 return -EINVAL; 2459 } 2460 2461 mutex_lock(&dev->mode_config.mutex); 2462 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2463 2464 if (connector->state == NULL) 2465 goto unlock; 2466 2467 state = to_dm_connector_state(connector->state); 2468 state->base.max_requested_bpc = param[0]; 2469 unlock: 2470 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2471 mutex_unlock(&dev->mode_config.mutex); 2472 2473 kfree(wr_buf); 2474 return size; 2475 } 2476 2477 /* 2478 * Backlight at this moment. Read only. 2479 * As written to display, taking ABM and backlight lut into account. 2480 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2481 * 2482 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2483 */ 2484 static int current_backlight_show(struct seq_file *m, void *unused) 2485 { 2486 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2487 struct dc_link *link = aconnector->dc_link; 2488 unsigned int backlight; 2489 2490 backlight = dc_link_get_backlight_level(link); 2491 seq_printf(m, "0x%x\n", backlight); 2492 2493 return 0; 2494 } 2495 2496 /* 2497 * Backlight value that is being approached. Read only. 2498 * As written to display, taking ABM and backlight lut into account. 2499 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2500 * 2501 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2502 */ 2503 static int target_backlight_show(struct seq_file *m, void *unused) 2504 { 2505 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2506 struct dc_link *link = aconnector->dc_link; 2507 unsigned int backlight; 2508 2509 backlight = dc_link_get_target_backlight_pwm(link); 2510 seq_printf(m, "0x%x\n", backlight); 2511 2512 return 0; 2513 } 2514 2515 /* 2516 * function description: Determine if the connector is mst connector 2517 * 2518 * This function helps to determine whether a connector is a mst connector. 2519 * - "root" stands for the root connector of the topology 2520 * - "branch" stands for branch device of the topology 2521 * - "end" stands for leaf node connector of the topology 2522 * - "no" stands for the connector is not a device of a mst topology 2523 * Access it with the following command: 2524 * 2525 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2526 * 2527 */ 2528 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2529 { 2530 struct drm_connector *connector = m->private; 2531 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2532 struct drm_dp_mst_topology_mgr *mgr = NULL; 2533 struct drm_dp_mst_port *port = NULL; 2534 char *role = NULL; 2535 2536 mutex_lock(&aconnector->hpd_lock); 2537 2538 if (aconnector->mst_mgr.mst_state) { 2539 role = "root"; 2540 } else if (aconnector->mst_root && 2541 aconnector->mst_root->mst_mgr.mst_state) { 2542 2543 role = "end"; 2544 2545 mgr = &aconnector->mst_root->mst_mgr; 2546 port = aconnector->mst_output_port; 2547 2548 drm_modeset_lock(&mgr->base.lock, NULL); 2549 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2550 port->mcs) 2551 role = "branch"; 2552 drm_modeset_unlock(&mgr->base.lock); 2553 2554 } else { 2555 role = "no"; 2556 } 2557 2558 seq_printf(m, "%s\n", role); 2559 2560 mutex_unlock(&aconnector->hpd_lock); 2561 2562 return 0; 2563 } 2564 2565 /* 2566 * function description: Read out the mst progress status 2567 * 2568 * This function helps to determine the mst progress status of 2569 * a mst connector. 2570 * 2571 * Access it with the following command: 2572 * 2573 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2574 * 2575 */ 2576 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2577 { 2578 struct drm_connector *connector = m->private; 2579 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2580 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2581 int i; 2582 2583 mutex_lock(&aconnector->hpd_lock); 2584 mutex_lock(&adev->dm.dc_lock); 2585 2586 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2587 seq_puts(m, "disabled\n"); 2588 } else { 2589 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2590 seq_printf(m, "%s:%s\n", 2591 mst_progress_status[i], 2592 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2593 } 2594 2595 mutex_unlock(&adev->dm.dc_lock); 2596 mutex_unlock(&aconnector->hpd_lock); 2597 2598 return 0; 2599 } 2600 2601 /* 2602 * Reports whether the connected display is a USB4 DPIA tunneled display 2603 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2604 */ 2605 static int is_dpia_link_show(struct seq_file *m, void *data) 2606 { 2607 struct drm_connector *connector = m->private; 2608 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2609 struct dc_link *link = aconnector->dc_link; 2610 2611 if (connector->status != connector_status_connected) 2612 return -ENODEV; 2613 2614 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2615 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2616 2617 return 0; 2618 } 2619 2620 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2621 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2622 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2623 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2624 #ifdef CONFIG_DRM_AMD_DC_HDCP 2625 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2626 #endif 2627 DEFINE_SHOW_ATTRIBUTE(internal_display); 2628 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2629 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2630 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2631 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2632 2633 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2634 .owner = THIS_MODULE, 2635 .read = dp_dsc_clock_en_read, 2636 .write = dp_dsc_clock_en_write, 2637 .llseek = default_llseek 2638 }; 2639 2640 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2641 .owner = THIS_MODULE, 2642 .read = dp_dsc_slice_width_read, 2643 .write = dp_dsc_slice_width_write, 2644 .llseek = default_llseek 2645 }; 2646 2647 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2648 .owner = THIS_MODULE, 2649 .read = dp_dsc_slice_height_read, 2650 .write = dp_dsc_slice_height_write, 2651 .llseek = default_llseek 2652 }; 2653 2654 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2655 .owner = THIS_MODULE, 2656 .read = dp_dsc_bits_per_pixel_read, 2657 .write = dp_dsc_bits_per_pixel_write, 2658 .llseek = default_llseek 2659 }; 2660 2661 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2662 .owner = THIS_MODULE, 2663 .read = dp_dsc_pic_width_read, 2664 .llseek = default_llseek 2665 }; 2666 2667 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2668 .owner = THIS_MODULE, 2669 .read = dp_dsc_pic_height_read, 2670 .llseek = default_llseek 2671 }; 2672 2673 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2674 .owner = THIS_MODULE, 2675 .read = dp_dsc_chunk_size_read, 2676 .llseek = default_llseek 2677 }; 2678 2679 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2680 .owner = THIS_MODULE, 2681 .read = dp_dsc_slice_bpg_offset_read, 2682 .llseek = default_llseek 2683 }; 2684 2685 static const struct file_operations trigger_hotplug_debugfs_fops = { 2686 .owner = THIS_MODULE, 2687 .write = trigger_hotplug, 2688 .llseek = default_llseek 2689 }; 2690 2691 static const struct file_operations dp_link_settings_debugfs_fops = { 2692 .owner = THIS_MODULE, 2693 .read = dp_link_settings_read, 2694 .write = dp_link_settings_write, 2695 .llseek = default_llseek 2696 }; 2697 2698 static const struct file_operations dp_phy_settings_debugfs_fop = { 2699 .owner = THIS_MODULE, 2700 .read = dp_phy_settings_read, 2701 .write = dp_phy_settings_write, 2702 .llseek = default_llseek 2703 }; 2704 2705 static const struct file_operations dp_phy_test_pattern_fops = { 2706 .owner = THIS_MODULE, 2707 .write = dp_phy_test_pattern_debugfs_write, 2708 .llseek = default_llseek 2709 }; 2710 2711 static const struct file_operations sdp_message_fops = { 2712 .owner = THIS_MODULE, 2713 .write = dp_sdp_message_debugfs_write, 2714 .llseek = default_llseek 2715 }; 2716 2717 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2718 .owner = THIS_MODULE, 2719 .write = dp_dpcd_address_write, 2720 .llseek = default_llseek 2721 }; 2722 2723 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2724 .owner = THIS_MODULE, 2725 .write = dp_dpcd_size_write, 2726 .llseek = default_llseek 2727 }; 2728 2729 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2730 .owner = THIS_MODULE, 2731 .read = dp_dpcd_data_read, 2732 .write = dp_dpcd_data_write, 2733 .llseek = default_llseek 2734 }; 2735 2736 static const struct file_operations dp_max_bpc_debugfs_fops = { 2737 .owner = THIS_MODULE, 2738 .read = dp_max_bpc_read, 2739 .write = dp_max_bpc_write, 2740 .llseek = default_llseek 2741 }; 2742 2743 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2744 .owner = THIS_MODULE, 2745 .write = dp_dsc_passthrough_set, 2746 .llseek = default_llseek 2747 }; 2748 2749 static const struct { 2750 char *name; 2751 const struct file_operations *fops; 2752 } dp_debugfs_entries[] = { 2753 {"link_settings", &dp_link_settings_debugfs_fops}, 2754 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2755 {"lttpr_status", &dp_lttpr_status_fops}, 2756 {"test_pattern", &dp_phy_test_pattern_fops}, 2757 #ifdef CONFIG_DRM_AMD_DC_HDCP 2758 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2759 #endif 2760 {"sdp_message", &sdp_message_fops}, 2761 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2762 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2763 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2764 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2765 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2766 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2767 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2768 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2769 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2770 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2771 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2772 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2773 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2774 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2775 {"is_mst_connector", &dp_is_mst_connector_fops}, 2776 {"mst_progress_status", &dp_mst_progress_status_fops}, 2777 {"is_dpia_link", &is_dpia_link_fops} 2778 }; 2779 2780 #ifdef CONFIG_DRM_AMD_DC_HDCP 2781 static const struct { 2782 char *name; 2783 const struct file_operations *fops; 2784 } hdmi_debugfs_entries[] = { 2785 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2786 }; 2787 #endif 2788 /* 2789 * Force YUV420 output if available from the given mode 2790 */ 2791 static int force_yuv420_output_set(void *data, u64 val) 2792 { 2793 struct amdgpu_dm_connector *connector = data; 2794 2795 connector->force_yuv420_output = (bool)val; 2796 2797 return 0; 2798 } 2799 2800 /* 2801 * Check if YUV420 is forced when available from the given mode 2802 */ 2803 static int force_yuv420_output_get(void *data, u64 *val) 2804 { 2805 struct amdgpu_dm_connector *connector = data; 2806 2807 *val = connector->force_yuv420_output; 2808 2809 return 0; 2810 } 2811 2812 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2813 force_yuv420_output_set, "%llu\n"); 2814 2815 /* 2816 * Read PSR state 2817 */ 2818 static int psr_get(void *data, u64 *val) 2819 { 2820 struct amdgpu_dm_connector *connector = data; 2821 struct dc_link *link = connector->dc_link; 2822 enum dc_psr_state state = PSR_STATE0; 2823 2824 dc_link_get_psr_state(link, &state); 2825 2826 *val = state; 2827 2828 return 0; 2829 } 2830 2831 /* 2832 * Set dmcub trace event IRQ enable or disable. 2833 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2834 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2835 */ 2836 static int dmcub_trace_event_state_set(void *data, u64 val) 2837 { 2838 struct amdgpu_device *adev = data; 2839 2840 if (val == 1 || val == 0) { 2841 dc_dmub_trace_event_control(adev->dm.dc, val); 2842 adev->dm.dmcub_trace_event_en = (bool)val; 2843 } else 2844 return 0; 2845 2846 return 0; 2847 } 2848 2849 /* 2850 * The interface doesn't need get function, so it will return the 2851 * value of zero 2852 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2853 */ 2854 static int dmcub_trace_event_state_get(void *data, u64 *val) 2855 { 2856 struct amdgpu_device *adev = data; 2857 2858 *val = adev->dm.dmcub_trace_event_en; 2859 return 0; 2860 } 2861 2862 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2863 dmcub_trace_event_state_set, "%llu\n"); 2864 2865 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2866 2867 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2868 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2869 2870 static const struct { 2871 char *name; 2872 const struct file_operations *fops; 2873 } connector_debugfs_entries[] = { 2874 {"force_yuv420_output", &force_yuv420_output_fops}, 2875 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2876 {"internal_display", &internal_display_fops} 2877 }; 2878 2879 /* 2880 * Returns supported customized link rates by this eDP panel. 2881 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2882 */ 2883 static int edp_ilr_show(struct seq_file *m, void *unused) 2884 { 2885 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2886 struct dc_link *link = aconnector->dc_link; 2887 uint8_t supported_link_rates[16]; 2888 uint32_t link_rate_in_khz; 2889 uint32_t entry = 0; 2890 uint8_t dpcd_rev; 2891 2892 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2893 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2894 supported_link_rates, sizeof(supported_link_rates)); 2895 2896 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2897 2898 if (dpcd_rev >= DP_DPCD_REV_13 && 2899 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2900 2901 for (entry = 0; entry < 16; entry += 2) { 2902 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2903 supported_link_rates[entry]) * 200; 2904 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2905 } 2906 } else { 2907 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2908 } 2909 2910 return 0; 2911 } 2912 2913 /* 2914 * Set supported customized link rate to eDP panel. 2915 * 2916 * echo <lane_count> <link_rate option> > ilr_setting 2917 * 2918 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2919 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2920 * to set 4 lanes and 2.16 GHz 2921 */ 2922 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2923 size_t size, loff_t *pos) 2924 { 2925 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2926 struct dc_link *link = connector->dc_link; 2927 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2928 struct dc *dc = (struct dc *)link->dc; 2929 struct dc_link_settings prefer_link_settings; 2930 char *wr_buf = NULL; 2931 const uint32_t wr_buf_size = 40; 2932 /* 0: lane_count; 1: link_rate */ 2933 int max_param_num = 2; 2934 uint8_t param_nums = 0; 2935 long param[2]; 2936 bool valid_input = true; 2937 2938 if (size == 0) 2939 return -EINVAL; 2940 2941 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2942 if (!wr_buf) 2943 return -ENOMEM; 2944 2945 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2946 (long *)param, buf, 2947 max_param_num, 2948 ¶m_nums)) { 2949 kfree(wr_buf); 2950 return -EINVAL; 2951 } 2952 2953 if (param_nums <= 0) { 2954 kfree(wr_buf); 2955 return -EINVAL; 2956 } 2957 2958 switch (param[0]) { 2959 case LANE_COUNT_ONE: 2960 case LANE_COUNT_TWO: 2961 case LANE_COUNT_FOUR: 2962 break; 2963 default: 2964 valid_input = false; 2965 break; 2966 } 2967 2968 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2969 valid_input = false; 2970 2971 if (!valid_input) { 2972 kfree(wr_buf); 2973 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2974 prefer_link_settings.use_link_rate_set = false; 2975 mutex_lock(&adev->dm.dc_lock); 2976 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2977 mutex_unlock(&adev->dm.dc_lock); 2978 return size; 2979 } 2980 2981 /* save user force lane_count, link_rate to preferred settings 2982 * spread spectrum will not be changed 2983 */ 2984 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2985 prefer_link_settings.lane_count = param[0]; 2986 prefer_link_settings.use_link_rate_set = true; 2987 prefer_link_settings.link_rate_set = param[1]; 2988 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2989 2990 mutex_lock(&adev->dm.dc_lock); 2991 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2992 NULL, link, false); 2993 mutex_unlock(&adev->dm.dc_lock); 2994 2995 kfree(wr_buf); 2996 return size; 2997 } 2998 2999 static int edp_ilr_open(struct inode *inode, struct file *file) 3000 { 3001 return single_open(file, edp_ilr_show, inode->i_private); 3002 } 3003 3004 static const struct file_operations edp_ilr_debugfs_fops = { 3005 .owner = THIS_MODULE, 3006 .open = edp_ilr_open, 3007 .read = seq_read, 3008 .llseek = seq_lseek, 3009 .release = single_release, 3010 .write = edp_ilr_write 3011 }; 3012 3013 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3014 { 3015 int i; 3016 struct dentry *dir = connector->base.debugfs_entry; 3017 3018 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3019 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3020 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3021 debugfs_create_file(dp_debugfs_entries[i].name, 3022 0644, dir, connector, 3023 dp_debugfs_entries[i].fops); 3024 } 3025 } 3026 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3027 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3028 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3029 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3030 ¤t_backlight_fops); 3031 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3032 &target_backlight_fops); 3033 debugfs_create_file("ilr_setting", 0644, dir, connector, 3034 &edp_ilr_debugfs_fops); 3035 } 3036 3037 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3038 debugfs_create_file(connector_debugfs_entries[i].name, 3039 0644, dir, connector, 3040 connector_debugfs_entries[i].fops); 3041 } 3042 3043 connector->debugfs_dpcd_address = 0; 3044 connector->debugfs_dpcd_size = 0; 3045 3046 #ifdef CONFIG_DRM_AMD_DC_HDCP 3047 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3048 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3049 debugfs_create_file(hdmi_debugfs_entries[i].name, 3050 0644, dir, connector, 3051 hdmi_debugfs_entries[i].fops); 3052 } 3053 } 3054 #endif 3055 } 3056 3057 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3058 /* 3059 * Set crc window coordinate x start 3060 */ 3061 static int crc_win_x_start_set(void *data, u64 val) 3062 { 3063 struct drm_crtc *crtc = data; 3064 struct drm_device *drm_dev = crtc->dev; 3065 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3066 3067 spin_lock_irq(&drm_dev->event_lock); 3068 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3069 acrtc->dm_irq_params.window_param.update_win = false; 3070 spin_unlock_irq(&drm_dev->event_lock); 3071 3072 return 0; 3073 } 3074 3075 /* 3076 * Get crc window coordinate x start 3077 */ 3078 static int crc_win_x_start_get(void *data, u64 *val) 3079 { 3080 struct drm_crtc *crtc = data; 3081 struct drm_device *drm_dev = crtc->dev; 3082 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3083 3084 spin_lock_irq(&drm_dev->event_lock); 3085 *val = acrtc->dm_irq_params.window_param.x_start; 3086 spin_unlock_irq(&drm_dev->event_lock); 3087 3088 return 0; 3089 } 3090 3091 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3092 crc_win_x_start_set, "%llu\n"); 3093 3094 3095 /* 3096 * Set crc window coordinate y start 3097 */ 3098 static int crc_win_y_start_set(void *data, u64 val) 3099 { 3100 struct drm_crtc *crtc = data; 3101 struct drm_device *drm_dev = crtc->dev; 3102 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3103 3104 spin_lock_irq(&drm_dev->event_lock); 3105 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3106 acrtc->dm_irq_params.window_param.update_win = false; 3107 spin_unlock_irq(&drm_dev->event_lock); 3108 3109 return 0; 3110 } 3111 3112 /* 3113 * Get crc window coordinate y start 3114 */ 3115 static int crc_win_y_start_get(void *data, u64 *val) 3116 { 3117 struct drm_crtc *crtc = data; 3118 struct drm_device *drm_dev = crtc->dev; 3119 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3120 3121 spin_lock_irq(&drm_dev->event_lock); 3122 *val = acrtc->dm_irq_params.window_param.y_start; 3123 spin_unlock_irq(&drm_dev->event_lock); 3124 3125 return 0; 3126 } 3127 3128 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3129 crc_win_y_start_set, "%llu\n"); 3130 3131 /* 3132 * Set crc window coordinate x end 3133 */ 3134 static int crc_win_x_end_set(void *data, u64 val) 3135 { 3136 struct drm_crtc *crtc = data; 3137 struct drm_device *drm_dev = crtc->dev; 3138 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3139 3140 spin_lock_irq(&drm_dev->event_lock); 3141 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3142 acrtc->dm_irq_params.window_param.update_win = false; 3143 spin_unlock_irq(&drm_dev->event_lock); 3144 3145 return 0; 3146 } 3147 3148 /* 3149 * Get crc window coordinate x end 3150 */ 3151 static int crc_win_x_end_get(void *data, u64 *val) 3152 { 3153 struct drm_crtc *crtc = data; 3154 struct drm_device *drm_dev = crtc->dev; 3155 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3156 3157 spin_lock_irq(&drm_dev->event_lock); 3158 *val = acrtc->dm_irq_params.window_param.x_end; 3159 spin_unlock_irq(&drm_dev->event_lock); 3160 3161 return 0; 3162 } 3163 3164 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3165 crc_win_x_end_set, "%llu\n"); 3166 3167 /* 3168 * Set crc window coordinate y end 3169 */ 3170 static int crc_win_y_end_set(void *data, u64 val) 3171 { 3172 struct drm_crtc *crtc = data; 3173 struct drm_device *drm_dev = crtc->dev; 3174 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3175 3176 spin_lock_irq(&drm_dev->event_lock); 3177 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3178 acrtc->dm_irq_params.window_param.update_win = false; 3179 spin_unlock_irq(&drm_dev->event_lock); 3180 3181 return 0; 3182 } 3183 3184 /* 3185 * Get crc window coordinate y end 3186 */ 3187 static int crc_win_y_end_get(void *data, u64 *val) 3188 { 3189 struct drm_crtc *crtc = data; 3190 struct drm_device *drm_dev = crtc->dev; 3191 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3192 3193 spin_lock_irq(&drm_dev->event_lock); 3194 *val = acrtc->dm_irq_params.window_param.y_end; 3195 spin_unlock_irq(&drm_dev->event_lock); 3196 3197 return 0; 3198 } 3199 3200 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3201 crc_win_y_end_set, "%llu\n"); 3202 /* 3203 * Trigger to commit crc window 3204 */ 3205 static int crc_win_update_set(void *data, u64 val) 3206 { 3207 struct drm_crtc *crtc = data; 3208 struct amdgpu_crtc *acrtc; 3209 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3210 3211 if (val) { 3212 acrtc = to_amdgpu_crtc(crtc); 3213 mutex_lock(&adev->dm.dc_lock); 3214 /* PSR may write to OTG CRC window control register, 3215 * so close it before starting secure_display. 3216 */ 3217 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3218 3219 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3220 3221 acrtc->dm_irq_params.window_param.activated = true; 3222 acrtc->dm_irq_params.window_param.update_win = true; 3223 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3224 3225 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3226 mutex_unlock(&adev->dm.dc_lock); 3227 } 3228 3229 return 0; 3230 } 3231 3232 /* 3233 * Get crc window update flag 3234 */ 3235 static int crc_win_update_get(void *data, u64 *val) 3236 { 3237 *val = 0; 3238 return 0; 3239 } 3240 3241 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3242 crc_win_update_set, "%llu\n"); 3243 #endif 3244 void crtc_debugfs_init(struct drm_crtc *crtc) 3245 { 3246 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3247 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3248 3249 if (!dir) 3250 return; 3251 3252 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3253 &crc_win_x_start_fops); 3254 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3255 &crc_win_y_start_fops); 3256 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3257 &crc_win_x_end_fops); 3258 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3259 &crc_win_y_end_fops); 3260 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3261 &crc_win_update_fops); 3262 dput(dir); 3263 #endif 3264 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3265 crtc, &amdgpu_current_bpc_fops); 3266 } 3267 3268 /* 3269 * Writes DTN log state to the user supplied buffer. 3270 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3271 */ 3272 static ssize_t dtn_log_read( 3273 struct file *f, 3274 char __user *buf, 3275 size_t size, 3276 loff_t *pos) 3277 { 3278 struct amdgpu_device *adev = file_inode(f)->i_private; 3279 struct dc *dc = adev->dm.dc; 3280 struct dc_log_buffer_ctx log_ctx = { 0 }; 3281 ssize_t result = 0; 3282 3283 if (!buf || !size) 3284 return -EINVAL; 3285 3286 if (!dc->hwss.log_hw_state) 3287 return 0; 3288 3289 dc->hwss.log_hw_state(dc, &log_ctx); 3290 3291 if (*pos < log_ctx.pos) { 3292 size_t to_copy = log_ctx.pos - *pos; 3293 3294 to_copy = min(to_copy, size); 3295 3296 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3297 *pos += to_copy; 3298 result = to_copy; 3299 } 3300 } 3301 3302 kfree(log_ctx.buf); 3303 3304 return result; 3305 } 3306 3307 /* 3308 * Writes DTN log state to dmesg when triggered via a write. 3309 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3310 */ 3311 static ssize_t dtn_log_write( 3312 struct file *f, 3313 const char __user *buf, 3314 size_t size, 3315 loff_t *pos) 3316 { 3317 struct amdgpu_device *adev = file_inode(f)->i_private; 3318 struct dc *dc = adev->dm.dc; 3319 3320 /* Write triggers log output via dmesg. */ 3321 if (size == 0) 3322 return 0; 3323 3324 if (dc->hwss.log_hw_state) 3325 dc->hwss.log_hw_state(dc, NULL); 3326 3327 return size; 3328 } 3329 3330 static int mst_topo_show(struct seq_file *m, void *unused) 3331 { 3332 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3333 struct drm_device *dev = adev_to_drm(adev); 3334 struct drm_connector *connector; 3335 struct drm_connector_list_iter conn_iter; 3336 struct amdgpu_dm_connector *aconnector; 3337 3338 drm_connector_list_iter_begin(dev, &conn_iter); 3339 drm_for_each_connector_iter(connector, &conn_iter) { 3340 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3341 continue; 3342 3343 aconnector = to_amdgpu_dm_connector(connector); 3344 3345 /* Ensure we're only dumping the topology of a root mst node */ 3346 if (!aconnector->mst_mgr.mst_state) 3347 continue; 3348 3349 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3350 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3351 } 3352 drm_connector_list_iter_end(&conn_iter); 3353 3354 return 0; 3355 } 3356 3357 /* 3358 * Sets trigger hpd for MST topologies. 3359 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3360 * All topologies will be disconnected if val of 0 is set . 3361 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3362 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3363 */ 3364 static int trigger_hpd_mst_set(void *data, u64 val) 3365 { 3366 struct amdgpu_device *adev = data; 3367 struct drm_device *dev = adev_to_drm(adev); 3368 struct drm_connector_list_iter iter; 3369 struct amdgpu_dm_connector *aconnector; 3370 struct drm_connector *connector; 3371 struct dc_link *link = NULL; 3372 3373 if (val == 1) { 3374 drm_connector_list_iter_begin(dev, &iter); 3375 drm_for_each_connector_iter(connector, &iter) { 3376 aconnector = to_amdgpu_dm_connector(connector); 3377 if (aconnector->dc_link->type == dc_connection_mst_branch && 3378 aconnector->mst_mgr.aux) { 3379 mutex_lock(&adev->dm.dc_lock); 3380 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3381 mutex_unlock(&adev->dm.dc_lock); 3382 3383 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3384 } 3385 } 3386 } else if (val == 0) { 3387 drm_connector_list_iter_begin(dev, &iter); 3388 drm_for_each_connector_iter(connector, &iter) { 3389 aconnector = to_amdgpu_dm_connector(connector); 3390 if (!aconnector->dc_link) 3391 continue; 3392 3393 if (!aconnector->mst_root) 3394 continue; 3395 3396 link = aconnector->dc_link; 3397 dc_link_dp_receiver_power_ctrl(link, false); 3398 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3399 link->mst_stream_alloc_table.stream_count = 0; 3400 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3401 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3402 } 3403 } else { 3404 return 0; 3405 } 3406 drm_kms_helper_hotplug_event(dev); 3407 3408 return 0; 3409 } 3410 3411 /* 3412 * The interface doesn't need get function, so it will return the 3413 * value of zero 3414 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3415 */ 3416 static int trigger_hpd_mst_get(void *data, u64 *val) 3417 { 3418 *val = 0; 3419 return 0; 3420 } 3421 3422 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3423 trigger_hpd_mst_set, "%llu\n"); 3424 3425 3426 /* 3427 * Sets the force_timing_sync debug option from the given string. 3428 * All connected displays will be force synchronized immediately. 3429 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3430 */ 3431 static int force_timing_sync_set(void *data, u64 val) 3432 { 3433 struct amdgpu_device *adev = data; 3434 3435 adev->dm.force_timing_sync = (bool)val; 3436 3437 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3438 3439 return 0; 3440 } 3441 3442 /* 3443 * Gets the force_timing_sync debug option value into the given buffer. 3444 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3445 */ 3446 static int force_timing_sync_get(void *data, u64 *val) 3447 { 3448 struct amdgpu_device *adev = data; 3449 3450 *val = adev->dm.force_timing_sync; 3451 3452 return 0; 3453 } 3454 3455 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3456 force_timing_sync_set, "%llu\n"); 3457 3458 3459 /* 3460 * Disables all HPD and HPD RX interrupt handling in the 3461 * driver when set to 1. Default is 0. 3462 */ 3463 static int disable_hpd_set(void *data, u64 val) 3464 { 3465 struct amdgpu_device *adev = data; 3466 3467 adev->dm.disable_hpd_irq = (bool)val; 3468 3469 return 0; 3470 } 3471 3472 3473 /* 3474 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3475 * 0 otherwise. 3476 */ 3477 static int disable_hpd_get(void *data, u64 *val) 3478 { 3479 struct amdgpu_device *adev = data; 3480 3481 *val = adev->dm.disable_hpd_irq; 3482 3483 return 0; 3484 } 3485 3486 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3487 disable_hpd_set, "%llu\n"); 3488 3489 /* 3490 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3491 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3492 */ 3493 static int dp_force_sst_set(void *data, u64 val) 3494 { 3495 struct amdgpu_device *adev = data; 3496 3497 adev->dm.dc->debug.set_mst_en_for_sst = val; 3498 3499 return 0; 3500 } 3501 3502 static int dp_force_sst_get(void *data, u64 *val) 3503 { 3504 struct amdgpu_device *adev = data; 3505 3506 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3507 3508 return 0; 3509 } 3510 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3511 dp_force_sst_set, "%llu\n"); 3512 3513 /* 3514 * Force DP2 sequence without VESA certified cable. 3515 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3516 */ 3517 static int dp_ignore_cable_id_set(void *data, u64 val) 3518 { 3519 struct amdgpu_device *adev = data; 3520 3521 adev->dm.dc->debug.ignore_cable_id = val; 3522 3523 return 0; 3524 } 3525 3526 static int dp_ignore_cable_id_get(void *data, u64 *val) 3527 { 3528 struct amdgpu_device *adev = data; 3529 3530 *val = adev->dm.dc->debug.ignore_cable_id; 3531 3532 return 0; 3533 } 3534 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3535 dp_ignore_cable_id_set, "%llu\n"); 3536 3537 /* 3538 * Sets the DC visual confirm debug option from the given string. 3539 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3540 */ 3541 static int visual_confirm_set(void *data, u64 val) 3542 { 3543 struct amdgpu_device *adev = data; 3544 3545 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3546 3547 return 0; 3548 } 3549 3550 /* 3551 * Reads the DC visual confirm debug option value into the given buffer. 3552 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3553 */ 3554 static int visual_confirm_get(void *data, u64 *val) 3555 { 3556 struct amdgpu_device *adev = data; 3557 3558 *val = adev->dm.dc->debug.visual_confirm; 3559 3560 return 0; 3561 } 3562 3563 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3564 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3565 visual_confirm_set, "%llu\n"); 3566 3567 3568 /* 3569 * Sets the DC skip_detection_link_training debug option from the given string. 3570 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3571 */ 3572 static int skip_detection_link_training_set(void *data, u64 val) 3573 { 3574 struct amdgpu_device *adev = data; 3575 3576 if (val == 0) 3577 adev->dm.dc->debug.skip_detection_link_training = false; 3578 else 3579 adev->dm.dc->debug.skip_detection_link_training = true; 3580 3581 return 0; 3582 } 3583 3584 /* 3585 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3586 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3587 */ 3588 static int skip_detection_link_training_get(void *data, u64 *val) 3589 { 3590 struct amdgpu_device *adev = data; 3591 3592 *val = adev->dm.dc->debug.skip_detection_link_training; 3593 3594 return 0; 3595 } 3596 3597 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3598 skip_detection_link_training_get, 3599 skip_detection_link_training_set, "%llu\n"); 3600 3601 /* 3602 * Dumps the DCC_EN bit for each pipe. 3603 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3604 */ 3605 static ssize_t dcc_en_bits_read( 3606 struct file *f, 3607 char __user *buf, 3608 size_t size, 3609 loff_t *pos) 3610 { 3611 struct amdgpu_device *adev = file_inode(f)->i_private; 3612 struct dc *dc = adev->dm.dc; 3613 char *rd_buf = NULL; 3614 const uint32_t rd_buf_size = 32; 3615 uint32_t result = 0; 3616 int offset = 0; 3617 int num_pipes = dc->res_pool->pipe_count; 3618 int *dcc_en_bits; 3619 int i, r; 3620 3621 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3622 if (!dcc_en_bits) 3623 return -ENOMEM; 3624 3625 if (!dc->hwss.get_dcc_en_bits) { 3626 kfree(dcc_en_bits); 3627 return 0; 3628 } 3629 3630 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3631 3632 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3633 if (!rd_buf) { 3634 kfree(dcc_en_bits); 3635 return -ENOMEM; 3636 } 3637 3638 for (i = 0; i < num_pipes; i++) 3639 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3640 "%d ", dcc_en_bits[i]); 3641 rd_buf[strlen(rd_buf)] = '\n'; 3642 3643 kfree(dcc_en_bits); 3644 3645 while (size) { 3646 if (*pos >= rd_buf_size) 3647 break; 3648 r = put_user(*(rd_buf + result), buf); 3649 if (r) { 3650 kfree(rd_buf); 3651 return r; /* r = -EFAULT */ 3652 } 3653 buf += 1; 3654 size -= 1; 3655 *pos += 1; 3656 result += 1; 3657 } 3658 3659 kfree(rd_buf); 3660 return result; 3661 } 3662 3663 void dtn_debugfs_init(struct amdgpu_device *adev) 3664 { 3665 static const struct file_operations dtn_log_fops = { 3666 .owner = THIS_MODULE, 3667 .read = dtn_log_read, 3668 .write = dtn_log_write, 3669 .llseek = default_llseek 3670 }; 3671 static const struct file_operations dcc_en_bits_fops = { 3672 .owner = THIS_MODULE, 3673 .read = dcc_en_bits_read, 3674 .llseek = default_llseek 3675 }; 3676 3677 struct drm_minor *minor = adev_to_drm(adev)->primary; 3678 struct dentry *root = minor->debugfs_root; 3679 3680 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3681 adev, &mst_topo_fops); 3682 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3683 &dtn_log_fops); 3684 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3685 &dp_set_mst_en_for_sst_ops); 3686 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3687 &dp_ignore_cable_id_ops); 3688 3689 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3690 &visual_confirm_fops); 3691 3692 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3693 &skip_detection_link_training_fops); 3694 3695 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3696 adev, &dmub_tracebuffer_fops); 3697 3698 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3699 adev, &dmub_fw_state_fops); 3700 3701 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3702 adev, &force_timing_sync_ops); 3703 3704 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3705 adev, &dmcub_trace_event_state_fops); 3706 3707 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3708 adev, &trigger_hpd_mst_ops); 3709 3710 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3711 &dcc_en_bits_fops); 3712 3713 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3714 &disable_hpd_ops); 3715 3716 } 3717