1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/uaccess.h> 27 28 #include "dc.h" 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "amdgpu_dm_debugfs.h" 32 #include "dm_helpers.h" 33 #include "dmub/dmub_srv.h" 34 #include "resource.h" 35 #include "dsc.h" 36 #include "dc_link_dp.h" 37 38 struct dmub_debugfs_trace_header { 39 uint32_t entry_count; 40 uint32_t reserved[3]; 41 }; 42 43 struct dmub_debugfs_trace_entry { 44 uint32_t trace_code; 45 uint32_t tick_count; 46 uint32_t param0; 47 uint32_t param1; 48 }; 49 50 static inline const char *yesno(bool v) 51 { 52 return v ? "yes" : "no"; 53 } 54 55 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 56 * 57 * Function takes in attributes passed to debugfs write entry 58 * and writes into param array. 59 * The user passes max_param_num to identify maximum number of 60 * parameters that could be parsed. 61 * 62 */ 63 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 64 long *param, const char __user *buf, 65 int max_param_num, 66 uint8_t *param_nums) 67 { 68 char *wr_buf_ptr = NULL; 69 uint32_t wr_buf_count = 0; 70 int r; 71 char *sub_str = NULL; 72 const char delimiter[3] = {' ', '\n', '\0'}; 73 uint8_t param_index = 0; 74 75 *param_nums = 0; 76 77 wr_buf_ptr = wr_buf; 78 79 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 80 81 /* r is bytes not be copied */ 82 if (r >= wr_buf_size) { 83 DRM_DEBUG_DRIVER("user data not be read\n"); 84 return -EINVAL; 85 } 86 87 /* check number of parameters. isspace could not differ space and \n */ 88 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 89 /* skip space*/ 90 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 91 wr_buf_ptr++; 92 wr_buf_count++; 93 } 94 95 if (wr_buf_count == wr_buf_size) 96 break; 97 98 /* skip non-space*/ 99 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 100 wr_buf_ptr++; 101 wr_buf_count++; 102 } 103 104 (*param_nums)++; 105 106 if (wr_buf_count == wr_buf_size) 107 break; 108 } 109 110 if (*param_nums > max_param_num) 111 *param_nums = max_param_num; 112 113 wr_buf_ptr = wr_buf; /* reset buf pointer */ 114 wr_buf_count = 0; /* number of char already checked */ 115 116 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 117 wr_buf_ptr++; 118 wr_buf_count++; 119 } 120 121 while (param_index < *param_nums) { 122 /* after strsep, wr_buf_ptr will be moved to after space */ 123 sub_str = strsep(&wr_buf_ptr, delimiter); 124 125 r = kstrtol(sub_str, 16, &(param[param_index])); 126 127 if (r) 128 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 129 130 param_index++; 131 } 132 133 return 0; 134 } 135 136 /* function description 137 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 138 * 139 * valid lane count value: 1, 2, 4 140 * valid link rate value: 141 * 06h = 1.62Gbps per lane 142 * 0Ah = 2.7Gbps per lane 143 * 0Ch = 3.24Gbps per lane 144 * 14h = 5.4Gbps per lane 145 * 1Eh = 8.1Gbps per lane 146 * 147 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 148 * 149 * --- to get dp configuration 150 * 151 * cat link_settings 152 * 153 * It will list current, verified, reported, preferred dp configuration. 154 * current -- for current video mode 155 * verified --- maximum configuration which pass link training 156 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 157 * preferred --- user force settings 158 * 159 * --- set (or force) dp configuration 160 * 161 * echo <lane_count> <link_rate> > link_settings 162 * 163 * for example, to force to 2 lane, 2.7GHz, 164 * echo 4 0xa > link_settings 165 * 166 * spread_spectrum could not be changed dynamically. 167 * 168 * in case invalid lane count, link rate are force, no hw programming will be 169 * done. please check link settings after force operation to see if HW get 170 * programming. 171 * 172 * cat link_settings 173 * 174 * check current and preferred settings. 175 * 176 */ 177 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 178 size_t size, loff_t *pos) 179 { 180 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 181 struct dc_link *link = connector->dc_link; 182 char *rd_buf = NULL; 183 char *rd_buf_ptr = NULL; 184 const uint32_t rd_buf_size = 100; 185 uint32_t result = 0; 186 uint8_t str_len = 0; 187 int r; 188 189 if (*pos & 3 || size & 3) 190 return -EINVAL; 191 192 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 193 if (!rd_buf) 194 return 0; 195 196 rd_buf_ptr = rd_buf; 197 198 str_len = strlen("Current: %d %d %d "); 199 snprintf(rd_buf_ptr, str_len, "Current: %d %d %d ", 200 link->cur_link_settings.lane_count, 201 link->cur_link_settings.link_rate, 202 link->cur_link_settings.link_spread); 203 rd_buf_ptr += str_len; 204 205 str_len = strlen("Verified: %d %d %d "); 206 snprintf(rd_buf_ptr, str_len, "Verified: %d %d %d ", 207 link->verified_link_cap.lane_count, 208 link->verified_link_cap.link_rate, 209 link->verified_link_cap.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Reported: %d %d %d "); 213 snprintf(rd_buf_ptr, str_len, "Reported: %d %d %d ", 214 link->reported_link_cap.lane_count, 215 link->reported_link_cap.link_rate, 216 link->reported_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Preferred: %d %d %d "); 220 snprintf(rd_buf_ptr, str_len, "Preferred: %d %d %d\n", 221 link->preferred_link_setting.lane_count, 222 link->preferred_link_setting.link_rate, 223 link->preferred_link_setting.link_spread); 224 225 while (size) { 226 if (*pos >= rd_buf_size) 227 break; 228 229 r = put_user(*(rd_buf + result), buf); 230 if (r) 231 return r; /* r = -EFAULT */ 232 233 buf += 1; 234 size -= 1; 235 *pos += 1; 236 result += 1; 237 } 238 239 kfree(rd_buf); 240 return result; 241 } 242 243 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 244 size_t size, loff_t *pos) 245 { 246 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 247 struct dc_link *link = connector->dc_link; 248 struct dc *dc = (struct dc *)link->dc; 249 struct dc_link_settings prefer_link_settings; 250 char *wr_buf = NULL; 251 const uint32_t wr_buf_size = 40; 252 /* 0: lane_count; 1: link_rate */ 253 int max_param_num = 2; 254 uint8_t param_nums = 0; 255 long param[2]; 256 bool valid_input = false; 257 258 if (size == 0) 259 return -EINVAL; 260 261 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 262 if (!wr_buf) 263 return -ENOSPC; 264 265 if (parse_write_buffer_into_params(wr_buf, size, 266 (long *)param, buf, 267 max_param_num, 268 ¶m_nums)) { 269 kfree(wr_buf); 270 return -EINVAL; 271 } 272 273 if (param_nums <= 0) { 274 kfree(wr_buf); 275 DRM_DEBUG_DRIVER("user data not be read\n"); 276 return -EINVAL; 277 } 278 279 switch (param[0]) { 280 case LANE_COUNT_ONE: 281 case LANE_COUNT_TWO: 282 case LANE_COUNT_FOUR: 283 valid_input = true; 284 break; 285 default: 286 break; 287 } 288 289 switch (param[1]) { 290 case LINK_RATE_LOW: 291 case LINK_RATE_HIGH: 292 case LINK_RATE_RBR2: 293 case LINK_RATE_HIGH2: 294 case LINK_RATE_HIGH3: 295 valid_input = true; 296 break; 297 default: 298 break; 299 } 300 301 if (!valid_input) { 302 kfree(wr_buf); 303 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 304 return size; 305 } 306 307 /* save user force lane_count, link_rate to preferred settings 308 * spread spectrum will not be changed 309 */ 310 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 311 prefer_link_settings.lane_count = param[0]; 312 prefer_link_settings.link_rate = param[1]; 313 314 dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link); 315 316 kfree(wr_buf); 317 return size; 318 } 319 320 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 321 * post-cursor2 (defined by VESA DP specification) 322 * 323 * valid values 324 * voltage swing: 0,1,2,3 325 * pre-emphasis : 0,1,2,3 326 * post cursor2 : 0,1,2,3 327 * 328 * 329 * how to use this debugfs 330 * 331 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 332 * 333 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 334 * 335 * To figure out which DP-x is the display for DP to be check, 336 * cd DP-x 337 * ls -ll 338 * There should be debugfs file, like link_settings, phy_settings. 339 * cat link_settings 340 * from lane_count, link_rate to figure which DP-x is for display to be worked 341 * on 342 * 343 * To get current DP PHY settings, 344 * cat phy_settings 345 * 346 * To change DP PHY settings, 347 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 348 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 349 * 0, 350 * echo 2 3 0 > phy_settings 351 * 352 * To check if change be applied, get current phy settings by 353 * cat phy_settings 354 * 355 * In case invalid values are set by user, like 356 * echo 1 4 0 > phy_settings 357 * 358 * HW will NOT be programmed by these settings. 359 * cat phy_settings will show the previous valid settings. 360 */ 361 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 362 size_t size, loff_t *pos) 363 { 364 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 365 struct dc_link *link = connector->dc_link; 366 char *rd_buf = NULL; 367 const uint32_t rd_buf_size = 20; 368 uint32_t result = 0; 369 int r; 370 371 if (*pos & 3 || size & 3) 372 return -EINVAL; 373 374 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 375 if (!rd_buf) 376 return -EINVAL; 377 378 snprintf(rd_buf, rd_buf_size, " %d %d %d ", 379 link->cur_lane_setting.VOLTAGE_SWING, 380 link->cur_lane_setting.PRE_EMPHASIS, 381 link->cur_lane_setting.POST_CURSOR2); 382 383 while (size) { 384 if (*pos >= rd_buf_size) 385 break; 386 387 r = put_user((*(rd_buf + result)), buf); 388 if (r) 389 return r; /* r = -EFAULT */ 390 391 buf += 1; 392 size -= 1; 393 *pos += 1; 394 result += 1; 395 } 396 397 kfree(rd_buf); 398 return result; 399 } 400 401 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 402 size_t size, loff_t *pos) 403 { 404 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 405 struct dc_link *link = connector->dc_link; 406 struct dc *dc = (struct dc *)link->dc; 407 char *wr_buf = NULL; 408 uint32_t wr_buf_size = 40; 409 long param[3]; 410 bool use_prefer_link_setting; 411 struct link_training_settings link_lane_settings; 412 int max_param_num = 3; 413 uint8_t param_nums = 0; 414 int r = 0; 415 416 417 if (size == 0) 418 return -EINVAL; 419 420 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 421 if (!wr_buf) 422 return -ENOSPC; 423 424 if (parse_write_buffer_into_params(wr_buf, size, 425 (long *)param, buf, 426 max_param_num, 427 ¶m_nums)) { 428 kfree(wr_buf); 429 return -EINVAL; 430 } 431 432 if (param_nums <= 0) { 433 kfree(wr_buf); 434 DRM_DEBUG_DRIVER("user data not be read\n"); 435 return -EINVAL; 436 } 437 438 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 439 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 440 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 441 kfree(wr_buf); 442 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 443 return size; 444 } 445 446 /* get link settings: lane count, link rate */ 447 use_prefer_link_setting = 448 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 449 (link->test_pattern_enabled)); 450 451 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 452 453 if (use_prefer_link_setting) { 454 link_lane_settings.link_settings.lane_count = 455 link->preferred_link_setting.lane_count; 456 link_lane_settings.link_settings.link_rate = 457 link->preferred_link_setting.link_rate; 458 link_lane_settings.link_settings.link_spread = 459 link->preferred_link_setting.link_spread; 460 } else { 461 link_lane_settings.link_settings.lane_count = 462 link->cur_link_settings.lane_count; 463 link_lane_settings.link_settings.link_rate = 464 link->cur_link_settings.link_rate; 465 link_lane_settings.link_settings.link_spread = 466 link->cur_link_settings.link_spread; 467 } 468 469 /* apply phy settings from user */ 470 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 471 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 472 (enum dc_voltage_swing) (param[0]); 473 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 474 (enum dc_pre_emphasis) (param[1]); 475 link_lane_settings.lane_settings[r].POST_CURSOR2 = 476 (enum dc_post_cursor2) (param[2]); 477 } 478 479 /* program ASIC registers and DPCD registers */ 480 dc_link_set_drive_settings(dc, &link_lane_settings, link); 481 482 kfree(wr_buf); 483 return size; 484 } 485 486 /* function description 487 * 488 * set PHY layer or Link layer test pattern 489 * PHY test pattern is used for PHY SI check. 490 * Link layer test will not affect PHY SI. 491 * 492 * Reset Test Pattern: 493 * 0 = DP_TEST_PATTERN_VIDEO_MODE 494 * 495 * PHY test pattern supported: 496 * 1 = DP_TEST_PATTERN_D102 497 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 498 * 3 = DP_TEST_PATTERN_PRBS7 499 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 500 * 5 = DP_TEST_PATTERN_CP2520_1 501 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 502 * 7 = DP_TEST_PATTERN_CP2520_3 503 * 504 * DP PHY Link Training Patterns 505 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 506 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 507 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 508 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 509 * 510 * DP Link Layer Test pattern 511 * c = DP_TEST_PATTERN_COLOR_SQUARES 512 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 513 * e = DP_TEST_PATTERN_VERTICAL_BARS 514 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 515 * 10= DP_TEST_PATTERN_COLOR_RAMP 516 * 517 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 518 * 519 * --- set test pattern 520 * echo <test pattern #> > test_pattern 521 * 522 * If test pattern # is not supported, NO HW programming will be done. 523 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 524 * for the user pattern. input 10 bytes data are separated by space 525 * 526 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 527 * 528 * --- reset test pattern 529 * echo 0 > test_pattern 530 * 531 * --- HPD detection is disabled when set PHY test pattern 532 * 533 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 534 * is disable. User could unplug DP display from DP connected and plug scope to 535 * check test pattern PHY SI. 536 * If there is need unplug scope and plug DP display back, do steps below: 537 * echo 0 > phy_test_pattern 538 * unplug scope 539 * plug DP display. 540 * 541 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 542 * driver could detect "unplug scope" and "plug DP display" 543 */ 544 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 545 size_t size, loff_t *pos) 546 { 547 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 548 struct dc_link *link = connector->dc_link; 549 char *wr_buf = NULL; 550 uint32_t wr_buf_size = 100; 551 long param[11] = {0x0}; 552 int max_param_num = 11; 553 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 554 bool disable_hpd = false; 555 bool valid_test_pattern = false; 556 uint8_t param_nums = 0; 557 /* init with default 80bit custom pattern */ 558 uint8_t custom_pattern[10] = { 559 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 560 0x1f, 0x7c, 0xf0, 0xc1, 0x07 561 }; 562 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 563 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 564 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 565 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 566 struct link_training_settings link_training_settings; 567 int i; 568 569 if (size == 0) 570 return -EINVAL; 571 572 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 573 if (!wr_buf) 574 return -ENOSPC; 575 576 if (parse_write_buffer_into_params(wr_buf, size, 577 (long *)param, buf, 578 max_param_num, 579 ¶m_nums)) { 580 kfree(wr_buf); 581 return -EINVAL; 582 } 583 584 if (param_nums <= 0) { 585 kfree(wr_buf); 586 DRM_DEBUG_DRIVER("user data not be read\n"); 587 return -EINVAL; 588 } 589 590 591 test_pattern = param[0]; 592 593 switch (test_pattern) { 594 case DP_TEST_PATTERN_VIDEO_MODE: 595 case DP_TEST_PATTERN_COLOR_SQUARES: 596 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 597 case DP_TEST_PATTERN_VERTICAL_BARS: 598 case DP_TEST_PATTERN_HORIZONTAL_BARS: 599 case DP_TEST_PATTERN_COLOR_RAMP: 600 valid_test_pattern = true; 601 break; 602 603 case DP_TEST_PATTERN_D102: 604 case DP_TEST_PATTERN_SYMBOL_ERROR: 605 case DP_TEST_PATTERN_PRBS7: 606 case DP_TEST_PATTERN_80BIT_CUSTOM: 607 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 608 case DP_TEST_PATTERN_TRAINING_PATTERN4: 609 disable_hpd = true; 610 valid_test_pattern = true; 611 break; 612 613 default: 614 valid_test_pattern = false; 615 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 616 break; 617 } 618 619 if (!valid_test_pattern) { 620 kfree(wr_buf); 621 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 622 return size; 623 } 624 625 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 626 for (i = 0; i < 10; i++) { 627 if ((uint8_t) param[i + 1] != 0x0) 628 break; 629 } 630 631 if (i < 10) { 632 /* not use default value */ 633 for (i = 0; i < 10; i++) 634 custom_pattern[i] = (uint8_t) param[i + 1]; 635 } 636 } 637 638 /* Usage: set DP physical test pattern using debugfs with normal DP 639 * panel. Then plug out DP panel and connect a scope to measure 640 * For normal video mode and test pattern generated from CRCT, 641 * they are visibile to user. So do not disable HPD. 642 * Video Mode is also set to clear the test pattern, so enable HPD 643 * because it might have been disabled after a test pattern was set. 644 * AUX depends on HPD * sequence dependent, do not move! 645 */ 646 if (!disable_hpd) 647 dc_link_enable_hpd(link); 648 649 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 650 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 651 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 652 653 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 654 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 655 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 656 657 link_training_settings.link_settings = cur_link_settings; 658 659 660 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 661 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 662 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 663 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 664 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 665 link_training_settings.link_settings = prefer_link_settings; 666 } 667 668 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 669 link_training_settings.lane_settings[i] = link->cur_lane_setting; 670 671 dc_link_set_test_pattern( 672 link, 673 test_pattern, 674 DP_TEST_PATTERN_COLOR_SPACE_RGB, 675 &link_training_settings, 676 custom_pattern, 677 10); 678 679 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 680 * Then plug out DP panel and connect a scope to measure DP PHY signal. 681 * Need disable interrupt to avoid SW driver disable DP output. This is 682 * done after the test pattern is set. 683 */ 684 if (valid_test_pattern && disable_hpd) 685 dc_link_disable_hpd(link); 686 687 kfree(wr_buf); 688 689 return size; 690 } 691 692 /* 693 * Returns the DMCUB tracebuffer contents. 694 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 695 */ 696 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 697 { 698 struct amdgpu_device *adev = m->private; 699 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 700 struct dmub_debugfs_trace_entry *entries; 701 uint8_t *tbuf_base; 702 uint32_t tbuf_size, max_entries, num_entries, i; 703 704 if (!fb_info) 705 return 0; 706 707 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 708 if (!tbuf_base) 709 return 0; 710 711 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 712 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 713 sizeof(struct dmub_debugfs_trace_entry); 714 715 num_entries = 716 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 717 718 num_entries = min(num_entries, max_entries); 719 720 entries = (struct dmub_debugfs_trace_entry 721 *)(tbuf_base + 722 sizeof(struct dmub_debugfs_trace_header)); 723 724 for (i = 0; i < num_entries; ++i) { 725 struct dmub_debugfs_trace_entry *entry = &entries[i]; 726 727 seq_printf(m, 728 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 729 entry->trace_code, entry->tick_count, entry->param0, 730 entry->param1); 731 } 732 733 return 0; 734 } 735 736 /* 737 * Returns the DMCUB firmware state contents. 738 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 739 */ 740 static int dmub_fw_state_show(struct seq_file *m, void *data) 741 { 742 struct amdgpu_device *adev = m->private; 743 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 744 uint8_t *state_base; 745 uint32_t state_size; 746 747 if (!fb_info) 748 return 0; 749 750 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 751 if (!state_base) 752 return 0; 753 754 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 755 756 return seq_write(m, state_base, state_size); 757 } 758 759 /* 760 * Returns the current and maximum output bpc for the connector. 761 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 762 */ 763 static int output_bpc_show(struct seq_file *m, void *data) 764 { 765 struct drm_connector *connector = m->private; 766 struct drm_device *dev = connector->dev; 767 struct drm_crtc *crtc = NULL; 768 struct dm_crtc_state *dm_crtc_state = NULL; 769 int res = -ENODEV; 770 unsigned int bpc; 771 772 mutex_lock(&dev->mode_config.mutex); 773 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 774 775 if (connector->state == NULL) 776 goto unlock; 777 778 crtc = connector->state->crtc; 779 if (crtc == NULL) 780 goto unlock; 781 782 drm_modeset_lock(&crtc->mutex, NULL); 783 if (crtc->state == NULL) 784 goto unlock; 785 786 dm_crtc_state = to_dm_crtc_state(crtc->state); 787 if (dm_crtc_state->stream == NULL) 788 goto unlock; 789 790 switch (dm_crtc_state->stream->timing.display_color_depth) { 791 case COLOR_DEPTH_666: 792 bpc = 6; 793 break; 794 case COLOR_DEPTH_888: 795 bpc = 8; 796 break; 797 case COLOR_DEPTH_101010: 798 bpc = 10; 799 break; 800 case COLOR_DEPTH_121212: 801 bpc = 12; 802 break; 803 case COLOR_DEPTH_161616: 804 bpc = 16; 805 break; 806 default: 807 goto unlock; 808 } 809 810 seq_printf(m, "Current: %u\n", bpc); 811 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 812 res = 0; 813 814 unlock: 815 if (crtc) 816 drm_modeset_unlock(&crtc->mutex); 817 818 drm_modeset_unlock(&dev->mode_config.connection_mutex); 819 mutex_unlock(&dev->mode_config.mutex); 820 821 return res; 822 } 823 824 #ifdef CONFIG_DRM_AMD_DC_HDCP 825 /* 826 * Returns the HDCP capability of the Display (1.4 for now). 827 * 828 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 829 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 830 * 831 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 832 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 833 */ 834 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 835 { 836 struct drm_connector *connector = m->private; 837 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 838 bool hdcp_cap, hdcp2_cap; 839 840 if (connector->status != connector_status_connected) 841 return -ENODEV; 842 843 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 844 845 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 846 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 847 848 849 if (hdcp_cap) 850 seq_printf(m, "%s ", "HDCP1.4"); 851 if (hdcp2_cap) 852 seq_printf(m, "%s ", "HDCP2.2"); 853 854 if (!hdcp_cap && !hdcp2_cap) 855 seq_printf(m, "%s ", "None"); 856 857 seq_puts(m, "\n"); 858 859 return 0; 860 } 861 #endif 862 /* function description 863 * 864 * generic SDP message access for testing 865 * 866 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 867 * 868 * SDP header 869 * Hb0 : Secondary-Data Packet ID 870 * Hb1 : Secondary-Data Packet type 871 * Hb2 : Secondary-Data-packet-specific header, Byte 0 872 * Hb3 : Secondary-Data-packet-specific header, Byte 1 873 * 874 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 875 */ 876 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 877 size_t size, loff_t *pos) 878 { 879 int r; 880 uint8_t data[36]; 881 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 882 struct dm_crtc_state *acrtc_state; 883 uint32_t write_size = 36; 884 885 if (connector->base.status != connector_status_connected) 886 return -ENODEV; 887 888 if (size == 0) 889 return 0; 890 891 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 892 893 r = copy_from_user(data, buf, write_size); 894 895 write_size -= r; 896 897 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 898 899 return write_size; 900 } 901 902 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 903 size_t size, loff_t *pos) 904 { 905 int r; 906 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 907 908 if (size < sizeof(connector->debugfs_dpcd_address)) 909 return -EINVAL; 910 911 r = copy_from_user(&connector->debugfs_dpcd_address, 912 buf, sizeof(connector->debugfs_dpcd_address)); 913 914 return size - r; 915 } 916 917 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 918 size_t size, loff_t *pos) 919 { 920 int r; 921 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 922 923 if (size < sizeof(connector->debugfs_dpcd_size)) 924 return -EINVAL; 925 926 r = copy_from_user(&connector->debugfs_dpcd_size, 927 buf, sizeof(connector->debugfs_dpcd_size)); 928 929 if (connector->debugfs_dpcd_size > 256) 930 connector->debugfs_dpcd_size = 0; 931 932 return size - r; 933 } 934 935 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 936 size_t size, loff_t *pos) 937 { 938 int r; 939 char *data; 940 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 941 struct dc_link *link = connector->dc_link; 942 uint32_t write_size = connector->debugfs_dpcd_size; 943 944 if (!write_size || size < write_size) 945 return -EINVAL; 946 947 data = kzalloc(write_size, GFP_KERNEL); 948 if (!data) 949 return 0; 950 951 r = copy_from_user(data, buf, write_size); 952 953 dm_helpers_dp_write_dpcd(link->ctx, link, 954 connector->debugfs_dpcd_address, data, write_size - r); 955 kfree(data); 956 return write_size - r; 957 } 958 959 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 960 size_t size, loff_t *pos) 961 { 962 int r; 963 char *data; 964 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 965 struct dc_link *link = connector->dc_link; 966 uint32_t read_size = connector->debugfs_dpcd_size; 967 968 if (!read_size || size < read_size) 969 return 0; 970 971 data = kzalloc(read_size, GFP_KERNEL); 972 if (!data) 973 return 0; 974 975 dm_helpers_dp_read_dpcd(link->ctx, link, 976 connector->debugfs_dpcd_address, data, read_size); 977 978 r = copy_to_user(buf, data, read_size); 979 980 kfree(data); 981 return read_size - r; 982 } 983 984 /* function: Read link's DSC & FEC capabilities 985 * 986 * 987 * Access it with the following command (you need to specify 988 * connector like DP-1): 989 * 990 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 991 * 992 */ 993 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 994 { 995 struct drm_connector *connector = m->private; 996 struct drm_modeset_acquire_ctx ctx; 997 struct drm_device *dev = connector->dev; 998 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 999 int ret = 0; 1000 bool try_again = false; 1001 bool is_fec_supported = false; 1002 bool is_dsc_supported = false; 1003 struct dpcd_caps dpcd_caps; 1004 1005 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1006 do { 1007 try_again = false; 1008 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1009 if (ret) { 1010 if (ret == -EDEADLK) { 1011 ret = drm_modeset_backoff(&ctx); 1012 if (!ret) { 1013 try_again = true; 1014 continue; 1015 } 1016 } 1017 break; 1018 } 1019 if (connector->status != connector_status_connected) { 1020 ret = -ENODEV; 1021 break; 1022 } 1023 dpcd_caps = aconnector->dc_link->dpcd_caps; 1024 if (aconnector->port) { 1025 /* aconnector sets dsc_aux during get_modes call 1026 * if MST connector has it means it can either 1027 * enable DSC on the sink device or on MST branch 1028 * its connected to. 1029 */ 1030 if (aconnector->dsc_aux) { 1031 is_fec_supported = true; 1032 is_dsc_supported = true; 1033 } 1034 } else { 1035 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1036 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1037 } 1038 } while (try_again); 1039 1040 drm_modeset_drop_locks(&ctx); 1041 drm_modeset_acquire_fini(&ctx); 1042 1043 seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported)); 1044 seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported)); 1045 1046 return ret; 1047 } 1048 1049 /* function: Trigger virtual HPD redetection on connector 1050 * 1051 * This function will perform link rediscovery, link disable 1052 * and enable, and dm connector state update. 1053 * 1054 * Retrigger HPD on an existing connector by echoing 1 into 1055 * its respectful "trigger_hotplug" debugfs entry: 1056 * 1057 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1058 * 1059 * This function can perform HPD unplug: 1060 * 1061 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1062 * 1063 */ 1064 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1065 size_t size, loff_t *pos) 1066 { 1067 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1068 struct drm_connector *connector = &aconnector->base; 1069 struct dc_link *link = NULL; 1070 struct drm_device *dev = connector->dev; 1071 enum dc_connection_type new_connection_type = dc_connection_none; 1072 char *wr_buf = NULL; 1073 uint32_t wr_buf_size = 42; 1074 int max_param_num = 1; 1075 long param[1] = {0}; 1076 uint8_t param_nums = 0; 1077 1078 if (!aconnector || !aconnector->dc_link) 1079 return -EINVAL; 1080 1081 if (size == 0) 1082 return -EINVAL; 1083 1084 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1085 1086 if (!wr_buf) { 1087 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1088 return -ENOSPC; 1089 } 1090 1091 if (parse_write_buffer_into_params(wr_buf, size, 1092 (long *)param, buf, 1093 max_param_num, 1094 ¶m_nums)) { 1095 kfree(wr_buf); 1096 return -EINVAL; 1097 } 1098 1099 if (param_nums <= 0) { 1100 DRM_DEBUG_DRIVER("user data not be read\n"); 1101 kfree(wr_buf); 1102 return -EINVAL; 1103 } 1104 1105 if (param[0] == 1) { 1106 mutex_lock(&aconnector->hpd_lock); 1107 1108 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1109 new_connection_type != dc_connection_none) 1110 goto unlock; 1111 1112 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1113 goto unlock; 1114 1115 amdgpu_dm_update_connector_after_detect(aconnector); 1116 1117 drm_modeset_lock_all(dev); 1118 dm_restore_drm_connector_state(dev, connector); 1119 drm_modeset_unlock_all(dev); 1120 1121 drm_kms_helper_hotplug_event(dev); 1122 } else if (param[0] == 0) { 1123 if (!aconnector->dc_link) 1124 goto unlock; 1125 1126 link = aconnector->dc_link; 1127 1128 if (link->local_sink) { 1129 dc_sink_release(link->local_sink); 1130 link->local_sink = NULL; 1131 } 1132 1133 link->dpcd_sink_count = 0; 1134 link->type = dc_connection_none; 1135 link->dongle_max_pix_clk = 0; 1136 1137 amdgpu_dm_update_connector_after_detect(aconnector); 1138 1139 drm_modeset_lock_all(dev); 1140 dm_restore_drm_connector_state(dev, connector); 1141 drm_modeset_unlock_all(dev); 1142 1143 drm_kms_helper_hotplug_event(dev); 1144 } 1145 1146 unlock: 1147 mutex_unlock(&aconnector->hpd_lock); 1148 1149 kfree(wr_buf); 1150 return size; 1151 } 1152 1153 /* function: read DSC status on the connector 1154 * 1155 * The read function: dp_dsc_clock_en_read 1156 * returns current status of DSC clock on the connector. 1157 * The return is a boolean flag: 1 or 0. 1158 * 1159 * Access it with the following command (you need to specify 1160 * connector like DP-1): 1161 * 1162 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1163 * 1164 * Expected output: 1165 * 1 - means that DSC is currently enabled 1166 * 0 - means that DSC is disabled 1167 */ 1168 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1169 size_t size, loff_t *pos) 1170 { 1171 char *rd_buf = NULL; 1172 char *rd_buf_ptr = NULL; 1173 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1174 struct display_stream_compressor *dsc; 1175 struct dcn_dsc_state dsc_state = {0}; 1176 const uint32_t rd_buf_size = 10; 1177 struct pipe_ctx *pipe_ctx; 1178 ssize_t result = 0; 1179 int i, r, str_len = 30; 1180 1181 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1182 1183 if (!rd_buf) 1184 return -ENOMEM; 1185 1186 rd_buf_ptr = rd_buf; 1187 1188 for (i = 0; i < MAX_PIPES; i++) { 1189 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1190 if (pipe_ctx && pipe_ctx->stream && 1191 pipe_ctx->stream->link == aconnector->dc_link) 1192 break; 1193 } 1194 1195 if (!pipe_ctx) 1196 return -ENXIO; 1197 1198 dsc = pipe_ctx->stream_res.dsc; 1199 if (dsc) 1200 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1201 1202 snprintf(rd_buf_ptr, str_len, 1203 "%d\n", 1204 dsc_state.dsc_clock_en); 1205 rd_buf_ptr += str_len; 1206 1207 while (size) { 1208 if (*pos >= rd_buf_size) 1209 break; 1210 1211 r = put_user(*(rd_buf + result), buf); 1212 if (r) 1213 return r; /* r = -EFAULT */ 1214 1215 buf += 1; 1216 size -= 1; 1217 *pos += 1; 1218 result += 1; 1219 } 1220 1221 kfree(rd_buf); 1222 return result; 1223 } 1224 1225 /* function: write force DSC on the connector 1226 * 1227 * The write function: dp_dsc_clock_en_write 1228 * enables to force DSC on the connector. 1229 * User can write to either force enable or force disable DSC 1230 * on the next modeset or set it to driver default 1231 * 1232 * Accepted inputs: 1233 * 0 - default DSC enablement policy 1234 * 1 - force enable DSC on the connector 1235 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1236 * 1237 * Writing DSC settings is done with the following command: 1238 * - To force enable DSC (you need to specify 1239 * connector like DP-1): 1240 * 1241 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1242 * 1243 * - To return to default state set the flag to zero and 1244 * let driver deal with DSC automatically 1245 * (you need to specify connector like DP-1): 1246 * 1247 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1248 * 1249 */ 1250 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1251 size_t size, loff_t *pos) 1252 { 1253 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1254 struct drm_connector *connector = &aconnector->base; 1255 struct drm_device *dev = connector->dev; 1256 struct drm_crtc *crtc = NULL; 1257 struct dm_crtc_state *dm_crtc_state = NULL; 1258 struct pipe_ctx *pipe_ctx; 1259 int i; 1260 char *wr_buf = NULL; 1261 uint32_t wr_buf_size = 42; 1262 int max_param_num = 1; 1263 long param[1] = {0}; 1264 uint8_t param_nums = 0; 1265 1266 if (size == 0) 1267 return -EINVAL; 1268 1269 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1270 1271 if (!wr_buf) { 1272 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1273 return -ENOSPC; 1274 } 1275 1276 if (parse_write_buffer_into_params(wr_buf, size, 1277 (long *)param, buf, 1278 max_param_num, 1279 ¶m_nums)) { 1280 kfree(wr_buf); 1281 return -EINVAL; 1282 } 1283 1284 if (param_nums <= 0) { 1285 DRM_DEBUG_DRIVER("user data not be read\n"); 1286 kfree(wr_buf); 1287 return -EINVAL; 1288 } 1289 1290 for (i = 0; i < MAX_PIPES; i++) { 1291 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1292 if (pipe_ctx && pipe_ctx->stream && 1293 pipe_ctx->stream->link == aconnector->dc_link) 1294 break; 1295 } 1296 1297 if (!pipe_ctx || !pipe_ctx->stream) 1298 goto done; 1299 1300 // Get CRTC state 1301 mutex_lock(&dev->mode_config.mutex); 1302 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1303 1304 if (connector->state == NULL) 1305 goto unlock; 1306 1307 crtc = connector->state->crtc; 1308 if (crtc == NULL) 1309 goto unlock; 1310 1311 drm_modeset_lock(&crtc->mutex, NULL); 1312 if (crtc->state == NULL) 1313 goto unlock; 1314 1315 dm_crtc_state = to_dm_crtc_state(crtc->state); 1316 if (dm_crtc_state->stream == NULL) 1317 goto unlock; 1318 1319 if (param[0] == 1) 1320 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1321 else if (param[0] == 2) 1322 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1323 else 1324 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1325 1326 dm_crtc_state->dsc_force_changed = true; 1327 1328 unlock: 1329 if (crtc) 1330 drm_modeset_unlock(&crtc->mutex); 1331 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1332 mutex_unlock(&dev->mode_config.mutex); 1333 1334 done: 1335 kfree(wr_buf); 1336 return size; 1337 } 1338 1339 /* function: read DSC slice width parameter on the connector 1340 * 1341 * The read function: dp_dsc_slice_width_read 1342 * returns dsc slice width used in the current configuration 1343 * The return is an integer: 0 or other positive number 1344 * 1345 * Access the status with the following command: 1346 * 1347 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1348 * 1349 * 0 - means that DSC is disabled 1350 * 1351 * Any other number more than zero represents the 1352 * slice width currently used by DSC in pixels 1353 * 1354 */ 1355 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1356 size_t size, loff_t *pos) 1357 { 1358 char *rd_buf = NULL; 1359 char *rd_buf_ptr = NULL; 1360 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1361 struct display_stream_compressor *dsc; 1362 struct dcn_dsc_state dsc_state = {0}; 1363 const uint32_t rd_buf_size = 100; 1364 struct pipe_ctx *pipe_ctx; 1365 ssize_t result = 0; 1366 int i, r, str_len = 30; 1367 1368 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1369 1370 if (!rd_buf) 1371 return -ENOMEM; 1372 1373 rd_buf_ptr = rd_buf; 1374 1375 for (i = 0; i < MAX_PIPES; i++) { 1376 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1377 if (pipe_ctx && pipe_ctx->stream && 1378 pipe_ctx->stream->link == aconnector->dc_link) 1379 break; 1380 } 1381 1382 if (!pipe_ctx) 1383 return -ENXIO; 1384 1385 dsc = pipe_ctx->stream_res.dsc; 1386 if (dsc) 1387 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1388 1389 snprintf(rd_buf_ptr, str_len, 1390 "%d\n", 1391 dsc_state.dsc_slice_width); 1392 rd_buf_ptr += str_len; 1393 1394 while (size) { 1395 if (*pos >= rd_buf_size) 1396 break; 1397 1398 r = put_user(*(rd_buf + result), buf); 1399 if (r) 1400 return r; /* r = -EFAULT */ 1401 1402 buf += 1; 1403 size -= 1; 1404 *pos += 1; 1405 result += 1; 1406 } 1407 1408 kfree(rd_buf); 1409 return result; 1410 } 1411 1412 /* function: write DSC slice width parameter 1413 * 1414 * The write function: dp_dsc_slice_width_write 1415 * overwrites automatically generated DSC configuration 1416 * of slice width. 1417 * 1418 * The user has to write the slice width divisible by the 1419 * picture width. 1420 * 1421 * Also the user has to write width in hexidecimal 1422 * rather than in decimal. 1423 * 1424 * Writing DSC settings is done with the following command: 1425 * - To force overwrite slice width: (example sets to 1920 pixels) 1426 * 1427 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1428 * 1429 * - To stop overwriting and let driver find the optimal size, 1430 * set the width to zero: 1431 * 1432 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1433 * 1434 */ 1435 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1436 size_t size, loff_t *pos) 1437 { 1438 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1439 struct pipe_ctx *pipe_ctx; 1440 struct drm_connector *connector = &aconnector->base; 1441 struct drm_device *dev = connector->dev; 1442 struct drm_crtc *crtc = NULL; 1443 struct dm_crtc_state *dm_crtc_state = NULL; 1444 int i; 1445 char *wr_buf = NULL; 1446 uint32_t wr_buf_size = 42; 1447 int max_param_num = 1; 1448 long param[1] = {0}; 1449 uint8_t param_nums = 0; 1450 1451 if (size == 0) 1452 return -EINVAL; 1453 1454 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1455 1456 if (!wr_buf) { 1457 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1458 return -ENOSPC; 1459 } 1460 1461 if (parse_write_buffer_into_params(wr_buf, size, 1462 (long *)param, buf, 1463 max_param_num, 1464 ¶m_nums)) { 1465 kfree(wr_buf); 1466 return -EINVAL; 1467 } 1468 1469 if (param_nums <= 0) { 1470 DRM_DEBUG_DRIVER("user data not be read\n"); 1471 kfree(wr_buf); 1472 return -EINVAL; 1473 } 1474 1475 for (i = 0; i < MAX_PIPES; i++) { 1476 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1477 if (pipe_ctx && pipe_ctx->stream && 1478 pipe_ctx->stream->link == aconnector->dc_link) 1479 break; 1480 } 1481 1482 if (!pipe_ctx || !pipe_ctx->stream) 1483 goto done; 1484 1485 // Safely get CRTC state 1486 mutex_lock(&dev->mode_config.mutex); 1487 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1488 1489 if (connector->state == NULL) 1490 goto unlock; 1491 1492 crtc = connector->state->crtc; 1493 if (crtc == NULL) 1494 goto unlock; 1495 1496 drm_modeset_lock(&crtc->mutex, NULL); 1497 if (crtc->state == NULL) 1498 goto unlock; 1499 1500 dm_crtc_state = to_dm_crtc_state(crtc->state); 1501 if (dm_crtc_state->stream == NULL) 1502 goto unlock; 1503 1504 if (param[0] > 0) 1505 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1506 pipe_ctx->stream->timing.h_addressable, 1507 param[0]); 1508 else 1509 aconnector->dsc_settings.dsc_num_slices_h = 0; 1510 1511 dm_crtc_state->dsc_force_changed = true; 1512 1513 unlock: 1514 if (crtc) 1515 drm_modeset_unlock(&crtc->mutex); 1516 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1517 mutex_unlock(&dev->mode_config.mutex); 1518 1519 done: 1520 kfree(wr_buf); 1521 return size; 1522 } 1523 1524 /* function: read DSC slice height parameter on the connector 1525 * 1526 * The read function: dp_dsc_slice_height_read 1527 * returns dsc slice height used in the current configuration 1528 * The return is an integer: 0 or other positive number 1529 * 1530 * Access the status with the following command: 1531 * 1532 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1533 * 1534 * 0 - means that DSC is disabled 1535 * 1536 * Any other number more than zero represents the 1537 * slice height currently used by DSC in pixels 1538 * 1539 */ 1540 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1541 size_t size, loff_t *pos) 1542 { 1543 char *rd_buf = NULL; 1544 char *rd_buf_ptr = NULL; 1545 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1546 struct display_stream_compressor *dsc; 1547 struct dcn_dsc_state dsc_state = {0}; 1548 const uint32_t rd_buf_size = 100; 1549 struct pipe_ctx *pipe_ctx; 1550 ssize_t result = 0; 1551 int i, r, str_len = 30; 1552 1553 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1554 1555 if (!rd_buf) 1556 return -ENOMEM; 1557 1558 rd_buf_ptr = rd_buf; 1559 1560 for (i = 0; i < MAX_PIPES; i++) { 1561 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1562 if (pipe_ctx && pipe_ctx->stream && 1563 pipe_ctx->stream->link == aconnector->dc_link) 1564 break; 1565 } 1566 1567 if (!pipe_ctx) 1568 return -ENXIO; 1569 1570 dsc = pipe_ctx->stream_res.dsc; 1571 if (dsc) 1572 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1573 1574 snprintf(rd_buf_ptr, str_len, 1575 "%d\n", 1576 dsc_state.dsc_slice_height); 1577 rd_buf_ptr += str_len; 1578 1579 while (size) { 1580 if (*pos >= rd_buf_size) 1581 break; 1582 1583 r = put_user(*(rd_buf + result), buf); 1584 if (r) 1585 return r; /* r = -EFAULT */ 1586 1587 buf += 1; 1588 size -= 1; 1589 *pos += 1; 1590 result += 1; 1591 } 1592 1593 kfree(rd_buf); 1594 return result; 1595 } 1596 1597 /* function: write DSC slice height parameter 1598 * 1599 * The write function: dp_dsc_slice_height_write 1600 * overwrites automatically generated DSC configuration 1601 * of slice height. 1602 * 1603 * The user has to write the slice height divisible by the 1604 * picture height. 1605 * 1606 * Also the user has to write height in hexidecimal 1607 * rather than in decimal. 1608 * 1609 * Writing DSC settings is done with the following command: 1610 * - To force overwrite slice height (example sets to 128 pixels): 1611 * 1612 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1613 * 1614 * - To stop overwriting and let driver find the optimal size, 1615 * set the height to zero: 1616 * 1617 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1618 * 1619 */ 1620 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1621 size_t size, loff_t *pos) 1622 { 1623 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1624 struct drm_connector *connector = &aconnector->base; 1625 struct drm_device *dev = connector->dev; 1626 struct drm_crtc *crtc = NULL; 1627 struct dm_crtc_state *dm_crtc_state = NULL; 1628 struct pipe_ctx *pipe_ctx; 1629 int i; 1630 char *wr_buf = NULL; 1631 uint32_t wr_buf_size = 42; 1632 int max_param_num = 1; 1633 uint8_t param_nums = 0; 1634 long param[1] = {0}; 1635 1636 if (size == 0) 1637 return -EINVAL; 1638 1639 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1640 1641 if (!wr_buf) { 1642 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1643 return -ENOSPC; 1644 } 1645 1646 if (parse_write_buffer_into_params(wr_buf, size, 1647 (long *)param, buf, 1648 max_param_num, 1649 ¶m_nums)) { 1650 kfree(wr_buf); 1651 return -EINVAL; 1652 } 1653 1654 if (param_nums <= 0) { 1655 DRM_DEBUG_DRIVER("user data not be read\n"); 1656 kfree(wr_buf); 1657 return -EINVAL; 1658 } 1659 1660 for (i = 0; i < MAX_PIPES; i++) { 1661 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1662 if (pipe_ctx && pipe_ctx->stream && 1663 pipe_ctx->stream->link == aconnector->dc_link) 1664 break; 1665 } 1666 1667 if (!pipe_ctx || !pipe_ctx->stream) 1668 goto done; 1669 1670 // Get CRTC state 1671 mutex_lock(&dev->mode_config.mutex); 1672 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1673 1674 if (connector->state == NULL) 1675 goto unlock; 1676 1677 crtc = connector->state->crtc; 1678 if (crtc == NULL) 1679 goto unlock; 1680 1681 drm_modeset_lock(&crtc->mutex, NULL); 1682 if (crtc->state == NULL) 1683 goto unlock; 1684 1685 dm_crtc_state = to_dm_crtc_state(crtc->state); 1686 if (dm_crtc_state->stream == NULL) 1687 goto unlock; 1688 1689 if (param[0] > 0) 1690 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1691 pipe_ctx->stream->timing.v_addressable, 1692 param[0]); 1693 else 1694 aconnector->dsc_settings.dsc_num_slices_v = 0; 1695 1696 dm_crtc_state->dsc_force_changed = true; 1697 1698 unlock: 1699 if (crtc) 1700 drm_modeset_unlock(&crtc->mutex); 1701 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1702 mutex_unlock(&dev->mode_config.mutex); 1703 1704 done: 1705 kfree(wr_buf); 1706 return size; 1707 } 1708 1709 /* function: read DSC target rate on the connector in bits per pixel 1710 * 1711 * The read function: dp_dsc_bits_per_pixel_read 1712 * returns target rate of compression in bits per pixel 1713 * The return is an integer: 0 or other positive integer 1714 * 1715 * Access it with the following command: 1716 * 1717 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1718 * 1719 * 0 - means that DSC is disabled 1720 */ 1721 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1722 size_t size, loff_t *pos) 1723 { 1724 char *rd_buf = NULL; 1725 char *rd_buf_ptr = NULL; 1726 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1727 struct display_stream_compressor *dsc; 1728 struct dcn_dsc_state dsc_state = {0}; 1729 const uint32_t rd_buf_size = 100; 1730 struct pipe_ctx *pipe_ctx; 1731 ssize_t result = 0; 1732 int i, r, str_len = 30; 1733 1734 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1735 1736 if (!rd_buf) 1737 return -ENOMEM; 1738 1739 rd_buf_ptr = rd_buf; 1740 1741 for (i = 0; i < MAX_PIPES; i++) { 1742 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1743 if (pipe_ctx && pipe_ctx->stream && 1744 pipe_ctx->stream->link == aconnector->dc_link) 1745 break; 1746 } 1747 1748 if (!pipe_ctx) 1749 return -ENXIO; 1750 1751 dsc = pipe_ctx->stream_res.dsc; 1752 if (dsc) 1753 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1754 1755 snprintf(rd_buf_ptr, str_len, 1756 "%d\n", 1757 dsc_state.dsc_bits_per_pixel); 1758 rd_buf_ptr += str_len; 1759 1760 while (size) { 1761 if (*pos >= rd_buf_size) 1762 break; 1763 1764 r = put_user(*(rd_buf + result), buf); 1765 if (r) 1766 return r; /* r = -EFAULT */ 1767 1768 buf += 1; 1769 size -= 1; 1770 *pos += 1; 1771 result += 1; 1772 } 1773 1774 kfree(rd_buf); 1775 return result; 1776 } 1777 1778 /* function: write DSC target rate in bits per pixel 1779 * 1780 * The write function: dp_dsc_bits_per_pixel_write 1781 * overwrites automatically generated DSC configuration 1782 * of DSC target bit rate. 1783 * 1784 * Also the user has to write bpp in hexidecimal 1785 * rather than in decimal. 1786 * 1787 * Writing DSC settings is done with the following command: 1788 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1789 * 1790 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1791 * 1792 * - To stop overwriting and let driver find the optimal rate, 1793 * set the rate to zero: 1794 * 1795 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1796 * 1797 */ 1798 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1799 size_t size, loff_t *pos) 1800 { 1801 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1802 struct drm_connector *connector = &aconnector->base; 1803 struct drm_device *dev = connector->dev; 1804 struct drm_crtc *crtc = NULL; 1805 struct dm_crtc_state *dm_crtc_state = NULL; 1806 struct pipe_ctx *pipe_ctx; 1807 int i; 1808 char *wr_buf = NULL; 1809 uint32_t wr_buf_size = 42; 1810 int max_param_num = 1; 1811 uint8_t param_nums = 0; 1812 long param[1] = {0}; 1813 1814 if (size == 0) 1815 return -EINVAL; 1816 1817 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1818 1819 if (!wr_buf) { 1820 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1821 return -ENOSPC; 1822 } 1823 1824 if (parse_write_buffer_into_params(wr_buf, size, 1825 (long *)param, buf, 1826 max_param_num, 1827 ¶m_nums)) { 1828 kfree(wr_buf); 1829 return -EINVAL; 1830 } 1831 1832 if (param_nums <= 0) { 1833 DRM_DEBUG_DRIVER("user data not be read\n"); 1834 kfree(wr_buf); 1835 return -EINVAL; 1836 } 1837 1838 for (i = 0; i < MAX_PIPES; i++) { 1839 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1840 if (pipe_ctx && pipe_ctx->stream && 1841 pipe_ctx->stream->link == aconnector->dc_link) 1842 break; 1843 } 1844 1845 if (!pipe_ctx || !pipe_ctx->stream) 1846 goto done; 1847 1848 // Get CRTC state 1849 mutex_lock(&dev->mode_config.mutex); 1850 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1851 1852 if (connector->state == NULL) 1853 goto unlock; 1854 1855 crtc = connector->state->crtc; 1856 if (crtc == NULL) 1857 goto unlock; 1858 1859 drm_modeset_lock(&crtc->mutex, NULL); 1860 if (crtc->state == NULL) 1861 goto unlock; 1862 1863 dm_crtc_state = to_dm_crtc_state(crtc->state); 1864 if (dm_crtc_state->stream == NULL) 1865 goto unlock; 1866 1867 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 1868 1869 dm_crtc_state->dsc_force_changed = true; 1870 1871 unlock: 1872 if (crtc) 1873 drm_modeset_unlock(&crtc->mutex); 1874 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1875 mutex_unlock(&dev->mode_config.mutex); 1876 1877 done: 1878 kfree(wr_buf); 1879 return size; 1880 } 1881 1882 /* function: read DSC picture width parameter on the connector 1883 * 1884 * The read function: dp_dsc_pic_width_read 1885 * returns dsc picture width used in the current configuration 1886 * It is the same as h_addressable of the current 1887 * display's timing 1888 * The return is an integer: 0 or other positive integer 1889 * If 0 then DSC is disabled. 1890 * 1891 * Access it with the following command: 1892 * 1893 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 1894 * 1895 * 0 - means that DSC is disabled 1896 */ 1897 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 1898 size_t size, loff_t *pos) 1899 { 1900 char *rd_buf = NULL; 1901 char *rd_buf_ptr = NULL; 1902 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1903 struct display_stream_compressor *dsc; 1904 struct dcn_dsc_state dsc_state = {0}; 1905 const uint32_t rd_buf_size = 100; 1906 struct pipe_ctx *pipe_ctx; 1907 ssize_t result = 0; 1908 int i, r, str_len = 30; 1909 1910 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1911 1912 if (!rd_buf) 1913 return -ENOMEM; 1914 1915 rd_buf_ptr = rd_buf; 1916 1917 for (i = 0; i < MAX_PIPES; i++) { 1918 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1919 if (pipe_ctx && pipe_ctx->stream && 1920 pipe_ctx->stream->link == aconnector->dc_link) 1921 break; 1922 } 1923 1924 if (!pipe_ctx) 1925 return -ENXIO; 1926 1927 dsc = pipe_ctx->stream_res.dsc; 1928 if (dsc) 1929 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1930 1931 snprintf(rd_buf_ptr, str_len, 1932 "%d\n", 1933 dsc_state.dsc_pic_width); 1934 rd_buf_ptr += str_len; 1935 1936 while (size) { 1937 if (*pos >= rd_buf_size) 1938 break; 1939 1940 r = put_user(*(rd_buf + result), buf); 1941 if (r) 1942 return r; /* r = -EFAULT */ 1943 1944 buf += 1; 1945 size -= 1; 1946 *pos += 1; 1947 result += 1; 1948 } 1949 1950 kfree(rd_buf); 1951 return result; 1952 } 1953 1954 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 1955 size_t size, loff_t *pos) 1956 { 1957 char *rd_buf = NULL; 1958 char *rd_buf_ptr = NULL; 1959 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1960 struct display_stream_compressor *dsc; 1961 struct dcn_dsc_state dsc_state = {0}; 1962 const uint32_t rd_buf_size = 100; 1963 struct pipe_ctx *pipe_ctx; 1964 ssize_t result = 0; 1965 int i, r, str_len = 30; 1966 1967 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1968 1969 if (!rd_buf) 1970 return -ENOMEM; 1971 1972 rd_buf_ptr = rd_buf; 1973 1974 for (i = 0; i < MAX_PIPES; i++) { 1975 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1976 if (pipe_ctx && pipe_ctx->stream && 1977 pipe_ctx->stream->link == aconnector->dc_link) 1978 break; 1979 } 1980 1981 if (!pipe_ctx) 1982 return -ENXIO; 1983 1984 dsc = pipe_ctx->stream_res.dsc; 1985 if (dsc) 1986 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1987 1988 snprintf(rd_buf_ptr, str_len, 1989 "%d\n", 1990 dsc_state.dsc_pic_height); 1991 rd_buf_ptr += str_len; 1992 1993 while (size) { 1994 if (*pos >= rd_buf_size) 1995 break; 1996 1997 r = put_user(*(rd_buf + result), buf); 1998 if (r) 1999 return r; /* r = -EFAULT */ 2000 2001 buf += 1; 2002 size -= 1; 2003 *pos += 1; 2004 result += 1; 2005 } 2006 2007 kfree(rd_buf); 2008 return result; 2009 } 2010 2011 /* function: read DSC chunk size parameter on the connector 2012 * 2013 * The read function: dp_dsc_chunk_size_read 2014 * returns dsc chunk size set in the current configuration 2015 * The value is calculated automatically by DSC code 2016 * and depends on slice parameters and bpp target rate 2017 * The return is an integer: 0 or other positive integer 2018 * If 0 then DSC is disabled. 2019 * 2020 * Access it with the following command: 2021 * 2022 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2023 * 2024 * 0 - means that DSC is disabled 2025 */ 2026 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2027 size_t size, loff_t *pos) 2028 { 2029 char *rd_buf = NULL; 2030 char *rd_buf_ptr = NULL; 2031 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2032 struct display_stream_compressor *dsc; 2033 struct dcn_dsc_state dsc_state = {0}; 2034 const uint32_t rd_buf_size = 100; 2035 struct pipe_ctx *pipe_ctx; 2036 ssize_t result = 0; 2037 int i, r, str_len = 30; 2038 2039 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2040 2041 if (!rd_buf) 2042 return -ENOMEM; 2043 2044 rd_buf_ptr = rd_buf; 2045 2046 for (i = 0; i < MAX_PIPES; i++) { 2047 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2048 if (pipe_ctx && pipe_ctx->stream && 2049 pipe_ctx->stream->link == aconnector->dc_link) 2050 break; 2051 } 2052 2053 if (!pipe_ctx) 2054 return -ENXIO; 2055 2056 dsc = pipe_ctx->stream_res.dsc; 2057 if (dsc) 2058 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2059 2060 snprintf(rd_buf_ptr, str_len, 2061 "%d\n", 2062 dsc_state.dsc_chunk_size); 2063 rd_buf_ptr += str_len; 2064 2065 while (size) { 2066 if (*pos >= rd_buf_size) 2067 break; 2068 2069 r = put_user(*(rd_buf + result), buf); 2070 if (r) 2071 return r; /* r = -EFAULT */ 2072 2073 buf += 1; 2074 size -= 1; 2075 *pos += 1; 2076 result += 1; 2077 } 2078 2079 kfree(rd_buf); 2080 return result; 2081 } 2082 2083 /* function: read DSC slice bpg offset on the connector 2084 * 2085 * The read function: dp_dsc_slice_bpg_offset_read 2086 * returns dsc bpg slice offset set in the current configuration 2087 * The value is calculated automatically by DSC code 2088 * and depends on slice parameters and bpp target rate 2089 * The return is an integer: 0 or other positive integer 2090 * If 0 then DSC is disabled. 2091 * 2092 * Access it with the following command: 2093 * 2094 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2095 * 2096 * 0 - means that DSC is disabled 2097 */ 2098 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2099 size_t size, loff_t *pos) 2100 { 2101 char *rd_buf = NULL; 2102 char *rd_buf_ptr = NULL; 2103 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2104 struct display_stream_compressor *dsc; 2105 struct dcn_dsc_state dsc_state = {0}; 2106 const uint32_t rd_buf_size = 100; 2107 struct pipe_ctx *pipe_ctx; 2108 ssize_t result = 0; 2109 int i, r, str_len = 30; 2110 2111 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2112 2113 if (!rd_buf) 2114 return -ENOMEM; 2115 2116 rd_buf_ptr = rd_buf; 2117 2118 for (i = 0; i < MAX_PIPES; i++) { 2119 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2120 if (pipe_ctx && pipe_ctx->stream && 2121 pipe_ctx->stream->link == aconnector->dc_link) 2122 break; 2123 } 2124 2125 if (!pipe_ctx) 2126 return -ENXIO; 2127 2128 dsc = pipe_ctx->stream_res.dsc; 2129 if (dsc) 2130 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2131 2132 snprintf(rd_buf_ptr, str_len, 2133 "%d\n", 2134 dsc_state.dsc_slice_bpg_offset); 2135 rd_buf_ptr += str_len; 2136 2137 while (size) { 2138 if (*pos >= rd_buf_size) 2139 break; 2140 2141 r = put_user(*(rd_buf + result), buf); 2142 if (r) 2143 return r; /* r = -EFAULT */ 2144 2145 buf += 1; 2146 size -= 1; 2147 *pos += 1; 2148 result += 1; 2149 } 2150 2151 kfree(rd_buf); 2152 return result; 2153 } 2154 2155 2156 /* 2157 * function description: Read max_requested_bpc property from the connector 2158 * 2159 * Access it with the following command: 2160 * 2161 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2162 * 2163 */ 2164 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2165 size_t size, loff_t *pos) 2166 { 2167 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2168 struct drm_connector *connector = &aconnector->base; 2169 struct drm_device *dev = connector->dev; 2170 struct dm_connector_state *state; 2171 ssize_t result = 0; 2172 char *rd_buf = NULL; 2173 char *rd_buf_ptr = NULL; 2174 const uint32_t rd_buf_size = 10; 2175 int r; 2176 2177 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2178 2179 if (!rd_buf) 2180 return -ENOMEM; 2181 2182 mutex_lock(&dev->mode_config.mutex); 2183 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2184 2185 if (connector->state == NULL) 2186 goto unlock; 2187 2188 state = to_dm_connector_state(connector->state); 2189 2190 rd_buf_ptr = rd_buf; 2191 snprintf(rd_buf_ptr, rd_buf_size, 2192 "%u\n", 2193 state->base.max_requested_bpc); 2194 2195 while (size) { 2196 if (*pos >= rd_buf_size) 2197 break; 2198 2199 r = put_user(*(rd_buf + result), buf); 2200 if (r) { 2201 result = r; /* r = -EFAULT */ 2202 goto unlock; 2203 } 2204 buf += 1; 2205 size -= 1; 2206 *pos += 1; 2207 result += 1; 2208 } 2209 unlock: 2210 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2211 mutex_unlock(&dev->mode_config.mutex); 2212 kfree(rd_buf); 2213 return result; 2214 } 2215 2216 2217 /* 2218 * function description: Set max_requested_bpc property on the connector 2219 * 2220 * This function will not force the input BPC on connector, it will only 2221 * change the max value. This is equivalent to setting max_bpc through 2222 * xrandr. 2223 * 2224 * The BPC value written must be >= 6 and <= 16. Values outside of this 2225 * range will result in errors. 2226 * 2227 * BPC values: 2228 * 0x6 - 6 BPC 2229 * 0x8 - 8 BPC 2230 * 0xa - 10 BPC 2231 * 0xc - 12 BPC 2232 * 0x10 - 16 BPC 2233 * 2234 * Write the max_bpc in the following way: 2235 * 2236 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2237 * 2238 */ 2239 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2240 size_t size, loff_t *pos) 2241 { 2242 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2243 struct drm_connector *connector = &aconnector->base; 2244 struct dm_connector_state *state; 2245 struct drm_device *dev = connector->dev; 2246 char *wr_buf = NULL; 2247 uint32_t wr_buf_size = 42; 2248 int max_param_num = 1; 2249 long param[1] = {0}; 2250 uint8_t param_nums = 0; 2251 2252 if (size == 0) 2253 return -EINVAL; 2254 2255 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2256 2257 if (!wr_buf) { 2258 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2259 return -ENOSPC; 2260 } 2261 2262 if (parse_write_buffer_into_params(wr_buf, size, 2263 (long *)param, buf, 2264 max_param_num, 2265 ¶m_nums)) { 2266 kfree(wr_buf); 2267 return -EINVAL; 2268 } 2269 2270 if (param_nums <= 0) { 2271 DRM_DEBUG_DRIVER("user data not be read\n"); 2272 kfree(wr_buf); 2273 return -EINVAL; 2274 } 2275 2276 if (param[0] < 6 || param[0] > 16) { 2277 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2278 kfree(wr_buf); 2279 return -EINVAL; 2280 } 2281 2282 mutex_lock(&dev->mode_config.mutex); 2283 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2284 2285 if (connector->state == NULL) 2286 goto unlock; 2287 2288 state = to_dm_connector_state(connector->state); 2289 state->base.max_requested_bpc = param[0]; 2290 unlock: 2291 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2292 mutex_unlock(&dev->mode_config.mutex); 2293 2294 kfree(wr_buf); 2295 return size; 2296 } 2297 2298 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2299 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2300 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2301 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2302 #ifdef CONFIG_DRM_AMD_DC_HDCP 2303 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2304 #endif 2305 2306 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2307 .owner = THIS_MODULE, 2308 .read = dp_dsc_clock_en_read, 2309 .write = dp_dsc_clock_en_write, 2310 .llseek = default_llseek 2311 }; 2312 2313 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2314 .owner = THIS_MODULE, 2315 .read = dp_dsc_slice_width_read, 2316 .write = dp_dsc_slice_width_write, 2317 .llseek = default_llseek 2318 }; 2319 2320 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2321 .owner = THIS_MODULE, 2322 .read = dp_dsc_slice_height_read, 2323 .write = dp_dsc_slice_height_write, 2324 .llseek = default_llseek 2325 }; 2326 2327 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2328 .owner = THIS_MODULE, 2329 .read = dp_dsc_bits_per_pixel_read, 2330 .write = dp_dsc_bits_per_pixel_write, 2331 .llseek = default_llseek 2332 }; 2333 2334 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2335 .owner = THIS_MODULE, 2336 .read = dp_dsc_pic_width_read, 2337 .llseek = default_llseek 2338 }; 2339 2340 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2341 .owner = THIS_MODULE, 2342 .read = dp_dsc_pic_height_read, 2343 .llseek = default_llseek 2344 }; 2345 2346 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2347 .owner = THIS_MODULE, 2348 .read = dp_dsc_chunk_size_read, 2349 .llseek = default_llseek 2350 }; 2351 2352 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2353 .owner = THIS_MODULE, 2354 .read = dp_dsc_slice_bpg_offset_read, 2355 .llseek = default_llseek 2356 }; 2357 2358 static const struct file_operations trigger_hotplug_debugfs_fops = { 2359 .owner = THIS_MODULE, 2360 .write = trigger_hotplug, 2361 .llseek = default_llseek 2362 }; 2363 2364 static const struct file_operations dp_link_settings_debugfs_fops = { 2365 .owner = THIS_MODULE, 2366 .read = dp_link_settings_read, 2367 .write = dp_link_settings_write, 2368 .llseek = default_llseek 2369 }; 2370 2371 static const struct file_operations dp_phy_settings_debugfs_fop = { 2372 .owner = THIS_MODULE, 2373 .read = dp_phy_settings_read, 2374 .write = dp_phy_settings_write, 2375 .llseek = default_llseek 2376 }; 2377 2378 static const struct file_operations dp_phy_test_pattern_fops = { 2379 .owner = THIS_MODULE, 2380 .write = dp_phy_test_pattern_debugfs_write, 2381 .llseek = default_llseek 2382 }; 2383 2384 static const struct file_operations sdp_message_fops = { 2385 .owner = THIS_MODULE, 2386 .write = dp_sdp_message_debugfs_write, 2387 .llseek = default_llseek 2388 }; 2389 2390 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2391 .owner = THIS_MODULE, 2392 .write = dp_dpcd_address_write, 2393 .llseek = default_llseek 2394 }; 2395 2396 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2397 .owner = THIS_MODULE, 2398 .write = dp_dpcd_size_write, 2399 .llseek = default_llseek 2400 }; 2401 2402 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2403 .owner = THIS_MODULE, 2404 .read = dp_dpcd_data_read, 2405 .write = dp_dpcd_data_write, 2406 .llseek = default_llseek 2407 }; 2408 2409 static const struct file_operations dp_max_bpc_debugfs_fops = { 2410 .owner = THIS_MODULE, 2411 .read = dp_max_bpc_read, 2412 .write = dp_max_bpc_write, 2413 .llseek = default_llseek 2414 }; 2415 2416 static const struct { 2417 char *name; 2418 const struct file_operations *fops; 2419 } dp_debugfs_entries[] = { 2420 {"link_settings", &dp_link_settings_debugfs_fops}, 2421 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2422 {"test_pattern", &dp_phy_test_pattern_fops}, 2423 #ifdef CONFIG_DRM_AMD_DC_HDCP 2424 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2425 #endif 2426 {"sdp_message", &sdp_message_fops}, 2427 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2428 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2429 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2430 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2431 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2432 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2433 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2434 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2435 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2436 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2437 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2438 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2439 {"max_bpc", &dp_max_bpc_debugfs_fops} 2440 }; 2441 2442 #ifdef CONFIG_DRM_AMD_DC_HDCP 2443 static const struct { 2444 char *name; 2445 const struct file_operations *fops; 2446 } hdmi_debugfs_entries[] = { 2447 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2448 }; 2449 #endif 2450 /* 2451 * Force YUV420 output if available from the given mode 2452 */ 2453 static int force_yuv420_output_set(void *data, u64 val) 2454 { 2455 struct amdgpu_dm_connector *connector = data; 2456 2457 connector->force_yuv420_output = (bool)val; 2458 2459 return 0; 2460 } 2461 2462 /* 2463 * Check if YUV420 is forced when available from the given mode 2464 */ 2465 static int force_yuv420_output_get(void *data, u64 *val) 2466 { 2467 struct amdgpu_dm_connector *connector = data; 2468 2469 *val = connector->force_yuv420_output; 2470 2471 return 0; 2472 } 2473 2474 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2475 force_yuv420_output_set, "%llu\n"); 2476 2477 /* 2478 * Read PSR state 2479 */ 2480 static int psr_get(void *data, u64 *val) 2481 { 2482 struct amdgpu_dm_connector *connector = data; 2483 struct dc_link *link = connector->dc_link; 2484 enum dc_psr_state state = PSR_STATE0; 2485 2486 dc_link_get_psr_state(link, &state); 2487 2488 *val = state; 2489 2490 return 0; 2491 } 2492 2493 2494 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2495 2496 static const struct { 2497 char *name; 2498 const struct file_operations *fops; 2499 } connector_debugfs_entries[] = { 2500 {"force_yuv420_output", &force_yuv420_output_fops}, 2501 {"output_bpc", &output_bpc_fops}, 2502 {"trigger_hotplug", &trigger_hotplug_debugfs_fops} 2503 }; 2504 2505 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2506 { 2507 int i; 2508 struct dentry *dir = connector->base.debugfs_entry; 2509 2510 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2511 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2512 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2513 debugfs_create_file(dp_debugfs_entries[i].name, 2514 0644, dir, connector, 2515 dp_debugfs_entries[i].fops); 2516 } 2517 } 2518 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 2519 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2520 2521 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2522 debugfs_create_file(connector_debugfs_entries[i].name, 2523 0644, dir, connector, 2524 connector_debugfs_entries[i].fops); 2525 } 2526 2527 connector->debugfs_dpcd_address = 0; 2528 connector->debugfs_dpcd_size = 0; 2529 2530 #ifdef CONFIG_DRM_AMD_DC_HDCP 2531 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2532 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2533 debugfs_create_file(hdmi_debugfs_entries[i].name, 2534 0644, dir, connector, 2535 hdmi_debugfs_entries[i].fops); 2536 } 2537 } 2538 #endif 2539 } 2540 2541 /* 2542 * Writes DTN log state to the user supplied buffer. 2543 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2544 */ 2545 static ssize_t dtn_log_read( 2546 struct file *f, 2547 char __user *buf, 2548 size_t size, 2549 loff_t *pos) 2550 { 2551 struct amdgpu_device *adev = file_inode(f)->i_private; 2552 struct dc *dc = adev->dm.dc; 2553 struct dc_log_buffer_ctx log_ctx = { 0 }; 2554 ssize_t result = 0; 2555 2556 if (!buf || !size) 2557 return -EINVAL; 2558 2559 if (!dc->hwss.log_hw_state) 2560 return 0; 2561 2562 dc->hwss.log_hw_state(dc, &log_ctx); 2563 2564 if (*pos < log_ctx.pos) { 2565 size_t to_copy = log_ctx.pos - *pos; 2566 2567 to_copy = min(to_copy, size); 2568 2569 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 2570 *pos += to_copy; 2571 result = to_copy; 2572 } 2573 } 2574 2575 kfree(log_ctx.buf); 2576 2577 return result; 2578 } 2579 2580 /* 2581 * Writes DTN log state to dmesg when triggered via a write. 2582 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2583 */ 2584 static ssize_t dtn_log_write( 2585 struct file *f, 2586 const char __user *buf, 2587 size_t size, 2588 loff_t *pos) 2589 { 2590 struct amdgpu_device *adev = file_inode(f)->i_private; 2591 struct dc *dc = adev->dm.dc; 2592 2593 /* Write triggers log output via dmesg. */ 2594 if (size == 0) 2595 return 0; 2596 2597 if (dc->hwss.log_hw_state) 2598 dc->hwss.log_hw_state(dc, NULL); 2599 2600 return size; 2601 } 2602 2603 /* 2604 * Backlight at this moment. Read only. 2605 * As written to display, taking ABM and backlight lut into account. 2606 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2607 */ 2608 static int current_backlight_show(struct seq_file *m, void *unused) 2609 { 2610 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2611 struct amdgpu_display_manager *dm = &adev->dm; 2612 2613 unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link); 2614 2615 seq_printf(m, "0x%x\n", backlight); 2616 return 0; 2617 } 2618 2619 /* 2620 * Backlight value that is being approached. Read only. 2621 * As written to display, taking ABM and backlight lut into account. 2622 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2623 */ 2624 static int target_backlight_show(struct seq_file *m, void *unused) 2625 { 2626 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2627 struct amdgpu_display_manager *dm = &adev->dm; 2628 2629 unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link); 2630 2631 seq_printf(m, "0x%x\n", backlight); 2632 return 0; 2633 } 2634 2635 static int mst_topo_show(struct seq_file *m, void *unused) 2636 { 2637 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2638 struct drm_device *dev = adev_to_drm(adev); 2639 struct drm_connector *connector; 2640 struct drm_connector_list_iter conn_iter; 2641 struct amdgpu_dm_connector *aconnector; 2642 2643 drm_connector_list_iter_begin(dev, &conn_iter); 2644 drm_for_each_connector_iter(connector, &conn_iter) { 2645 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 2646 continue; 2647 2648 aconnector = to_amdgpu_dm_connector(connector); 2649 2650 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 2651 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 2652 } 2653 drm_connector_list_iter_end(&conn_iter); 2654 2655 return 0; 2656 } 2657 2658 /* 2659 * Sets the force_timing_sync debug optino from the given string. 2660 * All connected displays will be force synchronized immediately. 2661 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 2662 */ 2663 static int force_timing_sync_set(void *data, u64 val) 2664 { 2665 struct amdgpu_device *adev = data; 2666 2667 adev->dm.force_timing_sync = (bool)val; 2668 2669 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 2670 2671 return 0; 2672 } 2673 2674 /* 2675 * Gets the force_timing_sync debug option value into the given buffer. 2676 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 2677 */ 2678 static int force_timing_sync_get(void *data, u64 *val) 2679 { 2680 struct amdgpu_device *adev = data; 2681 2682 *val = adev->dm.force_timing_sync; 2683 2684 return 0; 2685 } 2686 2687 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 2688 force_timing_sync_set, "%llu\n"); 2689 2690 /* 2691 * Sets the DC visual confirm debug option from the given string. 2692 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 2693 */ 2694 static int visual_confirm_set(void *data, u64 val) 2695 { 2696 struct amdgpu_device *adev = data; 2697 2698 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 2699 2700 return 0; 2701 } 2702 2703 /* 2704 * Reads the DC visual confirm debug option value into the given buffer. 2705 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 2706 */ 2707 static int visual_confirm_get(void *data, u64 *val) 2708 { 2709 struct amdgpu_device *adev = data; 2710 2711 *val = adev->dm.dc->debug.visual_confirm; 2712 2713 return 0; 2714 } 2715 2716 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2717 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2718 DEFINE_SHOW_ATTRIBUTE(mst_topo); 2719 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 2720 visual_confirm_set, "%llu\n"); 2721 2722 void dtn_debugfs_init(struct amdgpu_device *adev) 2723 { 2724 static const struct file_operations dtn_log_fops = { 2725 .owner = THIS_MODULE, 2726 .read = dtn_log_read, 2727 .write = dtn_log_write, 2728 .llseek = default_llseek 2729 }; 2730 2731 struct drm_minor *minor = adev_to_drm(adev)->primary; 2732 struct dentry *root = minor->debugfs_root; 2733 2734 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, 2735 root, adev, ¤t_backlight_fops); 2736 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, 2737 root, adev, &target_backlight_fops); 2738 debugfs_create_file("amdgpu_mst_topology", 0444, root, 2739 adev, &mst_topo_fops); 2740 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 2741 &dtn_log_fops); 2742 2743 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 2744 &visual_confirm_fops); 2745 2746 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 2747 adev, &dmub_tracebuffer_fops); 2748 2749 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 2750 adev, &dmub_fw_state_fops); 2751 2752 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 2753 adev, &force_timing_sync_ops); 2754 } 2755