1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/uaccess.h> 27 28 #include "dc.h" 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "amdgpu_dm_debugfs.h" 32 #include "dm_helpers.h" 33 #include "dmub/dmub_srv.h" 34 #include "resource.h" 35 #include "dsc.h" 36 #include "dc_link_dp.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 40 struct dmub_debugfs_trace_header { 41 uint32_t entry_count; 42 uint32_t reserved[3]; 43 }; 44 45 struct dmub_debugfs_trace_entry { 46 uint32_t trace_code; 47 uint32_t tick_count; 48 uint32_t param0; 49 uint32_t param1; 50 }; 51 52 static inline const char *yesno(bool v) 53 { 54 return v ? "yes" : "no"; 55 } 56 57 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 58 * 59 * Function takes in attributes passed to debugfs write entry 60 * and writes into param array. 61 * The user passes max_param_num to identify maximum number of 62 * parameters that could be parsed. 63 * 64 */ 65 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 66 long *param, const char __user *buf, 67 int max_param_num, 68 uint8_t *param_nums) 69 { 70 char *wr_buf_ptr = NULL; 71 uint32_t wr_buf_count = 0; 72 int r; 73 char *sub_str = NULL; 74 const char delimiter[3] = {' ', '\n', '\0'}; 75 uint8_t param_index = 0; 76 77 *param_nums = 0; 78 79 wr_buf_ptr = wr_buf; 80 81 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 82 83 /* r is bytes not be copied */ 84 if (r >= wr_buf_size) { 85 DRM_DEBUG_DRIVER("user data not be read\n"); 86 return -EINVAL; 87 } 88 89 /* check number of parameters. isspace could not differ space and \n */ 90 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 91 /* skip space*/ 92 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 93 wr_buf_ptr++; 94 wr_buf_count++; 95 } 96 97 if (wr_buf_count == wr_buf_size) 98 break; 99 100 /* skip non-space*/ 101 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 102 wr_buf_ptr++; 103 wr_buf_count++; 104 } 105 106 (*param_nums)++; 107 108 if (wr_buf_count == wr_buf_size) 109 break; 110 } 111 112 if (*param_nums > max_param_num) 113 *param_nums = max_param_num; 114 115 wr_buf_ptr = wr_buf; /* reset buf pointer */ 116 wr_buf_count = 0; /* number of char already checked */ 117 118 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 119 wr_buf_ptr++; 120 wr_buf_count++; 121 } 122 123 while (param_index < *param_nums) { 124 /* after strsep, wr_buf_ptr will be moved to after space */ 125 sub_str = strsep(&wr_buf_ptr, delimiter); 126 127 r = kstrtol(sub_str, 16, &(param[param_index])); 128 129 if (r) 130 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 131 132 param_index++; 133 } 134 135 return 0; 136 } 137 138 /* function description 139 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 140 * 141 * valid lane count value: 1, 2, 4 142 * valid link rate value: 143 * 06h = 1.62Gbps per lane 144 * 0Ah = 2.7Gbps per lane 145 * 0Ch = 3.24Gbps per lane 146 * 14h = 5.4Gbps per lane 147 * 1Eh = 8.1Gbps per lane 148 * 149 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 150 * 151 * --- to get dp configuration 152 * 153 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 154 * 155 * It will list current, verified, reported, preferred dp configuration. 156 * current -- for current video mode 157 * verified --- maximum configuration which pass link training 158 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 159 * preferred --- user force settings 160 * 161 * --- set (or force) dp configuration 162 * 163 * echo <lane_count> <link_rate> > link_settings 164 * 165 * for example, to force to 2 lane, 2.7GHz, 166 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 167 * 168 * spread_spectrum could not be changed dynamically. 169 * 170 * in case invalid lane count, link rate are force, no hw programming will be 171 * done. please check link settings after force operation to see if HW get 172 * programming. 173 * 174 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 175 * 176 * check current and preferred settings. 177 * 178 */ 179 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 180 size_t size, loff_t *pos) 181 { 182 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 183 struct dc_link *link = connector->dc_link; 184 char *rd_buf = NULL; 185 char *rd_buf_ptr = NULL; 186 const uint32_t rd_buf_size = 100; 187 uint32_t result = 0; 188 uint8_t str_len = 0; 189 int r; 190 191 if (*pos & 3 || size & 3) 192 return -EINVAL; 193 194 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 195 if (!rd_buf) 196 return 0; 197 198 rd_buf_ptr = rd_buf; 199 200 str_len = strlen("Current: %d %d %d "); 201 snprintf(rd_buf_ptr, str_len, "Current: %d %d %d ", 202 link->cur_link_settings.lane_count, 203 link->cur_link_settings.link_rate, 204 link->cur_link_settings.link_spread); 205 rd_buf_ptr += str_len; 206 207 str_len = strlen("Verified: %d %d %d "); 208 snprintf(rd_buf_ptr, str_len, "Verified: %d %d %d ", 209 link->verified_link_cap.lane_count, 210 link->verified_link_cap.link_rate, 211 link->verified_link_cap.link_spread); 212 rd_buf_ptr += str_len; 213 214 str_len = strlen("Reported: %d %d %d "); 215 snprintf(rd_buf_ptr, str_len, "Reported: %d %d %d ", 216 link->reported_link_cap.lane_count, 217 link->reported_link_cap.link_rate, 218 link->reported_link_cap.link_spread); 219 rd_buf_ptr += str_len; 220 221 str_len = strlen("Preferred: %d %d %d "); 222 snprintf(rd_buf_ptr, str_len, "Preferred: %d %d %d\n", 223 link->preferred_link_setting.lane_count, 224 link->preferred_link_setting.link_rate, 225 link->preferred_link_setting.link_spread); 226 227 while (size) { 228 if (*pos >= rd_buf_size) 229 break; 230 231 r = put_user(*(rd_buf + result), buf); 232 if (r) 233 return r; /* r = -EFAULT */ 234 235 buf += 1; 236 size -= 1; 237 *pos += 1; 238 result += 1; 239 } 240 241 kfree(rd_buf); 242 return result; 243 } 244 245 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 246 size_t size, loff_t *pos) 247 { 248 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 249 struct dc_link *link = connector->dc_link; 250 struct dc_link_settings prefer_link_settings; 251 char *wr_buf = NULL; 252 const uint32_t wr_buf_size = 40; 253 /* 0: lane_count; 1: link_rate */ 254 int max_param_num = 2; 255 uint8_t param_nums = 0; 256 long param[2]; 257 bool valid_input = true; 258 259 if (size == 0) 260 return -EINVAL; 261 262 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 263 if (!wr_buf) 264 return -ENOSPC; 265 266 if (parse_write_buffer_into_params(wr_buf, size, 267 (long *)param, buf, 268 max_param_num, 269 ¶m_nums)) { 270 kfree(wr_buf); 271 return -EINVAL; 272 } 273 274 if (param_nums <= 0) { 275 kfree(wr_buf); 276 DRM_DEBUG_DRIVER("user data not be read\n"); 277 return -EINVAL; 278 } 279 280 switch (param[0]) { 281 case LANE_COUNT_ONE: 282 case LANE_COUNT_TWO: 283 case LANE_COUNT_FOUR: 284 break; 285 default: 286 valid_input = false; 287 break; 288 } 289 290 switch (param[1]) { 291 case LINK_RATE_LOW: 292 case LINK_RATE_HIGH: 293 case LINK_RATE_RBR2: 294 case LINK_RATE_HIGH2: 295 case LINK_RATE_HIGH3: 296 break; 297 default: 298 valid_input = false; 299 break; 300 } 301 302 if (!valid_input) { 303 kfree(wr_buf); 304 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 305 return size; 306 } 307 308 /* save user force lane_count, link_rate to preferred settings 309 * spread spectrum will not be changed 310 */ 311 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 312 prefer_link_settings.use_link_rate_set = false; 313 prefer_link_settings.lane_count = param[0]; 314 prefer_link_settings.link_rate = param[1]; 315 316 dp_retrain_link_dp_test(link, &prefer_link_settings, false); 317 318 kfree(wr_buf); 319 return size; 320 } 321 322 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 323 * post-cursor2 (defined by VESA DP specification) 324 * 325 * valid values 326 * voltage swing: 0,1,2,3 327 * pre-emphasis : 0,1,2,3 328 * post cursor2 : 0,1,2,3 329 * 330 * 331 * how to use this debugfs 332 * 333 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 334 * 335 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 336 * 337 * To figure out which DP-x is the display for DP to be check, 338 * cd DP-x 339 * ls -ll 340 * There should be debugfs file, like link_settings, phy_settings. 341 * cat link_settings 342 * from lane_count, link_rate to figure which DP-x is for display to be worked 343 * on 344 * 345 * To get current DP PHY settings, 346 * cat phy_settings 347 * 348 * To change DP PHY settings, 349 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 350 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 351 * 0, 352 * echo 2 3 0 > phy_settings 353 * 354 * To check if change be applied, get current phy settings by 355 * cat phy_settings 356 * 357 * In case invalid values are set by user, like 358 * echo 1 4 0 > phy_settings 359 * 360 * HW will NOT be programmed by these settings. 361 * cat phy_settings will show the previous valid settings. 362 */ 363 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 364 size_t size, loff_t *pos) 365 { 366 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 367 struct dc_link *link = connector->dc_link; 368 char *rd_buf = NULL; 369 const uint32_t rd_buf_size = 20; 370 uint32_t result = 0; 371 int r; 372 373 if (*pos & 3 || size & 3) 374 return -EINVAL; 375 376 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 377 if (!rd_buf) 378 return -EINVAL; 379 380 snprintf(rd_buf, rd_buf_size, " %d %d %d ", 381 link->cur_lane_setting.VOLTAGE_SWING, 382 link->cur_lane_setting.PRE_EMPHASIS, 383 link->cur_lane_setting.POST_CURSOR2); 384 385 while (size) { 386 if (*pos >= rd_buf_size) 387 break; 388 389 r = put_user((*(rd_buf + result)), buf); 390 if (r) 391 return r; /* r = -EFAULT */ 392 393 buf += 1; 394 size -= 1; 395 *pos += 1; 396 result += 1; 397 } 398 399 kfree(rd_buf); 400 return result; 401 } 402 403 static int dp_lttpr_status_show(struct seq_file *m, void *d) 404 { 405 char *data; 406 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 407 struct dc_link *link = connector->dc_link; 408 uint32_t read_size = 1; 409 uint8_t repeater_count = 0; 410 411 data = kzalloc(read_size, GFP_KERNEL); 412 if (!data) 413 return 0; 414 415 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 416 417 switch ((uint8_t)*data) { 418 case 0x80: 419 repeater_count = 1; 420 break; 421 case 0x40: 422 repeater_count = 2; 423 break; 424 case 0x20: 425 repeater_count = 3; 426 break; 427 case 0x10: 428 repeater_count = 4; 429 break; 430 case 0x8: 431 repeater_count = 5; 432 break; 433 case 0x4: 434 repeater_count = 6; 435 break; 436 case 0x2: 437 repeater_count = 7; 438 break; 439 case 0x1: 440 repeater_count = 8; 441 break; 442 case 0x0: 443 repeater_count = 0; 444 break; 445 default: 446 repeater_count = (uint8_t)*data; 447 break; 448 } 449 450 seq_printf(m, "phy repeater count: %d\n", repeater_count); 451 452 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 453 454 if ((uint8_t)*data == 0x55) 455 seq_printf(m, "phy repeater mode: transparent\n"); 456 else if ((uint8_t)*data == 0xAA) 457 seq_printf(m, "phy repeater mode: non-transparent\n"); 458 else if ((uint8_t)*data == 0x00) 459 seq_printf(m, "phy repeater mode: non lttpr\n"); 460 else 461 seq_printf(m, "phy repeater mode: read error\n"); 462 463 kfree(data); 464 return 0; 465 } 466 467 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 468 size_t size, loff_t *pos) 469 { 470 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 471 struct dc_link *link = connector->dc_link; 472 struct dc *dc = (struct dc *)link->dc; 473 char *wr_buf = NULL; 474 uint32_t wr_buf_size = 40; 475 long param[3]; 476 bool use_prefer_link_setting; 477 struct link_training_settings link_lane_settings; 478 int max_param_num = 3; 479 uint8_t param_nums = 0; 480 int r = 0; 481 482 483 if (size == 0) 484 return -EINVAL; 485 486 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 487 if (!wr_buf) 488 return -ENOSPC; 489 490 if (parse_write_buffer_into_params(wr_buf, size, 491 (long *)param, buf, 492 max_param_num, 493 ¶m_nums)) { 494 kfree(wr_buf); 495 return -EINVAL; 496 } 497 498 if (param_nums <= 0) { 499 kfree(wr_buf); 500 DRM_DEBUG_DRIVER("user data not be read\n"); 501 return -EINVAL; 502 } 503 504 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 505 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 506 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 507 kfree(wr_buf); 508 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 509 return size; 510 } 511 512 /* get link settings: lane count, link rate */ 513 use_prefer_link_setting = 514 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 515 (link->test_pattern_enabled)); 516 517 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 518 519 if (use_prefer_link_setting) { 520 link_lane_settings.link_settings.lane_count = 521 link->preferred_link_setting.lane_count; 522 link_lane_settings.link_settings.link_rate = 523 link->preferred_link_setting.link_rate; 524 link_lane_settings.link_settings.link_spread = 525 link->preferred_link_setting.link_spread; 526 } else { 527 link_lane_settings.link_settings.lane_count = 528 link->cur_link_settings.lane_count; 529 link_lane_settings.link_settings.link_rate = 530 link->cur_link_settings.link_rate; 531 link_lane_settings.link_settings.link_spread = 532 link->cur_link_settings.link_spread; 533 } 534 535 /* apply phy settings from user */ 536 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 537 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 538 (enum dc_voltage_swing) (param[0]); 539 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 540 (enum dc_pre_emphasis) (param[1]); 541 link_lane_settings.lane_settings[r].POST_CURSOR2 = 542 (enum dc_post_cursor2) (param[2]); 543 } 544 545 /* program ASIC registers and DPCD registers */ 546 dc_link_set_drive_settings(dc, &link_lane_settings, link); 547 548 kfree(wr_buf); 549 return size; 550 } 551 552 /* function description 553 * 554 * set PHY layer or Link layer test pattern 555 * PHY test pattern is used for PHY SI check. 556 * Link layer test will not affect PHY SI. 557 * 558 * Reset Test Pattern: 559 * 0 = DP_TEST_PATTERN_VIDEO_MODE 560 * 561 * PHY test pattern supported: 562 * 1 = DP_TEST_PATTERN_D102 563 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 564 * 3 = DP_TEST_PATTERN_PRBS7 565 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 566 * 5 = DP_TEST_PATTERN_CP2520_1 567 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 568 * 7 = DP_TEST_PATTERN_CP2520_3 569 * 570 * DP PHY Link Training Patterns 571 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 572 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 573 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 574 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 575 * 576 * DP Link Layer Test pattern 577 * c = DP_TEST_PATTERN_COLOR_SQUARES 578 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 579 * e = DP_TEST_PATTERN_VERTICAL_BARS 580 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 581 * 10= DP_TEST_PATTERN_COLOR_RAMP 582 * 583 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 584 * 585 * --- set test pattern 586 * echo <test pattern #> > test_pattern 587 * 588 * If test pattern # is not supported, NO HW programming will be done. 589 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 590 * for the user pattern. input 10 bytes data are separated by space 591 * 592 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 593 * 594 * --- reset test pattern 595 * echo 0 > test_pattern 596 * 597 * --- HPD detection is disabled when set PHY test pattern 598 * 599 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 600 * is disable. User could unplug DP display from DP connected and plug scope to 601 * check test pattern PHY SI. 602 * If there is need unplug scope and plug DP display back, do steps below: 603 * echo 0 > phy_test_pattern 604 * unplug scope 605 * plug DP display. 606 * 607 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 608 * driver could detect "unplug scope" and "plug DP display" 609 */ 610 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 611 size_t size, loff_t *pos) 612 { 613 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 614 struct dc_link *link = connector->dc_link; 615 char *wr_buf = NULL; 616 uint32_t wr_buf_size = 100; 617 long param[11] = {0x0}; 618 int max_param_num = 11; 619 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 620 bool disable_hpd = false; 621 bool valid_test_pattern = false; 622 uint8_t param_nums = 0; 623 /* init with default 80bit custom pattern */ 624 uint8_t custom_pattern[10] = { 625 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 626 0x1f, 0x7c, 0xf0, 0xc1, 0x07 627 }; 628 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 629 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 630 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 631 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 632 struct link_training_settings link_training_settings; 633 int i; 634 635 if (size == 0) 636 return -EINVAL; 637 638 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 639 if (!wr_buf) 640 return -ENOSPC; 641 642 if (parse_write_buffer_into_params(wr_buf, size, 643 (long *)param, buf, 644 max_param_num, 645 ¶m_nums)) { 646 kfree(wr_buf); 647 return -EINVAL; 648 } 649 650 if (param_nums <= 0) { 651 kfree(wr_buf); 652 DRM_DEBUG_DRIVER("user data not be read\n"); 653 return -EINVAL; 654 } 655 656 657 test_pattern = param[0]; 658 659 switch (test_pattern) { 660 case DP_TEST_PATTERN_VIDEO_MODE: 661 case DP_TEST_PATTERN_COLOR_SQUARES: 662 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 663 case DP_TEST_PATTERN_VERTICAL_BARS: 664 case DP_TEST_PATTERN_HORIZONTAL_BARS: 665 case DP_TEST_PATTERN_COLOR_RAMP: 666 valid_test_pattern = true; 667 break; 668 669 case DP_TEST_PATTERN_D102: 670 case DP_TEST_PATTERN_SYMBOL_ERROR: 671 case DP_TEST_PATTERN_PRBS7: 672 case DP_TEST_PATTERN_80BIT_CUSTOM: 673 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 674 case DP_TEST_PATTERN_TRAINING_PATTERN4: 675 disable_hpd = true; 676 valid_test_pattern = true; 677 break; 678 679 default: 680 valid_test_pattern = false; 681 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 682 break; 683 } 684 685 if (!valid_test_pattern) { 686 kfree(wr_buf); 687 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 688 return size; 689 } 690 691 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 692 for (i = 0; i < 10; i++) { 693 if ((uint8_t) param[i + 1] != 0x0) 694 break; 695 } 696 697 if (i < 10) { 698 /* not use default value */ 699 for (i = 0; i < 10; i++) 700 custom_pattern[i] = (uint8_t) param[i + 1]; 701 } 702 } 703 704 /* Usage: set DP physical test pattern using debugfs with normal DP 705 * panel. Then plug out DP panel and connect a scope to measure 706 * For normal video mode and test pattern generated from CRCT, 707 * they are visibile to user. So do not disable HPD. 708 * Video Mode is also set to clear the test pattern, so enable HPD 709 * because it might have been disabled after a test pattern was set. 710 * AUX depends on HPD * sequence dependent, do not move! 711 */ 712 if (!disable_hpd) 713 dc_link_enable_hpd(link); 714 715 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 716 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 717 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 718 719 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 720 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 721 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 722 723 link_training_settings.link_settings = cur_link_settings; 724 725 726 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 727 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 728 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 729 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 730 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 731 link_training_settings.link_settings = prefer_link_settings; 732 } 733 734 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 735 link_training_settings.lane_settings[i] = link->cur_lane_setting; 736 737 dc_link_set_test_pattern( 738 link, 739 test_pattern, 740 DP_TEST_PATTERN_COLOR_SPACE_RGB, 741 &link_training_settings, 742 custom_pattern, 743 10); 744 745 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 746 * Then plug out DP panel and connect a scope to measure DP PHY signal. 747 * Need disable interrupt to avoid SW driver disable DP output. This is 748 * done after the test pattern is set. 749 */ 750 if (valid_test_pattern && disable_hpd) 751 dc_link_disable_hpd(link); 752 753 kfree(wr_buf); 754 755 return size; 756 } 757 758 /* 759 * Returns the DMCUB tracebuffer contents. 760 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 761 */ 762 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 763 { 764 struct amdgpu_device *adev = m->private; 765 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 766 struct dmub_debugfs_trace_entry *entries; 767 uint8_t *tbuf_base; 768 uint32_t tbuf_size, max_entries, num_entries, i; 769 770 if (!fb_info) 771 return 0; 772 773 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 774 if (!tbuf_base) 775 return 0; 776 777 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 778 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 779 sizeof(struct dmub_debugfs_trace_entry); 780 781 num_entries = 782 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 783 784 num_entries = min(num_entries, max_entries); 785 786 entries = (struct dmub_debugfs_trace_entry 787 *)(tbuf_base + 788 sizeof(struct dmub_debugfs_trace_header)); 789 790 for (i = 0; i < num_entries; ++i) { 791 struct dmub_debugfs_trace_entry *entry = &entries[i]; 792 793 seq_printf(m, 794 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 795 entry->trace_code, entry->tick_count, entry->param0, 796 entry->param1); 797 } 798 799 return 0; 800 } 801 802 /* 803 * Returns the DMCUB firmware state contents. 804 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 805 */ 806 static int dmub_fw_state_show(struct seq_file *m, void *data) 807 { 808 struct amdgpu_device *adev = m->private; 809 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 810 uint8_t *state_base; 811 uint32_t state_size; 812 813 if (!fb_info) 814 return 0; 815 816 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 817 if (!state_base) 818 return 0; 819 820 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 821 822 return seq_write(m, state_base, state_size); 823 } 824 825 /* 826 * Returns the current and maximum output bpc for the connector. 827 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 828 */ 829 static int output_bpc_show(struct seq_file *m, void *data) 830 { 831 struct drm_connector *connector = m->private; 832 struct drm_device *dev = connector->dev; 833 struct drm_crtc *crtc = NULL; 834 struct dm_crtc_state *dm_crtc_state = NULL; 835 int res = -ENODEV; 836 unsigned int bpc; 837 838 mutex_lock(&dev->mode_config.mutex); 839 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 840 841 if (connector->state == NULL) 842 goto unlock; 843 844 crtc = connector->state->crtc; 845 if (crtc == NULL) 846 goto unlock; 847 848 drm_modeset_lock(&crtc->mutex, NULL); 849 if (crtc->state == NULL) 850 goto unlock; 851 852 dm_crtc_state = to_dm_crtc_state(crtc->state); 853 if (dm_crtc_state->stream == NULL) 854 goto unlock; 855 856 switch (dm_crtc_state->stream->timing.display_color_depth) { 857 case COLOR_DEPTH_666: 858 bpc = 6; 859 break; 860 case COLOR_DEPTH_888: 861 bpc = 8; 862 break; 863 case COLOR_DEPTH_101010: 864 bpc = 10; 865 break; 866 case COLOR_DEPTH_121212: 867 bpc = 12; 868 break; 869 case COLOR_DEPTH_161616: 870 bpc = 16; 871 break; 872 default: 873 goto unlock; 874 } 875 876 seq_printf(m, "Current: %u\n", bpc); 877 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 878 res = 0; 879 880 unlock: 881 if (crtc) 882 drm_modeset_unlock(&crtc->mutex); 883 884 drm_modeset_unlock(&dev->mode_config.connection_mutex); 885 mutex_unlock(&dev->mode_config.mutex); 886 887 return res; 888 } 889 890 #ifdef CONFIG_DRM_AMD_DC_HDCP 891 /* 892 * Returns the HDCP capability of the Display (1.4 for now). 893 * 894 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 895 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 896 * 897 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 898 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 899 */ 900 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 901 { 902 struct drm_connector *connector = m->private; 903 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 904 bool hdcp_cap, hdcp2_cap; 905 906 if (connector->status != connector_status_connected) 907 return -ENODEV; 908 909 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 910 911 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 912 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 913 914 915 if (hdcp_cap) 916 seq_printf(m, "%s ", "HDCP1.4"); 917 if (hdcp2_cap) 918 seq_printf(m, "%s ", "HDCP2.2"); 919 920 if (!hdcp_cap && !hdcp2_cap) 921 seq_printf(m, "%s ", "None"); 922 923 seq_puts(m, "\n"); 924 925 return 0; 926 } 927 #endif 928 /* function description 929 * 930 * generic SDP message access for testing 931 * 932 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 933 * 934 * SDP header 935 * Hb0 : Secondary-Data Packet ID 936 * Hb1 : Secondary-Data Packet type 937 * Hb2 : Secondary-Data-packet-specific header, Byte 0 938 * Hb3 : Secondary-Data-packet-specific header, Byte 1 939 * 940 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 941 */ 942 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 943 size_t size, loff_t *pos) 944 { 945 int r; 946 uint8_t data[36]; 947 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 948 struct dm_crtc_state *acrtc_state; 949 uint32_t write_size = 36; 950 951 if (connector->base.status != connector_status_connected) 952 return -ENODEV; 953 954 if (size == 0) 955 return 0; 956 957 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 958 959 r = copy_from_user(data, buf, write_size); 960 961 write_size -= r; 962 963 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 964 965 return write_size; 966 } 967 968 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 969 size_t size, loff_t *pos) 970 { 971 int r; 972 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 973 974 if (size < sizeof(connector->debugfs_dpcd_address)) 975 return -EINVAL; 976 977 r = copy_from_user(&connector->debugfs_dpcd_address, 978 buf, sizeof(connector->debugfs_dpcd_address)); 979 980 return size - r; 981 } 982 983 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 984 size_t size, loff_t *pos) 985 { 986 int r; 987 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 988 989 if (size < sizeof(connector->debugfs_dpcd_size)) 990 return -EINVAL; 991 992 r = copy_from_user(&connector->debugfs_dpcd_size, 993 buf, sizeof(connector->debugfs_dpcd_size)); 994 995 if (connector->debugfs_dpcd_size > 256) 996 connector->debugfs_dpcd_size = 0; 997 998 return size - r; 999 } 1000 1001 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1002 size_t size, loff_t *pos) 1003 { 1004 int r; 1005 char *data; 1006 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1007 struct dc_link *link = connector->dc_link; 1008 uint32_t write_size = connector->debugfs_dpcd_size; 1009 1010 if (!write_size || size < write_size) 1011 return -EINVAL; 1012 1013 data = kzalloc(write_size, GFP_KERNEL); 1014 if (!data) 1015 return 0; 1016 1017 r = copy_from_user(data, buf, write_size); 1018 1019 dm_helpers_dp_write_dpcd(link->ctx, link, 1020 connector->debugfs_dpcd_address, data, write_size - r); 1021 kfree(data); 1022 return write_size - r; 1023 } 1024 1025 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1026 size_t size, loff_t *pos) 1027 { 1028 int r; 1029 char *data; 1030 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1031 struct dc_link *link = connector->dc_link; 1032 uint32_t read_size = connector->debugfs_dpcd_size; 1033 1034 if (!read_size || size < read_size) 1035 return 0; 1036 1037 data = kzalloc(read_size, GFP_KERNEL); 1038 if (!data) 1039 return 0; 1040 1041 dm_helpers_dp_read_dpcd(link->ctx, link, 1042 connector->debugfs_dpcd_address, data, read_size); 1043 1044 r = copy_to_user(buf, data, read_size); 1045 1046 kfree(data); 1047 return read_size - r; 1048 } 1049 1050 /* function: Read link's DSC & FEC capabilities 1051 * 1052 * 1053 * Access it with the following command (you need to specify 1054 * connector like DP-1): 1055 * 1056 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1057 * 1058 */ 1059 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1060 { 1061 struct drm_connector *connector = m->private; 1062 struct drm_modeset_acquire_ctx ctx; 1063 struct drm_device *dev = connector->dev; 1064 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1065 int ret = 0; 1066 bool try_again = false; 1067 bool is_fec_supported = false; 1068 bool is_dsc_supported = false; 1069 struct dpcd_caps dpcd_caps; 1070 1071 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1072 do { 1073 try_again = false; 1074 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1075 if (ret) { 1076 if (ret == -EDEADLK) { 1077 ret = drm_modeset_backoff(&ctx); 1078 if (!ret) { 1079 try_again = true; 1080 continue; 1081 } 1082 } 1083 break; 1084 } 1085 if (connector->status != connector_status_connected) { 1086 ret = -ENODEV; 1087 break; 1088 } 1089 dpcd_caps = aconnector->dc_link->dpcd_caps; 1090 if (aconnector->port) { 1091 /* aconnector sets dsc_aux during get_modes call 1092 * if MST connector has it means it can either 1093 * enable DSC on the sink device or on MST branch 1094 * its connected to. 1095 */ 1096 if (aconnector->dsc_aux) { 1097 is_fec_supported = true; 1098 is_dsc_supported = true; 1099 } 1100 } else { 1101 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1102 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1103 } 1104 } while (try_again); 1105 1106 drm_modeset_drop_locks(&ctx); 1107 drm_modeset_acquire_fini(&ctx); 1108 1109 seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported)); 1110 seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported)); 1111 1112 return ret; 1113 } 1114 1115 /* function: Trigger virtual HPD redetection on connector 1116 * 1117 * This function will perform link rediscovery, link disable 1118 * and enable, and dm connector state update. 1119 * 1120 * Retrigger HPD on an existing connector by echoing 1 into 1121 * its respectful "trigger_hotplug" debugfs entry: 1122 * 1123 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1124 * 1125 * This function can perform HPD unplug: 1126 * 1127 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1128 * 1129 */ 1130 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1131 size_t size, loff_t *pos) 1132 { 1133 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1134 struct drm_connector *connector = &aconnector->base; 1135 struct dc_link *link = NULL; 1136 struct drm_device *dev = connector->dev; 1137 enum dc_connection_type new_connection_type = dc_connection_none; 1138 char *wr_buf = NULL; 1139 uint32_t wr_buf_size = 42; 1140 int max_param_num = 1; 1141 long param[1] = {0}; 1142 uint8_t param_nums = 0; 1143 1144 if (!aconnector || !aconnector->dc_link) 1145 return -EINVAL; 1146 1147 if (size == 0) 1148 return -EINVAL; 1149 1150 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1151 1152 if (!wr_buf) { 1153 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1154 return -ENOSPC; 1155 } 1156 1157 if (parse_write_buffer_into_params(wr_buf, size, 1158 (long *)param, buf, 1159 max_param_num, 1160 ¶m_nums)) { 1161 kfree(wr_buf); 1162 return -EINVAL; 1163 } 1164 1165 if (param_nums <= 0) { 1166 DRM_DEBUG_DRIVER("user data not be read\n"); 1167 kfree(wr_buf); 1168 return -EINVAL; 1169 } 1170 1171 if (param[0] == 1) { 1172 mutex_lock(&aconnector->hpd_lock); 1173 1174 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1175 new_connection_type != dc_connection_none) 1176 goto unlock; 1177 1178 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1179 goto unlock; 1180 1181 amdgpu_dm_update_connector_after_detect(aconnector); 1182 1183 drm_modeset_lock_all(dev); 1184 dm_restore_drm_connector_state(dev, connector); 1185 drm_modeset_unlock_all(dev); 1186 1187 drm_kms_helper_hotplug_event(dev); 1188 } else if (param[0] == 0) { 1189 if (!aconnector->dc_link) 1190 goto unlock; 1191 1192 link = aconnector->dc_link; 1193 1194 if (link->local_sink) { 1195 dc_sink_release(link->local_sink); 1196 link->local_sink = NULL; 1197 } 1198 1199 link->dpcd_sink_count = 0; 1200 link->type = dc_connection_none; 1201 link->dongle_max_pix_clk = 0; 1202 1203 amdgpu_dm_update_connector_after_detect(aconnector); 1204 1205 drm_modeset_lock_all(dev); 1206 dm_restore_drm_connector_state(dev, connector); 1207 drm_modeset_unlock_all(dev); 1208 1209 drm_kms_helper_hotplug_event(dev); 1210 } 1211 1212 unlock: 1213 mutex_unlock(&aconnector->hpd_lock); 1214 1215 kfree(wr_buf); 1216 return size; 1217 } 1218 1219 /* function: read DSC status on the connector 1220 * 1221 * The read function: dp_dsc_clock_en_read 1222 * returns current status of DSC clock on the connector. 1223 * The return is a boolean flag: 1 or 0. 1224 * 1225 * Access it with the following command (you need to specify 1226 * connector like DP-1): 1227 * 1228 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1229 * 1230 * Expected output: 1231 * 1 - means that DSC is currently enabled 1232 * 0 - means that DSC is disabled 1233 */ 1234 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1235 size_t size, loff_t *pos) 1236 { 1237 char *rd_buf = NULL; 1238 char *rd_buf_ptr = NULL; 1239 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1240 struct display_stream_compressor *dsc; 1241 struct dcn_dsc_state dsc_state = {0}; 1242 const uint32_t rd_buf_size = 10; 1243 struct pipe_ctx *pipe_ctx; 1244 ssize_t result = 0; 1245 int i, r, str_len = 30; 1246 1247 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1248 1249 if (!rd_buf) 1250 return -ENOMEM; 1251 1252 rd_buf_ptr = rd_buf; 1253 1254 for (i = 0; i < MAX_PIPES; i++) { 1255 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1256 if (pipe_ctx && pipe_ctx->stream && 1257 pipe_ctx->stream->link == aconnector->dc_link) 1258 break; 1259 } 1260 1261 if (!pipe_ctx) 1262 return -ENXIO; 1263 1264 dsc = pipe_ctx->stream_res.dsc; 1265 if (dsc) 1266 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1267 1268 snprintf(rd_buf_ptr, str_len, 1269 "%d\n", 1270 dsc_state.dsc_clock_en); 1271 rd_buf_ptr += str_len; 1272 1273 while (size) { 1274 if (*pos >= rd_buf_size) 1275 break; 1276 1277 r = put_user(*(rd_buf + result), buf); 1278 if (r) 1279 return r; /* r = -EFAULT */ 1280 1281 buf += 1; 1282 size -= 1; 1283 *pos += 1; 1284 result += 1; 1285 } 1286 1287 kfree(rd_buf); 1288 return result; 1289 } 1290 1291 /* function: write force DSC on the connector 1292 * 1293 * The write function: dp_dsc_clock_en_write 1294 * enables to force DSC on the connector. 1295 * User can write to either force enable or force disable DSC 1296 * on the next modeset or set it to driver default 1297 * 1298 * Accepted inputs: 1299 * 0 - default DSC enablement policy 1300 * 1 - force enable DSC on the connector 1301 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1302 * 1303 * Writing DSC settings is done with the following command: 1304 * - To force enable DSC (you need to specify 1305 * connector like DP-1): 1306 * 1307 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1308 * 1309 * - To return to default state set the flag to zero and 1310 * let driver deal with DSC automatically 1311 * (you need to specify connector like DP-1): 1312 * 1313 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1314 * 1315 */ 1316 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1317 size_t size, loff_t *pos) 1318 { 1319 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1320 struct drm_connector *connector = &aconnector->base; 1321 struct drm_device *dev = connector->dev; 1322 struct drm_crtc *crtc = NULL; 1323 struct dm_crtc_state *dm_crtc_state = NULL; 1324 struct pipe_ctx *pipe_ctx; 1325 int i; 1326 char *wr_buf = NULL; 1327 uint32_t wr_buf_size = 42; 1328 int max_param_num = 1; 1329 long param[1] = {0}; 1330 uint8_t param_nums = 0; 1331 1332 if (size == 0) 1333 return -EINVAL; 1334 1335 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1336 1337 if (!wr_buf) { 1338 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1339 return -ENOSPC; 1340 } 1341 1342 if (parse_write_buffer_into_params(wr_buf, size, 1343 (long *)param, buf, 1344 max_param_num, 1345 ¶m_nums)) { 1346 kfree(wr_buf); 1347 return -EINVAL; 1348 } 1349 1350 if (param_nums <= 0) { 1351 DRM_DEBUG_DRIVER("user data not be read\n"); 1352 kfree(wr_buf); 1353 return -EINVAL; 1354 } 1355 1356 for (i = 0; i < MAX_PIPES; i++) { 1357 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1358 if (pipe_ctx && pipe_ctx->stream && 1359 pipe_ctx->stream->link == aconnector->dc_link) 1360 break; 1361 } 1362 1363 if (!pipe_ctx || !pipe_ctx->stream) 1364 goto done; 1365 1366 // Get CRTC state 1367 mutex_lock(&dev->mode_config.mutex); 1368 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1369 1370 if (connector->state == NULL) 1371 goto unlock; 1372 1373 crtc = connector->state->crtc; 1374 if (crtc == NULL) 1375 goto unlock; 1376 1377 drm_modeset_lock(&crtc->mutex, NULL); 1378 if (crtc->state == NULL) 1379 goto unlock; 1380 1381 dm_crtc_state = to_dm_crtc_state(crtc->state); 1382 if (dm_crtc_state->stream == NULL) 1383 goto unlock; 1384 1385 if (param[0] == 1) 1386 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1387 else if (param[0] == 2) 1388 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1389 else 1390 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1391 1392 dm_crtc_state->dsc_force_changed = true; 1393 1394 unlock: 1395 if (crtc) 1396 drm_modeset_unlock(&crtc->mutex); 1397 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1398 mutex_unlock(&dev->mode_config.mutex); 1399 1400 done: 1401 kfree(wr_buf); 1402 return size; 1403 } 1404 1405 /* function: read DSC slice width parameter on the connector 1406 * 1407 * The read function: dp_dsc_slice_width_read 1408 * returns dsc slice width used in the current configuration 1409 * The return is an integer: 0 or other positive number 1410 * 1411 * Access the status with the following command: 1412 * 1413 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1414 * 1415 * 0 - means that DSC is disabled 1416 * 1417 * Any other number more than zero represents the 1418 * slice width currently used by DSC in pixels 1419 * 1420 */ 1421 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1422 size_t size, loff_t *pos) 1423 { 1424 char *rd_buf = NULL; 1425 char *rd_buf_ptr = NULL; 1426 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1427 struct display_stream_compressor *dsc; 1428 struct dcn_dsc_state dsc_state = {0}; 1429 const uint32_t rd_buf_size = 100; 1430 struct pipe_ctx *pipe_ctx; 1431 ssize_t result = 0; 1432 int i, r, str_len = 30; 1433 1434 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1435 1436 if (!rd_buf) 1437 return -ENOMEM; 1438 1439 rd_buf_ptr = rd_buf; 1440 1441 for (i = 0; i < MAX_PIPES; i++) { 1442 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1443 if (pipe_ctx && pipe_ctx->stream && 1444 pipe_ctx->stream->link == aconnector->dc_link) 1445 break; 1446 } 1447 1448 if (!pipe_ctx) 1449 return -ENXIO; 1450 1451 dsc = pipe_ctx->stream_res.dsc; 1452 if (dsc) 1453 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1454 1455 snprintf(rd_buf_ptr, str_len, 1456 "%d\n", 1457 dsc_state.dsc_slice_width); 1458 rd_buf_ptr += str_len; 1459 1460 while (size) { 1461 if (*pos >= rd_buf_size) 1462 break; 1463 1464 r = put_user(*(rd_buf + result), buf); 1465 if (r) 1466 return r; /* r = -EFAULT */ 1467 1468 buf += 1; 1469 size -= 1; 1470 *pos += 1; 1471 result += 1; 1472 } 1473 1474 kfree(rd_buf); 1475 return result; 1476 } 1477 1478 /* function: write DSC slice width parameter 1479 * 1480 * The write function: dp_dsc_slice_width_write 1481 * overwrites automatically generated DSC configuration 1482 * of slice width. 1483 * 1484 * The user has to write the slice width divisible by the 1485 * picture width. 1486 * 1487 * Also the user has to write width in hexidecimal 1488 * rather than in decimal. 1489 * 1490 * Writing DSC settings is done with the following command: 1491 * - To force overwrite slice width: (example sets to 1920 pixels) 1492 * 1493 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1494 * 1495 * - To stop overwriting and let driver find the optimal size, 1496 * set the width to zero: 1497 * 1498 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1499 * 1500 */ 1501 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1502 size_t size, loff_t *pos) 1503 { 1504 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1505 struct pipe_ctx *pipe_ctx; 1506 struct drm_connector *connector = &aconnector->base; 1507 struct drm_device *dev = connector->dev; 1508 struct drm_crtc *crtc = NULL; 1509 struct dm_crtc_state *dm_crtc_state = NULL; 1510 int i; 1511 char *wr_buf = NULL; 1512 uint32_t wr_buf_size = 42; 1513 int max_param_num = 1; 1514 long param[1] = {0}; 1515 uint8_t param_nums = 0; 1516 1517 if (size == 0) 1518 return -EINVAL; 1519 1520 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1521 1522 if (!wr_buf) { 1523 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1524 return -ENOSPC; 1525 } 1526 1527 if (parse_write_buffer_into_params(wr_buf, size, 1528 (long *)param, buf, 1529 max_param_num, 1530 ¶m_nums)) { 1531 kfree(wr_buf); 1532 return -EINVAL; 1533 } 1534 1535 if (param_nums <= 0) { 1536 DRM_DEBUG_DRIVER("user data not be read\n"); 1537 kfree(wr_buf); 1538 return -EINVAL; 1539 } 1540 1541 for (i = 0; i < MAX_PIPES; i++) { 1542 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1543 if (pipe_ctx && pipe_ctx->stream && 1544 pipe_ctx->stream->link == aconnector->dc_link) 1545 break; 1546 } 1547 1548 if (!pipe_ctx || !pipe_ctx->stream) 1549 goto done; 1550 1551 // Safely get CRTC state 1552 mutex_lock(&dev->mode_config.mutex); 1553 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1554 1555 if (connector->state == NULL) 1556 goto unlock; 1557 1558 crtc = connector->state->crtc; 1559 if (crtc == NULL) 1560 goto unlock; 1561 1562 drm_modeset_lock(&crtc->mutex, NULL); 1563 if (crtc->state == NULL) 1564 goto unlock; 1565 1566 dm_crtc_state = to_dm_crtc_state(crtc->state); 1567 if (dm_crtc_state->stream == NULL) 1568 goto unlock; 1569 1570 if (param[0] > 0) 1571 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1572 pipe_ctx->stream->timing.h_addressable, 1573 param[0]); 1574 else 1575 aconnector->dsc_settings.dsc_num_slices_h = 0; 1576 1577 dm_crtc_state->dsc_force_changed = true; 1578 1579 unlock: 1580 if (crtc) 1581 drm_modeset_unlock(&crtc->mutex); 1582 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1583 mutex_unlock(&dev->mode_config.mutex); 1584 1585 done: 1586 kfree(wr_buf); 1587 return size; 1588 } 1589 1590 /* function: read DSC slice height parameter on the connector 1591 * 1592 * The read function: dp_dsc_slice_height_read 1593 * returns dsc slice height used in the current configuration 1594 * The return is an integer: 0 or other positive number 1595 * 1596 * Access the status with the following command: 1597 * 1598 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1599 * 1600 * 0 - means that DSC is disabled 1601 * 1602 * Any other number more than zero represents the 1603 * slice height currently used by DSC in pixels 1604 * 1605 */ 1606 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1607 size_t size, loff_t *pos) 1608 { 1609 char *rd_buf = NULL; 1610 char *rd_buf_ptr = NULL; 1611 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1612 struct display_stream_compressor *dsc; 1613 struct dcn_dsc_state dsc_state = {0}; 1614 const uint32_t rd_buf_size = 100; 1615 struct pipe_ctx *pipe_ctx; 1616 ssize_t result = 0; 1617 int i, r, str_len = 30; 1618 1619 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1620 1621 if (!rd_buf) 1622 return -ENOMEM; 1623 1624 rd_buf_ptr = rd_buf; 1625 1626 for (i = 0; i < MAX_PIPES; i++) { 1627 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1628 if (pipe_ctx && pipe_ctx->stream && 1629 pipe_ctx->stream->link == aconnector->dc_link) 1630 break; 1631 } 1632 1633 if (!pipe_ctx) 1634 return -ENXIO; 1635 1636 dsc = pipe_ctx->stream_res.dsc; 1637 if (dsc) 1638 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1639 1640 snprintf(rd_buf_ptr, str_len, 1641 "%d\n", 1642 dsc_state.dsc_slice_height); 1643 rd_buf_ptr += str_len; 1644 1645 while (size) { 1646 if (*pos >= rd_buf_size) 1647 break; 1648 1649 r = put_user(*(rd_buf + result), buf); 1650 if (r) 1651 return r; /* r = -EFAULT */ 1652 1653 buf += 1; 1654 size -= 1; 1655 *pos += 1; 1656 result += 1; 1657 } 1658 1659 kfree(rd_buf); 1660 return result; 1661 } 1662 1663 /* function: write DSC slice height parameter 1664 * 1665 * The write function: dp_dsc_slice_height_write 1666 * overwrites automatically generated DSC configuration 1667 * of slice height. 1668 * 1669 * The user has to write the slice height divisible by the 1670 * picture height. 1671 * 1672 * Also the user has to write height in hexidecimal 1673 * rather than in decimal. 1674 * 1675 * Writing DSC settings is done with the following command: 1676 * - To force overwrite slice height (example sets to 128 pixels): 1677 * 1678 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1679 * 1680 * - To stop overwriting and let driver find the optimal size, 1681 * set the height to zero: 1682 * 1683 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1684 * 1685 */ 1686 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1687 size_t size, loff_t *pos) 1688 { 1689 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1690 struct drm_connector *connector = &aconnector->base; 1691 struct drm_device *dev = connector->dev; 1692 struct drm_crtc *crtc = NULL; 1693 struct dm_crtc_state *dm_crtc_state = NULL; 1694 struct pipe_ctx *pipe_ctx; 1695 int i; 1696 char *wr_buf = NULL; 1697 uint32_t wr_buf_size = 42; 1698 int max_param_num = 1; 1699 uint8_t param_nums = 0; 1700 long param[1] = {0}; 1701 1702 if (size == 0) 1703 return -EINVAL; 1704 1705 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1706 1707 if (!wr_buf) { 1708 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1709 return -ENOSPC; 1710 } 1711 1712 if (parse_write_buffer_into_params(wr_buf, size, 1713 (long *)param, buf, 1714 max_param_num, 1715 ¶m_nums)) { 1716 kfree(wr_buf); 1717 return -EINVAL; 1718 } 1719 1720 if (param_nums <= 0) { 1721 DRM_DEBUG_DRIVER("user data not be read\n"); 1722 kfree(wr_buf); 1723 return -EINVAL; 1724 } 1725 1726 for (i = 0; i < MAX_PIPES; i++) { 1727 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1728 if (pipe_ctx && pipe_ctx->stream && 1729 pipe_ctx->stream->link == aconnector->dc_link) 1730 break; 1731 } 1732 1733 if (!pipe_ctx || !pipe_ctx->stream) 1734 goto done; 1735 1736 // Get CRTC state 1737 mutex_lock(&dev->mode_config.mutex); 1738 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1739 1740 if (connector->state == NULL) 1741 goto unlock; 1742 1743 crtc = connector->state->crtc; 1744 if (crtc == NULL) 1745 goto unlock; 1746 1747 drm_modeset_lock(&crtc->mutex, NULL); 1748 if (crtc->state == NULL) 1749 goto unlock; 1750 1751 dm_crtc_state = to_dm_crtc_state(crtc->state); 1752 if (dm_crtc_state->stream == NULL) 1753 goto unlock; 1754 1755 if (param[0] > 0) 1756 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1757 pipe_ctx->stream->timing.v_addressable, 1758 param[0]); 1759 else 1760 aconnector->dsc_settings.dsc_num_slices_v = 0; 1761 1762 dm_crtc_state->dsc_force_changed = true; 1763 1764 unlock: 1765 if (crtc) 1766 drm_modeset_unlock(&crtc->mutex); 1767 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1768 mutex_unlock(&dev->mode_config.mutex); 1769 1770 done: 1771 kfree(wr_buf); 1772 return size; 1773 } 1774 1775 /* function: read DSC target rate on the connector in bits per pixel 1776 * 1777 * The read function: dp_dsc_bits_per_pixel_read 1778 * returns target rate of compression in bits per pixel 1779 * The return is an integer: 0 or other positive integer 1780 * 1781 * Access it with the following command: 1782 * 1783 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1784 * 1785 * 0 - means that DSC is disabled 1786 */ 1787 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1788 size_t size, loff_t *pos) 1789 { 1790 char *rd_buf = NULL; 1791 char *rd_buf_ptr = NULL; 1792 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1793 struct display_stream_compressor *dsc; 1794 struct dcn_dsc_state dsc_state = {0}; 1795 const uint32_t rd_buf_size = 100; 1796 struct pipe_ctx *pipe_ctx; 1797 ssize_t result = 0; 1798 int i, r, str_len = 30; 1799 1800 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1801 1802 if (!rd_buf) 1803 return -ENOMEM; 1804 1805 rd_buf_ptr = rd_buf; 1806 1807 for (i = 0; i < MAX_PIPES; i++) { 1808 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1809 if (pipe_ctx && pipe_ctx->stream && 1810 pipe_ctx->stream->link == aconnector->dc_link) 1811 break; 1812 } 1813 1814 if (!pipe_ctx) 1815 return -ENXIO; 1816 1817 dsc = pipe_ctx->stream_res.dsc; 1818 if (dsc) 1819 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1820 1821 snprintf(rd_buf_ptr, str_len, 1822 "%d\n", 1823 dsc_state.dsc_bits_per_pixel); 1824 rd_buf_ptr += str_len; 1825 1826 while (size) { 1827 if (*pos >= rd_buf_size) 1828 break; 1829 1830 r = put_user(*(rd_buf + result), buf); 1831 if (r) 1832 return r; /* r = -EFAULT */ 1833 1834 buf += 1; 1835 size -= 1; 1836 *pos += 1; 1837 result += 1; 1838 } 1839 1840 kfree(rd_buf); 1841 return result; 1842 } 1843 1844 /* function: write DSC target rate in bits per pixel 1845 * 1846 * The write function: dp_dsc_bits_per_pixel_write 1847 * overwrites automatically generated DSC configuration 1848 * of DSC target bit rate. 1849 * 1850 * Also the user has to write bpp in hexidecimal 1851 * rather than in decimal. 1852 * 1853 * Writing DSC settings is done with the following command: 1854 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1855 * 1856 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1857 * 1858 * - To stop overwriting and let driver find the optimal rate, 1859 * set the rate to zero: 1860 * 1861 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1862 * 1863 */ 1864 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1865 size_t size, loff_t *pos) 1866 { 1867 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1868 struct drm_connector *connector = &aconnector->base; 1869 struct drm_device *dev = connector->dev; 1870 struct drm_crtc *crtc = NULL; 1871 struct dm_crtc_state *dm_crtc_state = NULL; 1872 struct pipe_ctx *pipe_ctx; 1873 int i; 1874 char *wr_buf = NULL; 1875 uint32_t wr_buf_size = 42; 1876 int max_param_num = 1; 1877 uint8_t param_nums = 0; 1878 long param[1] = {0}; 1879 1880 if (size == 0) 1881 return -EINVAL; 1882 1883 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1884 1885 if (!wr_buf) { 1886 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1887 return -ENOSPC; 1888 } 1889 1890 if (parse_write_buffer_into_params(wr_buf, size, 1891 (long *)param, buf, 1892 max_param_num, 1893 ¶m_nums)) { 1894 kfree(wr_buf); 1895 return -EINVAL; 1896 } 1897 1898 if (param_nums <= 0) { 1899 DRM_DEBUG_DRIVER("user data not be read\n"); 1900 kfree(wr_buf); 1901 return -EINVAL; 1902 } 1903 1904 for (i = 0; i < MAX_PIPES; i++) { 1905 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1906 if (pipe_ctx && pipe_ctx->stream && 1907 pipe_ctx->stream->link == aconnector->dc_link) 1908 break; 1909 } 1910 1911 if (!pipe_ctx || !pipe_ctx->stream) 1912 goto done; 1913 1914 // Get CRTC state 1915 mutex_lock(&dev->mode_config.mutex); 1916 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1917 1918 if (connector->state == NULL) 1919 goto unlock; 1920 1921 crtc = connector->state->crtc; 1922 if (crtc == NULL) 1923 goto unlock; 1924 1925 drm_modeset_lock(&crtc->mutex, NULL); 1926 if (crtc->state == NULL) 1927 goto unlock; 1928 1929 dm_crtc_state = to_dm_crtc_state(crtc->state); 1930 if (dm_crtc_state->stream == NULL) 1931 goto unlock; 1932 1933 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 1934 1935 dm_crtc_state->dsc_force_changed = true; 1936 1937 unlock: 1938 if (crtc) 1939 drm_modeset_unlock(&crtc->mutex); 1940 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1941 mutex_unlock(&dev->mode_config.mutex); 1942 1943 done: 1944 kfree(wr_buf); 1945 return size; 1946 } 1947 1948 /* function: read DSC picture width parameter on the connector 1949 * 1950 * The read function: dp_dsc_pic_width_read 1951 * returns dsc picture width used in the current configuration 1952 * It is the same as h_addressable of the current 1953 * display's timing 1954 * The return is an integer: 0 or other positive integer 1955 * If 0 then DSC is disabled. 1956 * 1957 * Access it with the following command: 1958 * 1959 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 1960 * 1961 * 0 - means that DSC is disabled 1962 */ 1963 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 1964 size_t size, loff_t *pos) 1965 { 1966 char *rd_buf = NULL; 1967 char *rd_buf_ptr = NULL; 1968 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1969 struct display_stream_compressor *dsc; 1970 struct dcn_dsc_state dsc_state = {0}; 1971 const uint32_t rd_buf_size = 100; 1972 struct pipe_ctx *pipe_ctx; 1973 ssize_t result = 0; 1974 int i, r, str_len = 30; 1975 1976 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1977 1978 if (!rd_buf) 1979 return -ENOMEM; 1980 1981 rd_buf_ptr = rd_buf; 1982 1983 for (i = 0; i < MAX_PIPES; i++) { 1984 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1985 if (pipe_ctx && pipe_ctx->stream && 1986 pipe_ctx->stream->link == aconnector->dc_link) 1987 break; 1988 } 1989 1990 if (!pipe_ctx) 1991 return -ENXIO; 1992 1993 dsc = pipe_ctx->stream_res.dsc; 1994 if (dsc) 1995 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1996 1997 snprintf(rd_buf_ptr, str_len, 1998 "%d\n", 1999 dsc_state.dsc_pic_width); 2000 rd_buf_ptr += str_len; 2001 2002 while (size) { 2003 if (*pos >= rd_buf_size) 2004 break; 2005 2006 r = put_user(*(rd_buf + result), buf); 2007 if (r) 2008 return r; /* r = -EFAULT */ 2009 2010 buf += 1; 2011 size -= 1; 2012 *pos += 1; 2013 result += 1; 2014 } 2015 2016 kfree(rd_buf); 2017 return result; 2018 } 2019 2020 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2021 size_t size, loff_t *pos) 2022 { 2023 char *rd_buf = NULL; 2024 char *rd_buf_ptr = NULL; 2025 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2026 struct display_stream_compressor *dsc; 2027 struct dcn_dsc_state dsc_state = {0}; 2028 const uint32_t rd_buf_size = 100; 2029 struct pipe_ctx *pipe_ctx; 2030 ssize_t result = 0; 2031 int i, r, str_len = 30; 2032 2033 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2034 2035 if (!rd_buf) 2036 return -ENOMEM; 2037 2038 rd_buf_ptr = rd_buf; 2039 2040 for (i = 0; i < MAX_PIPES; i++) { 2041 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2042 if (pipe_ctx && pipe_ctx->stream && 2043 pipe_ctx->stream->link == aconnector->dc_link) 2044 break; 2045 } 2046 2047 if (!pipe_ctx) 2048 return -ENXIO; 2049 2050 dsc = pipe_ctx->stream_res.dsc; 2051 if (dsc) 2052 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2053 2054 snprintf(rd_buf_ptr, str_len, 2055 "%d\n", 2056 dsc_state.dsc_pic_height); 2057 rd_buf_ptr += str_len; 2058 2059 while (size) { 2060 if (*pos >= rd_buf_size) 2061 break; 2062 2063 r = put_user(*(rd_buf + result), buf); 2064 if (r) 2065 return r; /* r = -EFAULT */ 2066 2067 buf += 1; 2068 size -= 1; 2069 *pos += 1; 2070 result += 1; 2071 } 2072 2073 kfree(rd_buf); 2074 return result; 2075 } 2076 2077 /* function: read DSC chunk size parameter on the connector 2078 * 2079 * The read function: dp_dsc_chunk_size_read 2080 * returns dsc chunk size set in the current configuration 2081 * The value is calculated automatically by DSC code 2082 * and depends on slice parameters and bpp target rate 2083 * The return is an integer: 0 or other positive integer 2084 * If 0 then DSC is disabled. 2085 * 2086 * Access it with the following command: 2087 * 2088 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2089 * 2090 * 0 - means that DSC is disabled 2091 */ 2092 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2093 size_t size, loff_t *pos) 2094 { 2095 char *rd_buf = NULL; 2096 char *rd_buf_ptr = NULL; 2097 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2098 struct display_stream_compressor *dsc; 2099 struct dcn_dsc_state dsc_state = {0}; 2100 const uint32_t rd_buf_size = 100; 2101 struct pipe_ctx *pipe_ctx; 2102 ssize_t result = 0; 2103 int i, r, str_len = 30; 2104 2105 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2106 2107 if (!rd_buf) 2108 return -ENOMEM; 2109 2110 rd_buf_ptr = rd_buf; 2111 2112 for (i = 0; i < MAX_PIPES; i++) { 2113 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2114 if (pipe_ctx && pipe_ctx->stream && 2115 pipe_ctx->stream->link == aconnector->dc_link) 2116 break; 2117 } 2118 2119 if (!pipe_ctx) 2120 return -ENXIO; 2121 2122 dsc = pipe_ctx->stream_res.dsc; 2123 if (dsc) 2124 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2125 2126 snprintf(rd_buf_ptr, str_len, 2127 "%d\n", 2128 dsc_state.dsc_chunk_size); 2129 rd_buf_ptr += str_len; 2130 2131 while (size) { 2132 if (*pos >= rd_buf_size) 2133 break; 2134 2135 r = put_user(*(rd_buf + result), buf); 2136 if (r) 2137 return r; /* r = -EFAULT */ 2138 2139 buf += 1; 2140 size -= 1; 2141 *pos += 1; 2142 result += 1; 2143 } 2144 2145 kfree(rd_buf); 2146 return result; 2147 } 2148 2149 /* function: read DSC slice bpg offset on the connector 2150 * 2151 * The read function: dp_dsc_slice_bpg_offset_read 2152 * returns dsc bpg slice offset set in the current configuration 2153 * The value is calculated automatically by DSC code 2154 * and depends on slice parameters and bpp target rate 2155 * The return is an integer: 0 or other positive integer 2156 * If 0 then DSC is disabled. 2157 * 2158 * Access it with the following command: 2159 * 2160 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2161 * 2162 * 0 - means that DSC is disabled 2163 */ 2164 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2165 size_t size, loff_t *pos) 2166 { 2167 char *rd_buf = NULL; 2168 char *rd_buf_ptr = NULL; 2169 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2170 struct display_stream_compressor *dsc; 2171 struct dcn_dsc_state dsc_state = {0}; 2172 const uint32_t rd_buf_size = 100; 2173 struct pipe_ctx *pipe_ctx; 2174 ssize_t result = 0; 2175 int i, r, str_len = 30; 2176 2177 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2178 2179 if (!rd_buf) 2180 return -ENOMEM; 2181 2182 rd_buf_ptr = rd_buf; 2183 2184 for (i = 0; i < MAX_PIPES; i++) { 2185 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2186 if (pipe_ctx && pipe_ctx->stream && 2187 pipe_ctx->stream->link == aconnector->dc_link) 2188 break; 2189 } 2190 2191 if (!pipe_ctx) 2192 return -ENXIO; 2193 2194 dsc = pipe_ctx->stream_res.dsc; 2195 if (dsc) 2196 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2197 2198 snprintf(rd_buf_ptr, str_len, 2199 "%d\n", 2200 dsc_state.dsc_slice_bpg_offset); 2201 rd_buf_ptr += str_len; 2202 2203 while (size) { 2204 if (*pos >= rd_buf_size) 2205 break; 2206 2207 r = put_user(*(rd_buf + result), buf); 2208 if (r) 2209 return r; /* r = -EFAULT */ 2210 2211 buf += 1; 2212 size -= 1; 2213 *pos += 1; 2214 result += 1; 2215 } 2216 2217 kfree(rd_buf); 2218 return result; 2219 } 2220 2221 2222 /* 2223 * function description: Read max_requested_bpc property from the connector 2224 * 2225 * Access it with the following command: 2226 * 2227 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2228 * 2229 */ 2230 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2231 size_t size, loff_t *pos) 2232 { 2233 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2234 struct drm_connector *connector = &aconnector->base; 2235 struct drm_device *dev = connector->dev; 2236 struct dm_connector_state *state; 2237 ssize_t result = 0; 2238 char *rd_buf = NULL; 2239 char *rd_buf_ptr = NULL; 2240 const uint32_t rd_buf_size = 10; 2241 int r; 2242 2243 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2244 2245 if (!rd_buf) 2246 return -ENOMEM; 2247 2248 mutex_lock(&dev->mode_config.mutex); 2249 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2250 2251 if (connector->state == NULL) 2252 goto unlock; 2253 2254 state = to_dm_connector_state(connector->state); 2255 2256 rd_buf_ptr = rd_buf; 2257 snprintf(rd_buf_ptr, rd_buf_size, 2258 "%u\n", 2259 state->base.max_requested_bpc); 2260 2261 while (size) { 2262 if (*pos >= rd_buf_size) 2263 break; 2264 2265 r = put_user(*(rd_buf + result), buf); 2266 if (r) { 2267 result = r; /* r = -EFAULT */ 2268 goto unlock; 2269 } 2270 buf += 1; 2271 size -= 1; 2272 *pos += 1; 2273 result += 1; 2274 } 2275 unlock: 2276 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2277 mutex_unlock(&dev->mode_config.mutex); 2278 kfree(rd_buf); 2279 return result; 2280 } 2281 2282 2283 /* 2284 * function description: Set max_requested_bpc property on the connector 2285 * 2286 * This function will not force the input BPC on connector, it will only 2287 * change the max value. This is equivalent to setting max_bpc through 2288 * xrandr. 2289 * 2290 * The BPC value written must be >= 6 and <= 16. Values outside of this 2291 * range will result in errors. 2292 * 2293 * BPC values: 2294 * 0x6 - 6 BPC 2295 * 0x8 - 8 BPC 2296 * 0xa - 10 BPC 2297 * 0xc - 12 BPC 2298 * 0x10 - 16 BPC 2299 * 2300 * Write the max_bpc in the following way: 2301 * 2302 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2303 * 2304 */ 2305 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2306 size_t size, loff_t *pos) 2307 { 2308 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2309 struct drm_connector *connector = &aconnector->base; 2310 struct dm_connector_state *state; 2311 struct drm_device *dev = connector->dev; 2312 char *wr_buf = NULL; 2313 uint32_t wr_buf_size = 42; 2314 int max_param_num = 1; 2315 long param[1] = {0}; 2316 uint8_t param_nums = 0; 2317 2318 if (size == 0) 2319 return -EINVAL; 2320 2321 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2322 2323 if (!wr_buf) { 2324 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2325 return -ENOSPC; 2326 } 2327 2328 if (parse_write_buffer_into_params(wr_buf, size, 2329 (long *)param, buf, 2330 max_param_num, 2331 ¶m_nums)) { 2332 kfree(wr_buf); 2333 return -EINVAL; 2334 } 2335 2336 if (param_nums <= 0) { 2337 DRM_DEBUG_DRIVER("user data not be read\n"); 2338 kfree(wr_buf); 2339 return -EINVAL; 2340 } 2341 2342 if (param[0] < 6 || param[0] > 16) { 2343 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2344 kfree(wr_buf); 2345 return -EINVAL; 2346 } 2347 2348 mutex_lock(&dev->mode_config.mutex); 2349 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2350 2351 if (connector->state == NULL) 2352 goto unlock; 2353 2354 state = to_dm_connector_state(connector->state); 2355 state->base.max_requested_bpc = param[0]; 2356 unlock: 2357 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2358 mutex_unlock(&dev->mode_config.mutex); 2359 2360 kfree(wr_buf); 2361 return size; 2362 } 2363 2364 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2365 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2366 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2367 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2368 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2369 #ifdef CONFIG_DRM_AMD_DC_HDCP 2370 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2371 #endif 2372 2373 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2374 .owner = THIS_MODULE, 2375 .read = dp_dsc_clock_en_read, 2376 .write = dp_dsc_clock_en_write, 2377 .llseek = default_llseek 2378 }; 2379 2380 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2381 .owner = THIS_MODULE, 2382 .read = dp_dsc_slice_width_read, 2383 .write = dp_dsc_slice_width_write, 2384 .llseek = default_llseek 2385 }; 2386 2387 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2388 .owner = THIS_MODULE, 2389 .read = dp_dsc_slice_height_read, 2390 .write = dp_dsc_slice_height_write, 2391 .llseek = default_llseek 2392 }; 2393 2394 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2395 .owner = THIS_MODULE, 2396 .read = dp_dsc_bits_per_pixel_read, 2397 .write = dp_dsc_bits_per_pixel_write, 2398 .llseek = default_llseek 2399 }; 2400 2401 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2402 .owner = THIS_MODULE, 2403 .read = dp_dsc_pic_width_read, 2404 .llseek = default_llseek 2405 }; 2406 2407 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2408 .owner = THIS_MODULE, 2409 .read = dp_dsc_pic_height_read, 2410 .llseek = default_llseek 2411 }; 2412 2413 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2414 .owner = THIS_MODULE, 2415 .read = dp_dsc_chunk_size_read, 2416 .llseek = default_llseek 2417 }; 2418 2419 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2420 .owner = THIS_MODULE, 2421 .read = dp_dsc_slice_bpg_offset_read, 2422 .llseek = default_llseek 2423 }; 2424 2425 static const struct file_operations trigger_hotplug_debugfs_fops = { 2426 .owner = THIS_MODULE, 2427 .write = trigger_hotplug, 2428 .llseek = default_llseek 2429 }; 2430 2431 static const struct file_operations dp_link_settings_debugfs_fops = { 2432 .owner = THIS_MODULE, 2433 .read = dp_link_settings_read, 2434 .write = dp_link_settings_write, 2435 .llseek = default_llseek 2436 }; 2437 2438 static const struct file_operations dp_phy_settings_debugfs_fop = { 2439 .owner = THIS_MODULE, 2440 .read = dp_phy_settings_read, 2441 .write = dp_phy_settings_write, 2442 .llseek = default_llseek 2443 }; 2444 2445 static const struct file_operations dp_phy_test_pattern_fops = { 2446 .owner = THIS_MODULE, 2447 .write = dp_phy_test_pattern_debugfs_write, 2448 .llseek = default_llseek 2449 }; 2450 2451 static const struct file_operations sdp_message_fops = { 2452 .owner = THIS_MODULE, 2453 .write = dp_sdp_message_debugfs_write, 2454 .llseek = default_llseek 2455 }; 2456 2457 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2458 .owner = THIS_MODULE, 2459 .write = dp_dpcd_address_write, 2460 .llseek = default_llseek 2461 }; 2462 2463 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2464 .owner = THIS_MODULE, 2465 .write = dp_dpcd_size_write, 2466 .llseek = default_llseek 2467 }; 2468 2469 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2470 .owner = THIS_MODULE, 2471 .read = dp_dpcd_data_read, 2472 .write = dp_dpcd_data_write, 2473 .llseek = default_llseek 2474 }; 2475 2476 static const struct file_operations dp_max_bpc_debugfs_fops = { 2477 .owner = THIS_MODULE, 2478 .read = dp_max_bpc_read, 2479 .write = dp_max_bpc_write, 2480 .llseek = default_llseek 2481 }; 2482 2483 static const struct { 2484 char *name; 2485 const struct file_operations *fops; 2486 } dp_debugfs_entries[] = { 2487 {"link_settings", &dp_link_settings_debugfs_fops}, 2488 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2489 {"lttpr_status", &dp_lttpr_status_fops}, 2490 {"test_pattern", &dp_phy_test_pattern_fops}, 2491 #ifdef CONFIG_DRM_AMD_DC_HDCP 2492 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2493 #endif 2494 {"sdp_message", &sdp_message_fops}, 2495 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2496 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2497 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2498 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2499 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2500 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2501 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2502 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2503 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2504 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2505 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2506 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2507 {"max_bpc", &dp_max_bpc_debugfs_fops} 2508 }; 2509 2510 #ifdef CONFIG_DRM_AMD_DC_HDCP 2511 static const struct { 2512 char *name; 2513 const struct file_operations *fops; 2514 } hdmi_debugfs_entries[] = { 2515 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2516 }; 2517 #endif 2518 /* 2519 * Force YUV420 output if available from the given mode 2520 */ 2521 static int force_yuv420_output_set(void *data, u64 val) 2522 { 2523 struct amdgpu_dm_connector *connector = data; 2524 2525 connector->force_yuv420_output = (bool)val; 2526 2527 return 0; 2528 } 2529 2530 /* 2531 * Check if YUV420 is forced when available from the given mode 2532 */ 2533 static int force_yuv420_output_get(void *data, u64 *val) 2534 { 2535 struct amdgpu_dm_connector *connector = data; 2536 2537 *val = connector->force_yuv420_output; 2538 2539 return 0; 2540 } 2541 2542 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2543 force_yuv420_output_set, "%llu\n"); 2544 2545 /* 2546 * Read PSR state 2547 */ 2548 static int psr_get(void *data, u64 *val) 2549 { 2550 struct amdgpu_dm_connector *connector = data; 2551 struct dc_link *link = connector->dc_link; 2552 enum dc_psr_state state = PSR_STATE0; 2553 2554 dc_link_get_psr_state(link, &state); 2555 2556 *val = state; 2557 2558 return 0; 2559 } 2560 2561 /* 2562 * Set dmcub trace event IRQ enable or disable. 2563 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2564 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2565 */ 2566 static int dmcub_trace_event_state_set(void *data, u64 val) 2567 { 2568 struct amdgpu_device *adev = data; 2569 2570 if (val == 1 || val == 0) { 2571 dc_dmub_trace_event_control(adev->dm.dc, val); 2572 adev->dm.dmcub_trace_event_en = (bool)val; 2573 } else 2574 return 0; 2575 2576 return 0; 2577 } 2578 2579 /* 2580 * The interface doesn't need get function, so it will return the 2581 * value of zero 2582 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2583 */ 2584 static int dmcub_trace_event_state_get(void *data, u64 *val) 2585 { 2586 struct amdgpu_device *adev = data; 2587 2588 *val = adev->dm.dmcub_trace_event_en; 2589 return 0; 2590 } 2591 2592 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2593 dmcub_trace_event_state_set, "%llu\n"); 2594 2595 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2596 2597 static const struct { 2598 char *name; 2599 const struct file_operations *fops; 2600 } connector_debugfs_entries[] = { 2601 {"force_yuv420_output", &force_yuv420_output_fops}, 2602 {"output_bpc", &output_bpc_fops}, 2603 {"trigger_hotplug", &trigger_hotplug_debugfs_fops} 2604 }; 2605 2606 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2607 { 2608 int i; 2609 struct dentry *dir = connector->base.debugfs_entry; 2610 2611 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2612 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2613 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2614 debugfs_create_file(dp_debugfs_entries[i].name, 2615 0644, dir, connector, 2616 dp_debugfs_entries[i].fops); 2617 } 2618 } 2619 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 2620 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2621 2622 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2623 debugfs_create_file(connector_debugfs_entries[i].name, 2624 0644, dir, connector, 2625 connector_debugfs_entries[i].fops); 2626 } 2627 2628 connector->debugfs_dpcd_address = 0; 2629 connector->debugfs_dpcd_size = 0; 2630 2631 #ifdef CONFIG_DRM_AMD_DC_HDCP 2632 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2633 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2634 debugfs_create_file(hdmi_debugfs_entries[i].name, 2635 0644, dir, connector, 2636 hdmi_debugfs_entries[i].fops); 2637 } 2638 } 2639 #endif 2640 } 2641 2642 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2643 /* 2644 * Set crc window coordinate x start 2645 */ 2646 static int crc_win_x_start_set(void *data, u64 val) 2647 { 2648 struct drm_crtc *crtc = data; 2649 struct drm_device *drm_dev = crtc->dev; 2650 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2651 2652 spin_lock_irq(&drm_dev->event_lock); 2653 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2654 acrtc->dm_irq_params.crc_window.update_win = false; 2655 spin_unlock_irq(&drm_dev->event_lock); 2656 2657 return 0; 2658 } 2659 2660 /* 2661 * Get crc window coordinate x start 2662 */ 2663 static int crc_win_x_start_get(void *data, u64 *val) 2664 { 2665 struct drm_crtc *crtc = data; 2666 struct drm_device *drm_dev = crtc->dev; 2667 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2668 2669 spin_lock_irq(&drm_dev->event_lock); 2670 *val = acrtc->dm_irq_params.crc_window.x_start; 2671 spin_unlock_irq(&drm_dev->event_lock); 2672 2673 return 0; 2674 } 2675 2676 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 2677 crc_win_x_start_set, "%llu\n"); 2678 2679 2680 /* 2681 * Set crc window coordinate y start 2682 */ 2683 static int crc_win_y_start_set(void *data, u64 val) 2684 { 2685 struct drm_crtc *crtc = data; 2686 struct drm_device *drm_dev = crtc->dev; 2687 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2688 2689 spin_lock_irq(&drm_dev->event_lock); 2690 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 2691 acrtc->dm_irq_params.crc_window.update_win = false; 2692 spin_unlock_irq(&drm_dev->event_lock); 2693 2694 return 0; 2695 } 2696 2697 /* 2698 * Get crc window coordinate y start 2699 */ 2700 static int crc_win_y_start_get(void *data, u64 *val) 2701 { 2702 struct drm_crtc *crtc = data; 2703 struct drm_device *drm_dev = crtc->dev; 2704 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2705 2706 spin_lock_irq(&drm_dev->event_lock); 2707 *val = acrtc->dm_irq_params.crc_window.y_start; 2708 spin_unlock_irq(&drm_dev->event_lock); 2709 2710 return 0; 2711 } 2712 2713 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 2714 crc_win_y_start_set, "%llu\n"); 2715 2716 /* 2717 * Set crc window coordinate x end 2718 */ 2719 static int crc_win_x_end_set(void *data, u64 val) 2720 { 2721 struct drm_crtc *crtc = data; 2722 struct drm_device *drm_dev = crtc->dev; 2723 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2724 2725 spin_lock_irq(&drm_dev->event_lock); 2726 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 2727 acrtc->dm_irq_params.crc_window.update_win = false; 2728 spin_unlock_irq(&drm_dev->event_lock); 2729 2730 return 0; 2731 } 2732 2733 /* 2734 * Get crc window coordinate x end 2735 */ 2736 static int crc_win_x_end_get(void *data, u64 *val) 2737 { 2738 struct drm_crtc *crtc = data; 2739 struct drm_device *drm_dev = crtc->dev; 2740 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2741 2742 spin_lock_irq(&drm_dev->event_lock); 2743 *val = acrtc->dm_irq_params.crc_window.x_end; 2744 spin_unlock_irq(&drm_dev->event_lock); 2745 2746 return 0; 2747 } 2748 2749 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 2750 crc_win_x_end_set, "%llu\n"); 2751 2752 /* 2753 * Set crc window coordinate y end 2754 */ 2755 static int crc_win_y_end_set(void *data, u64 val) 2756 { 2757 struct drm_crtc *crtc = data; 2758 struct drm_device *drm_dev = crtc->dev; 2759 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2760 2761 spin_lock_irq(&drm_dev->event_lock); 2762 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 2763 acrtc->dm_irq_params.crc_window.update_win = false; 2764 spin_unlock_irq(&drm_dev->event_lock); 2765 2766 return 0; 2767 } 2768 2769 /* 2770 * Get crc window coordinate y end 2771 */ 2772 static int crc_win_y_end_get(void *data, u64 *val) 2773 { 2774 struct drm_crtc *crtc = data; 2775 struct drm_device *drm_dev = crtc->dev; 2776 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2777 2778 spin_lock_irq(&drm_dev->event_lock); 2779 *val = acrtc->dm_irq_params.crc_window.y_end; 2780 spin_unlock_irq(&drm_dev->event_lock); 2781 2782 return 0; 2783 } 2784 2785 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 2786 crc_win_y_end_set, "%llu\n"); 2787 /* 2788 * Trigger to commit crc window 2789 */ 2790 static int crc_win_update_set(void *data, u64 val) 2791 { 2792 struct drm_crtc *new_crtc = data; 2793 struct drm_crtc *old_crtc = NULL; 2794 struct amdgpu_crtc *new_acrtc, *old_acrtc; 2795 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 2796 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 2797 2798 if (val) { 2799 spin_lock_irq(&adev_to_drm(adev)->event_lock); 2800 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 2801 if (crc_rd_wrk && crc_rd_wrk->crtc) { 2802 old_crtc = crc_rd_wrk->crtc; 2803 old_acrtc = to_amdgpu_crtc(old_crtc); 2804 } 2805 new_acrtc = to_amdgpu_crtc(new_crtc); 2806 2807 if (old_crtc && old_crtc != new_crtc) { 2808 old_acrtc->dm_irq_params.crc_window.activated = false; 2809 old_acrtc->dm_irq_params.crc_window.update_win = false; 2810 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2811 2812 new_acrtc->dm_irq_params.crc_window.activated = true; 2813 new_acrtc->dm_irq_params.crc_window.update_win = true; 2814 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2815 crc_rd_wrk->crtc = new_crtc; 2816 } else { 2817 new_acrtc->dm_irq_params.crc_window.activated = true; 2818 new_acrtc->dm_irq_params.crc_window.update_win = true; 2819 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2820 crc_rd_wrk->crtc = new_crtc; 2821 } 2822 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 2823 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 2824 } 2825 2826 return 0; 2827 } 2828 2829 /* 2830 * Get crc window update flag 2831 */ 2832 static int crc_win_update_get(void *data, u64 *val) 2833 { 2834 *val = 0; 2835 return 0; 2836 } 2837 2838 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 2839 crc_win_update_set, "%llu\n"); 2840 2841 void crtc_debugfs_init(struct drm_crtc *crtc) 2842 { 2843 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 2844 2845 if (!dir) 2846 return; 2847 2848 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 2849 &crc_win_x_start_fops); 2850 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 2851 &crc_win_y_start_fops); 2852 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 2853 &crc_win_x_end_fops); 2854 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 2855 &crc_win_y_end_fops); 2856 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 2857 &crc_win_update_fops); 2858 2859 } 2860 #endif 2861 /* 2862 * Writes DTN log state to the user supplied buffer. 2863 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2864 */ 2865 static ssize_t dtn_log_read( 2866 struct file *f, 2867 char __user *buf, 2868 size_t size, 2869 loff_t *pos) 2870 { 2871 struct amdgpu_device *adev = file_inode(f)->i_private; 2872 struct dc *dc = adev->dm.dc; 2873 struct dc_log_buffer_ctx log_ctx = { 0 }; 2874 ssize_t result = 0; 2875 2876 if (!buf || !size) 2877 return -EINVAL; 2878 2879 if (!dc->hwss.log_hw_state) 2880 return 0; 2881 2882 dc->hwss.log_hw_state(dc, &log_ctx); 2883 2884 if (*pos < log_ctx.pos) { 2885 size_t to_copy = log_ctx.pos - *pos; 2886 2887 to_copy = min(to_copy, size); 2888 2889 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 2890 *pos += to_copy; 2891 result = to_copy; 2892 } 2893 } 2894 2895 kfree(log_ctx.buf); 2896 2897 return result; 2898 } 2899 2900 /* 2901 * Writes DTN log state to dmesg when triggered via a write. 2902 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2903 */ 2904 static ssize_t dtn_log_write( 2905 struct file *f, 2906 const char __user *buf, 2907 size_t size, 2908 loff_t *pos) 2909 { 2910 struct amdgpu_device *adev = file_inode(f)->i_private; 2911 struct dc *dc = adev->dm.dc; 2912 2913 /* Write triggers log output via dmesg. */ 2914 if (size == 0) 2915 return 0; 2916 2917 if (dc->hwss.log_hw_state) 2918 dc->hwss.log_hw_state(dc, NULL); 2919 2920 return size; 2921 } 2922 2923 /* 2924 * Backlight at this moment. Read only. 2925 * As written to display, taking ABM and backlight lut into account. 2926 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2927 */ 2928 static int current_backlight_show(struct seq_file *m, void *unused) 2929 { 2930 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2931 struct amdgpu_display_manager *dm = &adev->dm; 2932 2933 unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link); 2934 2935 seq_printf(m, "0x%x\n", backlight); 2936 return 0; 2937 } 2938 2939 /* 2940 * Backlight value that is being approached. Read only. 2941 * As written to display, taking ABM and backlight lut into account. 2942 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2943 */ 2944 static int target_backlight_show(struct seq_file *m, void *unused) 2945 { 2946 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2947 struct amdgpu_display_manager *dm = &adev->dm; 2948 2949 unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link); 2950 2951 seq_printf(m, "0x%x\n", backlight); 2952 return 0; 2953 } 2954 2955 static int mst_topo_show(struct seq_file *m, void *unused) 2956 { 2957 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2958 struct drm_device *dev = adev_to_drm(adev); 2959 struct drm_connector *connector; 2960 struct drm_connector_list_iter conn_iter; 2961 struct amdgpu_dm_connector *aconnector; 2962 2963 drm_connector_list_iter_begin(dev, &conn_iter); 2964 drm_for_each_connector_iter(connector, &conn_iter) { 2965 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 2966 continue; 2967 2968 aconnector = to_amdgpu_dm_connector(connector); 2969 2970 /* Ensure we're only dumping the topology of a root mst node */ 2971 if (!aconnector->mst_mgr.mst_state) 2972 continue; 2973 2974 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 2975 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 2976 } 2977 drm_connector_list_iter_end(&conn_iter); 2978 2979 return 0; 2980 } 2981 2982 /* 2983 * Sets trigger hpd for MST topologies. 2984 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 2985 * All topologies will be disconnected if val of 0 is set . 2986 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 2987 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 2988 */ 2989 static int trigger_hpd_mst_set(void *data, u64 val) 2990 { 2991 struct amdgpu_device *adev = data; 2992 struct drm_device *dev = adev_to_drm(adev); 2993 struct drm_connector_list_iter iter; 2994 struct amdgpu_dm_connector *aconnector; 2995 struct drm_connector *connector; 2996 struct dc_link *link = NULL; 2997 2998 if (val == 1) { 2999 drm_connector_list_iter_begin(dev, &iter); 3000 drm_for_each_connector_iter(connector, &iter) { 3001 aconnector = to_amdgpu_dm_connector(connector); 3002 if (aconnector->dc_link->type == dc_connection_mst_branch && 3003 aconnector->mst_mgr.aux) { 3004 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3005 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3006 } 3007 } 3008 } else if (val == 0) { 3009 drm_connector_list_iter_begin(dev, &iter); 3010 drm_for_each_connector_iter(connector, &iter) { 3011 aconnector = to_amdgpu_dm_connector(connector); 3012 if (!aconnector->dc_link) 3013 continue; 3014 3015 if (!aconnector->mst_port) 3016 continue; 3017 3018 link = aconnector->dc_link; 3019 dp_receiver_power_ctrl(link, false); 3020 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3021 link->mst_stream_alloc_table.stream_count = 0; 3022 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3023 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3024 } 3025 } else { 3026 return 0; 3027 } 3028 drm_kms_helper_hotplug_event(dev); 3029 3030 return 0; 3031 } 3032 3033 /* 3034 * The interface doesn't need get function, so it will return the 3035 * value of zero 3036 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3037 */ 3038 static int trigger_hpd_mst_get(void *data, u64 *val) 3039 { 3040 *val = 0; 3041 return 0; 3042 } 3043 3044 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3045 trigger_hpd_mst_set, "%llu\n"); 3046 3047 3048 /* 3049 * Sets the force_timing_sync debug option from the given string. 3050 * All connected displays will be force synchronized immediately. 3051 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3052 */ 3053 static int force_timing_sync_set(void *data, u64 val) 3054 { 3055 struct amdgpu_device *adev = data; 3056 3057 adev->dm.force_timing_sync = (bool)val; 3058 3059 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3060 3061 return 0; 3062 } 3063 3064 /* 3065 * Gets the force_timing_sync debug option value into the given buffer. 3066 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3067 */ 3068 static int force_timing_sync_get(void *data, u64 *val) 3069 { 3070 struct amdgpu_device *adev = data; 3071 3072 *val = adev->dm.force_timing_sync; 3073 3074 return 0; 3075 } 3076 3077 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3078 force_timing_sync_set, "%llu\n"); 3079 3080 3081 /* 3082 * Disables all HPD and HPD RX interrupt handling in the 3083 * driver when set to 1. Default is 0. 3084 */ 3085 static int disable_hpd_set(void *data, u64 val) 3086 { 3087 struct amdgpu_device *adev = data; 3088 3089 adev->dm.disable_hpd_irq = (bool)val; 3090 3091 return 0; 3092 } 3093 3094 3095 /* 3096 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3097 * 0 otherwise. 3098 */ 3099 static int disable_hpd_get(void *data, u64 *val) 3100 { 3101 struct amdgpu_device *adev = data; 3102 3103 *val = adev->dm.disable_hpd_irq; 3104 3105 return 0; 3106 } 3107 3108 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3109 disable_hpd_set, "%llu\n"); 3110 3111 /* 3112 * Sets the DC visual confirm debug option from the given string. 3113 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3114 */ 3115 static int visual_confirm_set(void *data, u64 val) 3116 { 3117 struct amdgpu_device *adev = data; 3118 3119 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3120 3121 return 0; 3122 } 3123 3124 /* 3125 * Reads the DC visual confirm debug option value into the given buffer. 3126 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3127 */ 3128 static int visual_confirm_get(void *data, u64 *val) 3129 { 3130 struct amdgpu_device *adev = data; 3131 3132 *val = adev->dm.dc->debug.visual_confirm; 3133 3134 return 0; 3135 } 3136 3137 DEFINE_SHOW_ATTRIBUTE(current_backlight); 3138 DEFINE_SHOW_ATTRIBUTE(target_backlight); 3139 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3140 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3141 visual_confirm_set, "%llu\n"); 3142 3143 /* 3144 * Dumps the DCC_EN bit for each pipe. 3145 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3146 */ 3147 static ssize_t dcc_en_bits_read( 3148 struct file *f, 3149 char __user *buf, 3150 size_t size, 3151 loff_t *pos) 3152 { 3153 struct amdgpu_device *adev = file_inode(f)->i_private; 3154 struct dc *dc = adev->dm.dc; 3155 char *rd_buf = NULL; 3156 const uint32_t rd_buf_size = 32; 3157 uint32_t result = 0; 3158 int offset = 0; 3159 int num_pipes = dc->res_pool->pipe_count; 3160 int *dcc_en_bits; 3161 int i, r; 3162 3163 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3164 if (!dcc_en_bits) 3165 return -ENOMEM; 3166 3167 if (!dc->hwss.get_dcc_en_bits) { 3168 kfree(dcc_en_bits); 3169 return 0; 3170 } 3171 3172 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3173 3174 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3175 if (!rd_buf) 3176 return -ENOMEM; 3177 3178 for (i = 0; i < num_pipes; i++) 3179 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3180 "%d ", dcc_en_bits[i]); 3181 rd_buf[strlen(rd_buf)] = '\n'; 3182 3183 kfree(dcc_en_bits); 3184 3185 while (size) { 3186 if (*pos >= rd_buf_size) 3187 break; 3188 r = put_user(*(rd_buf + result), buf); 3189 if (r) 3190 return r; /* r = -EFAULT */ 3191 buf += 1; 3192 size -= 1; 3193 *pos += 1; 3194 result += 1; 3195 } 3196 3197 kfree(rd_buf); 3198 return result; 3199 } 3200 3201 void dtn_debugfs_init(struct amdgpu_device *adev) 3202 { 3203 static const struct file_operations dtn_log_fops = { 3204 .owner = THIS_MODULE, 3205 .read = dtn_log_read, 3206 .write = dtn_log_write, 3207 .llseek = default_llseek 3208 }; 3209 static const struct file_operations dcc_en_bits_fops = { 3210 .owner = THIS_MODULE, 3211 .read = dcc_en_bits_read, 3212 .llseek = default_llseek 3213 }; 3214 3215 struct drm_minor *minor = adev_to_drm(adev)->primary; 3216 struct dentry *root = minor->debugfs_root; 3217 3218 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, 3219 root, adev, ¤t_backlight_fops); 3220 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, 3221 root, adev, &target_backlight_fops); 3222 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3223 adev, &mst_topo_fops); 3224 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3225 &dtn_log_fops); 3226 3227 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3228 &visual_confirm_fops); 3229 3230 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3231 adev, &dmub_tracebuffer_fops); 3232 3233 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3234 adev, &dmub_fw_state_fops); 3235 3236 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3237 adev, &force_timing_sync_ops); 3238 3239 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3240 adev, &dmcub_trace_event_state_fops); 3241 3242 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3243 adev, &trigger_hpd_mst_ops); 3244 3245 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3246 &dcc_en_bits_fops); 3247 3248 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3249 &disable_hpd_ops); 3250 3251 } 3252