1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/uaccess.h> 27 28 #include "dc.h" 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "amdgpu_dm_debugfs.h" 32 #include "dm_helpers.h" 33 #include "dmub/dmub_srv.h" 34 #include "resource.h" 35 #include "dsc.h" 36 #include "dc_link_dp.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 40 struct dmub_debugfs_trace_header { 41 uint32_t entry_count; 42 uint32_t reserved[3]; 43 }; 44 45 struct dmub_debugfs_trace_entry { 46 uint32_t trace_code; 47 uint32_t tick_count; 48 uint32_t param0; 49 uint32_t param1; 50 }; 51 52 static inline const char *yesno(bool v) 53 { 54 return v ? "yes" : "no"; 55 } 56 57 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 58 * 59 * Function takes in attributes passed to debugfs write entry 60 * and writes into param array. 61 * The user passes max_param_num to identify maximum number of 62 * parameters that could be parsed. 63 * 64 */ 65 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 66 long *param, const char __user *buf, 67 int max_param_num, 68 uint8_t *param_nums) 69 { 70 char *wr_buf_ptr = NULL; 71 uint32_t wr_buf_count = 0; 72 int r; 73 char *sub_str = NULL; 74 const char delimiter[3] = {' ', '\n', '\0'}; 75 uint8_t param_index = 0; 76 77 *param_nums = 0; 78 79 wr_buf_ptr = wr_buf; 80 81 /* r is bytes not be copied */ 82 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 83 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 84 return -EFAULT; 85 } 86 87 /* check number of parameters. isspace could not differ space and \n */ 88 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 89 /* skip space*/ 90 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 91 wr_buf_ptr++; 92 wr_buf_count++; 93 } 94 95 if (wr_buf_count == wr_buf_size) 96 break; 97 98 /* skip non-space*/ 99 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 100 wr_buf_ptr++; 101 wr_buf_count++; 102 } 103 104 (*param_nums)++; 105 106 if (wr_buf_count == wr_buf_size) 107 break; 108 } 109 110 if (*param_nums > max_param_num) 111 *param_nums = max_param_num; 112 113 wr_buf_ptr = wr_buf; /* reset buf pointer */ 114 wr_buf_count = 0; /* number of char already checked */ 115 116 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 117 wr_buf_ptr++; 118 wr_buf_count++; 119 } 120 121 while (param_index < *param_nums) { 122 /* after strsep, wr_buf_ptr will be moved to after space */ 123 sub_str = strsep(&wr_buf_ptr, delimiter); 124 125 r = kstrtol(sub_str, 16, &(param[param_index])); 126 127 if (r) 128 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 129 130 param_index++; 131 } 132 133 return 0; 134 } 135 136 /* function description 137 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 138 * 139 * valid lane count value: 1, 2, 4 140 * valid link rate value: 141 * 06h = 1.62Gbps per lane 142 * 0Ah = 2.7Gbps per lane 143 * 0Ch = 3.24Gbps per lane 144 * 14h = 5.4Gbps per lane 145 * 1Eh = 8.1Gbps per lane 146 * 147 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 148 * 149 * --- to get dp configuration 150 * 151 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 152 * 153 * It will list current, verified, reported, preferred dp configuration. 154 * current -- for current video mode 155 * verified --- maximum configuration which pass link training 156 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 157 * preferred --- user force settings 158 * 159 * --- set (or force) dp configuration 160 * 161 * echo <lane_count> <link_rate> > link_settings 162 * 163 * for example, to force to 2 lane, 2.7GHz, 164 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 165 * 166 * spread_spectrum could not be changed dynamically. 167 * 168 * in case invalid lane count, link rate are force, no hw programming will be 169 * done. please check link settings after force operation to see if HW get 170 * programming. 171 * 172 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 173 * 174 * check current and preferred settings. 175 * 176 */ 177 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 178 size_t size, loff_t *pos) 179 { 180 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 181 struct dc_link *link = connector->dc_link; 182 char *rd_buf = NULL; 183 char *rd_buf_ptr = NULL; 184 const uint32_t rd_buf_size = 100; 185 uint32_t result = 0; 186 uint8_t str_len = 0; 187 int r; 188 189 if (*pos & 3 || size & 3) 190 return -EINVAL; 191 192 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 193 if (!rd_buf) 194 return 0; 195 196 rd_buf_ptr = rd_buf; 197 198 str_len = strlen("Current: %d 0x%x %d "); 199 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 200 link->cur_link_settings.lane_count, 201 link->cur_link_settings.link_rate, 202 link->cur_link_settings.link_spread); 203 rd_buf_ptr += str_len; 204 205 str_len = strlen("Verified: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 207 link->verified_link_cap.lane_count, 208 link->verified_link_cap.link_rate, 209 link->verified_link_cap.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Reported: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 214 link->reported_link_cap.lane_count, 215 link->reported_link_cap.link_rate, 216 link->reported_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Preferred: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 221 link->preferred_link_setting.lane_count, 222 link->preferred_link_setting.link_rate, 223 link->preferred_link_setting.link_spread); 224 225 while (size) { 226 if (*pos >= rd_buf_size) 227 break; 228 229 r = put_user(*(rd_buf + result), buf); 230 if (r) 231 return r; /* r = -EFAULT */ 232 233 buf += 1; 234 size -= 1; 235 *pos += 1; 236 result += 1; 237 } 238 239 kfree(rd_buf); 240 return result; 241 } 242 243 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 244 size_t size, loff_t *pos) 245 { 246 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 247 struct dc_link *link = connector->dc_link; 248 struct dc *dc = (struct dc *)link->dc; 249 struct dc_link_settings prefer_link_settings; 250 char *wr_buf = NULL; 251 const uint32_t wr_buf_size = 40; 252 /* 0: lane_count; 1: link_rate */ 253 int max_param_num = 2; 254 uint8_t param_nums = 0; 255 long param[2]; 256 bool valid_input = true; 257 258 if (size == 0) 259 return -EINVAL; 260 261 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 262 if (!wr_buf) 263 return -ENOSPC; 264 265 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 266 (long *)param, buf, 267 max_param_num, 268 ¶m_nums)) { 269 kfree(wr_buf); 270 return -EINVAL; 271 } 272 273 if (param_nums <= 0) { 274 kfree(wr_buf); 275 DRM_DEBUG_DRIVER("user data not be read\n"); 276 return -EINVAL; 277 } 278 279 switch (param[0]) { 280 case LANE_COUNT_ONE: 281 case LANE_COUNT_TWO: 282 case LANE_COUNT_FOUR: 283 break; 284 default: 285 valid_input = false; 286 break; 287 } 288 289 switch (param[1]) { 290 case LINK_RATE_LOW: 291 case LINK_RATE_HIGH: 292 case LINK_RATE_RBR2: 293 case LINK_RATE_HIGH2: 294 case LINK_RATE_HIGH3: 295 #if defined(CONFIG_DRM_AMD_DC_DCN) 296 case LINK_RATE_UHBR10: 297 #endif 298 break; 299 default: 300 valid_input = false; 301 break; 302 } 303 304 if (!valid_input) { 305 kfree(wr_buf); 306 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 307 return size; 308 } 309 310 /* save user force lane_count, link_rate to preferred settings 311 * spread spectrum will not be changed 312 */ 313 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 314 prefer_link_settings.use_link_rate_set = false; 315 prefer_link_settings.lane_count = param[0]; 316 prefer_link_settings.link_rate = param[1]; 317 318 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 319 320 kfree(wr_buf); 321 return size; 322 } 323 324 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 325 * post-cursor2 (defined by VESA DP specification) 326 * 327 * valid values 328 * voltage swing: 0,1,2,3 329 * pre-emphasis : 0,1,2,3 330 * post cursor2 : 0,1,2,3 331 * 332 * 333 * how to use this debugfs 334 * 335 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 336 * 337 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 338 * 339 * To figure out which DP-x is the display for DP to be check, 340 * cd DP-x 341 * ls -ll 342 * There should be debugfs file, like link_settings, phy_settings. 343 * cat link_settings 344 * from lane_count, link_rate to figure which DP-x is for display to be worked 345 * on 346 * 347 * To get current DP PHY settings, 348 * cat phy_settings 349 * 350 * To change DP PHY settings, 351 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 352 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 353 * 0, 354 * echo 2 3 0 > phy_settings 355 * 356 * To check if change be applied, get current phy settings by 357 * cat phy_settings 358 * 359 * In case invalid values are set by user, like 360 * echo 1 4 0 > phy_settings 361 * 362 * HW will NOT be programmed by these settings. 363 * cat phy_settings will show the previous valid settings. 364 */ 365 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 366 size_t size, loff_t *pos) 367 { 368 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 369 struct dc_link *link = connector->dc_link; 370 char *rd_buf = NULL; 371 const uint32_t rd_buf_size = 20; 372 uint32_t result = 0; 373 int r; 374 375 if (*pos & 3 || size & 3) 376 return -EINVAL; 377 378 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 379 if (!rd_buf) 380 return -EINVAL; 381 382 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 383 link->cur_lane_setting[0].VOLTAGE_SWING, 384 link->cur_lane_setting[0].PRE_EMPHASIS, 385 link->cur_lane_setting[0].POST_CURSOR2); 386 387 while (size) { 388 if (*pos >= rd_buf_size) 389 break; 390 391 r = put_user((*(rd_buf + result)), buf); 392 if (r) 393 return r; /* r = -EFAULT */ 394 395 buf += 1; 396 size -= 1; 397 *pos += 1; 398 result += 1; 399 } 400 401 kfree(rd_buf); 402 return result; 403 } 404 405 static int dp_lttpr_status_show(struct seq_file *m, void *d) 406 { 407 char *data; 408 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 409 struct dc_link *link = connector->dc_link; 410 uint32_t read_size = 1; 411 uint8_t repeater_count = 0; 412 413 data = kzalloc(read_size, GFP_KERNEL); 414 if (!data) 415 return 0; 416 417 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 418 419 switch ((uint8_t)*data) { 420 case 0x80: 421 repeater_count = 1; 422 break; 423 case 0x40: 424 repeater_count = 2; 425 break; 426 case 0x20: 427 repeater_count = 3; 428 break; 429 case 0x10: 430 repeater_count = 4; 431 break; 432 case 0x8: 433 repeater_count = 5; 434 break; 435 case 0x4: 436 repeater_count = 6; 437 break; 438 case 0x2: 439 repeater_count = 7; 440 break; 441 case 0x1: 442 repeater_count = 8; 443 break; 444 case 0x0: 445 repeater_count = 0; 446 break; 447 default: 448 repeater_count = (uint8_t)*data; 449 break; 450 } 451 452 seq_printf(m, "phy repeater count: %d\n", repeater_count); 453 454 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 455 456 if ((uint8_t)*data == 0x55) 457 seq_printf(m, "phy repeater mode: transparent\n"); 458 else if ((uint8_t)*data == 0xAA) 459 seq_printf(m, "phy repeater mode: non-transparent\n"); 460 else if ((uint8_t)*data == 0x00) 461 seq_printf(m, "phy repeater mode: non lttpr\n"); 462 else 463 seq_printf(m, "phy repeater mode: read error\n"); 464 465 kfree(data); 466 return 0; 467 } 468 469 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 470 size_t size, loff_t *pos) 471 { 472 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 473 struct dc_link *link = connector->dc_link; 474 struct dc *dc = (struct dc *)link->dc; 475 char *wr_buf = NULL; 476 uint32_t wr_buf_size = 40; 477 long param[3]; 478 bool use_prefer_link_setting; 479 struct link_training_settings link_lane_settings; 480 int max_param_num = 3; 481 uint8_t param_nums = 0; 482 int r = 0; 483 484 485 if (size == 0) 486 return -EINVAL; 487 488 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 489 if (!wr_buf) 490 return -ENOSPC; 491 492 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 493 (long *)param, buf, 494 max_param_num, 495 ¶m_nums)) { 496 kfree(wr_buf); 497 return -EINVAL; 498 } 499 500 if (param_nums <= 0) { 501 kfree(wr_buf); 502 DRM_DEBUG_DRIVER("user data not be read\n"); 503 return -EINVAL; 504 } 505 506 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 507 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 508 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 509 kfree(wr_buf); 510 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 511 return size; 512 } 513 514 /* get link settings: lane count, link rate */ 515 use_prefer_link_setting = 516 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 517 (link->test_pattern_enabled)); 518 519 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 520 521 if (use_prefer_link_setting) { 522 link_lane_settings.link_settings.lane_count = 523 link->preferred_link_setting.lane_count; 524 link_lane_settings.link_settings.link_rate = 525 link->preferred_link_setting.link_rate; 526 link_lane_settings.link_settings.link_spread = 527 link->preferred_link_setting.link_spread; 528 } else { 529 link_lane_settings.link_settings.lane_count = 530 link->cur_link_settings.lane_count; 531 link_lane_settings.link_settings.link_rate = 532 link->cur_link_settings.link_rate; 533 link_lane_settings.link_settings.link_spread = 534 link->cur_link_settings.link_spread; 535 } 536 537 /* apply phy settings from user */ 538 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 539 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 540 (enum dc_voltage_swing) (param[0]); 541 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 542 (enum dc_pre_emphasis) (param[1]); 543 link_lane_settings.lane_settings[r].POST_CURSOR2 = 544 (enum dc_post_cursor2) (param[2]); 545 } 546 547 /* program ASIC registers and DPCD registers */ 548 dc_link_set_drive_settings(dc, &link_lane_settings, link); 549 550 kfree(wr_buf); 551 return size; 552 } 553 554 /* function description 555 * 556 * set PHY layer or Link layer test pattern 557 * PHY test pattern is used for PHY SI check. 558 * Link layer test will not affect PHY SI. 559 * 560 * Reset Test Pattern: 561 * 0 = DP_TEST_PATTERN_VIDEO_MODE 562 * 563 * PHY test pattern supported: 564 * 1 = DP_TEST_PATTERN_D102 565 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 566 * 3 = DP_TEST_PATTERN_PRBS7 567 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 568 * 5 = DP_TEST_PATTERN_CP2520_1 569 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 570 * 7 = DP_TEST_PATTERN_CP2520_3 571 * 572 * DP PHY Link Training Patterns 573 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 574 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 575 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 576 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 577 * 578 * DP Link Layer Test pattern 579 * c = DP_TEST_PATTERN_COLOR_SQUARES 580 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 581 * e = DP_TEST_PATTERN_VERTICAL_BARS 582 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 583 * 10= DP_TEST_PATTERN_COLOR_RAMP 584 * 585 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 586 * 587 * --- set test pattern 588 * echo <test pattern #> > test_pattern 589 * 590 * If test pattern # is not supported, NO HW programming will be done. 591 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 592 * for the user pattern. input 10 bytes data are separated by space 593 * 594 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 595 * 596 * --- reset test pattern 597 * echo 0 > test_pattern 598 * 599 * --- HPD detection is disabled when set PHY test pattern 600 * 601 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 602 * is disable. User could unplug DP display from DP connected and plug scope to 603 * check test pattern PHY SI. 604 * If there is need unplug scope and plug DP display back, do steps below: 605 * echo 0 > phy_test_pattern 606 * unplug scope 607 * plug DP display. 608 * 609 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 610 * driver could detect "unplug scope" and "plug DP display" 611 */ 612 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 613 size_t size, loff_t *pos) 614 { 615 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 616 struct dc_link *link = connector->dc_link; 617 char *wr_buf = NULL; 618 uint32_t wr_buf_size = 100; 619 long param[11] = {0x0}; 620 int max_param_num = 11; 621 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 622 bool disable_hpd = false; 623 bool valid_test_pattern = false; 624 uint8_t param_nums = 0; 625 /* init with default 80bit custom pattern */ 626 uint8_t custom_pattern[10] = { 627 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 628 0x1f, 0x7c, 0xf0, 0xc1, 0x07 629 }; 630 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 631 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 632 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 633 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 634 struct link_training_settings link_training_settings; 635 int i; 636 637 if (size == 0) 638 return -EINVAL; 639 640 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 641 if (!wr_buf) 642 return -ENOSPC; 643 644 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 645 (long *)param, buf, 646 max_param_num, 647 ¶m_nums)) { 648 kfree(wr_buf); 649 return -EINVAL; 650 } 651 652 if (param_nums <= 0) { 653 kfree(wr_buf); 654 DRM_DEBUG_DRIVER("user data not be read\n"); 655 return -EINVAL; 656 } 657 658 659 test_pattern = param[0]; 660 661 switch (test_pattern) { 662 case DP_TEST_PATTERN_VIDEO_MODE: 663 case DP_TEST_PATTERN_COLOR_SQUARES: 664 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 665 case DP_TEST_PATTERN_VERTICAL_BARS: 666 case DP_TEST_PATTERN_HORIZONTAL_BARS: 667 case DP_TEST_PATTERN_COLOR_RAMP: 668 valid_test_pattern = true; 669 break; 670 671 case DP_TEST_PATTERN_D102: 672 case DP_TEST_PATTERN_SYMBOL_ERROR: 673 case DP_TEST_PATTERN_PRBS7: 674 case DP_TEST_PATTERN_80BIT_CUSTOM: 675 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 676 case DP_TEST_PATTERN_TRAINING_PATTERN4: 677 disable_hpd = true; 678 valid_test_pattern = true; 679 break; 680 681 default: 682 valid_test_pattern = false; 683 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 684 break; 685 } 686 687 if (!valid_test_pattern) { 688 kfree(wr_buf); 689 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 690 return size; 691 } 692 693 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 694 for (i = 0; i < 10; i++) { 695 if ((uint8_t) param[i + 1] != 0x0) 696 break; 697 } 698 699 if (i < 10) { 700 /* not use default value */ 701 for (i = 0; i < 10; i++) 702 custom_pattern[i] = (uint8_t) param[i + 1]; 703 } 704 } 705 706 /* Usage: set DP physical test pattern using debugfs with normal DP 707 * panel. Then plug out DP panel and connect a scope to measure 708 * For normal video mode and test pattern generated from CRCT, 709 * they are visibile to user. So do not disable HPD. 710 * Video Mode is also set to clear the test pattern, so enable HPD 711 * because it might have been disabled after a test pattern was set. 712 * AUX depends on HPD * sequence dependent, do not move! 713 */ 714 if (!disable_hpd) 715 dc_link_enable_hpd(link); 716 717 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 718 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 719 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 720 721 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 722 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 723 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 724 725 link_training_settings.link_settings = cur_link_settings; 726 727 728 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 729 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 730 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 731 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 732 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 733 link_training_settings.link_settings = prefer_link_settings; 734 } 735 736 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 737 link_training_settings.lane_settings[i] = link->cur_lane_setting[i]; 738 739 dc_link_set_test_pattern( 740 link, 741 test_pattern, 742 DP_TEST_PATTERN_COLOR_SPACE_RGB, 743 &link_training_settings, 744 custom_pattern, 745 10); 746 747 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 748 * Then plug out DP panel and connect a scope to measure DP PHY signal. 749 * Need disable interrupt to avoid SW driver disable DP output. This is 750 * done after the test pattern is set. 751 */ 752 if (valid_test_pattern && disable_hpd) 753 dc_link_disable_hpd(link); 754 755 kfree(wr_buf); 756 757 return size; 758 } 759 760 /* 761 * Returns the DMCUB tracebuffer contents. 762 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 763 */ 764 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 765 { 766 struct amdgpu_device *adev = m->private; 767 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 768 struct dmub_debugfs_trace_entry *entries; 769 uint8_t *tbuf_base; 770 uint32_t tbuf_size, max_entries, num_entries, i; 771 772 if (!fb_info) 773 return 0; 774 775 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 776 if (!tbuf_base) 777 return 0; 778 779 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 780 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 781 sizeof(struct dmub_debugfs_trace_entry); 782 783 num_entries = 784 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 785 786 num_entries = min(num_entries, max_entries); 787 788 entries = (struct dmub_debugfs_trace_entry 789 *)(tbuf_base + 790 sizeof(struct dmub_debugfs_trace_header)); 791 792 for (i = 0; i < num_entries; ++i) { 793 struct dmub_debugfs_trace_entry *entry = &entries[i]; 794 795 seq_printf(m, 796 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 797 entry->trace_code, entry->tick_count, entry->param0, 798 entry->param1); 799 } 800 801 return 0; 802 } 803 804 /* 805 * Returns the DMCUB firmware state contents. 806 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 807 */ 808 static int dmub_fw_state_show(struct seq_file *m, void *data) 809 { 810 struct amdgpu_device *adev = m->private; 811 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 812 uint8_t *state_base; 813 uint32_t state_size; 814 815 if (!fb_info) 816 return 0; 817 818 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 819 if (!state_base) 820 return 0; 821 822 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 823 824 return seq_write(m, state_base, state_size); 825 } 826 827 /* 828 * Returns the current and maximum output bpc for the connector. 829 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 830 */ 831 static int output_bpc_show(struct seq_file *m, void *data) 832 { 833 struct drm_connector *connector = m->private; 834 struct drm_device *dev = connector->dev; 835 struct drm_crtc *crtc = NULL; 836 struct dm_crtc_state *dm_crtc_state = NULL; 837 int res = -ENODEV; 838 unsigned int bpc; 839 840 mutex_lock(&dev->mode_config.mutex); 841 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 842 843 if (connector->state == NULL) 844 goto unlock; 845 846 crtc = connector->state->crtc; 847 if (crtc == NULL) 848 goto unlock; 849 850 drm_modeset_lock(&crtc->mutex, NULL); 851 if (crtc->state == NULL) 852 goto unlock; 853 854 dm_crtc_state = to_dm_crtc_state(crtc->state); 855 if (dm_crtc_state->stream == NULL) 856 goto unlock; 857 858 switch (dm_crtc_state->stream->timing.display_color_depth) { 859 case COLOR_DEPTH_666: 860 bpc = 6; 861 break; 862 case COLOR_DEPTH_888: 863 bpc = 8; 864 break; 865 case COLOR_DEPTH_101010: 866 bpc = 10; 867 break; 868 case COLOR_DEPTH_121212: 869 bpc = 12; 870 break; 871 case COLOR_DEPTH_161616: 872 bpc = 16; 873 break; 874 default: 875 goto unlock; 876 } 877 878 seq_printf(m, "Current: %u\n", bpc); 879 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 880 res = 0; 881 882 unlock: 883 if (crtc) 884 drm_modeset_unlock(&crtc->mutex); 885 886 drm_modeset_unlock(&dev->mode_config.connection_mutex); 887 mutex_unlock(&dev->mode_config.mutex); 888 889 return res; 890 } 891 892 /* 893 * Example usage: 894 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 895 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 896 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 897 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 898 */ 899 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 900 size_t size, loff_t *pos) 901 { 902 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 903 char *wr_buf = NULL; 904 uint32_t wr_buf_size = 42; 905 int max_param_num = 1; 906 long param; 907 uint8_t param_nums = 0; 908 909 if (size == 0) 910 return -EINVAL; 911 912 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 913 914 if (!wr_buf) { 915 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 916 return -ENOSPC; 917 } 918 919 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 920 ¶m, buf, 921 max_param_num, 922 ¶m_nums)) { 923 kfree(wr_buf); 924 return -EINVAL; 925 } 926 927 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 928 929 kfree(wr_buf); 930 return 0; 931 } 932 933 #ifdef CONFIG_DRM_AMD_DC_HDCP 934 /* 935 * Returns the HDCP capability of the Display (1.4 for now). 936 * 937 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 938 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 939 * 940 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 941 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 942 */ 943 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 944 { 945 struct drm_connector *connector = m->private; 946 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 947 bool hdcp_cap, hdcp2_cap; 948 949 if (connector->status != connector_status_connected) 950 return -ENODEV; 951 952 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 953 954 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 955 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 956 957 958 if (hdcp_cap) 959 seq_printf(m, "%s ", "HDCP1.4"); 960 if (hdcp2_cap) 961 seq_printf(m, "%s ", "HDCP2.2"); 962 963 if (!hdcp_cap && !hdcp2_cap) 964 seq_printf(m, "%s ", "None"); 965 966 seq_puts(m, "\n"); 967 968 return 0; 969 } 970 #endif 971 972 /* 973 * Returns whether the connected display is internal and not hotpluggable. 974 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 975 */ 976 static int internal_display_show(struct seq_file *m, void *data) 977 { 978 struct drm_connector *connector = m->private; 979 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 980 struct dc_link *link = aconnector->dc_link; 981 982 seq_printf(m, "Internal: %u\n", link->is_internal_display); 983 984 return 0; 985 } 986 987 /* function description 988 * 989 * generic SDP message access for testing 990 * 991 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 992 * 993 * SDP header 994 * Hb0 : Secondary-Data Packet ID 995 * Hb1 : Secondary-Data Packet type 996 * Hb2 : Secondary-Data-packet-specific header, Byte 0 997 * Hb3 : Secondary-Data-packet-specific header, Byte 1 998 * 999 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1000 */ 1001 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1002 size_t size, loff_t *pos) 1003 { 1004 int r; 1005 uint8_t data[36]; 1006 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1007 struct dm_crtc_state *acrtc_state; 1008 uint32_t write_size = 36; 1009 1010 if (connector->base.status != connector_status_connected) 1011 return -ENODEV; 1012 1013 if (size == 0) 1014 return 0; 1015 1016 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1017 1018 r = copy_from_user(data, buf, write_size); 1019 1020 write_size -= r; 1021 1022 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1023 1024 return write_size; 1025 } 1026 1027 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1028 size_t size, loff_t *pos) 1029 { 1030 int r; 1031 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1032 1033 if (size < sizeof(connector->debugfs_dpcd_address)) 1034 return -EINVAL; 1035 1036 r = copy_from_user(&connector->debugfs_dpcd_address, 1037 buf, sizeof(connector->debugfs_dpcd_address)); 1038 1039 return size - r; 1040 } 1041 1042 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1043 size_t size, loff_t *pos) 1044 { 1045 int r; 1046 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1047 1048 if (size < sizeof(connector->debugfs_dpcd_size)) 1049 return -EINVAL; 1050 1051 r = copy_from_user(&connector->debugfs_dpcd_size, 1052 buf, sizeof(connector->debugfs_dpcd_size)); 1053 1054 if (connector->debugfs_dpcd_size > 256) 1055 connector->debugfs_dpcd_size = 0; 1056 1057 return size - r; 1058 } 1059 1060 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1061 size_t size, loff_t *pos) 1062 { 1063 int r; 1064 char *data; 1065 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1066 struct dc_link *link = connector->dc_link; 1067 uint32_t write_size = connector->debugfs_dpcd_size; 1068 1069 if (!write_size || size < write_size) 1070 return -EINVAL; 1071 1072 data = kzalloc(write_size, GFP_KERNEL); 1073 if (!data) 1074 return 0; 1075 1076 r = copy_from_user(data, buf, write_size); 1077 1078 dm_helpers_dp_write_dpcd(link->ctx, link, 1079 connector->debugfs_dpcd_address, data, write_size - r); 1080 kfree(data); 1081 return write_size - r; 1082 } 1083 1084 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1085 size_t size, loff_t *pos) 1086 { 1087 int r; 1088 char *data; 1089 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1090 struct dc_link *link = connector->dc_link; 1091 uint32_t read_size = connector->debugfs_dpcd_size; 1092 1093 if (!read_size || size < read_size) 1094 return 0; 1095 1096 data = kzalloc(read_size, GFP_KERNEL); 1097 if (!data) 1098 return 0; 1099 1100 dm_helpers_dp_read_dpcd(link->ctx, link, 1101 connector->debugfs_dpcd_address, data, read_size); 1102 1103 r = copy_to_user(buf, data, read_size); 1104 1105 kfree(data); 1106 return read_size - r; 1107 } 1108 1109 /* function: Read link's DSC & FEC capabilities 1110 * 1111 * 1112 * Access it with the following command (you need to specify 1113 * connector like DP-1): 1114 * 1115 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1116 * 1117 */ 1118 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1119 { 1120 struct drm_connector *connector = m->private; 1121 struct drm_modeset_acquire_ctx ctx; 1122 struct drm_device *dev = connector->dev; 1123 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1124 int ret = 0; 1125 bool try_again = false; 1126 bool is_fec_supported = false; 1127 bool is_dsc_supported = false; 1128 struct dpcd_caps dpcd_caps; 1129 1130 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1131 do { 1132 try_again = false; 1133 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1134 if (ret) { 1135 if (ret == -EDEADLK) { 1136 ret = drm_modeset_backoff(&ctx); 1137 if (!ret) { 1138 try_again = true; 1139 continue; 1140 } 1141 } 1142 break; 1143 } 1144 if (connector->status != connector_status_connected) { 1145 ret = -ENODEV; 1146 break; 1147 } 1148 dpcd_caps = aconnector->dc_link->dpcd_caps; 1149 if (aconnector->port) { 1150 /* aconnector sets dsc_aux during get_modes call 1151 * if MST connector has it means it can either 1152 * enable DSC on the sink device or on MST branch 1153 * its connected to. 1154 */ 1155 if (aconnector->dsc_aux) { 1156 is_fec_supported = true; 1157 is_dsc_supported = true; 1158 } 1159 } else { 1160 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1161 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1162 } 1163 } while (try_again); 1164 1165 drm_modeset_drop_locks(&ctx); 1166 drm_modeset_acquire_fini(&ctx); 1167 1168 seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported)); 1169 seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported)); 1170 1171 return ret; 1172 } 1173 1174 /* function: Trigger virtual HPD redetection on connector 1175 * 1176 * This function will perform link rediscovery, link disable 1177 * and enable, and dm connector state update. 1178 * 1179 * Retrigger HPD on an existing connector by echoing 1 into 1180 * its respectful "trigger_hotplug" debugfs entry: 1181 * 1182 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1183 * 1184 * This function can perform HPD unplug: 1185 * 1186 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1187 * 1188 */ 1189 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1190 size_t size, loff_t *pos) 1191 { 1192 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1193 struct drm_connector *connector = &aconnector->base; 1194 struct dc_link *link = NULL; 1195 struct drm_device *dev = connector->dev; 1196 enum dc_connection_type new_connection_type = dc_connection_none; 1197 char *wr_buf = NULL; 1198 uint32_t wr_buf_size = 42; 1199 int max_param_num = 1; 1200 long param[1] = {0}; 1201 uint8_t param_nums = 0; 1202 1203 if (!aconnector || !aconnector->dc_link) 1204 return -EINVAL; 1205 1206 if (size == 0) 1207 return -EINVAL; 1208 1209 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1210 1211 if (!wr_buf) { 1212 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1213 return -ENOSPC; 1214 } 1215 1216 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1217 (long *)param, buf, 1218 max_param_num, 1219 ¶m_nums)) { 1220 kfree(wr_buf); 1221 return -EINVAL; 1222 } 1223 1224 if (param_nums <= 0) { 1225 DRM_DEBUG_DRIVER("user data not be read\n"); 1226 kfree(wr_buf); 1227 return -EINVAL; 1228 } 1229 1230 if (param[0] == 1) { 1231 mutex_lock(&aconnector->hpd_lock); 1232 1233 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1234 new_connection_type != dc_connection_none) 1235 goto unlock; 1236 1237 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1238 goto unlock; 1239 1240 amdgpu_dm_update_connector_after_detect(aconnector); 1241 1242 drm_modeset_lock_all(dev); 1243 dm_restore_drm_connector_state(dev, connector); 1244 drm_modeset_unlock_all(dev); 1245 1246 drm_kms_helper_hotplug_event(dev); 1247 } else if (param[0] == 0) { 1248 if (!aconnector->dc_link) 1249 goto unlock; 1250 1251 link = aconnector->dc_link; 1252 1253 if (link->local_sink) { 1254 dc_sink_release(link->local_sink); 1255 link->local_sink = NULL; 1256 } 1257 1258 link->dpcd_sink_count = 0; 1259 link->type = dc_connection_none; 1260 link->dongle_max_pix_clk = 0; 1261 1262 amdgpu_dm_update_connector_after_detect(aconnector); 1263 1264 drm_modeset_lock_all(dev); 1265 dm_restore_drm_connector_state(dev, connector); 1266 drm_modeset_unlock_all(dev); 1267 1268 drm_kms_helper_hotplug_event(dev); 1269 } 1270 1271 unlock: 1272 mutex_unlock(&aconnector->hpd_lock); 1273 1274 kfree(wr_buf); 1275 return size; 1276 } 1277 1278 /* function: read DSC status on the connector 1279 * 1280 * The read function: dp_dsc_clock_en_read 1281 * returns current status of DSC clock on the connector. 1282 * The return is a boolean flag: 1 or 0. 1283 * 1284 * Access it with the following command (you need to specify 1285 * connector like DP-1): 1286 * 1287 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1288 * 1289 * Expected output: 1290 * 1 - means that DSC is currently enabled 1291 * 0 - means that DSC is disabled 1292 */ 1293 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1294 size_t size, loff_t *pos) 1295 { 1296 char *rd_buf = NULL; 1297 char *rd_buf_ptr = NULL; 1298 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1299 struct display_stream_compressor *dsc; 1300 struct dcn_dsc_state dsc_state = {0}; 1301 const uint32_t rd_buf_size = 10; 1302 struct pipe_ctx *pipe_ctx; 1303 ssize_t result = 0; 1304 int i, r, str_len = 30; 1305 1306 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1307 1308 if (!rd_buf) 1309 return -ENOMEM; 1310 1311 rd_buf_ptr = rd_buf; 1312 1313 for (i = 0; i < MAX_PIPES; i++) { 1314 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1315 if (pipe_ctx && pipe_ctx->stream && 1316 pipe_ctx->stream->link == aconnector->dc_link) 1317 break; 1318 } 1319 1320 if (!pipe_ctx) 1321 return -ENXIO; 1322 1323 dsc = pipe_ctx->stream_res.dsc; 1324 if (dsc) 1325 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1326 1327 snprintf(rd_buf_ptr, str_len, 1328 "%d\n", 1329 dsc_state.dsc_clock_en); 1330 rd_buf_ptr += str_len; 1331 1332 while (size) { 1333 if (*pos >= rd_buf_size) 1334 break; 1335 1336 r = put_user(*(rd_buf + result), buf); 1337 if (r) 1338 return r; /* r = -EFAULT */ 1339 1340 buf += 1; 1341 size -= 1; 1342 *pos += 1; 1343 result += 1; 1344 } 1345 1346 kfree(rd_buf); 1347 return result; 1348 } 1349 1350 /* function: write force DSC on the connector 1351 * 1352 * The write function: dp_dsc_clock_en_write 1353 * enables to force DSC on the connector. 1354 * User can write to either force enable or force disable DSC 1355 * on the next modeset or set it to driver default 1356 * 1357 * Accepted inputs: 1358 * 0 - default DSC enablement policy 1359 * 1 - force enable DSC on the connector 1360 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1361 * 1362 * Writing DSC settings is done with the following command: 1363 * - To force enable DSC (you need to specify 1364 * connector like DP-1): 1365 * 1366 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1367 * 1368 * - To return to default state set the flag to zero and 1369 * let driver deal with DSC automatically 1370 * (you need to specify connector like DP-1): 1371 * 1372 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1373 * 1374 */ 1375 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1376 size_t size, loff_t *pos) 1377 { 1378 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1379 struct drm_connector *connector = &aconnector->base; 1380 struct drm_device *dev = connector->dev; 1381 struct drm_crtc *crtc = NULL; 1382 struct dm_crtc_state *dm_crtc_state = NULL; 1383 struct pipe_ctx *pipe_ctx; 1384 int i; 1385 char *wr_buf = NULL; 1386 uint32_t wr_buf_size = 42; 1387 int max_param_num = 1; 1388 long param[1] = {0}; 1389 uint8_t param_nums = 0; 1390 1391 if (size == 0) 1392 return -EINVAL; 1393 1394 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1395 1396 if (!wr_buf) { 1397 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1398 return -ENOSPC; 1399 } 1400 1401 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1402 (long *)param, buf, 1403 max_param_num, 1404 ¶m_nums)) { 1405 kfree(wr_buf); 1406 return -EINVAL; 1407 } 1408 1409 if (param_nums <= 0) { 1410 DRM_DEBUG_DRIVER("user data not be read\n"); 1411 kfree(wr_buf); 1412 return -EINVAL; 1413 } 1414 1415 for (i = 0; i < MAX_PIPES; i++) { 1416 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1417 if (pipe_ctx && pipe_ctx->stream && 1418 pipe_ctx->stream->link == aconnector->dc_link) 1419 break; 1420 } 1421 1422 if (!pipe_ctx || !pipe_ctx->stream) 1423 goto done; 1424 1425 // Get CRTC state 1426 mutex_lock(&dev->mode_config.mutex); 1427 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1428 1429 if (connector->state == NULL) 1430 goto unlock; 1431 1432 crtc = connector->state->crtc; 1433 if (crtc == NULL) 1434 goto unlock; 1435 1436 drm_modeset_lock(&crtc->mutex, NULL); 1437 if (crtc->state == NULL) 1438 goto unlock; 1439 1440 dm_crtc_state = to_dm_crtc_state(crtc->state); 1441 if (dm_crtc_state->stream == NULL) 1442 goto unlock; 1443 1444 if (param[0] == 1) 1445 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1446 else if (param[0] == 2) 1447 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1448 else 1449 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1450 1451 dm_crtc_state->dsc_force_changed = true; 1452 1453 unlock: 1454 if (crtc) 1455 drm_modeset_unlock(&crtc->mutex); 1456 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1457 mutex_unlock(&dev->mode_config.mutex); 1458 1459 done: 1460 kfree(wr_buf); 1461 return size; 1462 } 1463 1464 /* function: read DSC slice width parameter on the connector 1465 * 1466 * The read function: dp_dsc_slice_width_read 1467 * returns dsc slice width used in the current configuration 1468 * The return is an integer: 0 or other positive number 1469 * 1470 * Access the status with the following command: 1471 * 1472 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1473 * 1474 * 0 - means that DSC is disabled 1475 * 1476 * Any other number more than zero represents the 1477 * slice width currently used by DSC in pixels 1478 * 1479 */ 1480 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1481 size_t size, loff_t *pos) 1482 { 1483 char *rd_buf = NULL; 1484 char *rd_buf_ptr = NULL; 1485 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1486 struct display_stream_compressor *dsc; 1487 struct dcn_dsc_state dsc_state = {0}; 1488 const uint32_t rd_buf_size = 100; 1489 struct pipe_ctx *pipe_ctx; 1490 ssize_t result = 0; 1491 int i, r, str_len = 30; 1492 1493 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1494 1495 if (!rd_buf) 1496 return -ENOMEM; 1497 1498 rd_buf_ptr = rd_buf; 1499 1500 for (i = 0; i < MAX_PIPES; i++) { 1501 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1502 if (pipe_ctx && pipe_ctx->stream && 1503 pipe_ctx->stream->link == aconnector->dc_link) 1504 break; 1505 } 1506 1507 if (!pipe_ctx) 1508 return -ENXIO; 1509 1510 dsc = pipe_ctx->stream_res.dsc; 1511 if (dsc) 1512 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1513 1514 snprintf(rd_buf_ptr, str_len, 1515 "%d\n", 1516 dsc_state.dsc_slice_width); 1517 rd_buf_ptr += str_len; 1518 1519 while (size) { 1520 if (*pos >= rd_buf_size) 1521 break; 1522 1523 r = put_user(*(rd_buf + result), buf); 1524 if (r) 1525 return r; /* r = -EFAULT */ 1526 1527 buf += 1; 1528 size -= 1; 1529 *pos += 1; 1530 result += 1; 1531 } 1532 1533 kfree(rd_buf); 1534 return result; 1535 } 1536 1537 /* function: write DSC slice width parameter 1538 * 1539 * The write function: dp_dsc_slice_width_write 1540 * overwrites automatically generated DSC configuration 1541 * of slice width. 1542 * 1543 * The user has to write the slice width divisible by the 1544 * picture width. 1545 * 1546 * Also the user has to write width in hexidecimal 1547 * rather than in decimal. 1548 * 1549 * Writing DSC settings is done with the following command: 1550 * - To force overwrite slice width: (example sets to 1920 pixels) 1551 * 1552 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1553 * 1554 * - To stop overwriting and let driver find the optimal size, 1555 * set the width to zero: 1556 * 1557 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1558 * 1559 */ 1560 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1561 size_t size, loff_t *pos) 1562 { 1563 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1564 struct pipe_ctx *pipe_ctx; 1565 struct drm_connector *connector = &aconnector->base; 1566 struct drm_device *dev = connector->dev; 1567 struct drm_crtc *crtc = NULL; 1568 struct dm_crtc_state *dm_crtc_state = NULL; 1569 int i; 1570 char *wr_buf = NULL; 1571 uint32_t wr_buf_size = 42; 1572 int max_param_num = 1; 1573 long param[1] = {0}; 1574 uint8_t param_nums = 0; 1575 1576 if (size == 0) 1577 return -EINVAL; 1578 1579 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1580 1581 if (!wr_buf) { 1582 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1583 return -ENOSPC; 1584 } 1585 1586 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1587 (long *)param, buf, 1588 max_param_num, 1589 ¶m_nums)) { 1590 kfree(wr_buf); 1591 return -EINVAL; 1592 } 1593 1594 if (param_nums <= 0) { 1595 DRM_DEBUG_DRIVER("user data not be read\n"); 1596 kfree(wr_buf); 1597 return -EINVAL; 1598 } 1599 1600 for (i = 0; i < MAX_PIPES; i++) { 1601 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1602 if (pipe_ctx && pipe_ctx->stream && 1603 pipe_ctx->stream->link == aconnector->dc_link) 1604 break; 1605 } 1606 1607 if (!pipe_ctx || !pipe_ctx->stream) 1608 goto done; 1609 1610 // Safely get CRTC state 1611 mutex_lock(&dev->mode_config.mutex); 1612 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1613 1614 if (connector->state == NULL) 1615 goto unlock; 1616 1617 crtc = connector->state->crtc; 1618 if (crtc == NULL) 1619 goto unlock; 1620 1621 drm_modeset_lock(&crtc->mutex, NULL); 1622 if (crtc->state == NULL) 1623 goto unlock; 1624 1625 dm_crtc_state = to_dm_crtc_state(crtc->state); 1626 if (dm_crtc_state->stream == NULL) 1627 goto unlock; 1628 1629 if (param[0] > 0) 1630 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1631 pipe_ctx->stream->timing.h_addressable, 1632 param[0]); 1633 else 1634 aconnector->dsc_settings.dsc_num_slices_h = 0; 1635 1636 dm_crtc_state->dsc_force_changed = true; 1637 1638 unlock: 1639 if (crtc) 1640 drm_modeset_unlock(&crtc->mutex); 1641 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1642 mutex_unlock(&dev->mode_config.mutex); 1643 1644 done: 1645 kfree(wr_buf); 1646 return size; 1647 } 1648 1649 /* function: read DSC slice height parameter on the connector 1650 * 1651 * The read function: dp_dsc_slice_height_read 1652 * returns dsc slice height used in the current configuration 1653 * The return is an integer: 0 or other positive number 1654 * 1655 * Access the status with the following command: 1656 * 1657 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1658 * 1659 * 0 - means that DSC is disabled 1660 * 1661 * Any other number more than zero represents the 1662 * slice height currently used by DSC in pixels 1663 * 1664 */ 1665 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1666 size_t size, loff_t *pos) 1667 { 1668 char *rd_buf = NULL; 1669 char *rd_buf_ptr = NULL; 1670 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1671 struct display_stream_compressor *dsc; 1672 struct dcn_dsc_state dsc_state = {0}; 1673 const uint32_t rd_buf_size = 100; 1674 struct pipe_ctx *pipe_ctx; 1675 ssize_t result = 0; 1676 int i, r, str_len = 30; 1677 1678 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1679 1680 if (!rd_buf) 1681 return -ENOMEM; 1682 1683 rd_buf_ptr = rd_buf; 1684 1685 for (i = 0; i < MAX_PIPES; i++) { 1686 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1687 if (pipe_ctx && pipe_ctx->stream && 1688 pipe_ctx->stream->link == aconnector->dc_link) 1689 break; 1690 } 1691 1692 if (!pipe_ctx) 1693 return -ENXIO; 1694 1695 dsc = pipe_ctx->stream_res.dsc; 1696 if (dsc) 1697 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1698 1699 snprintf(rd_buf_ptr, str_len, 1700 "%d\n", 1701 dsc_state.dsc_slice_height); 1702 rd_buf_ptr += str_len; 1703 1704 while (size) { 1705 if (*pos >= rd_buf_size) 1706 break; 1707 1708 r = put_user(*(rd_buf + result), buf); 1709 if (r) 1710 return r; /* r = -EFAULT */ 1711 1712 buf += 1; 1713 size -= 1; 1714 *pos += 1; 1715 result += 1; 1716 } 1717 1718 kfree(rd_buf); 1719 return result; 1720 } 1721 1722 /* function: write DSC slice height parameter 1723 * 1724 * The write function: dp_dsc_slice_height_write 1725 * overwrites automatically generated DSC configuration 1726 * of slice height. 1727 * 1728 * The user has to write the slice height divisible by the 1729 * picture height. 1730 * 1731 * Also the user has to write height in hexidecimal 1732 * rather than in decimal. 1733 * 1734 * Writing DSC settings is done with the following command: 1735 * - To force overwrite slice height (example sets to 128 pixels): 1736 * 1737 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1738 * 1739 * - To stop overwriting and let driver find the optimal size, 1740 * set the height to zero: 1741 * 1742 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1743 * 1744 */ 1745 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1746 size_t size, loff_t *pos) 1747 { 1748 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1749 struct drm_connector *connector = &aconnector->base; 1750 struct drm_device *dev = connector->dev; 1751 struct drm_crtc *crtc = NULL; 1752 struct dm_crtc_state *dm_crtc_state = NULL; 1753 struct pipe_ctx *pipe_ctx; 1754 int i; 1755 char *wr_buf = NULL; 1756 uint32_t wr_buf_size = 42; 1757 int max_param_num = 1; 1758 uint8_t param_nums = 0; 1759 long param[1] = {0}; 1760 1761 if (size == 0) 1762 return -EINVAL; 1763 1764 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1765 1766 if (!wr_buf) { 1767 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1768 return -ENOSPC; 1769 } 1770 1771 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1772 (long *)param, buf, 1773 max_param_num, 1774 ¶m_nums)) { 1775 kfree(wr_buf); 1776 return -EINVAL; 1777 } 1778 1779 if (param_nums <= 0) { 1780 DRM_DEBUG_DRIVER("user data not be read\n"); 1781 kfree(wr_buf); 1782 return -EINVAL; 1783 } 1784 1785 for (i = 0; i < MAX_PIPES; i++) { 1786 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1787 if (pipe_ctx && pipe_ctx->stream && 1788 pipe_ctx->stream->link == aconnector->dc_link) 1789 break; 1790 } 1791 1792 if (!pipe_ctx || !pipe_ctx->stream) 1793 goto done; 1794 1795 // Get CRTC state 1796 mutex_lock(&dev->mode_config.mutex); 1797 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1798 1799 if (connector->state == NULL) 1800 goto unlock; 1801 1802 crtc = connector->state->crtc; 1803 if (crtc == NULL) 1804 goto unlock; 1805 1806 drm_modeset_lock(&crtc->mutex, NULL); 1807 if (crtc->state == NULL) 1808 goto unlock; 1809 1810 dm_crtc_state = to_dm_crtc_state(crtc->state); 1811 if (dm_crtc_state->stream == NULL) 1812 goto unlock; 1813 1814 if (param[0] > 0) 1815 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1816 pipe_ctx->stream->timing.v_addressable, 1817 param[0]); 1818 else 1819 aconnector->dsc_settings.dsc_num_slices_v = 0; 1820 1821 dm_crtc_state->dsc_force_changed = true; 1822 1823 unlock: 1824 if (crtc) 1825 drm_modeset_unlock(&crtc->mutex); 1826 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1827 mutex_unlock(&dev->mode_config.mutex); 1828 1829 done: 1830 kfree(wr_buf); 1831 return size; 1832 } 1833 1834 /* function: read DSC target rate on the connector in bits per pixel 1835 * 1836 * The read function: dp_dsc_bits_per_pixel_read 1837 * returns target rate of compression in bits per pixel 1838 * The return is an integer: 0 or other positive integer 1839 * 1840 * Access it with the following command: 1841 * 1842 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1843 * 1844 * 0 - means that DSC is disabled 1845 */ 1846 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1847 size_t size, loff_t *pos) 1848 { 1849 char *rd_buf = NULL; 1850 char *rd_buf_ptr = NULL; 1851 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1852 struct display_stream_compressor *dsc; 1853 struct dcn_dsc_state dsc_state = {0}; 1854 const uint32_t rd_buf_size = 100; 1855 struct pipe_ctx *pipe_ctx; 1856 ssize_t result = 0; 1857 int i, r, str_len = 30; 1858 1859 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1860 1861 if (!rd_buf) 1862 return -ENOMEM; 1863 1864 rd_buf_ptr = rd_buf; 1865 1866 for (i = 0; i < MAX_PIPES; i++) { 1867 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1868 if (pipe_ctx && pipe_ctx->stream && 1869 pipe_ctx->stream->link == aconnector->dc_link) 1870 break; 1871 } 1872 1873 if (!pipe_ctx) 1874 return -ENXIO; 1875 1876 dsc = pipe_ctx->stream_res.dsc; 1877 if (dsc) 1878 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1879 1880 snprintf(rd_buf_ptr, str_len, 1881 "%d\n", 1882 dsc_state.dsc_bits_per_pixel); 1883 rd_buf_ptr += str_len; 1884 1885 while (size) { 1886 if (*pos >= rd_buf_size) 1887 break; 1888 1889 r = put_user(*(rd_buf + result), buf); 1890 if (r) 1891 return r; /* r = -EFAULT */ 1892 1893 buf += 1; 1894 size -= 1; 1895 *pos += 1; 1896 result += 1; 1897 } 1898 1899 kfree(rd_buf); 1900 return result; 1901 } 1902 1903 /* function: write DSC target rate in bits per pixel 1904 * 1905 * The write function: dp_dsc_bits_per_pixel_write 1906 * overwrites automatically generated DSC configuration 1907 * of DSC target bit rate. 1908 * 1909 * Also the user has to write bpp in hexidecimal 1910 * rather than in decimal. 1911 * 1912 * Writing DSC settings is done with the following command: 1913 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1914 * 1915 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1916 * 1917 * - To stop overwriting and let driver find the optimal rate, 1918 * set the rate to zero: 1919 * 1920 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1921 * 1922 */ 1923 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1924 size_t size, loff_t *pos) 1925 { 1926 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1927 struct drm_connector *connector = &aconnector->base; 1928 struct drm_device *dev = connector->dev; 1929 struct drm_crtc *crtc = NULL; 1930 struct dm_crtc_state *dm_crtc_state = NULL; 1931 struct pipe_ctx *pipe_ctx; 1932 int i; 1933 char *wr_buf = NULL; 1934 uint32_t wr_buf_size = 42; 1935 int max_param_num = 1; 1936 uint8_t param_nums = 0; 1937 long param[1] = {0}; 1938 1939 if (size == 0) 1940 return -EINVAL; 1941 1942 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1943 1944 if (!wr_buf) { 1945 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1946 return -ENOSPC; 1947 } 1948 1949 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1950 (long *)param, buf, 1951 max_param_num, 1952 ¶m_nums)) { 1953 kfree(wr_buf); 1954 return -EINVAL; 1955 } 1956 1957 if (param_nums <= 0) { 1958 DRM_DEBUG_DRIVER("user data not be read\n"); 1959 kfree(wr_buf); 1960 return -EINVAL; 1961 } 1962 1963 for (i = 0; i < MAX_PIPES; i++) { 1964 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1965 if (pipe_ctx && pipe_ctx->stream && 1966 pipe_ctx->stream->link == aconnector->dc_link) 1967 break; 1968 } 1969 1970 if (!pipe_ctx || !pipe_ctx->stream) 1971 goto done; 1972 1973 // Get CRTC state 1974 mutex_lock(&dev->mode_config.mutex); 1975 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1976 1977 if (connector->state == NULL) 1978 goto unlock; 1979 1980 crtc = connector->state->crtc; 1981 if (crtc == NULL) 1982 goto unlock; 1983 1984 drm_modeset_lock(&crtc->mutex, NULL); 1985 if (crtc->state == NULL) 1986 goto unlock; 1987 1988 dm_crtc_state = to_dm_crtc_state(crtc->state); 1989 if (dm_crtc_state->stream == NULL) 1990 goto unlock; 1991 1992 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 1993 1994 dm_crtc_state->dsc_force_changed = true; 1995 1996 unlock: 1997 if (crtc) 1998 drm_modeset_unlock(&crtc->mutex); 1999 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2000 mutex_unlock(&dev->mode_config.mutex); 2001 2002 done: 2003 kfree(wr_buf); 2004 return size; 2005 } 2006 2007 /* function: read DSC picture width parameter on the connector 2008 * 2009 * The read function: dp_dsc_pic_width_read 2010 * returns dsc picture width used in the current configuration 2011 * It is the same as h_addressable of the current 2012 * display's timing 2013 * The return is an integer: 0 or other positive integer 2014 * If 0 then DSC is disabled. 2015 * 2016 * Access it with the following command: 2017 * 2018 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2019 * 2020 * 0 - means that DSC is disabled 2021 */ 2022 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2023 size_t size, loff_t *pos) 2024 { 2025 char *rd_buf = NULL; 2026 char *rd_buf_ptr = NULL; 2027 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2028 struct display_stream_compressor *dsc; 2029 struct dcn_dsc_state dsc_state = {0}; 2030 const uint32_t rd_buf_size = 100; 2031 struct pipe_ctx *pipe_ctx; 2032 ssize_t result = 0; 2033 int i, r, str_len = 30; 2034 2035 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2036 2037 if (!rd_buf) 2038 return -ENOMEM; 2039 2040 rd_buf_ptr = rd_buf; 2041 2042 for (i = 0; i < MAX_PIPES; i++) { 2043 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2044 if (pipe_ctx && pipe_ctx->stream && 2045 pipe_ctx->stream->link == aconnector->dc_link) 2046 break; 2047 } 2048 2049 if (!pipe_ctx) 2050 return -ENXIO; 2051 2052 dsc = pipe_ctx->stream_res.dsc; 2053 if (dsc) 2054 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2055 2056 snprintf(rd_buf_ptr, str_len, 2057 "%d\n", 2058 dsc_state.dsc_pic_width); 2059 rd_buf_ptr += str_len; 2060 2061 while (size) { 2062 if (*pos >= rd_buf_size) 2063 break; 2064 2065 r = put_user(*(rd_buf + result), buf); 2066 if (r) 2067 return r; /* r = -EFAULT */ 2068 2069 buf += 1; 2070 size -= 1; 2071 *pos += 1; 2072 result += 1; 2073 } 2074 2075 kfree(rd_buf); 2076 return result; 2077 } 2078 2079 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2080 size_t size, loff_t *pos) 2081 { 2082 char *rd_buf = NULL; 2083 char *rd_buf_ptr = NULL; 2084 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2085 struct display_stream_compressor *dsc; 2086 struct dcn_dsc_state dsc_state = {0}; 2087 const uint32_t rd_buf_size = 100; 2088 struct pipe_ctx *pipe_ctx; 2089 ssize_t result = 0; 2090 int i, r, str_len = 30; 2091 2092 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2093 2094 if (!rd_buf) 2095 return -ENOMEM; 2096 2097 rd_buf_ptr = rd_buf; 2098 2099 for (i = 0; i < MAX_PIPES; i++) { 2100 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2101 if (pipe_ctx && pipe_ctx->stream && 2102 pipe_ctx->stream->link == aconnector->dc_link) 2103 break; 2104 } 2105 2106 if (!pipe_ctx) 2107 return -ENXIO; 2108 2109 dsc = pipe_ctx->stream_res.dsc; 2110 if (dsc) 2111 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2112 2113 snprintf(rd_buf_ptr, str_len, 2114 "%d\n", 2115 dsc_state.dsc_pic_height); 2116 rd_buf_ptr += str_len; 2117 2118 while (size) { 2119 if (*pos >= rd_buf_size) 2120 break; 2121 2122 r = put_user(*(rd_buf + result), buf); 2123 if (r) 2124 return r; /* r = -EFAULT */ 2125 2126 buf += 1; 2127 size -= 1; 2128 *pos += 1; 2129 result += 1; 2130 } 2131 2132 kfree(rd_buf); 2133 return result; 2134 } 2135 2136 /* function: read DSC chunk size parameter on the connector 2137 * 2138 * The read function: dp_dsc_chunk_size_read 2139 * returns dsc chunk size set in the current configuration 2140 * The value is calculated automatically by DSC code 2141 * and depends on slice parameters and bpp target rate 2142 * The return is an integer: 0 or other positive integer 2143 * If 0 then DSC is disabled. 2144 * 2145 * Access it with the following command: 2146 * 2147 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2148 * 2149 * 0 - means that DSC is disabled 2150 */ 2151 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2152 size_t size, loff_t *pos) 2153 { 2154 char *rd_buf = NULL; 2155 char *rd_buf_ptr = NULL; 2156 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2157 struct display_stream_compressor *dsc; 2158 struct dcn_dsc_state dsc_state = {0}; 2159 const uint32_t rd_buf_size = 100; 2160 struct pipe_ctx *pipe_ctx; 2161 ssize_t result = 0; 2162 int i, r, str_len = 30; 2163 2164 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2165 2166 if (!rd_buf) 2167 return -ENOMEM; 2168 2169 rd_buf_ptr = rd_buf; 2170 2171 for (i = 0; i < MAX_PIPES; i++) { 2172 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2173 if (pipe_ctx && pipe_ctx->stream && 2174 pipe_ctx->stream->link == aconnector->dc_link) 2175 break; 2176 } 2177 2178 if (!pipe_ctx) 2179 return -ENXIO; 2180 2181 dsc = pipe_ctx->stream_res.dsc; 2182 if (dsc) 2183 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2184 2185 snprintf(rd_buf_ptr, str_len, 2186 "%d\n", 2187 dsc_state.dsc_chunk_size); 2188 rd_buf_ptr += str_len; 2189 2190 while (size) { 2191 if (*pos >= rd_buf_size) 2192 break; 2193 2194 r = put_user(*(rd_buf + result), buf); 2195 if (r) 2196 return r; /* r = -EFAULT */ 2197 2198 buf += 1; 2199 size -= 1; 2200 *pos += 1; 2201 result += 1; 2202 } 2203 2204 kfree(rd_buf); 2205 return result; 2206 } 2207 2208 /* function: read DSC slice bpg offset on the connector 2209 * 2210 * The read function: dp_dsc_slice_bpg_offset_read 2211 * returns dsc bpg slice offset set in the current configuration 2212 * The value is calculated automatically by DSC code 2213 * and depends on slice parameters and bpp target rate 2214 * The return is an integer: 0 or other positive integer 2215 * If 0 then DSC is disabled. 2216 * 2217 * Access it with the following command: 2218 * 2219 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2220 * 2221 * 0 - means that DSC is disabled 2222 */ 2223 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2224 size_t size, loff_t *pos) 2225 { 2226 char *rd_buf = NULL; 2227 char *rd_buf_ptr = NULL; 2228 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2229 struct display_stream_compressor *dsc; 2230 struct dcn_dsc_state dsc_state = {0}; 2231 const uint32_t rd_buf_size = 100; 2232 struct pipe_ctx *pipe_ctx; 2233 ssize_t result = 0; 2234 int i, r, str_len = 30; 2235 2236 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2237 2238 if (!rd_buf) 2239 return -ENOMEM; 2240 2241 rd_buf_ptr = rd_buf; 2242 2243 for (i = 0; i < MAX_PIPES; i++) { 2244 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2245 if (pipe_ctx && pipe_ctx->stream && 2246 pipe_ctx->stream->link == aconnector->dc_link) 2247 break; 2248 } 2249 2250 if (!pipe_ctx) 2251 return -ENXIO; 2252 2253 dsc = pipe_ctx->stream_res.dsc; 2254 if (dsc) 2255 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2256 2257 snprintf(rd_buf_ptr, str_len, 2258 "%d\n", 2259 dsc_state.dsc_slice_bpg_offset); 2260 rd_buf_ptr += str_len; 2261 2262 while (size) { 2263 if (*pos >= rd_buf_size) 2264 break; 2265 2266 r = put_user(*(rd_buf + result), buf); 2267 if (r) 2268 return r; /* r = -EFAULT */ 2269 2270 buf += 1; 2271 size -= 1; 2272 *pos += 1; 2273 result += 1; 2274 } 2275 2276 kfree(rd_buf); 2277 return result; 2278 } 2279 2280 2281 /* 2282 * function description: Read max_requested_bpc property from the connector 2283 * 2284 * Access it with the following command: 2285 * 2286 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2287 * 2288 */ 2289 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2290 size_t size, loff_t *pos) 2291 { 2292 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2293 struct drm_connector *connector = &aconnector->base; 2294 struct drm_device *dev = connector->dev; 2295 struct dm_connector_state *state; 2296 ssize_t result = 0; 2297 char *rd_buf = NULL; 2298 char *rd_buf_ptr = NULL; 2299 const uint32_t rd_buf_size = 10; 2300 int r; 2301 2302 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2303 2304 if (!rd_buf) 2305 return -ENOMEM; 2306 2307 mutex_lock(&dev->mode_config.mutex); 2308 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2309 2310 if (connector->state == NULL) 2311 goto unlock; 2312 2313 state = to_dm_connector_state(connector->state); 2314 2315 rd_buf_ptr = rd_buf; 2316 snprintf(rd_buf_ptr, rd_buf_size, 2317 "%u\n", 2318 state->base.max_requested_bpc); 2319 2320 while (size) { 2321 if (*pos >= rd_buf_size) 2322 break; 2323 2324 r = put_user(*(rd_buf + result), buf); 2325 if (r) { 2326 result = r; /* r = -EFAULT */ 2327 goto unlock; 2328 } 2329 buf += 1; 2330 size -= 1; 2331 *pos += 1; 2332 result += 1; 2333 } 2334 unlock: 2335 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2336 mutex_unlock(&dev->mode_config.mutex); 2337 kfree(rd_buf); 2338 return result; 2339 } 2340 2341 2342 /* 2343 * function description: Set max_requested_bpc property on the connector 2344 * 2345 * This function will not force the input BPC on connector, it will only 2346 * change the max value. This is equivalent to setting max_bpc through 2347 * xrandr. 2348 * 2349 * The BPC value written must be >= 6 and <= 16. Values outside of this 2350 * range will result in errors. 2351 * 2352 * BPC values: 2353 * 0x6 - 6 BPC 2354 * 0x8 - 8 BPC 2355 * 0xa - 10 BPC 2356 * 0xc - 12 BPC 2357 * 0x10 - 16 BPC 2358 * 2359 * Write the max_bpc in the following way: 2360 * 2361 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2362 * 2363 */ 2364 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2365 size_t size, loff_t *pos) 2366 { 2367 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2368 struct drm_connector *connector = &aconnector->base; 2369 struct dm_connector_state *state; 2370 struct drm_device *dev = connector->dev; 2371 char *wr_buf = NULL; 2372 uint32_t wr_buf_size = 42; 2373 int max_param_num = 1; 2374 long param[1] = {0}; 2375 uint8_t param_nums = 0; 2376 2377 if (size == 0) 2378 return -EINVAL; 2379 2380 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2381 2382 if (!wr_buf) { 2383 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2384 return -ENOSPC; 2385 } 2386 2387 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2388 (long *)param, buf, 2389 max_param_num, 2390 ¶m_nums)) { 2391 kfree(wr_buf); 2392 return -EINVAL; 2393 } 2394 2395 if (param_nums <= 0) { 2396 DRM_DEBUG_DRIVER("user data not be read\n"); 2397 kfree(wr_buf); 2398 return -EINVAL; 2399 } 2400 2401 if (param[0] < 6 || param[0] > 16) { 2402 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2403 kfree(wr_buf); 2404 return -EINVAL; 2405 } 2406 2407 mutex_lock(&dev->mode_config.mutex); 2408 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2409 2410 if (connector->state == NULL) 2411 goto unlock; 2412 2413 state = to_dm_connector_state(connector->state); 2414 state->base.max_requested_bpc = param[0]; 2415 unlock: 2416 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2417 mutex_unlock(&dev->mode_config.mutex); 2418 2419 kfree(wr_buf); 2420 return size; 2421 } 2422 2423 /* 2424 * Backlight at this moment. Read only. 2425 * As written to display, taking ABM and backlight lut into account. 2426 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2427 * 2428 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2429 */ 2430 static int current_backlight_show(struct seq_file *m, void *unused) 2431 { 2432 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2433 struct dc_link *link = aconnector->dc_link; 2434 unsigned int backlight; 2435 2436 backlight = dc_link_get_backlight_level(link); 2437 seq_printf(m, "0x%x\n", backlight); 2438 2439 return 0; 2440 } 2441 2442 /* 2443 * Backlight value that is being approached. Read only. 2444 * As written to display, taking ABM and backlight lut into account. 2445 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2446 * 2447 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2448 */ 2449 static int target_backlight_show(struct seq_file *m, void *unused) 2450 { 2451 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2452 struct dc_link *link = aconnector->dc_link; 2453 unsigned int backlight; 2454 2455 backlight = dc_link_get_target_backlight_pwm(link); 2456 seq_printf(m, "0x%x\n", backlight); 2457 2458 return 0; 2459 } 2460 2461 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2462 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2463 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2464 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2465 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2466 #ifdef CONFIG_DRM_AMD_DC_HDCP 2467 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2468 #endif 2469 DEFINE_SHOW_ATTRIBUTE(internal_display); 2470 2471 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2472 .owner = THIS_MODULE, 2473 .read = dp_dsc_clock_en_read, 2474 .write = dp_dsc_clock_en_write, 2475 .llseek = default_llseek 2476 }; 2477 2478 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2479 .owner = THIS_MODULE, 2480 .read = dp_dsc_slice_width_read, 2481 .write = dp_dsc_slice_width_write, 2482 .llseek = default_llseek 2483 }; 2484 2485 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2486 .owner = THIS_MODULE, 2487 .read = dp_dsc_slice_height_read, 2488 .write = dp_dsc_slice_height_write, 2489 .llseek = default_llseek 2490 }; 2491 2492 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2493 .owner = THIS_MODULE, 2494 .read = dp_dsc_bits_per_pixel_read, 2495 .write = dp_dsc_bits_per_pixel_write, 2496 .llseek = default_llseek 2497 }; 2498 2499 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2500 .owner = THIS_MODULE, 2501 .read = dp_dsc_pic_width_read, 2502 .llseek = default_llseek 2503 }; 2504 2505 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2506 .owner = THIS_MODULE, 2507 .read = dp_dsc_pic_height_read, 2508 .llseek = default_llseek 2509 }; 2510 2511 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2512 .owner = THIS_MODULE, 2513 .read = dp_dsc_chunk_size_read, 2514 .llseek = default_llseek 2515 }; 2516 2517 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2518 .owner = THIS_MODULE, 2519 .read = dp_dsc_slice_bpg_offset_read, 2520 .llseek = default_llseek 2521 }; 2522 2523 static const struct file_operations trigger_hotplug_debugfs_fops = { 2524 .owner = THIS_MODULE, 2525 .write = trigger_hotplug, 2526 .llseek = default_llseek 2527 }; 2528 2529 static const struct file_operations dp_link_settings_debugfs_fops = { 2530 .owner = THIS_MODULE, 2531 .read = dp_link_settings_read, 2532 .write = dp_link_settings_write, 2533 .llseek = default_llseek 2534 }; 2535 2536 static const struct file_operations dp_phy_settings_debugfs_fop = { 2537 .owner = THIS_MODULE, 2538 .read = dp_phy_settings_read, 2539 .write = dp_phy_settings_write, 2540 .llseek = default_llseek 2541 }; 2542 2543 static const struct file_operations dp_phy_test_pattern_fops = { 2544 .owner = THIS_MODULE, 2545 .write = dp_phy_test_pattern_debugfs_write, 2546 .llseek = default_llseek 2547 }; 2548 2549 static const struct file_operations sdp_message_fops = { 2550 .owner = THIS_MODULE, 2551 .write = dp_sdp_message_debugfs_write, 2552 .llseek = default_llseek 2553 }; 2554 2555 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2556 .owner = THIS_MODULE, 2557 .write = dp_dpcd_address_write, 2558 .llseek = default_llseek 2559 }; 2560 2561 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2562 .owner = THIS_MODULE, 2563 .write = dp_dpcd_size_write, 2564 .llseek = default_llseek 2565 }; 2566 2567 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2568 .owner = THIS_MODULE, 2569 .read = dp_dpcd_data_read, 2570 .write = dp_dpcd_data_write, 2571 .llseek = default_llseek 2572 }; 2573 2574 static const struct file_operations dp_max_bpc_debugfs_fops = { 2575 .owner = THIS_MODULE, 2576 .read = dp_max_bpc_read, 2577 .write = dp_max_bpc_write, 2578 .llseek = default_llseek 2579 }; 2580 2581 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2582 .owner = THIS_MODULE, 2583 .write = dp_dsc_passthrough_set, 2584 .llseek = default_llseek 2585 }; 2586 2587 static const struct { 2588 char *name; 2589 const struct file_operations *fops; 2590 } dp_debugfs_entries[] = { 2591 {"link_settings", &dp_link_settings_debugfs_fops}, 2592 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2593 {"lttpr_status", &dp_lttpr_status_fops}, 2594 {"test_pattern", &dp_phy_test_pattern_fops}, 2595 #ifdef CONFIG_DRM_AMD_DC_HDCP 2596 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2597 #endif 2598 {"sdp_message", &sdp_message_fops}, 2599 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2600 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2601 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2602 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2603 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2604 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2605 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2606 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2607 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2608 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2609 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2610 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2611 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2612 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2613 }; 2614 2615 #ifdef CONFIG_DRM_AMD_DC_HDCP 2616 static const struct { 2617 char *name; 2618 const struct file_operations *fops; 2619 } hdmi_debugfs_entries[] = { 2620 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2621 }; 2622 #endif 2623 /* 2624 * Force YUV420 output if available from the given mode 2625 */ 2626 static int force_yuv420_output_set(void *data, u64 val) 2627 { 2628 struct amdgpu_dm_connector *connector = data; 2629 2630 connector->force_yuv420_output = (bool)val; 2631 2632 return 0; 2633 } 2634 2635 /* 2636 * Check if YUV420 is forced when available from the given mode 2637 */ 2638 static int force_yuv420_output_get(void *data, u64 *val) 2639 { 2640 struct amdgpu_dm_connector *connector = data; 2641 2642 *val = connector->force_yuv420_output; 2643 2644 return 0; 2645 } 2646 2647 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2648 force_yuv420_output_set, "%llu\n"); 2649 2650 /* 2651 * Read PSR state 2652 */ 2653 static int psr_get(void *data, u64 *val) 2654 { 2655 struct amdgpu_dm_connector *connector = data; 2656 struct dc_link *link = connector->dc_link; 2657 enum dc_psr_state state = PSR_STATE0; 2658 2659 dc_link_get_psr_state(link, &state); 2660 2661 *val = state; 2662 2663 return 0; 2664 } 2665 2666 /* 2667 * Set dmcub trace event IRQ enable or disable. 2668 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2669 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2670 */ 2671 static int dmcub_trace_event_state_set(void *data, u64 val) 2672 { 2673 struct amdgpu_device *adev = data; 2674 2675 if (val == 1 || val == 0) { 2676 dc_dmub_trace_event_control(adev->dm.dc, val); 2677 adev->dm.dmcub_trace_event_en = (bool)val; 2678 } else 2679 return 0; 2680 2681 return 0; 2682 } 2683 2684 /* 2685 * The interface doesn't need get function, so it will return the 2686 * value of zero 2687 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2688 */ 2689 static int dmcub_trace_event_state_get(void *data, u64 *val) 2690 { 2691 struct amdgpu_device *adev = data; 2692 2693 *val = adev->dm.dmcub_trace_event_en; 2694 return 0; 2695 } 2696 2697 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2698 dmcub_trace_event_state_set, "%llu\n"); 2699 2700 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2701 2702 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2703 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2704 2705 static const struct { 2706 char *name; 2707 const struct file_operations *fops; 2708 } connector_debugfs_entries[] = { 2709 {"force_yuv420_output", &force_yuv420_output_fops}, 2710 {"output_bpc", &output_bpc_fops}, 2711 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2712 {"internal_display", &internal_display_fops} 2713 }; 2714 2715 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2716 { 2717 int i; 2718 struct dentry *dir = connector->base.debugfs_entry; 2719 2720 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2721 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2722 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2723 debugfs_create_file(dp_debugfs_entries[i].name, 2724 0644, dir, connector, 2725 dp_debugfs_entries[i].fops); 2726 } 2727 } 2728 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2729 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2730 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2731 ¤t_backlight_fops); 2732 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2733 &target_backlight_fops); 2734 } 2735 2736 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2737 debugfs_create_file(connector_debugfs_entries[i].name, 2738 0644, dir, connector, 2739 connector_debugfs_entries[i].fops); 2740 } 2741 2742 connector->debugfs_dpcd_address = 0; 2743 connector->debugfs_dpcd_size = 0; 2744 2745 #ifdef CONFIG_DRM_AMD_DC_HDCP 2746 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2747 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2748 debugfs_create_file(hdmi_debugfs_entries[i].name, 2749 0644, dir, connector, 2750 hdmi_debugfs_entries[i].fops); 2751 } 2752 } 2753 #endif 2754 } 2755 2756 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2757 /* 2758 * Set crc window coordinate x start 2759 */ 2760 static int crc_win_x_start_set(void *data, u64 val) 2761 { 2762 struct drm_crtc *crtc = data; 2763 struct drm_device *drm_dev = crtc->dev; 2764 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2765 2766 spin_lock_irq(&drm_dev->event_lock); 2767 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2768 acrtc->dm_irq_params.crc_window.update_win = false; 2769 spin_unlock_irq(&drm_dev->event_lock); 2770 2771 return 0; 2772 } 2773 2774 /* 2775 * Get crc window coordinate x start 2776 */ 2777 static int crc_win_x_start_get(void *data, u64 *val) 2778 { 2779 struct drm_crtc *crtc = data; 2780 struct drm_device *drm_dev = crtc->dev; 2781 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2782 2783 spin_lock_irq(&drm_dev->event_lock); 2784 *val = acrtc->dm_irq_params.crc_window.x_start; 2785 spin_unlock_irq(&drm_dev->event_lock); 2786 2787 return 0; 2788 } 2789 2790 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 2791 crc_win_x_start_set, "%llu\n"); 2792 2793 2794 /* 2795 * Set crc window coordinate y start 2796 */ 2797 static int crc_win_y_start_set(void *data, u64 val) 2798 { 2799 struct drm_crtc *crtc = data; 2800 struct drm_device *drm_dev = crtc->dev; 2801 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2802 2803 spin_lock_irq(&drm_dev->event_lock); 2804 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 2805 acrtc->dm_irq_params.crc_window.update_win = false; 2806 spin_unlock_irq(&drm_dev->event_lock); 2807 2808 return 0; 2809 } 2810 2811 /* 2812 * Get crc window coordinate y start 2813 */ 2814 static int crc_win_y_start_get(void *data, u64 *val) 2815 { 2816 struct drm_crtc *crtc = data; 2817 struct drm_device *drm_dev = crtc->dev; 2818 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2819 2820 spin_lock_irq(&drm_dev->event_lock); 2821 *val = acrtc->dm_irq_params.crc_window.y_start; 2822 spin_unlock_irq(&drm_dev->event_lock); 2823 2824 return 0; 2825 } 2826 2827 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 2828 crc_win_y_start_set, "%llu\n"); 2829 2830 /* 2831 * Set crc window coordinate x end 2832 */ 2833 static int crc_win_x_end_set(void *data, u64 val) 2834 { 2835 struct drm_crtc *crtc = data; 2836 struct drm_device *drm_dev = crtc->dev; 2837 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2838 2839 spin_lock_irq(&drm_dev->event_lock); 2840 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 2841 acrtc->dm_irq_params.crc_window.update_win = false; 2842 spin_unlock_irq(&drm_dev->event_lock); 2843 2844 return 0; 2845 } 2846 2847 /* 2848 * Get crc window coordinate x end 2849 */ 2850 static int crc_win_x_end_get(void *data, u64 *val) 2851 { 2852 struct drm_crtc *crtc = data; 2853 struct drm_device *drm_dev = crtc->dev; 2854 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2855 2856 spin_lock_irq(&drm_dev->event_lock); 2857 *val = acrtc->dm_irq_params.crc_window.x_end; 2858 spin_unlock_irq(&drm_dev->event_lock); 2859 2860 return 0; 2861 } 2862 2863 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 2864 crc_win_x_end_set, "%llu\n"); 2865 2866 /* 2867 * Set crc window coordinate y end 2868 */ 2869 static int crc_win_y_end_set(void *data, u64 val) 2870 { 2871 struct drm_crtc *crtc = data; 2872 struct drm_device *drm_dev = crtc->dev; 2873 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2874 2875 spin_lock_irq(&drm_dev->event_lock); 2876 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 2877 acrtc->dm_irq_params.crc_window.update_win = false; 2878 spin_unlock_irq(&drm_dev->event_lock); 2879 2880 return 0; 2881 } 2882 2883 /* 2884 * Get crc window coordinate y end 2885 */ 2886 static int crc_win_y_end_get(void *data, u64 *val) 2887 { 2888 struct drm_crtc *crtc = data; 2889 struct drm_device *drm_dev = crtc->dev; 2890 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2891 2892 spin_lock_irq(&drm_dev->event_lock); 2893 *val = acrtc->dm_irq_params.crc_window.y_end; 2894 spin_unlock_irq(&drm_dev->event_lock); 2895 2896 return 0; 2897 } 2898 2899 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 2900 crc_win_y_end_set, "%llu\n"); 2901 /* 2902 * Trigger to commit crc window 2903 */ 2904 static int crc_win_update_set(void *data, u64 val) 2905 { 2906 struct drm_crtc *new_crtc = data; 2907 struct drm_crtc *old_crtc = NULL; 2908 struct amdgpu_crtc *new_acrtc, *old_acrtc; 2909 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 2910 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 2911 2912 if (val) { 2913 spin_lock_irq(&adev_to_drm(adev)->event_lock); 2914 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 2915 if (crc_rd_wrk && crc_rd_wrk->crtc) { 2916 old_crtc = crc_rd_wrk->crtc; 2917 old_acrtc = to_amdgpu_crtc(old_crtc); 2918 } 2919 new_acrtc = to_amdgpu_crtc(new_crtc); 2920 2921 if (old_crtc && old_crtc != new_crtc) { 2922 old_acrtc->dm_irq_params.crc_window.activated = false; 2923 old_acrtc->dm_irq_params.crc_window.update_win = false; 2924 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2925 2926 new_acrtc->dm_irq_params.crc_window.activated = true; 2927 new_acrtc->dm_irq_params.crc_window.update_win = true; 2928 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2929 crc_rd_wrk->crtc = new_crtc; 2930 } else { 2931 new_acrtc->dm_irq_params.crc_window.activated = true; 2932 new_acrtc->dm_irq_params.crc_window.update_win = true; 2933 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2934 crc_rd_wrk->crtc = new_crtc; 2935 } 2936 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 2937 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 2938 } 2939 2940 return 0; 2941 } 2942 2943 /* 2944 * Get crc window update flag 2945 */ 2946 static int crc_win_update_get(void *data, u64 *val) 2947 { 2948 *val = 0; 2949 return 0; 2950 } 2951 2952 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 2953 crc_win_update_set, "%llu\n"); 2954 2955 void crtc_debugfs_init(struct drm_crtc *crtc) 2956 { 2957 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 2958 2959 if (!dir) 2960 return; 2961 2962 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 2963 &crc_win_x_start_fops); 2964 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 2965 &crc_win_y_start_fops); 2966 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 2967 &crc_win_x_end_fops); 2968 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 2969 &crc_win_y_end_fops); 2970 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 2971 &crc_win_update_fops); 2972 2973 } 2974 #endif 2975 /* 2976 * Writes DTN log state to the user supplied buffer. 2977 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2978 */ 2979 static ssize_t dtn_log_read( 2980 struct file *f, 2981 char __user *buf, 2982 size_t size, 2983 loff_t *pos) 2984 { 2985 struct amdgpu_device *adev = file_inode(f)->i_private; 2986 struct dc *dc = adev->dm.dc; 2987 struct dc_log_buffer_ctx log_ctx = { 0 }; 2988 ssize_t result = 0; 2989 2990 if (!buf || !size) 2991 return -EINVAL; 2992 2993 if (!dc->hwss.log_hw_state) 2994 return 0; 2995 2996 dc->hwss.log_hw_state(dc, &log_ctx); 2997 2998 if (*pos < log_ctx.pos) { 2999 size_t to_copy = log_ctx.pos - *pos; 3000 3001 to_copy = min(to_copy, size); 3002 3003 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3004 *pos += to_copy; 3005 result = to_copy; 3006 } 3007 } 3008 3009 kfree(log_ctx.buf); 3010 3011 return result; 3012 } 3013 3014 /* 3015 * Writes DTN log state to dmesg when triggered via a write. 3016 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3017 */ 3018 static ssize_t dtn_log_write( 3019 struct file *f, 3020 const char __user *buf, 3021 size_t size, 3022 loff_t *pos) 3023 { 3024 struct amdgpu_device *adev = file_inode(f)->i_private; 3025 struct dc *dc = adev->dm.dc; 3026 3027 /* Write triggers log output via dmesg. */ 3028 if (size == 0) 3029 return 0; 3030 3031 if (dc->hwss.log_hw_state) 3032 dc->hwss.log_hw_state(dc, NULL); 3033 3034 return size; 3035 } 3036 3037 static int mst_topo_show(struct seq_file *m, void *unused) 3038 { 3039 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3040 struct drm_device *dev = adev_to_drm(adev); 3041 struct drm_connector *connector; 3042 struct drm_connector_list_iter conn_iter; 3043 struct amdgpu_dm_connector *aconnector; 3044 3045 drm_connector_list_iter_begin(dev, &conn_iter); 3046 drm_for_each_connector_iter(connector, &conn_iter) { 3047 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3048 continue; 3049 3050 aconnector = to_amdgpu_dm_connector(connector); 3051 3052 /* Ensure we're only dumping the topology of a root mst node */ 3053 if (!aconnector->mst_mgr.mst_state) 3054 continue; 3055 3056 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3057 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3058 } 3059 drm_connector_list_iter_end(&conn_iter); 3060 3061 return 0; 3062 } 3063 3064 /* 3065 * Sets trigger hpd for MST topologies. 3066 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3067 * All topologies will be disconnected if val of 0 is set . 3068 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3069 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3070 */ 3071 static int trigger_hpd_mst_set(void *data, u64 val) 3072 { 3073 struct amdgpu_device *adev = data; 3074 struct drm_device *dev = adev_to_drm(adev); 3075 struct drm_connector_list_iter iter; 3076 struct amdgpu_dm_connector *aconnector; 3077 struct drm_connector *connector; 3078 struct dc_link *link = NULL; 3079 3080 if (val == 1) { 3081 drm_connector_list_iter_begin(dev, &iter); 3082 drm_for_each_connector_iter(connector, &iter) { 3083 aconnector = to_amdgpu_dm_connector(connector); 3084 if (aconnector->dc_link->type == dc_connection_mst_branch && 3085 aconnector->mst_mgr.aux) { 3086 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3087 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3088 } 3089 } 3090 } else if (val == 0) { 3091 drm_connector_list_iter_begin(dev, &iter); 3092 drm_for_each_connector_iter(connector, &iter) { 3093 aconnector = to_amdgpu_dm_connector(connector); 3094 if (!aconnector->dc_link) 3095 continue; 3096 3097 if (!aconnector->mst_port) 3098 continue; 3099 3100 link = aconnector->dc_link; 3101 dp_receiver_power_ctrl(link, false); 3102 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3103 link->mst_stream_alloc_table.stream_count = 0; 3104 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3105 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3106 } 3107 } else { 3108 return 0; 3109 } 3110 drm_kms_helper_hotplug_event(dev); 3111 3112 return 0; 3113 } 3114 3115 /* 3116 * The interface doesn't need get function, so it will return the 3117 * value of zero 3118 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3119 */ 3120 static int trigger_hpd_mst_get(void *data, u64 *val) 3121 { 3122 *val = 0; 3123 return 0; 3124 } 3125 3126 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3127 trigger_hpd_mst_set, "%llu\n"); 3128 3129 3130 /* 3131 * Sets the force_timing_sync debug option from the given string. 3132 * All connected displays will be force synchronized immediately. 3133 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3134 */ 3135 static int force_timing_sync_set(void *data, u64 val) 3136 { 3137 struct amdgpu_device *adev = data; 3138 3139 adev->dm.force_timing_sync = (bool)val; 3140 3141 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3142 3143 return 0; 3144 } 3145 3146 /* 3147 * Gets the force_timing_sync debug option value into the given buffer. 3148 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3149 */ 3150 static int force_timing_sync_get(void *data, u64 *val) 3151 { 3152 struct amdgpu_device *adev = data; 3153 3154 *val = adev->dm.force_timing_sync; 3155 3156 return 0; 3157 } 3158 3159 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3160 force_timing_sync_set, "%llu\n"); 3161 3162 3163 /* 3164 * Disables all HPD and HPD RX interrupt handling in the 3165 * driver when set to 1. Default is 0. 3166 */ 3167 static int disable_hpd_set(void *data, u64 val) 3168 { 3169 struct amdgpu_device *adev = data; 3170 3171 adev->dm.disable_hpd_irq = (bool)val; 3172 3173 return 0; 3174 } 3175 3176 3177 /* 3178 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3179 * 0 otherwise. 3180 */ 3181 static int disable_hpd_get(void *data, u64 *val) 3182 { 3183 struct amdgpu_device *adev = data; 3184 3185 *val = adev->dm.disable_hpd_irq; 3186 3187 return 0; 3188 } 3189 3190 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3191 disable_hpd_set, "%llu\n"); 3192 3193 /* 3194 * Sets the DC visual confirm debug option from the given string. 3195 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3196 */ 3197 static int visual_confirm_set(void *data, u64 val) 3198 { 3199 struct amdgpu_device *adev = data; 3200 3201 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3202 3203 return 0; 3204 } 3205 3206 /* 3207 * Reads the DC visual confirm debug option value into the given buffer. 3208 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3209 */ 3210 static int visual_confirm_get(void *data, u64 *val) 3211 { 3212 struct amdgpu_device *adev = data; 3213 3214 *val = adev->dm.dc->debug.visual_confirm; 3215 3216 return 0; 3217 } 3218 3219 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3220 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3221 visual_confirm_set, "%llu\n"); 3222 3223 /* 3224 * Dumps the DCC_EN bit for each pipe. 3225 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3226 */ 3227 static ssize_t dcc_en_bits_read( 3228 struct file *f, 3229 char __user *buf, 3230 size_t size, 3231 loff_t *pos) 3232 { 3233 struct amdgpu_device *adev = file_inode(f)->i_private; 3234 struct dc *dc = adev->dm.dc; 3235 char *rd_buf = NULL; 3236 const uint32_t rd_buf_size = 32; 3237 uint32_t result = 0; 3238 int offset = 0; 3239 int num_pipes = dc->res_pool->pipe_count; 3240 int *dcc_en_bits; 3241 int i, r; 3242 3243 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3244 if (!dcc_en_bits) 3245 return -ENOMEM; 3246 3247 if (!dc->hwss.get_dcc_en_bits) { 3248 kfree(dcc_en_bits); 3249 return 0; 3250 } 3251 3252 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3253 3254 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3255 if (!rd_buf) 3256 return -ENOMEM; 3257 3258 for (i = 0; i < num_pipes; i++) 3259 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3260 "%d ", dcc_en_bits[i]); 3261 rd_buf[strlen(rd_buf)] = '\n'; 3262 3263 kfree(dcc_en_bits); 3264 3265 while (size) { 3266 if (*pos >= rd_buf_size) 3267 break; 3268 r = put_user(*(rd_buf + result), buf); 3269 if (r) 3270 return r; /* r = -EFAULT */ 3271 buf += 1; 3272 size -= 1; 3273 *pos += 1; 3274 result += 1; 3275 } 3276 3277 kfree(rd_buf); 3278 return result; 3279 } 3280 3281 void dtn_debugfs_init(struct amdgpu_device *adev) 3282 { 3283 static const struct file_operations dtn_log_fops = { 3284 .owner = THIS_MODULE, 3285 .read = dtn_log_read, 3286 .write = dtn_log_write, 3287 .llseek = default_llseek 3288 }; 3289 static const struct file_operations dcc_en_bits_fops = { 3290 .owner = THIS_MODULE, 3291 .read = dcc_en_bits_read, 3292 .llseek = default_llseek 3293 }; 3294 3295 struct drm_minor *minor = adev_to_drm(adev)->primary; 3296 struct dentry *root = minor->debugfs_root; 3297 3298 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3299 adev, &mst_topo_fops); 3300 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3301 &dtn_log_fops); 3302 3303 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3304 &visual_confirm_fops); 3305 3306 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3307 adev, &dmub_tracebuffer_fops); 3308 3309 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3310 adev, &dmub_fw_state_fops); 3311 3312 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3313 adev, &force_timing_sync_ops); 3314 3315 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3316 adev, &dmcub_trace_event_state_fops); 3317 3318 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3319 adev, &trigger_hpd_mst_ops); 3320 3321 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3322 &dcc_en_bits_fops); 3323 3324 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3325 &disable_hpd_ops); 3326 3327 } 3328