1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/debugfs.h> 27 28 #include "dc.h" 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "amdgpu_dm_debugfs.h" 32 #include "dm_helpers.h" 33 34 /* function description 35 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 36 * 37 * valid lane count value: 1, 2, 4 38 * valid link rate value: 39 * 06h = 1.62Gbps per lane 40 * 0Ah = 2.7Gbps per lane 41 * 0Ch = 3.24Gbps per lane 42 * 14h = 5.4Gbps per lane 43 * 1Eh = 8.1Gbps per lane 44 * 45 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 46 * 47 * --- to get dp configuration 48 * 49 * cat link_settings 50 * 51 * It will list current, verified, reported, preferred dp configuration. 52 * current -- for current video mode 53 * verified --- maximum configuration which pass link training 54 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 55 * preferred --- user force settings 56 * 57 * --- set (or force) dp configuration 58 * 59 * echo <lane_count> <link_rate> > link_settings 60 * 61 * for example, to force to 2 lane, 2.7GHz, 62 * echo 4 0xa > link_settings 63 * 64 * spread_spectrum could not be changed dynamically. 65 * 66 * in case invalid lane count, link rate are force, no hw programming will be 67 * done. please check link settings after force operation to see if HW get 68 * programming. 69 * 70 * cat link_settings 71 * 72 * check current and preferred settings. 73 * 74 */ 75 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 76 size_t size, loff_t *pos) 77 { 78 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 79 struct dc_link *link = connector->dc_link; 80 char *rd_buf = NULL; 81 char *rd_buf_ptr = NULL; 82 const uint32_t rd_buf_size = 100; 83 uint32_t result = 0; 84 uint8_t str_len = 0; 85 int r; 86 87 if (*pos & 3 || size & 3) 88 return -EINVAL; 89 90 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 91 if (!rd_buf) 92 return 0; 93 94 rd_buf_ptr = rd_buf; 95 96 str_len = strlen("Current: %d %d %d "); 97 snprintf(rd_buf_ptr, str_len, "Current: %d %d %d ", 98 link->cur_link_settings.lane_count, 99 link->cur_link_settings.link_rate, 100 link->cur_link_settings.link_spread); 101 rd_buf_ptr += str_len; 102 103 str_len = strlen("Verified: %d %d %d "); 104 snprintf(rd_buf_ptr, str_len, "Verified: %d %d %d ", 105 link->verified_link_cap.lane_count, 106 link->verified_link_cap.link_rate, 107 link->verified_link_cap.link_spread); 108 rd_buf_ptr += str_len; 109 110 str_len = strlen("Reported: %d %d %d "); 111 snprintf(rd_buf_ptr, str_len, "Reported: %d %d %d ", 112 link->reported_link_cap.lane_count, 113 link->reported_link_cap.link_rate, 114 link->reported_link_cap.link_spread); 115 rd_buf_ptr += str_len; 116 117 str_len = strlen("Preferred: %d %d %d "); 118 snprintf(rd_buf_ptr, str_len, "Preferred: %d %d %d\n", 119 link->preferred_link_setting.lane_count, 120 link->preferred_link_setting.link_rate, 121 link->preferred_link_setting.link_spread); 122 123 while (size) { 124 if (*pos >= rd_buf_size) 125 break; 126 127 r = put_user(*(rd_buf + result), buf); 128 if (r) 129 return r; /* r = -EFAULT */ 130 131 buf += 1; 132 size -= 1; 133 *pos += 1; 134 result += 1; 135 } 136 137 kfree(rd_buf); 138 return result; 139 } 140 141 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 142 size_t size, loff_t *pos) 143 { 144 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 145 struct dc_link *link = connector->dc_link; 146 struct dc *dc = (struct dc *)link->dc; 147 struct dc_link_settings prefer_link_settings; 148 char *wr_buf = NULL; 149 char *wr_buf_ptr = NULL; 150 const uint32_t wr_buf_size = 40; 151 int r; 152 int bytes_from_user; 153 char *sub_str; 154 /* 0: lane_count; 1: link_rate */ 155 uint8_t param_index = 0; 156 long param[2]; 157 const char delimiter[3] = {' ', '\n', '\0'}; 158 bool valid_input = false; 159 160 if (size == 0) 161 return -EINVAL; 162 163 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 164 if (!wr_buf) 165 return -EINVAL; 166 wr_buf_ptr = wr_buf; 167 168 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 169 170 /* r is bytes not be copied */ 171 if (r >= wr_buf_size) { 172 kfree(wr_buf); 173 DRM_DEBUG_DRIVER("user data not read\n"); 174 return -EINVAL; 175 } 176 177 bytes_from_user = wr_buf_size - r; 178 179 while (isspace(*wr_buf_ptr)) 180 wr_buf_ptr++; 181 182 while ((*wr_buf_ptr != '\0') && (param_index < 2)) { 183 184 sub_str = strsep(&wr_buf_ptr, delimiter); 185 186 r = kstrtol(sub_str, 16, ¶m[param_index]); 187 188 if (r) 189 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 190 191 param_index++; 192 while (isspace(*wr_buf_ptr)) 193 wr_buf_ptr++; 194 } 195 196 switch (param[0]) { 197 case LANE_COUNT_ONE: 198 case LANE_COUNT_TWO: 199 case LANE_COUNT_FOUR: 200 valid_input = true; 201 break; 202 default: 203 break; 204 } 205 206 switch (param[1]) { 207 case LINK_RATE_LOW: 208 case LINK_RATE_HIGH: 209 case LINK_RATE_RBR2: 210 case LINK_RATE_HIGH2: 211 case LINK_RATE_HIGH3: 212 valid_input = true; 213 break; 214 default: 215 break; 216 } 217 218 if (!valid_input) { 219 kfree(wr_buf); 220 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 221 return bytes_from_user; 222 } 223 224 /* save user force lane_count, link_rate to preferred settings 225 * spread spectrum will not be changed 226 */ 227 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 228 prefer_link_settings.lane_count = param[0]; 229 prefer_link_settings.link_rate = param[1]; 230 231 dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link); 232 233 kfree(wr_buf); 234 return bytes_from_user; 235 } 236 237 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 238 * post-cursor2 (defined by VESA DP specification) 239 * 240 * valid values 241 * voltage swing: 0,1,2,3 242 * pre-emphasis : 0,1,2,3 243 * post cursor2 : 0,1,2,3 244 * 245 * 246 * how to use this debugfs 247 * 248 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 249 * 250 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 251 * 252 * To figure out which DP-x is the display for DP to be check, 253 * cd DP-x 254 * ls -ll 255 * There should be debugfs file, like link_settings, phy_settings. 256 * cat link_settings 257 * from lane_count, link_rate to figure which DP-x is for display to be worked 258 * on 259 * 260 * To get current DP PHY settings, 261 * cat phy_settings 262 * 263 * To change DP PHY settings, 264 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 265 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 266 * 0, 267 * echo 2 3 0 > phy_settings 268 * 269 * To check if change be applied, get current phy settings by 270 * cat phy_settings 271 * 272 * In case invalid values are set by user, like 273 * echo 1 4 0 > phy_settings 274 * 275 * HW will NOT be programmed by these settings. 276 * cat phy_settings will show the previous valid settings. 277 */ 278 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 279 size_t size, loff_t *pos) 280 { 281 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 282 struct dc_link *link = connector->dc_link; 283 char *rd_buf = NULL; 284 const uint32_t rd_buf_size = 20; 285 uint32_t result = 0; 286 int r; 287 288 if (*pos & 3 || size & 3) 289 return -EINVAL; 290 291 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 292 if (!rd_buf) 293 return -EINVAL; 294 295 snprintf(rd_buf, rd_buf_size, " %d %d %d ", 296 link->cur_lane_setting.VOLTAGE_SWING, 297 link->cur_lane_setting.PRE_EMPHASIS, 298 link->cur_lane_setting.POST_CURSOR2); 299 300 while (size) { 301 if (*pos >= rd_buf_size) 302 break; 303 304 r = put_user((*(rd_buf + result)), buf); 305 if (r) 306 return r; /* r = -EFAULT */ 307 308 buf += 1; 309 size -= 1; 310 *pos += 1; 311 result += 1; 312 } 313 314 kfree(rd_buf); 315 return result; 316 } 317 318 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 319 size_t size, loff_t *pos) 320 { 321 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 322 struct dc_link *link = connector->dc_link; 323 struct dc *dc = (struct dc *)link->dc; 324 char *wr_buf = NULL; 325 char *wr_buf_ptr = NULL; 326 uint32_t wr_buf_size = 40; 327 int r; 328 int bytes_from_user; 329 char *sub_str; 330 uint8_t param_index = 0; 331 long param[3]; 332 const char delimiter[3] = {' ', '\n', '\0'}; 333 bool use_prefer_link_setting; 334 struct link_training_settings link_lane_settings; 335 336 if (size == 0) 337 return 0; 338 339 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 340 if (!wr_buf) 341 return 0; 342 wr_buf_ptr = wr_buf; 343 344 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 345 346 /* r is bytes not be copied */ 347 if (r >= wr_buf_size) { 348 kfree(wr_buf); 349 DRM_DEBUG_DRIVER("user data not be read\n"); 350 return 0; 351 } 352 353 bytes_from_user = wr_buf_size - r; 354 355 while (isspace(*wr_buf_ptr)) 356 wr_buf_ptr++; 357 358 while ((*wr_buf_ptr != '\0') && (param_index < 3)) { 359 360 sub_str = strsep(&wr_buf_ptr, delimiter); 361 362 r = kstrtol(sub_str, 16, ¶m[param_index]); 363 364 if (r) 365 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 366 367 param_index++; 368 while (isspace(*wr_buf_ptr)) 369 wr_buf_ptr++; 370 } 371 372 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 373 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 374 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 375 kfree(wr_buf); 376 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 377 return bytes_from_user; 378 } 379 380 /* get link settings: lane count, link rate */ 381 use_prefer_link_setting = 382 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 383 (link->test_pattern_enabled)); 384 385 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 386 387 if (use_prefer_link_setting) { 388 link_lane_settings.link_settings.lane_count = 389 link->preferred_link_setting.lane_count; 390 link_lane_settings.link_settings.link_rate = 391 link->preferred_link_setting.link_rate; 392 link_lane_settings.link_settings.link_spread = 393 link->preferred_link_setting.link_spread; 394 } else { 395 link_lane_settings.link_settings.lane_count = 396 link->cur_link_settings.lane_count; 397 link_lane_settings.link_settings.link_rate = 398 link->cur_link_settings.link_rate; 399 link_lane_settings.link_settings.link_spread = 400 link->cur_link_settings.link_spread; 401 } 402 403 /* apply phy settings from user */ 404 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 405 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 406 (enum dc_voltage_swing) (param[0]); 407 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 408 (enum dc_pre_emphasis) (param[1]); 409 link_lane_settings.lane_settings[r].POST_CURSOR2 = 410 (enum dc_post_cursor2) (param[2]); 411 } 412 413 /* program ASIC registers and DPCD registers */ 414 dc_link_set_drive_settings(dc, &link_lane_settings, link); 415 416 kfree(wr_buf); 417 return bytes_from_user; 418 } 419 420 /* function description 421 * 422 * set PHY layer or Link layer test pattern 423 * PHY test pattern is used for PHY SI check. 424 * Link layer test will not affect PHY SI. 425 * 426 * Reset Test Pattern: 427 * 0 = DP_TEST_PATTERN_VIDEO_MODE 428 * 429 * PHY test pattern supported: 430 * 1 = DP_TEST_PATTERN_D102 431 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 432 * 3 = DP_TEST_PATTERN_PRBS7 433 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 434 * 5 = DP_TEST_PATTERN_CP2520_1 435 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 436 * 7 = DP_TEST_PATTERN_CP2520_3 437 * 438 * DP PHY Link Training Patterns 439 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 440 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 441 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 442 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 443 * 444 * DP Link Layer Test pattern 445 * c = DP_TEST_PATTERN_COLOR_SQUARES 446 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 447 * e = DP_TEST_PATTERN_VERTICAL_BARS 448 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 449 * 10= DP_TEST_PATTERN_COLOR_RAMP 450 * 451 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 452 * 453 * --- set test pattern 454 * echo <test pattern #> > test_pattern 455 * 456 * If test pattern # is not supported, NO HW programming will be done. 457 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 458 * for the user pattern. input 10 bytes data are separated by space 459 * 460 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 461 * 462 * --- reset test pattern 463 * echo 0 > test_pattern 464 * 465 * --- HPD detection is disabled when set PHY test pattern 466 * 467 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 468 * is disable. User could unplug DP display from DP connected and plug scope to 469 * check test pattern PHY SI. 470 * If there is need unplug scope and plug DP display back, do steps below: 471 * echo 0 > phy_test_pattern 472 * unplug scope 473 * plug DP display. 474 * 475 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 476 * driver could detect "unplug scope" and "plug DP display" 477 */ 478 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 479 size_t size, loff_t *pos) 480 { 481 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 482 struct dc_link *link = connector->dc_link; 483 char *wr_buf = NULL; 484 char *wr_buf_ptr = NULL; 485 uint32_t wr_buf_size = 100; 486 uint32_t wr_buf_count = 0; 487 int r; 488 int bytes_from_user; 489 char *sub_str = NULL; 490 uint8_t param_index = 0; 491 uint8_t param_nums = 0; 492 long param[11] = {0x0}; 493 const char delimiter[3] = {' ', '\n', '\0'}; 494 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 495 bool disable_hpd = false; 496 bool valid_test_pattern = false; 497 /* init with defalut 80bit custom pattern */ 498 uint8_t custom_pattern[10] = { 499 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 500 0x1f, 0x7c, 0xf0, 0xc1, 0x07 501 }; 502 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 503 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 504 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 505 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 506 struct link_training_settings link_training_settings; 507 int i; 508 509 if (size == 0) 510 return 0; 511 512 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 513 if (!wr_buf) 514 return 0; 515 wr_buf_ptr = wr_buf; 516 517 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 518 519 /* r is bytes not be copied */ 520 if (r >= wr_buf_size) { 521 kfree(wr_buf); 522 DRM_DEBUG_DRIVER("user data not be read\n"); 523 return 0; 524 } 525 526 bytes_from_user = wr_buf_size - r; 527 528 /* check number of parameters. isspace could not differ space and \n */ 529 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 530 /* skip space*/ 531 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 532 wr_buf_ptr++; 533 wr_buf_count++; 534 } 535 536 if (wr_buf_count == wr_buf_size) 537 break; 538 539 /* skip non-space*/ 540 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 541 wr_buf_ptr++; 542 wr_buf_count++; 543 } 544 545 param_nums++; 546 547 if (wr_buf_count == wr_buf_size) 548 break; 549 } 550 551 /* max 11 parameters */ 552 if (param_nums > 11) 553 param_nums = 11; 554 555 wr_buf_ptr = wr_buf; /* reset buf pinter */ 556 wr_buf_count = 0; /* number of char already checked */ 557 558 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 559 wr_buf_ptr++; 560 wr_buf_count++; 561 } 562 563 while (param_index < param_nums) { 564 /* after strsep, wr_buf_ptr will be moved to after space */ 565 sub_str = strsep(&wr_buf_ptr, delimiter); 566 567 r = kstrtol(sub_str, 16, ¶m[param_index]); 568 569 if (r) 570 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 571 572 param_index++; 573 } 574 575 test_pattern = param[0]; 576 577 switch (test_pattern) { 578 case DP_TEST_PATTERN_VIDEO_MODE: 579 case DP_TEST_PATTERN_COLOR_SQUARES: 580 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 581 case DP_TEST_PATTERN_VERTICAL_BARS: 582 case DP_TEST_PATTERN_HORIZONTAL_BARS: 583 case DP_TEST_PATTERN_COLOR_RAMP: 584 valid_test_pattern = true; 585 break; 586 587 case DP_TEST_PATTERN_D102: 588 case DP_TEST_PATTERN_SYMBOL_ERROR: 589 case DP_TEST_PATTERN_PRBS7: 590 case DP_TEST_PATTERN_80BIT_CUSTOM: 591 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 592 case DP_TEST_PATTERN_TRAINING_PATTERN4: 593 disable_hpd = true; 594 valid_test_pattern = true; 595 break; 596 597 default: 598 valid_test_pattern = false; 599 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 600 break; 601 } 602 603 if (!valid_test_pattern) { 604 kfree(wr_buf); 605 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 606 return bytes_from_user; 607 } 608 609 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 610 for (i = 0; i < 10; i++) { 611 if ((uint8_t) param[i + 1] != 0x0) 612 break; 613 } 614 615 if (i < 10) { 616 /* not use default value */ 617 for (i = 0; i < 10; i++) 618 custom_pattern[i] = (uint8_t) param[i + 1]; 619 } 620 } 621 622 /* Usage: set DP physical test pattern using debugfs with normal DP 623 * panel. Then plug out DP panel and connect a scope to measure 624 * For normal video mode and test pattern generated from CRCT, 625 * they are visibile to user. So do not disable HPD. 626 * Video Mode is also set to clear the test pattern, so enable HPD 627 * because it might have been disabled after a test pattern was set. 628 * AUX depends on HPD * sequence dependent, do not move! 629 */ 630 if (!disable_hpd) 631 dc_link_enable_hpd(link); 632 633 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 634 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 635 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 636 637 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 638 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 639 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 640 641 link_training_settings.link_settings = cur_link_settings; 642 643 644 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 645 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 646 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 647 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 648 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 649 link_training_settings.link_settings = prefer_link_settings; 650 } 651 652 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 653 link_training_settings.lane_settings[i] = link->cur_lane_setting; 654 655 dc_link_set_test_pattern( 656 link, 657 test_pattern, 658 &link_training_settings, 659 custom_pattern, 660 10); 661 662 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 663 * Then plug out DP panel and connect a scope to measure DP PHY signal. 664 * Need disable interrupt to avoid SW driver disable DP output. This is 665 * done after the test pattern is set. 666 */ 667 if (valid_test_pattern && disable_hpd) 668 dc_link_disable_hpd(link); 669 670 kfree(wr_buf); 671 672 return bytes_from_user; 673 } 674 675 /* 676 * Returns the min and max vrr vfreq through the connector's debugfs file. 677 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range 678 */ 679 static int vrr_range_show(struct seq_file *m, void *data) 680 { 681 struct drm_connector *connector = m->private; 682 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 683 684 if (connector->status != connector_status_connected) 685 return -ENODEV; 686 687 seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); 688 seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); 689 690 return 0; 691 } 692 693 /* function description 694 * 695 * generic SDP message access for testing 696 * 697 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 698 * 699 * SDP header 700 * Hb0 : Secondary-Data Packet ID 701 * Hb1 : Secondary-Data Packet type 702 * Hb2 : Secondary-Data-packet-specific header, Byte 0 703 * Hb3 : Secondary-Data-packet-specific header, Byte 1 704 * 705 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 706 */ 707 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 708 size_t size, loff_t *pos) 709 { 710 int r; 711 uint8_t data[36]; 712 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 713 struct dm_crtc_state *acrtc_state; 714 uint32_t write_size = 36; 715 716 if (connector->base.status != connector_status_connected) 717 return -ENODEV; 718 719 if (size == 0) 720 return 0; 721 722 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 723 724 r = copy_from_user(data, buf, write_size); 725 726 write_size -= r; 727 728 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 729 730 return write_size; 731 } 732 733 DEFINE_SHOW_ATTRIBUTE(vrr_range); 734 735 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 736 size_t size, loff_t *pos) 737 { 738 int r; 739 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 740 741 if (size < sizeof(connector->debugfs_dpcd_address)) 742 return 0; 743 744 r = copy_from_user(&connector->debugfs_dpcd_address, 745 buf, sizeof(connector->debugfs_dpcd_address)); 746 747 return size - r; 748 } 749 750 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 751 size_t size, loff_t *pos) 752 { 753 int r; 754 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 755 756 if (size < sizeof(connector->debugfs_dpcd_size)) 757 return 0; 758 759 r = copy_from_user(&connector->debugfs_dpcd_size, 760 buf, sizeof(connector->debugfs_dpcd_size)); 761 762 if (connector->debugfs_dpcd_size > 256) 763 connector->debugfs_dpcd_size = 0; 764 765 return size - r; 766 } 767 768 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 769 size_t size, loff_t *pos) 770 { 771 int r; 772 char *data; 773 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 774 struct dc_link *link = connector->dc_link; 775 uint32_t write_size = connector->debugfs_dpcd_size; 776 777 if (size < write_size) 778 return 0; 779 780 data = kzalloc(write_size, GFP_KERNEL); 781 if (!data) 782 return 0; 783 784 r = copy_from_user(data, buf, write_size); 785 786 dm_helpers_dp_write_dpcd(link->ctx, link, 787 connector->debugfs_dpcd_address, data, write_size - r); 788 kfree(data); 789 return write_size - r; 790 } 791 792 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 793 size_t size, loff_t *pos) 794 { 795 int r; 796 char *data; 797 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 798 struct dc_link *link = connector->dc_link; 799 uint32_t read_size = connector->debugfs_dpcd_size; 800 801 if (size < read_size) 802 return 0; 803 804 data = kzalloc(read_size, GFP_KERNEL); 805 if (!data) 806 return 0; 807 808 dm_helpers_dp_read_dpcd(link->ctx, link, 809 connector->debugfs_dpcd_address, data, read_size); 810 811 r = copy_to_user(buf, data, read_size); 812 813 kfree(data); 814 return read_size - r; 815 } 816 817 static const struct file_operations dp_link_settings_debugfs_fops = { 818 .owner = THIS_MODULE, 819 .read = dp_link_settings_read, 820 .write = dp_link_settings_write, 821 .llseek = default_llseek 822 }; 823 824 static const struct file_operations dp_phy_settings_debugfs_fop = { 825 .owner = THIS_MODULE, 826 .read = dp_phy_settings_read, 827 .write = dp_phy_settings_write, 828 .llseek = default_llseek 829 }; 830 831 static const struct file_operations dp_phy_test_pattern_fops = { 832 .owner = THIS_MODULE, 833 .write = dp_phy_test_pattern_debugfs_write, 834 .llseek = default_llseek 835 }; 836 837 static const struct file_operations sdp_message_fops = { 838 .owner = THIS_MODULE, 839 .write = dp_sdp_message_debugfs_write, 840 .llseek = default_llseek 841 }; 842 843 static const struct file_operations dp_dpcd_address_debugfs_fops = { 844 .owner = THIS_MODULE, 845 .write = dp_dpcd_address_write, 846 .llseek = default_llseek 847 }; 848 849 static const struct file_operations dp_dpcd_size_debugfs_fops = { 850 .owner = THIS_MODULE, 851 .write = dp_dpcd_size_write, 852 .llseek = default_llseek 853 }; 854 855 static const struct file_operations dp_dpcd_data_debugfs_fops = { 856 .owner = THIS_MODULE, 857 .read = dp_dpcd_data_read, 858 .write = dp_dpcd_data_write, 859 .llseek = default_llseek 860 }; 861 862 static const struct { 863 char *name; 864 const struct file_operations *fops; 865 } dp_debugfs_entries[] = { 866 {"link_settings", &dp_link_settings_debugfs_fops}, 867 {"phy_settings", &dp_phy_settings_debugfs_fop}, 868 {"test_pattern", &dp_phy_test_pattern_fops}, 869 {"vrr_range", &vrr_range_fops}, 870 {"sdp_message", &sdp_message_fops}, 871 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 872 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 873 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops} 874 }; 875 876 int connector_debugfs_init(struct amdgpu_dm_connector *connector) 877 { 878 int i; 879 struct dentry *ent, *dir = connector->base.debugfs_entry; 880 881 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 882 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 883 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 884 ent = debugfs_create_file(dp_debugfs_entries[i].name, 885 0644, 886 dir, 887 connector, 888 dp_debugfs_entries[i].fops); 889 if (IS_ERR(ent)) 890 return PTR_ERR(ent); 891 } 892 } 893 894 return 0; 895 } 896 897 /* 898 * Writes DTN log state to the user supplied buffer. 899 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 900 */ 901 static ssize_t dtn_log_read( 902 struct file *f, 903 char __user *buf, 904 size_t size, 905 loff_t *pos) 906 { 907 struct amdgpu_device *adev = file_inode(f)->i_private; 908 struct dc *dc = adev->dm.dc; 909 struct dc_log_buffer_ctx log_ctx = { 0 }; 910 ssize_t result = 0; 911 912 if (!buf || !size) 913 return -EINVAL; 914 915 if (!dc->hwss.log_hw_state) 916 return 0; 917 918 dc->hwss.log_hw_state(dc, &log_ctx); 919 920 if (*pos < log_ctx.pos) { 921 size_t to_copy = log_ctx.pos - *pos; 922 923 to_copy = min(to_copy, size); 924 925 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 926 *pos += to_copy; 927 result = to_copy; 928 } 929 } 930 931 kfree(log_ctx.buf); 932 933 return result; 934 } 935 936 /* 937 * Writes DTN log state to dmesg when triggered via a write. 938 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 939 */ 940 static ssize_t dtn_log_write( 941 struct file *f, 942 const char __user *buf, 943 size_t size, 944 loff_t *pos) 945 { 946 struct amdgpu_device *adev = file_inode(f)->i_private; 947 struct dc *dc = adev->dm.dc; 948 949 /* Write triggers log output via dmesg. */ 950 if (size == 0) 951 return 0; 952 953 if (dc->hwss.log_hw_state) 954 dc->hwss.log_hw_state(dc, NULL); 955 956 return size; 957 } 958 959 /* 960 * Backlight at this moment. Read only. 961 * As written to display, taking ABM and backlight lut into account. 962 * Ranges from 0x0 to 0x10000 (= 100% PWM) 963 */ 964 static int current_backlight_read(struct seq_file *m, void *data) 965 { 966 struct drm_info_node *node = (struct drm_info_node *)m->private; 967 struct drm_device *dev = node->minor->dev; 968 struct amdgpu_device *adev = dev->dev_private; 969 struct dc *dc = adev->dm.dc; 970 unsigned int backlight = dc_get_current_backlight_pwm(dc); 971 972 seq_printf(m, "0x%x\n", backlight); 973 return 0; 974 } 975 976 /* 977 * Backlight value that is being approached. Read only. 978 * As written to display, taking ABM and backlight lut into account. 979 * Ranges from 0x0 to 0x10000 (= 100% PWM) 980 */ 981 static int target_backlight_read(struct seq_file *m, void *data) 982 { 983 struct drm_info_node *node = (struct drm_info_node *)m->private; 984 struct drm_device *dev = node->minor->dev; 985 struct amdgpu_device *adev = dev->dev_private; 986 struct dc *dc = adev->dm.dc; 987 unsigned int backlight = dc_get_target_backlight_pwm(dc); 988 989 seq_printf(m, "0x%x\n", backlight); 990 return 0; 991 } 992 993 static const struct drm_info_list amdgpu_dm_debugfs_list[] = { 994 {"amdgpu_current_backlight_pwm", ¤t_backlight_read}, 995 {"amdgpu_target_backlight_pwm", &target_backlight_read}, 996 }; 997 998 /* 999 * Sets the DC visual confirm debug option from the given string. 1000 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 1001 */ 1002 static int visual_confirm_set(void *data, u64 val) 1003 { 1004 struct amdgpu_device *adev = data; 1005 1006 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 1007 1008 return 0; 1009 } 1010 1011 /* 1012 * Reads the DC visual confirm debug option value into the given buffer. 1013 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 1014 */ 1015 static int visual_confirm_get(void *data, u64 *val) 1016 { 1017 struct amdgpu_device *adev = data; 1018 1019 *val = adev->dm.dc->debug.visual_confirm; 1020 1021 return 0; 1022 } 1023 1024 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 1025 visual_confirm_set, "%llu\n"); 1026 1027 int dtn_debugfs_init(struct amdgpu_device *adev) 1028 { 1029 static const struct file_operations dtn_log_fops = { 1030 .owner = THIS_MODULE, 1031 .read = dtn_log_read, 1032 .write = dtn_log_write, 1033 .llseek = default_llseek 1034 }; 1035 1036 struct drm_minor *minor = adev->ddev->primary; 1037 struct dentry *ent, *root = minor->debugfs_root; 1038 int ret; 1039 1040 ret = amdgpu_debugfs_add_files(adev, amdgpu_dm_debugfs_list, 1041 ARRAY_SIZE(amdgpu_dm_debugfs_list)); 1042 if (ret) 1043 return ret; 1044 1045 ent = debugfs_create_file( 1046 "amdgpu_dm_dtn_log", 1047 0644, 1048 root, 1049 adev, 1050 &dtn_log_fops); 1051 1052 if (IS_ERR(ent)) 1053 return PTR_ERR(ent); 1054 1055 ent = debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, 1056 adev, &visual_confirm_fops); 1057 if (IS_ERR(ent)) 1058 return PTR_ERR(ent); 1059 1060 return 0; 1061 } 1062