1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 41 struct dmub_debugfs_trace_header { 42 uint32_t entry_count; 43 uint32_t reserved[3]; 44 }; 45 46 struct dmub_debugfs_trace_entry { 47 uint32_t trace_code; 48 uint32_t tick_count; 49 uint32_t param0; 50 uint32_t param1; 51 }; 52 53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 54 * 55 * Function takes in attributes passed to debugfs write entry 56 * and writes into param array. 57 * The user passes max_param_num to identify maximum number of 58 * parameters that could be parsed. 59 * 60 */ 61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 62 long *param, const char __user *buf, 63 int max_param_num, 64 uint8_t *param_nums) 65 { 66 char *wr_buf_ptr = NULL; 67 uint32_t wr_buf_count = 0; 68 int r; 69 char *sub_str = NULL; 70 const char delimiter[3] = {' ', '\n', '\0'}; 71 uint8_t param_index = 0; 72 73 *param_nums = 0; 74 75 wr_buf_ptr = wr_buf; 76 77 /* r is bytes not be copied */ 78 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 79 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 80 return -EFAULT; 81 } 82 83 /* check number of parameters. isspace could not differ space and \n */ 84 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 85 /* skip space*/ 86 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 87 wr_buf_ptr++; 88 wr_buf_count++; 89 } 90 91 if (wr_buf_count == wr_buf_size) 92 break; 93 94 /* skip non-space*/ 95 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 96 wr_buf_ptr++; 97 wr_buf_count++; 98 } 99 100 (*param_nums)++; 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 } 105 106 if (*param_nums > max_param_num) 107 *param_nums = max_param_num; 108 109 wr_buf_ptr = wr_buf; /* reset buf pointer */ 110 wr_buf_count = 0; /* number of char already checked */ 111 112 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 113 wr_buf_ptr++; 114 wr_buf_count++; 115 } 116 117 while (param_index < *param_nums) { 118 /* after strsep, wr_buf_ptr will be moved to after space */ 119 sub_str = strsep(&wr_buf_ptr, delimiter); 120 121 r = kstrtol(sub_str, 16, &(param[param_index])); 122 123 if (r) 124 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 125 126 param_index++; 127 } 128 129 return 0; 130 } 131 132 /* function description 133 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 134 * 135 * valid lane count value: 1, 2, 4 136 * valid link rate value: 137 * 06h = 1.62Gbps per lane 138 * 0Ah = 2.7Gbps per lane 139 * 0Ch = 3.24Gbps per lane 140 * 14h = 5.4Gbps per lane 141 * 1Eh = 8.1Gbps per lane 142 * 143 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 144 * 145 * --- to get dp configuration 146 * 147 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 148 * 149 * It will list current, verified, reported, preferred dp configuration. 150 * current -- for current video mode 151 * verified --- maximum configuration which pass link training 152 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 153 * preferred --- user force settings 154 * 155 * --- set (or force) dp configuration 156 * 157 * echo <lane_count> <link_rate> > link_settings 158 * 159 * for example, to force to 2 lane, 2.7GHz, 160 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * spread_spectrum could not be changed dynamically. 163 * 164 * in case invalid lane count, link rate are force, no hw programming will be 165 * done. please check link settings after force operation to see if HW get 166 * programming. 167 * 168 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 169 * 170 * check current and preferred settings. 171 * 172 */ 173 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 174 size_t size, loff_t *pos) 175 { 176 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 177 struct dc_link *link = connector->dc_link; 178 char *rd_buf = NULL; 179 char *rd_buf_ptr = NULL; 180 const uint32_t rd_buf_size = 100; 181 uint32_t result = 0; 182 uint8_t str_len = 0; 183 int r; 184 185 if (*pos & 3 || size & 3) 186 return -EINVAL; 187 188 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 189 if (!rd_buf) 190 return 0; 191 192 rd_buf_ptr = rd_buf; 193 194 str_len = strlen("Current: %d 0x%x %d "); 195 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 196 link->cur_link_settings.lane_count, 197 link->cur_link_settings.link_rate, 198 link->cur_link_settings.link_spread); 199 rd_buf_ptr += str_len; 200 201 str_len = strlen("Verified: %d 0x%x %d "); 202 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 203 link->verified_link_cap.lane_count, 204 link->verified_link_cap.link_rate, 205 link->verified_link_cap.link_spread); 206 rd_buf_ptr += str_len; 207 208 str_len = strlen("Reported: %d 0x%x %d "); 209 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 210 link->reported_link_cap.lane_count, 211 link->reported_link_cap.link_rate, 212 link->reported_link_cap.link_spread); 213 rd_buf_ptr += str_len; 214 215 str_len = strlen("Preferred: %d 0x%x %d "); 216 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 217 link->preferred_link_setting.lane_count, 218 link->preferred_link_setting.link_rate, 219 link->preferred_link_setting.link_spread); 220 221 while (size) { 222 if (*pos >= rd_buf_size) 223 break; 224 225 r = put_user(*(rd_buf + result), buf); 226 if (r) { 227 kfree(rd_buf); 228 return r; /* r = -EFAULT */ 229 } 230 231 buf += 1; 232 size -= 1; 233 *pos += 1; 234 result += 1; 235 } 236 237 kfree(rd_buf); 238 return result; 239 } 240 241 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 242 size_t size, loff_t *pos) 243 { 244 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 245 struct dc_link *link = connector->dc_link; 246 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 247 struct dc *dc = (struct dc *)link->dc; 248 struct dc_link_settings prefer_link_settings; 249 char *wr_buf = NULL; 250 const uint32_t wr_buf_size = 40; 251 /* 0: lane_count; 1: link_rate */ 252 int max_param_num = 2; 253 uint8_t param_nums = 0; 254 long param[2]; 255 bool valid_input = true; 256 257 if (size == 0) 258 return -EINVAL; 259 260 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 261 if (!wr_buf) 262 return -ENOSPC; 263 264 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 265 (long *)param, buf, 266 max_param_num, 267 ¶m_nums)) { 268 kfree(wr_buf); 269 return -EINVAL; 270 } 271 272 if (param_nums <= 0) { 273 kfree(wr_buf); 274 DRM_DEBUG_DRIVER("user data not be read\n"); 275 return -EINVAL; 276 } 277 278 switch (param[0]) { 279 case LANE_COUNT_ONE: 280 case LANE_COUNT_TWO: 281 case LANE_COUNT_FOUR: 282 break; 283 default: 284 valid_input = false; 285 break; 286 } 287 288 switch (param[1]) { 289 case LINK_RATE_LOW: 290 case LINK_RATE_HIGH: 291 case LINK_RATE_RBR2: 292 case LINK_RATE_HIGH2: 293 case LINK_RATE_HIGH3: 294 #if defined(CONFIG_DRM_AMD_DC_DCN) 295 case LINK_RATE_UHBR10: 296 #endif 297 break; 298 default: 299 valid_input = false; 300 break; 301 } 302 303 if (!valid_input) { 304 kfree(wr_buf); 305 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 306 mutex_lock(&adev->dm.dc_lock); 307 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 308 mutex_unlock(&adev->dm.dc_lock); 309 return size; 310 } 311 312 /* save user force lane_count, link_rate to preferred settings 313 * spread spectrum will not be changed 314 */ 315 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 316 prefer_link_settings.use_link_rate_set = false; 317 prefer_link_settings.lane_count = param[0]; 318 prefer_link_settings.link_rate = param[1]; 319 320 mutex_lock(&adev->dm.dc_lock); 321 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 322 mutex_unlock(&adev->dm.dc_lock); 323 324 kfree(wr_buf); 325 return size; 326 } 327 328 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 329 * post-cursor2 (defined by VESA DP specification) 330 * 331 * valid values 332 * voltage swing: 0,1,2,3 333 * pre-emphasis : 0,1,2,3 334 * post cursor2 : 0,1,2,3 335 * 336 * 337 * how to use this debugfs 338 * 339 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 340 * 341 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 342 * 343 * To figure out which DP-x is the display for DP to be check, 344 * cd DP-x 345 * ls -ll 346 * There should be debugfs file, like link_settings, phy_settings. 347 * cat link_settings 348 * from lane_count, link_rate to figure which DP-x is for display to be worked 349 * on 350 * 351 * To get current DP PHY settings, 352 * cat phy_settings 353 * 354 * To change DP PHY settings, 355 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 356 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 357 * 0, 358 * echo 2 3 0 > phy_settings 359 * 360 * To check if change be applied, get current phy settings by 361 * cat phy_settings 362 * 363 * In case invalid values are set by user, like 364 * echo 1 4 0 > phy_settings 365 * 366 * HW will NOT be programmed by these settings. 367 * cat phy_settings will show the previous valid settings. 368 */ 369 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 370 size_t size, loff_t *pos) 371 { 372 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 373 struct dc_link *link = connector->dc_link; 374 char *rd_buf = NULL; 375 const uint32_t rd_buf_size = 20; 376 uint32_t result = 0; 377 int r; 378 379 if (*pos & 3 || size & 3) 380 return -EINVAL; 381 382 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 383 if (!rd_buf) 384 return -EINVAL; 385 386 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 387 link->cur_lane_setting[0].VOLTAGE_SWING, 388 link->cur_lane_setting[0].PRE_EMPHASIS, 389 link->cur_lane_setting[0].POST_CURSOR2); 390 391 while (size) { 392 if (*pos >= rd_buf_size) 393 break; 394 395 r = put_user((*(rd_buf + result)), buf); 396 if (r) { 397 kfree(rd_buf); 398 return r; /* r = -EFAULT */ 399 } 400 401 buf += 1; 402 size -= 1; 403 *pos += 1; 404 result += 1; 405 } 406 407 kfree(rd_buf); 408 return result; 409 } 410 411 static int dp_lttpr_status_show(struct seq_file *m, void *d) 412 { 413 char *data; 414 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 415 struct dc_link *link = connector->dc_link; 416 uint32_t read_size = 1; 417 uint8_t repeater_count = 0; 418 419 data = kzalloc(read_size, GFP_KERNEL); 420 if (!data) 421 return 0; 422 423 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 424 425 switch ((uint8_t)*data) { 426 case 0x80: 427 repeater_count = 1; 428 break; 429 case 0x40: 430 repeater_count = 2; 431 break; 432 case 0x20: 433 repeater_count = 3; 434 break; 435 case 0x10: 436 repeater_count = 4; 437 break; 438 case 0x8: 439 repeater_count = 5; 440 break; 441 case 0x4: 442 repeater_count = 6; 443 break; 444 case 0x2: 445 repeater_count = 7; 446 break; 447 case 0x1: 448 repeater_count = 8; 449 break; 450 case 0x0: 451 repeater_count = 0; 452 break; 453 default: 454 repeater_count = (uint8_t)*data; 455 break; 456 } 457 458 seq_printf(m, "phy repeater count: %d\n", repeater_count); 459 460 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 461 462 if ((uint8_t)*data == 0x55) 463 seq_printf(m, "phy repeater mode: transparent\n"); 464 else if ((uint8_t)*data == 0xAA) 465 seq_printf(m, "phy repeater mode: non-transparent\n"); 466 else if ((uint8_t)*data == 0x00) 467 seq_printf(m, "phy repeater mode: non lttpr\n"); 468 else 469 seq_printf(m, "phy repeater mode: read error\n"); 470 471 kfree(data); 472 return 0; 473 } 474 475 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 476 size_t size, loff_t *pos) 477 { 478 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 479 struct dc_link *link = connector->dc_link; 480 struct dc *dc = (struct dc *)link->dc; 481 char *wr_buf = NULL; 482 uint32_t wr_buf_size = 40; 483 long param[3]; 484 bool use_prefer_link_setting; 485 struct link_training_settings link_lane_settings; 486 int max_param_num = 3; 487 uint8_t param_nums = 0; 488 int r = 0; 489 490 491 if (size == 0) 492 return -EINVAL; 493 494 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 495 if (!wr_buf) 496 return -ENOSPC; 497 498 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 499 (long *)param, buf, 500 max_param_num, 501 ¶m_nums)) { 502 kfree(wr_buf); 503 return -EINVAL; 504 } 505 506 if (param_nums <= 0) { 507 kfree(wr_buf); 508 DRM_DEBUG_DRIVER("user data not be read\n"); 509 return -EINVAL; 510 } 511 512 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 513 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 514 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 515 kfree(wr_buf); 516 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 517 return size; 518 } 519 520 /* get link settings: lane count, link rate */ 521 use_prefer_link_setting = 522 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 523 (link->test_pattern_enabled)); 524 525 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 526 527 if (use_prefer_link_setting) { 528 link_lane_settings.link_settings.lane_count = 529 link->preferred_link_setting.lane_count; 530 link_lane_settings.link_settings.link_rate = 531 link->preferred_link_setting.link_rate; 532 link_lane_settings.link_settings.link_spread = 533 link->preferred_link_setting.link_spread; 534 } else { 535 link_lane_settings.link_settings.lane_count = 536 link->cur_link_settings.lane_count; 537 link_lane_settings.link_settings.link_rate = 538 link->cur_link_settings.link_rate; 539 link_lane_settings.link_settings.link_spread = 540 link->cur_link_settings.link_spread; 541 } 542 543 /* apply phy settings from user */ 544 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 545 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 546 (enum dc_voltage_swing) (param[0]); 547 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 548 (enum dc_pre_emphasis) (param[1]); 549 link_lane_settings.lane_settings[r].POST_CURSOR2 = 550 (enum dc_post_cursor2) (param[2]); 551 } 552 553 /* program ASIC registers and DPCD registers */ 554 dc_link_set_drive_settings(dc, &link_lane_settings, link); 555 556 kfree(wr_buf); 557 return size; 558 } 559 560 /* function description 561 * 562 * set PHY layer or Link layer test pattern 563 * PHY test pattern is used for PHY SI check. 564 * Link layer test will not affect PHY SI. 565 * 566 * Reset Test Pattern: 567 * 0 = DP_TEST_PATTERN_VIDEO_MODE 568 * 569 * PHY test pattern supported: 570 * 1 = DP_TEST_PATTERN_D102 571 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 572 * 3 = DP_TEST_PATTERN_PRBS7 573 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 574 * 5 = DP_TEST_PATTERN_CP2520_1 575 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 576 * 7 = DP_TEST_PATTERN_CP2520_3 577 * 578 * DP PHY Link Training Patterns 579 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 580 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 581 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 582 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 583 * 584 * DP Link Layer Test pattern 585 * c = DP_TEST_PATTERN_COLOR_SQUARES 586 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 587 * e = DP_TEST_PATTERN_VERTICAL_BARS 588 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 589 * 10= DP_TEST_PATTERN_COLOR_RAMP 590 * 591 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 592 * 593 * --- set test pattern 594 * echo <test pattern #> > test_pattern 595 * 596 * If test pattern # is not supported, NO HW programming will be done. 597 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 598 * for the user pattern. input 10 bytes data are separated by space 599 * 600 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 601 * 602 * --- reset test pattern 603 * echo 0 > test_pattern 604 * 605 * --- HPD detection is disabled when set PHY test pattern 606 * 607 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 608 * is disable. User could unplug DP display from DP connected and plug scope to 609 * check test pattern PHY SI. 610 * If there is need unplug scope and plug DP display back, do steps below: 611 * echo 0 > phy_test_pattern 612 * unplug scope 613 * plug DP display. 614 * 615 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 616 * driver could detect "unplug scope" and "plug DP display" 617 */ 618 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 619 size_t size, loff_t *pos) 620 { 621 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 622 struct dc_link *link = connector->dc_link; 623 char *wr_buf = NULL; 624 uint32_t wr_buf_size = 100; 625 long param[11] = {0x0}; 626 int max_param_num = 11; 627 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 628 bool disable_hpd = false; 629 bool valid_test_pattern = false; 630 uint8_t param_nums = 0; 631 /* init with default 80bit custom pattern */ 632 uint8_t custom_pattern[10] = { 633 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 634 0x1f, 0x7c, 0xf0, 0xc1, 0x07 635 }; 636 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 637 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 638 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 639 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 640 struct link_training_settings link_training_settings; 641 int i; 642 643 if (size == 0) 644 return -EINVAL; 645 646 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 647 if (!wr_buf) 648 return -ENOSPC; 649 650 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 651 (long *)param, buf, 652 max_param_num, 653 ¶m_nums)) { 654 kfree(wr_buf); 655 return -EINVAL; 656 } 657 658 if (param_nums <= 0) { 659 kfree(wr_buf); 660 DRM_DEBUG_DRIVER("user data not be read\n"); 661 return -EINVAL; 662 } 663 664 665 test_pattern = param[0]; 666 667 switch (test_pattern) { 668 case DP_TEST_PATTERN_VIDEO_MODE: 669 case DP_TEST_PATTERN_COLOR_SQUARES: 670 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 671 case DP_TEST_PATTERN_VERTICAL_BARS: 672 case DP_TEST_PATTERN_HORIZONTAL_BARS: 673 case DP_TEST_PATTERN_COLOR_RAMP: 674 valid_test_pattern = true; 675 break; 676 677 case DP_TEST_PATTERN_D102: 678 case DP_TEST_PATTERN_SYMBOL_ERROR: 679 case DP_TEST_PATTERN_PRBS7: 680 case DP_TEST_PATTERN_80BIT_CUSTOM: 681 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 682 case DP_TEST_PATTERN_TRAINING_PATTERN4: 683 disable_hpd = true; 684 valid_test_pattern = true; 685 break; 686 687 default: 688 valid_test_pattern = false; 689 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 690 break; 691 } 692 693 if (!valid_test_pattern) { 694 kfree(wr_buf); 695 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 696 return size; 697 } 698 699 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 700 for (i = 0; i < 10; i++) { 701 if ((uint8_t) param[i + 1] != 0x0) 702 break; 703 } 704 705 if (i < 10) { 706 /* not use default value */ 707 for (i = 0; i < 10; i++) 708 custom_pattern[i] = (uint8_t) param[i + 1]; 709 } 710 } 711 712 /* Usage: set DP physical test pattern using debugfs with normal DP 713 * panel. Then plug out DP panel and connect a scope to measure 714 * For normal video mode and test pattern generated from CRCT, 715 * they are visibile to user. So do not disable HPD. 716 * Video Mode is also set to clear the test pattern, so enable HPD 717 * because it might have been disabled after a test pattern was set. 718 * AUX depends on HPD * sequence dependent, do not move! 719 */ 720 if (!disable_hpd) 721 dc_link_enable_hpd(link); 722 723 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 724 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 725 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 726 727 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 728 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 729 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 730 731 link_training_settings.link_settings = cur_link_settings; 732 733 734 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 735 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 736 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 737 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 738 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 739 link_training_settings.link_settings = prefer_link_settings; 740 } 741 742 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 743 link_training_settings.lane_settings[i] = link->cur_lane_setting[i]; 744 745 dc_link_set_test_pattern( 746 link, 747 test_pattern, 748 DP_TEST_PATTERN_COLOR_SPACE_RGB, 749 &link_training_settings, 750 custom_pattern, 751 10); 752 753 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 754 * Then plug out DP panel and connect a scope to measure DP PHY signal. 755 * Need disable interrupt to avoid SW driver disable DP output. This is 756 * done after the test pattern is set. 757 */ 758 if (valid_test_pattern && disable_hpd) 759 dc_link_disable_hpd(link); 760 761 kfree(wr_buf); 762 763 return size; 764 } 765 766 /* 767 * Returns the DMCUB tracebuffer contents. 768 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 769 */ 770 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 771 { 772 struct amdgpu_device *adev = m->private; 773 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 774 struct dmub_debugfs_trace_entry *entries; 775 uint8_t *tbuf_base; 776 uint32_t tbuf_size, max_entries, num_entries, i; 777 778 if (!fb_info) 779 return 0; 780 781 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 782 if (!tbuf_base) 783 return 0; 784 785 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 786 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 787 sizeof(struct dmub_debugfs_trace_entry); 788 789 num_entries = 790 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 791 792 num_entries = min(num_entries, max_entries); 793 794 entries = (struct dmub_debugfs_trace_entry 795 *)(tbuf_base + 796 sizeof(struct dmub_debugfs_trace_header)); 797 798 for (i = 0; i < num_entries; ++i) { 799 struct dmub_debugfs_trace_entry *entry = &entries[i]; 800 801 seq_printf(m, 802 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 803 entry->trace_code, entry->tick_count, entry->param0, 804 entry->param1); 805 } 806 807 return 0; 808 } 809 810 /* 811 * Returns the DMCUB firmware state contents. 812 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 813 */ 814 static int dmub_fw_state_show(struct seq_file *m, void *data) 815 { 816 struct amdgpu_device *adev = m->private; 817 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 818 uint8_t *state_base; 819 uint32_t state_size; 820 821 if (!fb_info) 822 return 0; 823 824 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 825 if (!state_base) 826 return 0; 827 828 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 829 830 return seq_write(m, state_base, state_size); 831 } 832 833 /* psr_capability_show() - show eDP panel PSR capability 834 * 835 * The read function: sink_psr_capability_show 836 * Shows if sink has PSR capability or not. 837 * If yes - the PSR version is appended 838 * 839 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 840 * 841 * Expected output: 842 * "Sink support: no\n" - if panel doesn't support PSR 843 * "Sink support: yes [0x01]\n" - if panel supports PSR1 844 * "Driver support: no\n" - if driver doesn't support PSR 845 * "Driver support: yes [0x01]\n" - if driver supports PSR1 846 */ 847 static int psr_capability_show(struct seq_file *m, void *data) 848 { 849 struct drm_connector *connector = m->private; 850 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 851 struct dc_link *link = aconnector->dc_link; 852 853 if (!link) 854 return -ENODEV; 855 856 if (link->type == dc_connection_none) 857 return -ENODEV; 858 859 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 860 return -ENODEV; 861 862 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 863 if (link->dpcd_caps.psr_info.psr_version) 864 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 865 seq_puts(m, "\n"); 866 867 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 868 if (link->psr_settings.psr_version) 869 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 870 seq_puts(m, "\n"); 871 872 return 0; 873 } 874 875 /* 876 * Returns the current bpc for the crtc. 877 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 878 */ 879 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 880 { 881 struct drm_crtc *crtc = m->private; 882 struct drm_device *dev = crtc->dev; 883 struct dm_crtc_state *dm_crtc_state = NULL; 884 int res = -ENODEV; 885 unsigned int bpc; 886 887 mutex_lock(&dev->mode_config.mutex); 888 drm_modeset_lock(&crtc->mutex, NULL); 889 if (crtc->state == NULL) 890 goto unlock; 891 892 dm_crtc_state = to_dm_crtc_state(crtc->state); 893 if (dm_crtc_state->stream == NULL) 894 goto unlock; 895 896 switch (dm_crtc_state->stream->timing.display_color_depth) { 897 case COLOR_DEPTH_666: 898 bpc = 6; 899 break; 900 case COLOR_DEPTH_888: 901 bpc = 8; 902 break; 903 case COLOR_DEPTH_101010: 904 bpc = 10; 905 break; 906 case COLOR_DEPTH_121212: 907 bpc = 12; 908 break; 909 case COLOR_DEPTH_161616: 910 bpc = 16; 911 break; 912 default: 913 goto unlock; 914 } 915 916 seq_printf(m, "Current: %u\n", bpc); 917 res = 0; 918 919 unlock: 920 drm_modeset_unlock(&crtc->mutex); 921 mutex_unlock(&dev->mode_config.mutex); 922 923 return res; 924 } 925 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 926 927 /* 928 * Example usage: 929 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 930 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 931 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 932 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 933 */ 934 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 935 size_t size, loff_t *pos) 936 { 937 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 938 char *wr_buf = NULL; 939 uint32_t wr_buf_size = 42; 940 int max_param_num = 1; 941 long param; 942 uint8_t param_nums = 0; 943 944 if (size == 0) 945 return -EINVAL; 946 947 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 948 949 if (!wr_buf) { 950 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 951 return -ENOSPC; 952 } 953 954 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 955 ¶m, buf, 956 max_param_num, 957 ¶m_nums)) { 958 kfree(wr_buf); 959 return -EINVAL; 960 } 961 962 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 963 964 kfree(wr_buf); 965 return 0; 966 } 967 968 #ifdef CONFIG_DRM_AMD_DC_HDCP 969 /* 970 * Returns the HDCP capability of the Display (1.4 for now). 971 * 972 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 973 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 974 * 975 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 976 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 977 */ 978 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 979 { 980 struct drm_connector *connector = m->private; 981 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 982 bool hdcp_cap, hdcp2_cap; 983 984 if (connector->status != connector_status_connected) 985 return -ENODEV; 986 987 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 988 989 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 990 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 991 992 993 if (hdcp_cap) 994 seq_printf(m, "%s ", "HDCP1.4"); 995 if (hdcp2_cap) 996 seq_printf(m, "%s ", "HDCP2.2"); 997 998 if (!hdcp_cap && !hdcp2_cap) 999 seq_printf(m, "%s ", "None"); 1000 1001 seq_puts(m, "\n"); 1002 1003 return 0; 1004 } 1005 #endif 1006 1007 /* 1008 * Returns whether the connected display is internal and not hotpluggable. 1009 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1010 */ 1011 static int internal_display_show(struct seq_file *m, void *data) 1012 { 1013 struct drm_connector *connector = m->private; 1014 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1015 struct dc_link *link = aconnector->dc_link; 1016 1017 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1018 1019 return 0; 1020 } 1021 1022 /* function description 1023 * 1024 * generic SDP message access for testing 1025 * 1026 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1027 * 1028 * SDP header 1029 * Hb0 : Secondary-Data Packet ID 1030 * Hb1 : Secondary-Data Packet type 1031 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1032 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1033 * 1034 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1035 */ 1036 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1037 size_t size, loff_t *pos) 1038 { 1039 int r; 1040 uint8_t data[36]; 1041 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1042 struct dm_crtc_state *acrtc_state; 1043 uint32_t write_size = 36; 1044 1045 if (connector->base.status != connector_status_connected) 1046 return -ENODEV; 1047 1048 if (size == 0) 1049 return 0; 1050 1051 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1052 1053 r = copy_from_user(data, buf, write_size); 1054 1055 write_size -= r; 1056 1057 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1058 1059 return write_size; 1060 } 1061 1062 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1063 size_t size, loff_t *pos) 1064 { 1065 int r; 1066 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1067 1068 if (size < sizeof(connector->debugfs_dpcd_address)) 1069 return -EINVAL; 1070 1071 r = copy_from_user(&connector->debugfs_dpcd_address, 1072 buf, sizeof(connector->debugfs_dpcd_address)); 1073 1074 return size - r; 1075 } 1076 1077 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1078 size_t size, loff_t *pos) 1079 { 1080 int r; 1081 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1082 1083 if (size < sizeof(connector->debugfs_dpcd_size)) 1084 return -EINVAL; 1085 1086 r = copy_from_user(&connector->debugfs_dpcd_size, 1087 buf, sizeof(connector->debugfs_dpcd_size)); 1088 1089 if (connector->debugfs_dpcd_size > 256) 1090 connector->debugfs_dpcd_size = 0; 1091 1092 return size - r; 1093 } 1094 1095 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1096 size_t size, loff_t *pos) 1097 { 1098 int r; 1099 char *data; 1100 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1101 struct dc_link *link = connector->dc_link; 1102 uint32_t write_size = connector->debugfs_dpcd_size; 1103 1104 if (!write_size || size < write_size) 1105 return -EINVAL; 1106 1107 data = kzalloc(write_size, GFP_KERNEL); 1108 if (!data) 1109 return 0; 1110 1111 r = copy_from_user(data, buf, write_size); 1112 1113 dm_helpers_dp_write_dpcd(link->ctx, link, 1114 connector->debugfs_dpcd_address, data, write_size - r); 1115 kfree(data); 1116 return write_size - r; 1117 } 1118 1119 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1120 size_t size, loff_t *pos) 1121 { 1122 int r; 1123 char *data; 1124 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1125 struct dc_link *link = connector->dc_link; 1126 uint32_t read_size = connector->debugfs_dpcd_size; 1127 1128 if (!read_size || size < read_size) 1129 return 0; 1130 1131 data = kzalloc(read_size, GFP_KERNEL); 1132 if (!data) 1133 return 0; 1134 1135 dm_helpers_dp_read_dpcd(link->ctx, link, 1136 connector->debugfs_dpcd_address, data, read_size); 1137 1138 r = copy_to_user(buf, data, read_size); 1139 1140 kfree(data); 1141 return read_size - r; 1142 } 1143 1144 /* function: Read link's DSC & FEC capabilities 1145 * 1146 * 1147 * Access it with the following command (you need to specify 1148 * connector like DP-1): 1149 * 1150 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1151 * 1152 */ 1153 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1154 { 1155 struct drm_connector *connector = m->private; 1156 struct drm_modeset_acquire_ctx ctx; 1157 struct drm_device *dev = connector->dev; 1158 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1159 int ret = 0; 1160 bool try_again = false; 1161 bool is_fec_supported = false; 1162 bool is_dsc_supported = false; 1163 struct dpcd_caps dpcd_caps; 1164 1165 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1166 do { 1167 try_again = false; 1168 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1169 if (ret) { 1170 if (ret == -EDEADLK) { 1171 ret = drm_modeset_backoff(&ctx); 1172 if (!ret) { 1173 try_again = true; 1174 continue; 1175 } 1176 } 1177 break; 1178 } 1179 if (connector->status != connector_status_connected) { 1180 ret = -ENODEV; 1181 break; 1182 } 1183 dpcd_caps = aconnector->dc_link->dpcd_caps; 1184 if (aconnector->port) { 1185 /* aconnector sets dsc_aux during get_modes call 1186 * if MST connector has it means it can either 1187 * enable DSC on the sink device or on MST branch 1188 * its connected to. 1189 */ 1190 if (aconnector->dsc_aux) { 1191 is_fec_supported = true; 1192 is_dsc_supported = true; 1193 } 1194 } else { 1195 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1196 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1197 } 1198 } while (try_again); 1199 1200 drm_modeset_drop_locks(&ctx); 1201 drm_modeset_acquire_fini(&ctx); 1202 1203 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1204 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1205 1206 return ret; 1207 } 1208 1209 /* function: Trigger virtual HPD redetection on connector 1210 * 1211 * This function will perform link rediscovery, link disable 1212 * and enable, and dm connector state update. 1213 * 1214 * Retrigger HPD on an existing connector by echoing 1 into 1215 * its respectful "trigger_hotplug" debugfs entry: 1216 * 1217 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1218 * 1219 * This function can perform HPD unplug: 1220 * 1221 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1222 * 1223 */ 1224 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1225 size_t size, loff_t *pos) 1226 { 1227 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1228 struct drm_connector *connector = &aconnector->base; 1229 struct dc_link *link = NULL; 1230 struct drm_device *dev = connector->dev; 1231 enum dc_connection_type new_connection_type = dc_connection_none; 1232 char *wr_buf = NULL; 1233 uint32_t wr_buf_size = 42; 1234 int max_param_num = 1; 1235 long param[1] = {0}; 1236 uint8_t param_nums = 0; 1237 1238 if (!aconnector || !aconnector->dc_link) 1239 return -EINVAL; 1240 1241 if (size == 0) 1242 return -EINVAL; 1243 1244 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1245 1246 if (!wr_buf) { 1247 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1248 return -ENOSPC; 1249 } 1250 1251 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1252 (long *)param, buf, 1253 max_param_num, 1254 ¶m_nums)) { 1255 kfree(wr_buf); 1256 return -EINVAL; 1257 } 1258 1259 if (param_nums <= 0) { 1260 DRM_DEBUG_DRIVER("user data not be read\n"); 1261 kfree(wr_buf); 1262 return -EINVAL; 1263 } 1264 1265 if (param[0] == 1) { 1266 mutex_lock(&aconnector->hpd_lock); 1267 1268 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1269 new_connection_type != dc_connection_none) 1270 goto unlock; 1271 1272 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1273 goto unlock; 1274 1275 amdgpu_dm_update_connector_after_detect(aconnector); 1276 1277 drm_modeset_lock_all(dev); 1278 dm_restore_drm_connector_state(dev, connector); 1279 drm_modeset_unlock_all(dev); 1280 1281 drm_kms_helper_connector_hotplug_event(connector); 1282 } else if (param[0] == 0) { 1283 if (!aconnector->dc_link) 1284 goto unlock; 1285 1286 link = aconnector->dc_link; 1287 1288 if (link->local_sink) { 1289 dc_sink_release(link->local_sink); 1290 link->local_sink = NULL; 1291 } 1292 1293 link->dpcd_sink_count = 0; 1294 link->type = dc_connection_none; 1295 link->dongle_max_pix_clk = 0; 1296 1297 amdgpu_dm_update_connector_after_detect(aconnector); 1298 1299 drm_modeset_lock_all(dev); 1300 dm_restore_drm_connector_state(dev, connector); 1301 drm_modeset_unlock_all(dev); 1302 1303 drm_kms_helper_connector_hotplug_event(connector); 1304 } 1305 1306 unlock: 1307 mutex_unlock(&aconnector->hpd_lock); 1308 1309 kfree(wr_buf); 1310 return size; 1311 } 1312 1313 /* function: read DSC status on the connector 1314 * 1315 * The read function: dp_dsc_clock_en_read 1316 * returns current status of DSC clock on the connector. 1317 * The return is a boolean flag: 1 or 0. 1318 * 1319 * Access it with the following command (you need to specify 1320 * connector like DP-1): 1321 * 1322 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1323 * 1324 * Expected output: 1325 * 1 - means that DSC is currently enabled 1326 * 0 - means that DSC is disabled 1327 */ 1328 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1329 size_t size, loff_t *pos) 1330 { 1331 char *rd_buf = NULL; 1332 char *rd_buf_ptr = NULL; 1333 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1334 struct display_stream_compressor *dsc; 1335 struct dcn_dsc_state dsc_state = {0}; 1336 const uint32_t rd_buf_size = 10; 1337 struct pipe_ctx *pipe_ctx; 1338 ssize_t result = 0; 1339 int i, r, str_len = 30; 1340 1341 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1342 1343 if (!rd_buf) 1344 return -ENOMEM; 1345 1346 rd_buf_ptr = rd_buf; 1347 1348 for (i = 0; i < MAX_PIPES; i++) { 1349 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1350 if (pipe_ctx && pipe_ctx->stream && 1351 pipe_ctx->stream->link == aconnector->dc_link) 1352 break; 1353 } 1354 1355 if (!pipe_ctx) { 1356 kfree(rd_buf); 1357 return -ENXIO; 1358 } 1359 1360 dsc = pipe_ctx->stream_res.dsc; 1361 if (dsc) 1362 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1363 1364 snprintf(rd_buf_ptr, str_len, 1365 "%d\n", 1366 dsc_state.dsc_clock_en); 1367 rd_buf_ptr += str_len; 1368 1369 while (size) { 1370 if (*pos >= rd_buf_size) 1371 break; 1372 1373 r = put_user(*(rd_buf + result), buf); 1374 if (r) { 1375 kfree(rd_buf); 1376 return r; /* r = -EFAULT */ 1377 } 1378 1379 buf += 1; 1380 size -= 1; 1381 *pos += 1; 1382 result += 1; 1383 } 1384 1385 kfree(rd_buf); 1386 return result; 1387 } 1388 1389 /* function: write force DSC on the connector 1390 * 1391 * The write function: dp_dsc_clock_en_write 1392 * enables to force DSC on the connector. 1393 * User can write to either force enable or force disable DSC 1394 * on the next modeset or set it to driver default 1395 * 1396 * Accepted inputs: 1397 * 0 - default DSC enablement policy 1398 * 1 - force enable DSC on the connector 1399 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1400 * 1401 * Writing DSC settings is done with the following command: 1402 * - To force enable DSC (you need to specify 1403 * connector like DP-1): 1404 * 1405 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1406 * 1407 * - To return to default state set the flag to zero and 1408 * let driver deal with DSC automatically 1409 * (you need to specify connector like DP-1): 1410 * 1411 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1412 * 1413 */ 1414 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1415 size_t size, loff_t *pos) 1416 { 1417 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1418 struct drm_connector *connector = &aconnector->base; 1419 struct drm_device *dev = connector->dev; 1420 struct drm_crtc *crtc = NULL; 1421 struct dm_crtc_state *dm_crtc_state = NULL; 1422 struct pipe_ctx *pipe_ctx; 1423 int i; 1424 char *wr_buf = NULL; 1425 uint32_t wr_buf_size = 42; 1426 int max_param_num = 1; 1427 long param[1] = {0}; 1428 uint8_t param_nums = 0; 1429 1430 if (size == 0) 1431 return -EINVAL; 1432 1433 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1434 1435 if (!wr_buf) { 1436 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1437 return -ENOSPC; 1438 } 1439 1440 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1441 (long *)param, buf, 1442 max_param_num, 1443 ¶m_nums)) { 1444 kfree(wr_buf); 1445 return -EINVAL; 1446 } 1447 1448 if (param_nums <= 0) { 1449 DRM_DEBUG_DRIVER("user data not be read\n"); 1450 kfree(wr_buf); 1451 return -EINVAL; 1452 } 1453 1454 for (i = 0; i < MAX_PIPES; i++) { 1455 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1456 if (pipe_ctx && pipe_ctx->stream && 1457 pipe_ctx->stream->link == aconnector->dc_link) 1458 break; 1459 } 1460 1461 if (!pipe_ctx || !pipe_ctx->stream) 1462 goto done; 1463 1464 // Get CRTC state 1465 mutex_lock(&dev->mode_config.mutex); 1466 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1467 1468 if (connector->state == NULL) 1469 goto unlock; 1470 1471 crtc = connector->state->crtc; 1472 if (crtc == NULL) 1473 goto unlock; 1474 1475 drm_modeset_lock(&crtc->mutex, NULL); 1476 if (crtc->state == NULL) 1477 goto unlock; 1478 1479 dm_crtc_state = to_dm_crtc_state(crtc->state); 1480 if (dm_crtc_state->stream == NULL) 1481 goto unlock; 1482 1483 if (param[0] == 1) 1484 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1485 else if (param[0] == 2) 1486 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1487 else 1488 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1489 1490 dm_crtc_state->dsc_force_changed = true; 1491 1492 unlock: 1493 if (crtc) 1494 drm_modeset_unlock(&crtc->mutex); 1495 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1496 mutex_unlock(&dev->mode_config.mutex); 1497 1498 done: 1499 kfree(wr_buf); 1500 return size; 1501 } 1502 1503 /* function: read DSC slice width parameter on the connector 1504 * 1505 * The read function: dp_dsc_slice_width_read 1506 * returns dsc slice width used in the current configuration 1507 * The return is an integer: 0 or other positive number 1508 * 1509 * Access the status with the following command: 1510 * 1511 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1512 * 1513 * 0 - means that DSC is disabled 1514 * 1515 * Any other number more than zero represents the 1516 * slice width currently used by DSC in pixels 1517 * 1518 */ 1519 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1520 size_t size, loff_t *pos) 1521 { 1522 char *rd_buf = NULL; 1523 char *rd_buf_ptr = NULL; 1524 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1525 struct display_stream_compressor *dsc; 1526 struct dcn_dsc_state dsc_state = {0}; 1527 const uint32_t rd_buf_size = 100; 1528 struct pipe_ctx *pipe_ctx; 1529 ssize_t result = 0; 1530 int i, r, str_len = 30; 1531 1532 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1533 1534 if (!rd_buf) 1535 return -ENOMEM; 1536 1537 rd_buf_ptr = rd_buf; 1538 1539 for (i = 0; i < MAX_PIPES; i++) { 1540 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1541 if (pipe_ctx && pipe_ctx->stream && 1542 pipe_ctx->stream->link == aconnector->dc_link) 1543 break; 1544 } 1545 1546 if (!pipe_ctx) { 1547 kfree(rd_buf); 1548 return -ENXIO; 1549 } 1550 1551 dsc = pipe_ctx->stream_res.dsc; 1552 if (dsc) 1553 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1554 1555 snprintf(rd_buf_ptr, str_len, 1556 "%d\n", 1557 dsc_state.dsc_slice_width); 1558 rd_buf_ptr += str_len; 1559 1560 while (size) { 1561 if (*pos >= rd_buf_size) 1562 break; 1563 1564 r = put_user(*(rd_buf + result), buf); 1565 if (r) { 1566 kfree(rd_buf); 1567 return r; /* r = -EFAULT */ 1568 } 1569 1570 buf += 1; 1571 size -= 1; 1572 *pos += 1; 1573 result += 1; 1574 } 1575 1576 kfree(rd_buf); 1577 return result; 1578 } 1579 1580 /* function: write DSC slice width parameter 1581 * 1582 * The write function: dp_dsc_slice_width_write 1583 * overwrites automatically generated DSC configuration 1584 * of slice width. 1585 * 1586 * The user has to write the slice width divisible by the 1587 * picture width. 1588 * 1589 * Also the user has to write width in hexidecimal 1590 * rather than in decimal. 1591 * 1592 * Writing DSC settings is done with the following command: 1593 * - To force overwrite slice width: (example sets to 1920 pixels) 1594 * 1595 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1596 * 1597 * - To stop overwriting and let driver find the optimal size, 1598 * set the width to zero: 1599 * 1600 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1601 * 1602 */ 1603 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1604 size_t size, loff_t *pos) 1605 { 1606 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1607 struct pipe_ctx *pipe_ctx; 1608 struct drm_connector *connector = &aconnector->base; 1609 struct drm_device *dev = connector->dev; 1610 struct drm_crtc *crtc = NULL; 1611 struct dm_crtc_state *dm_crtc_state = NULL; 1612 int i; 1613 char *wr_buf = NULL; 1614 uint32_t wr_buf_size = 42; 1615 int max_param_num = 1; 1616 long param[1] = {0}; 1617 uint8_t param_nums = 0; 1618 1619 if (size == 0) 1620 return -EINVAL; 1621 1622 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1623 1624 if (!wr_buf) { 1625 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1626 return -ENOSPC; 1627 } 1628 1629 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1630 (long *)param, buf, 1631 max_param_num, 1632 ¶m_nums)) { 1633 kfree(wr_buf); 1634 return -EINVAL; 1635 } 1636 1637 if (param_nums <= 0) { 1638 DRM_DEBUG_DRIVER("user data not be read\n"); 1639 kfree(wr_buf); 1640 return -EINVAL; 1641 } 1642 1643 for (i = 0; i < MAX_PIPES; i++) { 1644 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1645 if (pipe_ctx && pipe_ctx->stream && 1646 pipe_ctx->stream->link == aconnector->dc_link) 1647 break; 1648 } 1649 1650 if (!pipe_ctx || !pipe_ctx->stream) 1651 goto done; 1652 1653 // Safely get CRTC state 1654 mutex_lock(&dev->mode_config.mutex); 1655 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1656 1657 if (connector->state == NULL) 1658 goto unlock; 1659 1660 crtc = connector->state->crtc; 1661 if (crtc == NULL) 1662 goto unlock; 1663 1664 drm_modeset_lock(&crtc->mutex, NULL); 1665 if (crtc->state == NULL) 1666 goto unlock; 1667 1668 dm_crtc_state = to_dm_crtc_state(crtc->state); 1669 if (dm_crtc_state->stream == NULL) 1670 goto unlock; 1671 1672 if (param[0] > 0) 1673 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1674 pipe_ctx->stream->timing.h_addressable, 1675 param[0]); 1676 else 1677 aconnector->dsc_settings.dsc_num_slices_h = 0; 1678 1679 dm_crtc_state->dsc_force_changed = true; 1680 1681 unlock: 1682 if (crtc) 1683 drm_modeset_unlock(&crtc->mutex); 1684 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1685 mutex_unlock(&dev->mode_config.mutex); 1686 1687 done: 1688 kfree(wr_buf); 1689 return size; 1690 } 1691 1692 /* function: read DSC slice height parameter on the connector 1693 * 1694 * The read function: dp_dsc_slice_height_read 1695 * returns dsc slice height used in the current configuration 1696 * The return is an integer: 0 or other positive number 1697 * 1698 * Access the status with the following command: 1699 * 1700 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1701 * 1702 * 0 - means that DSC is disabled 1703 * 1704 * Any other number more than zero represents the 1705 * slice height currently used by DSC in pixels 1706 * 1707 */ 1708 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1709 size_t size, loff_t *pos) 1710 { 1711 char *rd_buf = NULL; 1712 char *rd_buf_ptr = NULL; 1713 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1714 struct display_stream_compressor *dsc; 1715 struct dcn_dsc_state dsc_state = {0}; 1716 const uint32_t rd_buf_size = 100; 1717 struct pipe_ctx *pipe_ctx; 1718 ssize_t result = 0; 1719 int i, r, str_len = 30; 1720 1721 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1722 1723 if (!rd_buf) 1724 return -ENOMEM; 1725 1726 rd_buf_ptr = rd_buf; 1727 1728 for (i = 0; i < MAX_PIPES; i++) { 1729 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1730 if (pipe_ctx && pipe_ctx->stream && 1731 pipe_ctx->stream->link == aconnector->dc_link) 1732 break; 1733 } 1734 1735 if (!pipe_ctx) { 1736 kfree(rd_buf); 1737 return -ENXIO; 1738 } 1739 1740 dsc = pipe_ctx->stream_res.dsc; 1741 if (dsc) 1742 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1743 1744 snprintf(rd_buf_ptr, str_len, 1745 "%d\n", 1746 dsc_state.dsc_slice_height); 1747 rd_buf_ptr += str_len; 1748 1749 while (size) { 1750 if (*pos >= rd_buf_size) 1751 break; 1752 1753 r = put_user(*(rd_buf + result), buf); 1754 if (r) { 1755 kfree(rd_buf); 1756 return r; /* r = -EFAULT */ 1757 } 1758 1759 buf += 1; 1760 size -= 1; 1761 *pos += 1; 1762 result += 1; 1763 } 1764 1765 kfree(rd_buf); 1766 return result; 1767 } 1768 1769 /* function: write DSC slice height parameter 1770 * 1771 * The write function: dp_dsc_slice_height_write 1772 * overwrites automatically generated DSC configuration 1773 * of slice height. 1774 * 1775 * The user has to write the slice height divisible by the 1776 * picture height. 1777 * 1778 * Also the user has to write height in hexidecimal 1779 * rather than in decimal. 1780 * 1781 * Writing DSC settings is done with the following command: 1782 * - To force overwrite slice height (example sets to 128 pixels): 1783 * 1784 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1785 * 1786 * - To stop overwriting and let driver find the optimal size, 1787 * set the height to zero: 1788 * 1789 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1790 * 1791 */ 1792 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1793 size_t size, loff_t *pos) 1794 { 1795 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1796 struct drm_connector *connector = &aconnector->base; 1797 struct drm_device *dev = connector->dev; 1798 struct drm_crtc *crtc = NULL; 1799 struct dm_crtc_state *dm_crtc_state = NULL; 1800 struct pipe_ctx *pipe_ctx; 1801 int i; 1802 char *wr_buf = NULL; 1803 uint32_t wr_buf_size = 42; 1804 int max_param_num = 1; 1805 uint8_t param_nums = 0; 1806 long param[1] = {0}; 1807 1808 if (size == 0) 1809 return -EINVAL; 1810 1811 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1812 1813 if (!wr_buf) { 1814 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1815 return -ENOSPC; 1816 } 1817 1818 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1819 (long *)param, buf, 1820 max_param_num, 1821 ¶m_nums)) { 1822 kfree(wr_buf); 1823 return -EINVAL; 1824 } 1825 1826 if (param_nums <= 0) { 1827 DRM_DEBUG_DRIVER("user data not be read\n"); 1828 kfree(wr_buf); 1829 return -EINVAL; 1830 } 1831 1832 for (i = 0; i < MAX_PIPES; i++) { 1833 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1834 if (pipe_ctx && pipe_ctx->stream && 1835 pipe_ctx->stream->link == aconnector->dc_link) 1836 break; 1837 } 1838 1839 if (!pipe_ctx || !pipe_ctx->stream) 1840 goto done; 1841 1842 // Get CRTC state 1843 mutex_lock(&dev->mode_config.mutex); 1844 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1845 1846 if (connector->state == NULL) 1847 goto unlock; 1848 1849 crtc = connector->state->crtc; 1850 if (crtc == NULL) 1851 goto unlock; 1852 1853 drm_modeset_lock(&crtc->mutex, NULL); 1854 if (crtc->state == NULL) 1855 goto unlock; 1856 1857 dm_crtc_state = to_dm_crtc_state(crtc->state); 1858 if (dm_crtc_state->stream == NULL) 1859 goto unlock; 1860 1861 if (param[0] > 0) 1862 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1863 pipe_ctx->stream->timing.v_addressable, 1864 param[0]); 1865 else 1866 aconnector->dsc_settings.dsc_num_slices_v = 0; 1867 1868 dm_crtc_state->dsc_force_changed = true; 1869 1870 unlock: 1871 if (crtc) 1872 drm_modeset_unlock(&crtc->mutex); 1873 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1874 mutex_unlock(&dev->mode_config.mutex); 1875 1876 done: 1877 kfree(wr_buf); 1878 return size; 1879 } 1880 1881 /* function: read DSC target rate on the connector in bits per pixel 1882 * 1883 * The read function: dp_dsc_bits_per_pixel_read 1884 * returns target rate of compression in bits per pixel 1885 * The return is an integer: 0 or other positive integer 1886 * 1887 * Access it with the following command: 1888 * 1889 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1890 * 1891 * 0 - means that DSC is disabled 1892 */ 1893 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1894 size_t size, loff_t *pos) 1895 { 1896 char *rd_buf = NULL; 1897 char *rd_buf_ptr = NULL; 1898 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1899 struct display_stream_compressor *dsc; 1900 struct dcn_dsc_state dsc_state = {0}; 1901 const uint32_t rd_buf_size = 100; 1902 struct pipe_ctx *pipe_ctx; 1903 ssize_t result = 0; 1904 int i, r, str_len = 30; 1905 1906 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1907 1908 if (!rd_buf) 1909 return -ENOMEM; 1910 1911 rd_buf_ptr = rd_buf; 1912 1913 for (i = 0; i < MAX_PIPES; i++) { 1914 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1915 if (pipe_ctx && pipe_ctx->stream && 1916 pipe_ctx->stream->link == aconnector->dc_link) 1917 break; 1918 } 1919 1920 if (!pipe_ctx) { 1921 kfree(rd_buf); 1922 return -ENXIO; 1923 } 1924 1925 dsc = pipe_ctx->stream_res.dsc; 1926 if (dsc) 1927 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1928 1929 snprintf(rd_buf_ptr, str_len, 1930 "%d\n", 1931 dsc_state.dsc_bits_per_pixel); 1932 rd_buf_ptr += str_len; 1933 1934 while (size) { 1935 if (*pos >= rd_buf_size) 1936 break; 1937 1938 r = put_user(*(rd_buf + result), buf); 1939 if (r) { 1940 kfree(rd_buf); 1941 return r; /* r = -EFAULT */ 1942 } 1943 1944 buf += 1; 1945 size -= 1; 1946 *pos += 1; 1947 result += 1; 1948 } 1949 1950 kfree(rd_buf); 1951 return result; 1952 } 1953 1954 /* function: write DSC target rate in bits per pixel 1955 * 1956 * The write function: dp_dsc_bits_per_pixel_write 1957 * overwrites automatically generated DSC configuration 1958 * of DSC target bit rate. 1959 * 1960 * Also the user has to write bpp in hexidecimal 1961 * rather than in decimal. 1962 * 1963 * Writing DSC settings is done with the following command: 1964 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1965 * 1966 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1967 * 1968 * - To stop overwriting and let driver find the optimal rate, 1969 * set the rate to zero: 1970 * 1971 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1972 * 1973 */ 1974 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1975 size_t size, loff_t *pos) 1976 { 1977 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1978 struct drm_connector *connector = &aconnector->base; 1979 struct drm_device *dev = connector->dev; 1980 struct drm_crtc *crtc = NULL; 1981 struct dm_crtc_state *dm_crtc_state = NULL; 1982 struct pipe_ctx *pipe_ctx; 1983 int i; 1984 char *wr_buf = NULL; 1985 uint32_t wr_buf_size = 42; 1986 int max_param_num = 1; 1987 uint8_t param_nums = 0; 1988 long param[1] = {0}; 1989 1990 if (size == 0) 1991 return -EINVAL; 1992 1993 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1994 1995 if (!wr_buf) { 1996 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1997 return -ENOSPC; 1998 } 1999 2000 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2001 (long *)param, buf, 2002 max_param_num, 2003 ¶m_nums)) { 2004 kfree(wr_buf); 2005 return -EINVAL; 2006 } 2007 2008 if (param_nums <= 0) { 2009 DRM_DEBUG_DRIVER("user data not be read\n"); 2010 kfree(wr_buf); 2011 return -EINVAL; 2012 } 2013 2014 for (i = 0; i < MAX_PIPES; i++) { 2015 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2016 if (pipe_ctx && pipe_ctx->stream && 2017 pipe_ctx->stream->link == aconnector->dc_link) 2018 break; 2019 } 2020 2021 if (!pipe_ctx || !pipe_ctx->stream) 2022 goto done; 2023 2024 // Get CRTC state 2025 mutex_lock(&dev->mode_config.mutex); 2026 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2027 2028 if (connector->state == NULL) 2029 goto unlock; 2030 2031 crtc = connector->state->crtc; 2032 if (crtc == NULL) 2033 goto unlock; 2034 2035 drm_modeset_lock(&crtc->mutex, NULL); 2036 if (crtc->state == NULL) 2037 goto unlock; 2038 2039 dm_crtc_state = to_dm_crtc_state(crtc->state); 2040 if (dm_crtc_state->stream == NULL) 2041 goto unlock; 2042 2043 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2044 2045 dm_crtc_state->dsc_force_changed = true; 2046 2047 unlock: 2048 if (crtc) 2049 drm_modeset_unlock(&crtc->mutex); 2050 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2051 mutex_unlock(&dev->mode_config.mutex); 2052 2053 done: 2054 kfree(wr_buf); 2055 return size; 2056 } 2057 2058 /* function: read DSC picture width parameter on the connector 2059 * 2060 * The read function: dp_dsc_pic_width_read 2061 * returns dsc picture width used in the current configuration 2062 * It is the same as h_addressable of the current 2063 * display's timing 2064 * The return is an integer: 0 or other positive integer 2065 * If 0 then DSC is disabled. 2066 * 2067 * Access it with the following command: 2068 * 2069 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2070 * 2071 * 0 - means that DSC is disabled 2072 */ 2073 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2074 size_t size, loff_t *pos) 2075 { 2076 char *rd_buf = NULL; 2077 char *rd_buf_ptr = NULL; 2078 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2079 struct display_stream_compressor *dsc; 2080 struct dcn_dsc_state dsc_state = {0}; 2081 const uint32_t rd_buf_size = 100; 2082 struct pipe_ctx *pipe_ctx; 2083 ssize_t result = 0; 2084 int i, r, str_len = 30; 2085 2086 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2087 2088 if (!rd_buf) 2089 return -ENOMEM; 2090 2091 rd_buf_ptr = rd_buf; 2092 2093 for (i = 0; i < MAX_PIPES; i++) { 2094 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2095 if (pipe_ctx && pipe_ctx->stream && 2096 pipe_ctx->stream->link == aconnector->dc_link) 2097 break; 2098 } 2099 2100 if (!pipe_ctx) { 2101 kfree(rd_buf); 2102 return -ENXIO; 2103 } 2104 2105 dsc = pipe_ctx->stream_res.dsc; 2106 if (dsc) 2107 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2108 2109 snprintf(rd_buf_ptr, str_len, 2110 "%d\n", 2111 dsc_state.dsc_pic_width); 2112 rd_buf_ptr += str_len; 2113 2114 while (size) { 2115 if (*pos >= rd_buf_size) 2116 break; 2117 2118 r = put_user(*(rd_buf + result), buf); 2119 if (r) { 2120 kfree(rd_buf); 2121 return r; /* r = -EFAULT */ 2122 } 2123 2124 buf += 1; 2125 size -= 1; 2126 *pos += 1; 2127 result += 1; 2128 } 2129 2130 kfree(rd_buf); 2131 return result; 2132 } 2133 2134 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2135 size_t size, loff_t *pos) 2136 { 2137 char *rd_buf = NULL; 2138 char *rd_buf_ptr = NULL; 2139 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2140 struct display_stream_compressor *dsc; 2141 struct dcn_dsc_state dsc_state = {0}; 2142 const uint32_t rd_buf_size = 100; 2143 struct pipe_ctx *pipe_ctx; 2144 ssize_t result = 0; 2145 int i, r, str_len = 30; 2146 2147 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2148 2149 if (!rd_buf) 2150 return -ENOMEM; 2151 2152 rd_buf_ptr = rd_buf; 2153 2154 for (i = 0; i < MAX_PIPES; i++) { 2155 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2156 if (pipe_ctx && pipe_ctx->stream && 2157 pipe_ctx->stream->link == aconnector->dc_link) 2158 break; 2159 } 2160 2161 if (!pipe_ctx) { 2162 kfree(rd_buf); 2163 return -ENXIO; 2164 } 2165 2166 dsc = pipe_ctx->stream_res.dsc; 2167 if (dsc) 2168 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2169 2170 snprintf(rd_buf_ptr, str_len, 2171 "%d\n", 2172 dsc_state.dsc_pic_height); 2173 rd_buf_ptr += str_len; 2174 2175 while (size) { 2176 if (*pos >= rd_buf_size) 2177 break; 2178 2179 r = put_user(*(rd_buf + result), buf); 2180 if (r) { 2181 kfree(rd_buf); 2182 return r; /* r = -EFAULT */ 2183 } 2184 2185 buf += 1; 2186 size -= 1; 2187 *pos += 1; 2188 result += 1; 2189 } 2190 2191 kfree(rd_buf); 2192 return result; 2193 } 2194 2195 /* function: read DSC chunk size parameter on the connector 2196 * 2197 * The read function: dp_dsc_chunk_size_read 2198 * returns dsc chunk size set in the current configuration 2199 * The value is calculated automatically by DSC code 2200 * and depends on slice parameters and bpp target rate 2201 * The return is an integer: 0 or other positive integer 2202 * If 0 then DSC is disabled. 2203 * 2204 * Access it with the following command: 2205 * 2206 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2207 * 2208 * 0 - means that DSC is disabled 2209 */ 2210 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2211 size_t size, loff_t *pos) 2212 { 2213 char *rd_buf = NULL; 2214 char *rd_buf_ptr = NULL; 2215 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2216 struct display_stream_compressor *dsc; 2217 struct dcn_dsc_state dsc_state = {0}; 2218 const uint32_t rd_buf_size = 100; 2219 struct pipe_ctx *pipe_ctx; 2220 ssize_t result = 0; 2221 int i, r, str_len = 30; 2222 2223 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2224 2225 if (!rd_buf) 2226 return -ENOMEM; 2227 2228 rd_buf_ptr = rd_buf; 2229 2230 for (i = 0; i < MAX_PIPES; i++) { 2231 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2232 if (pipe_ctx && pipe_ctx->stream && 2233 pipe_ctx->stream->link == aconnector->dc_link) 2234 break; 2235 } 2236 2237 if (!pipe_ctx) { 2238 kfree(rd_buf); 2239 return -ENXIO; 2240 } 2241 2242 dsc = pipe_ctx->stream_res.dsc; 2243 if (dsc) 2244 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2245 2246 snprintf(rd_buf_ptr, str_len, 2247 "%d\n", 2248 dsc_state.dsc_chunk_size); 2249 rd_buf_ptr += str_len; 2250 2251 while (size) { 2252 if (*pos >= rd_buf_size) 2253 break; 2254 2255 r = put_user(*(rd_buf + result), buf); 2256 if (r) { 2257 kfree(rd_buf); 2258 return r; /* r = -EFAULT */ 2259 } 2260 2261 buf += 1; 2262 size -= 1; 2263 *pos += 1; 2264 result += 1; 2265 } 2266 2267 kfree(rd_buf); 2268 return result; 2269 } 2270 2271 /* function: read DSC slice bpg offset on the connector 2272 * 2273 * The read function: dp_dsc_slice_bpg_offset_read 2274 * returns dsc bpg slice offset set in the current configuration 2275 * The value is calculated automatically by DSC code 2276 * and depends on slice parameters and bpp target rate 2277 * The return is an integer: 0 or other positive integer 2278 * If 0 then DSC is disabled. 2279 * 2280 * Access it with the following command: 2281 * 2282 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2283 * 2284 * 0 - means that DSC is disabled 2285 */ 2286 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2287 size_t size, loff_t *pos) 2288 { 2289 char *rd_buf = NULL; 2290 char *rd_buf_ptr = NULL; 2291 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2292 struct display_stream_compressor *dsc; 2293 struct dcn_dsc_state dsc_state = {0}; 2294 const uint32_t rd_buf_size = 100; 2295 struct pipe_ctx *pipe_ctx; 2296 ssize_t result = 0; 2297 int i, r, str_len = 30; 2298 2299 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2300 2301 if (!rd_buf) 2302 return -ENOMEM; 2303 2304 rd_buf_ptr = rd_buf; 2305 2306 for (i = 0; i < MAX_PIPES; i++) { 2307 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2308 if (pipe_ctx && pipe_ctx->stream && 2309 pipe_ctx->stream->link == aconnector->dc_link) 2310 break; 2311 } 2312 2313 if (!pipe_ctx) { 2314 kfree(rd_buf); 2315 return -ENXIO; 2316 } 2317 2318 dsc = pipe_ctx->stream_res.dsc; 2319 if (dsc) 2320 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2321 2322 snprintf(rd_buf_ptr, str_len, 2323 "%d\n", 2324 dsc_state.dsc_slice_bpg_offset); 2325 rd_buf_ptr += str_len; 2326 2327 while (size) { 2328 if (*pos >= rd_buf_size) 2329 break; 2330 2331 r = put_user(*(rd_buf + result), buf); 2332 if (r) { 2333 kfree(rd_buf); 2334 return r; /* r = -EFAULT */ 2335 } 2336 2337 buf += 1; 2338 size -= 1; 2339 *pos += 1; 2340 result += 1; 2341 } 2342 2343 kfree(rd_buf); 2344 return result; 2345 } 2346 2347 2348 /* 2349 * function description: Read max_requested_bpc property from the connector 2350 * 2351 * Access it with the following command: 2352 * 2353 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2354 * 2355 */ 2356 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2357 size_t size, loff_t *pos) 2358 { 2359 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2360 struct drm_connector *connector = &aconnector->base; 2361 struct drm_device *dev = connector->dev; 2362 struct dm_connector_state *state; 2363 ssize_t result = 0; 2364 char *rd_buf = NULL; 2365 char *rd_buf_ptr = NULL; 2366 const uint32_t rd_buf_size = 10; 2367 int r; 2368 2369 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2370 2371 if (!rd_buf) 2372 return -ENOMEM; 2373 2374 mutex_lock(&dev->mode_config.mutex); 2375 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2376 2377 if (connector->state == NULL) 2378 goto unlock; 2379 2380 state = to_dm_connector_state(connector->state); 2381 2382 rd_buf_ptr = rd_buf; 2383 snprintf(rd_buf_ptr, rd_buf_size, 2384 "%u\n", 2385 state->base.max_requested_bpc); 2386 2387 while (size) { 2388 if (*pos >= rd_buf_size) 2389 break; 2390 2391 r = put_user(*(rd_buf + result), buf); 2392 if (r) { 2393 result = r; /* r = -EFAULT */ 2394 goto unlock; 2395 } 2396 buf += 1; 2397 size -= 1; 2398 *pos += 1; 2399 result += 1; 2400 } 2401 unlock: 2402 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2403 mutex_unlock(&dev->mode_config.mutex); 2404 kfree(rd_buf); 2405 return result; 2406 } 2407 2408 2409 /* 2410 * function description: Set max_requested_bpc property on the connector 2411 * 2412 * This function will not force the input BPC on connector, it will only 2413 * change the max value. This is equivalent to setting max_bpc through 2414 * xrandr. 2415 * 2416 * The BPC value written must be >= 6 and <= 16. Values outside of this 2417 * range will result in errors. 2418 * 2419 * BPC values: 2420 * 0x6 - 6 BPC 2421 * 0x8 - 8 BPC 2422 * 0xa - 10 BPC 2423 * 0xc - 12 BPC 2424 * 0x10 - 16 BPC 2425 * 2426 * Write the max_bpc in the following way: 2427 * 2428 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2429 * 2430 */ 2431 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2432 size_t size, loff_t *pos) 2433 { 2434 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2435 struct drm_connector *connector = &aconnector->base; 2436 struct dm_connector_state *state; 2437 struct drm_device *dev = connector->dev; 2438 char *wr_buf = NULL; 2439 uint32_t wr_buf_size = 42; 2440 int max_param_num = 1; 2441 long param[1] = {0}; 2442 uint8_t param_nums = 0; 2443 2444 if (size == 0) 2445 return -EINVAL; 2446 2447 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2448 2449 if (!wr_buf) { 2450 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2451 return -ENOSPC; 2452 } 2453 2454 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2455 (long *)param, buf, 2456 max_param_num, 2457 ¶m_nums)) { 2458 kfree(wr_buf); 2459 return -EINVAL; 2460 } 2461 2462 if (param_nums <= 0) { 2463 DRM_DEBUG_DRIVER("user data not be read\n"); 2464 kfree(wr_buf); 2465 return -EINVAL; 2466 } 2467 2468 if (param[0] < 6 || param[0] > 16) { 2469 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2470 kfree(wr_buf); 2471 return -EINVAL; 2472 } 2473 2474 mutex_lock(&dev->mode_config.mutex); 2475 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2476 2477 if (connector->state == NULL) 2478 goto unlock; 2479 2480 state = to_dm_connector_state(connector->state); 2481 state->base.max_requested_bpc = param[0]; 2482 unlock: 2483 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2484 mutex_unlock(&dev->mode_config.mutex); 2485 2486 kfree(wr_buf); 2487 return size; 2488 } 2489 2490 /* 2491 * Backlight at this moment. Read only. 2492 * As written to display, taking ABM and backlight lut into account. 2493 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2494 * 2495 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2496 */ 2497 static int current_backlight_show(struct seq_file *m, void *unused) 2498 { 2499 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2500 struct dc_link *link = aconnector->dc_link; 2501 unsigned int backlight; 2502 2503 backlight = dc_link_get_backlight_level(link); 2504 seq_printf(m, "0x%x\n", backlight); 2505 2506 return 0; 2507 } 2508 2509 /* 2510 * Backlight value that is being approached. Read only. 2511 * As written to display, taking ABM and backlight lut into account. 2512 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2513 * 2514 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2515 */ 2516 static int target_backlight_show(struct seq_file *m, void *unused) 2517 { 2518 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2519 struct dc_link *link = aconnector->dc_link; 2520 unsigned int backlight; 2521 2522 backlight = dc_link_get_target_backlight_pwm(link); 2523 seq_printf(m, "0x%x\n", backlight); 2524 2525 return 0; 2526 } 2527 2528 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2529 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2530 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2531 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2532 #ifdef CONFIG_DRM_AMD_DC_HDCP 2533 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2534 #endif 2535 DEFINE_SHOW_ATTRIBUTE(internal_display); 2536 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2537 2538 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2539 .owner = THIS_MODULE, 2540 .read = dp_dsc_clock_en_read, 2541 .write = dp_dsc_clock_en_write, 2542 .llseek = default_llseek 2543 }; 2544 2545 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2546 .owner = THIS_MODULE, 2547 .read = dp_dsc_slice_width_read, 2548 .write = dp_dsc_slice_width_write, 2549 .llseek = default_llseek 2550 }; 2551 2552 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2553 .owner = THIS_MODULE, 2554 .read = dp_dsc_slice_height_read, 2555 .write = dp_dsc_slice_height_write, 2556 .llseek = default_llseek 2557 }; 2558 2559 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2560 .owner = THIS_MODULE, 2561 .read = dp_dsc_bits_per_pixel_read, 2562 .write = dp_dsc_bits_per_pixel_write, 2563 .llseek = default_llseek 2564 }; 2565 2566 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2567 .owner = THIS_MODULE, 2568 .read = dp_dsc_pic_width_read, 2569 .llseek = default_llseek 2570 }; 2571 2572 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2573 .owner = THIS_MODULE, 2574 .read = dp_dsc_pic_height_read, 2575 .llseek = default_llseek 2576 }; 2577 2578 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2579 .owner = THIS_MODULE, 2580 .read = dp_dsc_chunk_size_read, 2581 .llseek = default_llseek 2582 }; 2583 2584 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2585 .owner = THIS_MODULE, 2586 .read = dp_dsc_slice_bpg_offset_read, 2587 .llseek = default_llseek 2588 }; 2589 2590 static const struct file_operations trigger_hotplug_debugfs_fops = { 2591 .owner = THIS_MODULE, 2592 .write = trigger_hotplug, 2593 .llseek = default_llseek 2594 }; 2595 2596 static const struct file_operations dp_link_settings_debugfs_fops = { 2597 .owner = THIS_MODULE, 2598 .read = dp_link_settings_read, 2599 .write = dp_link_settings_write, 2600 .llseek = default_llseek 2601 }; 2602 2603 static const struct file_operations dp_phy_settings_debugfs_fop = { 2604 .owner = THIS_MODULE, 2605 .read = dp_phy_settings_read, 2606 .write = dp_phy_settings_write, 2607 .llseek = default_llseek 2608 }; 2609 2610 static const struct file_operations dp_phy_test_pattern_fops = { 2611 .owner = THIS_MODULE, 2612 .write = dp_phy_test_pattern_debugfs_write, 2613 .llseek = default_llseek 2614 }; 2615 2616 static const struct file_operations sdp_message_fops = { 2617 .owner = THIS_MODULE, 2618 .write = dp_sdp_message_debugfs_write, 2619 .llseek = default_llseek 2620 }; 2621 2622 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2623 .owner = THIS_MODULE, 2624 .write = dp_dpcd_address_write, 2625 .llseek = default_llseek 2626 }; 2627 2628 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2629 .owner = THIS_MODULE, 2630 .write = dp_dpcd_size_write, 2631 .llseek = default_llseek 2632 }; 2633 2634 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2635 .owner = THIS_MODULE, 2636 .read = dp_dpcd_data_read, 2637 .write = dp_dpcd_data_write, 2638 .llseek = default_llseek 2639 }; 2640 2641 static const struct file_operations dp_max_bpc_debugfs_fops = { 2642 .owner = THIS_MODULE, 2643 .read = dp_max_bpc_read, 2644 .write = dp_max_bpc_write, 2645 .llseek = default_llseek 2646 }; 2647 2648 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2649 .owner = THIS_MODULE, 2650 .write = dp_dsc_passthrough_set, 2651 .llseek = default_llseek 2652 }; 2653 2654 static const struct { 2655 char *name; 2656 const struct file_operations *fops; 2657 } dp_debugfs_entries[] = { 2658 {"link_settings", &dp_link_settings_debugfs_fops}, 2659 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2660 {"lttpr_status", &dp_lttpr_status_fops}, 2661 {"test_pattern", &dp_phy_test_pattern_fops}, 2662 #ifdef CONFIG_DRM_AMD_DC_HDCP 2663 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2664 #endif 2665 {"sdp_message", &sdp_message_fops}, 2666 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2667 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2668 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2669 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2670 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2671 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2672 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2673 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2674 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2675 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2676 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2677 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2678 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2679 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2680 }; 2681 2682 #ifdef CONFIG_DRM_AMD_DC_HDCP 2683 static const struct { 2684 char *name; 2685 const struct file_operations *fops; 2686 } hdmi_debugfs_entries[] = { 2687 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2688 }; 2689 #endif 2690 /* 2691 * Force YUV420 output if available from the given mode 2692 */ 2693 static int force_yuv420_output_set(void *data, u64 val) 2694 { 2695 struct amdgpu_dm_connector *connector = data; 2696 2697 connector->force_yuv420_output = (bool)val; 2698 2699 return 0; 2700 } 2701 2702 /* 2703 * Check if YUV420 is forced when available from the given mode 2704 */ 2705 static int force_yuv420_output_get(void *data, u64 *val) 2706 { 2707 struct amdgpu_dm_connector *connector = data; 2708 2709 *val = connector->force_yuv420_output; 2710 2711 return 0; 2712 } 2713 2714 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2715 force_yuv420_output_set, "%llu\n"); 2716 2717 /* 2718 * Read PSR state 2719 */ 2720 static int psr_get(void *data, u64 *val) 2721 { 2722 struct amdgpu_dm_connector *connector = data; 2723 struct dc_link *link = connector->dc_link; 2724 enum dc_psr_state state = PSR_STATE0; 2725 2726 dc_link_get_psr_state(link, &state); 2727 2728 *val = state; 2729 2730 return 0; 2731 } 2732 2733 /* 2734 * Set dmcub trace event IRQ enable or disable. 2735 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2736 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2737 */ 2738 static int dmcub_trace_event_state_set(void *data, u64 val) 2739 { 2740 struct amdgpu_device *adev = data; 2741 2742 if (val == 1 || val == 0) { 2743 dc_dmub_trace_event_control(adev->dm.dc, val); 2744 adev->dm.dmcub_trace_event_en = (bool)val; 2745 } else 2746 return 0; 2747 2748 return 0; 2749 } 2750 2751 /* 2752 * The interface doesn't need get function, so it will return the 2753 * value of zero 2754 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2755 */ 2756 static int dmcub_trace_event_state_get(void *data, u64 *val) 2757 { 2758 struct amdgpu_device *adev = data; 2759 2760 *val = adev->dm.dmcub_trace_event_en; 2761 return 0; 2762 } 2763 2764 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2765 dmcub_trace_event_state_set, "%llu\n"); 2766 2767 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2768 2769 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2770 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2771 2772 static const struct { 2773 char *name; 2774 const struct file_operations *fops; 2775 } connector_debugfs_entries[] = { 2776 {"force_yuv420_output", &force_yuv420_output_fops}, 2777 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2778 {"internal_display", &internal_display_fops} 2779 }; 2780 2781 /* 2782 * Returns supported customized link rates by this eDP panel. 2783 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2784 */ 2785 static int edp_ilr_show(struct seq_file *m, void *unused) 2786 { 2787 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2788 struct dc_link *link = aconnector->dc_link; 2789 uint8_t supported_link_rates[16]; 2790 uint32_t link_rate_in_khz; 2791 uint32_t entry = 0; 2792 uint8_t dpcd_rev; 2793 2794 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2795 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2796 supported_link_rates, sizeof(supported_link_rates)); 2797 2798 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2799 2800 if (dpcd_rev >= DP_DPCD_REV_13 && 2801 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2802 2803 for (entry = 0; entry < 16; entry += 2) { 2804 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2805 supported_link_rates[entry]) * 200; 2806 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2807 } 2808 } else { 2809 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2810 } 2811 2812 return 0; 2813 } 2814 2815 /* 2816 * Set supported customized link rate to eDP panel. 2817 * 2818 * echo <lane_count> <link_rate option> > ilr_setting 2819 * 2820 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2821 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2822 * to set 4 lanes and 2.16 GHz 2823 */ 2824 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2825 size_t size, loff_t *pos) 2826 { 2827 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2828 struct dc_link *link = connector->dc_link; 2829 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2830 struct dc *dc = (struct dc *)link->dc; 2831 struct dc_link_settings prefer_link_settings; 2832 char *wr_buf = NULL; 2833 const uint32_t wr_buf_size = 40; 2834 /* 0: lane_count; 1: link_rate */ 2835 int max_param_num = 2; 2836 uint8_t param_nums = 0; 2837 long param[2]; 2838 bool valid_input = true; 2839 2840 if (size == 0) 2841 return -EINVAL; 2842 2843 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2844 if (!wr_buf) 2845 return -ENOMEM; 2846 2847 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2848 (long *)param, buf, 2849 max_param_num, 2850 ¶m_nums)) { 2851 kfree(wr_buf); 2852 return -EINVAL; 2853 } 2854 2855 if (param_nums <= 0) { 2856 kfree(wr_buf); 2857 return -EINVAL; 2858 } 2859 2860 switch (param[0]) { 2861 case LANE_COUNT_ONE: 2862 case LANE_COUNT_TWO: 2863 case LANE_COUNT_FOUR: 2864 break; 2865 default: 2866 valid_input = false; 2867 break; 2868 } 2869 2870 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2871 valid_input = false; 2872 2873 if (!valid_input) { 2874 kfree(wr_buf); 2875 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2876 prefer_link_settings.use_link_rate_set = false; 2877 mutex_lock(&adev->dm.dc_lock); 2878 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2879 mutex_unlock(&adev->dm.dc_lock); 2880 return size; 2881 } 2882 2883 /* save user force lane_count, link_rate to preferred settings 2884 * spread spectrum will not be changed 2885 */ 2886 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2887 prefer_link_settings.lane_count = param[0]; 2888 prefer_link_settings.use_link_rate_set = true; 2889 prefer_link_settings.link_rate_set = param[1]; 2890 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2891 2892 mutex_lock(&adev->dm.dc_lock); 2893 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2894 NULL, link, false); 2895 mutex_unlock(&adev->dm.dc_lock); 2896 2897 kfree(wr_buf); 2898 return size; 2899 } 2900 2901 static int edp_ilr_open(struct inode *inode, struct file *file) 2902 { 2903 return single_open(file, edp_ilr_show, inode->i_private); 2904 } 2905 2906 static const struct file_operations edp_ilr_debugfs_fops = { 2907 .owner = THIS_MODULE, 2908 .open = edp_ilr_open, 2909 .read = seq_read, 2910 .llseek = seq_lseek, 2911 .release = single_release, 2912 .write = edp_ilr_write 2913 }; 2914 2915 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2916 { 2917 int i; 2918 struct dentry *dir = connector->base.debugfs_entry; 2919 2920 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2921 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2922 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2923 debugfs_create_file(dp_debugfs_entries[i].name, 2924 0644, dir, connector, 2925 dp_debugfs_entries[i].fops); 2926 } 2927 } 2928 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2929 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 2930 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2931 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2932 ¤t_backlight_fops); 2933 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2934 &target_backlight_fops); 2935 debugfs_create_file("ilr_setting", 0644, dir, connector, 2936 &edp_ilr_debugfs_fops); 2937 } 2938 2939 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2940 debugfs_create_file(connector_debugfs_entries[i].name, 2941 0644, dir, connector, 2942 connector_debugfs_entries[i].fops); 2943 } 2944 2945 connector->debugfs_dpcd_address = 0; 2946 connector->debugfs_dpcd_size = 0; 2947 2948 #ifdef CONFIG_DRM_AMD_DC_HDCP 2949 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2950 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2951 debugfs_create_file(hdmi_debugfs_entries[i].name, 2952 0644, dir, connector, 2953 hdmi_debugfs_entries[i].fops); 2954 } 2955 } 2956 #endif 2957 } 2958 2959 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2960 /* 2961 * Set crc window coordinate x start 2962 */ 2963 static int crc_win_x_start_set(void *data, u64 val) 2964 { 2965 struct drm_crtc *crtc = data; 2966 struct drm_device *drm_dev = crtc->dev; 2967 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2968 2969 spin_lock_irq(&drm_dev->event_lock); 2970 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2971 acrtc->dm_irq_params.crc_window.update_win = false; 2972 spin_unlock_irq(&drm_dev->event_lock); 2973 2974 return 0; 2975 } 2976 2977 /* 2978 * Get crc window coordinate x start 2979 */ 2980 static int crc_win_x_start_get(void *data, u64 *val) 2981 { 2982 struct drm_crtc *crtc = data; 2983 struct drm_device *drm_dev = crtc->dev; 2984 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2985 2986 spin_lock_irq(&drm_dev->event_lock); 2987 *val = acrtc->dm_irq_params.crc_window.x_start; 2988 spin_unlock_irq(&drm_dev->event_lock); 2989 2990 return 0; 2991 } 2992 2993 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 2994 crc_win_x_start_set, "%llu\n"); 2995 2996 2997 /* 2998 * Set crc window coordinate y start 2999 */ 3000 static int crc_win_y_start_set(void *data, u64 val) 3001 { 3002 struct drm_crtc *crtc = data; 3003 struct drm_device *drm_dev = crtc->dev; 3004 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3005 3006 spin_lock_irq(&drm_dev->event_lock); 3007 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 3008 acrtc->dm_irq_params.crc_window.update_win = false; 3009 spin_unlock_irq(&drm_dev->event_lock); 3010 3011 return 0; 3012 } 3013 3014 /* 3015 * Get crc window coordinate y start 3016 */ 3017 static int crc_win_y_start_get(void *data, u64 *val) 3018 { 3019 struct drm_crtc *crtc = data; 3020 struct drm_device *drm_dev = crtc->dev; 3021 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3022 3023 spin_lock_irq(&drm_dev->event_lock); 3024 *val = acrtc->dm_irq_params.crc_window.y_start; 3025 spin_unlock_irq(&drm_dev->event_lock); 3026 3027 return 0; 3028 } 3029 3030 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3031 crc_win_y_start_set, "%llu\n"); 3032 3033 /* 3034 * Set crc window coordinate x end 3035 */ 3036 static int crc_win_x_end_set(void *data, u64 val) 3037 { 3038 struct drm_crtc *crtc = data; 3039 struct drm_device *drm_dev = crtc->dev; 3040 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3041 3042 spin_lock_irq(&drm_dev->event_lock); 3043 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 3044 acrtc->dm_irq_params.crc_window.update_win = false; 3045 spin_unlock_irq(&drm_dev->event_lock); 3046 3047 return 0; 3048 } 3049 3050 /* 3051 * Get crc window coordinate x end 3052 */ 3053 static int crc_win_x_end_get(void *data, u64 *val) 3054 { 3055 struct drm_crtc *crtc = data; 3056 struct drm_device *drm_dev = crtc->dev; 3057 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3058 3059 spin_lock_irq(&drm_dev->event_lock); 3060 *val = acrtc->dm_irq_params.crc_window.x_end; 3061 spin_unlock_irq(&drm_dev->event_lock); 3062 3063 return 0; 3064 } 3065 3066 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3067 crc_win_x_end_set, "%llu\n"); 3068 3069 /* 3070 * Set crc window coordinate y end 3071 */ 3072 static int crc_win_y_end_set(void *data, u64 val) 3073 { 3074 struct drm_crtc *crtc = data; 3075 struct drm_device *drm_dev = crtc->dev; 3076 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3077 3078 spin_lock_irq(&drm_dev->event_lock); 3079 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 3080 acrtc->dm_irq_params.crc_window.update_win = false; 3081 spin_unlock_irq(&drm_dev->event_lock); 3082 3083 return 0; 3084 } 3085 3086 /* 3087 * Get crc window coordinate y end 3088 */ 3089 static int crc_win_y_end_get(void *data, u64 *val) 3090 { 3091 struct drm_crtc *crtc = data; 3092 struct drm_device *drm_dev = crtc->dev; 3093 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3094 3095 spin_lock_irq(&drm_dev->event_lock); 3096 *val = acrtc->dm_irq_params.crc_window.y_end; 3097 spin_unlock_irq(&drm_dev->event_lock); 3098 3099 return 0; 3100 } 3101 3102 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3103 crc_win_y_end_set, "%llu\n"); 3104 /* 3105 * Trigger to commit crc window 3106 */ 3107 static int crc_win_update_set(void *data, u64 val) 3108 { 3109 struct drm_crtc *new_crtc = data; 3110 struct drm_crtc *old_crtc = NULL; 3111 struct amdgpu_crtc *new_acrtc, *old_acrtc; 3112 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 3113 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 3114 3115 if (!crc_rd_wrk) 3116 return 0; 3117 3118 if (val) { 3119 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3120 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 3121 if (crc_rd_wrk->crtc) { 3122 old_crtc = crc_rd_wrk->crtc; 3123 old_acrtc = to_amdgpu_crtc(old_crtc); 3124 } 3125 new_acrtc = to_amdgpu_crtc(new_crtc); 3126 3127 if (old_crtc && old_crtc != new_crtc) { 3128 old_acrtc->dm_irq_params.crc_window.activated = false; 3129 old_acrtc->dm_irq_params.crc_window.update_win = false; 3130 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3131 3132 new_acrtc->dm_irq_params.crc_window.activated = true; 3133 new_acrtc->dm_irq_params.crc_window.update_win = true; 3134 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3135 crc_rd_wrk->crtc = new_crtc; 3136 } else { 3137 new_acrtc->dm_irq_params.crc_window.activated = true; 3138 new_acrtc->dm_irq_params.crc_window.update_win = true; 3139 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3140 crc_rd_wrk->crtc = new_crtc; 3141 } 3142 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 3143 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3144 } 3145 3146 return 0; 3147 } 3148 3149 /* 3150 * Get crc window update flag 3151 */ 3152 static int crc_win_update_get(void *data, u64 *val) 3153 { 3154 *val = 0; 3155 return 0; 3156 } 3157 3158 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3159 crc_win_update_set, "%llu\n"); 3160 #endif 3161 void crtc_debugfs_init(struct drm_crtc *crtc) 3162 { 3163 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3164 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3165 3166 if (!dir) 3167 return; 3168 3169 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3170 &crc_win_x_start_fops); 3171 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3172 &crc_win_y_start_fops); 3173 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3174 &crc_win_x_end_fops); 3175 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3176 &crc_win_y_end_fops); 3177 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3178 &crc_win_update_fops); 3179 #endif 3180 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3181 crtc, &amdgpu_current_bpc_fops); 3182 } 3183 3184 /* 3185 * Writes DTN log state to the user supplied buffer. 3186 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3187 */ 3188 static ssize_t dtn_log_read( 3189 struct file *f, 3190 char __user *buf, 3191 size_t size, 3192 loff_t *pos) 3193 { 3194 struct amdgpu_device *adev = file_inode(f)->i_private; 3195 struct dc *dc = adev->dm.dc; 3196 struct dc_log_buffer_ctx log_ctx = { 0 }; 3197 ssize_t result = 0; 3198 3199 if (!buf || !size) 3200 return -EINVAL; 3201 3202 if (!dc->hwss.log_hw_state) 3203 return 0; 3204 3205 dc->hwss.log_hw_state(dc, &log_ctx); 3206 3207 if (*pos < log_ctx.pos) { 3208 size_t to_copy = log_ctx.pos - *pos; 3209 3210 to_copy = min(to_copy, size); 3211 3212 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3213 *pos += to_copy; 3214 result = to_copy; 3215 } 3216 } 3217 3218 kfree(log_ctx.buf); 3219 3220 return result; 3221 } 3222 3223 /* 3224 * Writes DTN log state to dmesg when triggered via a write. 3225 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3226 */ 3227 static ssize_t dtn_log_write( 3228 struct file *f, 3229 const char __user *buf, 3230 size_t size, 3231 loff_t *pos) 3232 { 3233 struct amdgpu_device *adev = file_inode(f)->i_private; 3234 struct dc *dc = adev->dm.dc; 3235 3236 /* Write triggers log output via dmesg. */ 3237 if (size == 0) 3238 return 0; 3239 3240 if (dc->hwss.log_hw_state) 3241 dc->hwss.log_hw_state(dc, NULL); 3242 3243 return size; 3244 } 3245 3246 static int mst_topo_show(struct seq_file *m, void *unused) 3247 { 3248 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3249 struct drm_device *dev = adev_to_drm(adev); 3250 struct drm_connector *connector; 3251 struct drm_connector_list_iter conn_iter; 3252 struct amdgpu_dm_connector *aconnector; 3253 3254 drm_connector_list_iter_begin(dev, &conn_iter); 3255 drm_for_each_connector_iter(connector, &conn_iter) { 3256 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3257 continue; 3258 3259 aconnector = to_amdgpu_dm_connector(connector); 3260 3261 /* Ensure we're only dumping the topology of a root mst node */ 3262 if (!aconnector->mst_mgr.mst_state) 3263 continue; 3264 3265 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3266 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3267 } 3268 drm_connector_list_iter_end(&conn_iter); 3269 3270 return 0; 3271 } 3272 3273 /* 3274 * Sets trigger hpd for MST topologies. 3275 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3276 * All topologies will be disconnected if val of 0 is set . 3277 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3278 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3279 */ 3280 static int trigger_hpd_mst_set(void *data, u64 val) 3281 { 3282 struct amdgpu_device *adev = data; 3283 struct drm_device *dev = adev_to_drm(adev); 3284 struct drm_connector_list_iter iter; 3285 struct amdgpu_dm_connector *aconnector; 3286 struct drm_connector *connector; 3287 struct dc_link *link = NULL; 3288 3289 if (val == 1) { 3290 drm_connector_list_iter_begin(dev, &iter); 3291 drm_for_each_connector_iter(connector, &iter) { 3292 aconnector = to_amdgpu_dm_connector(connector); 3293 if (aconnector->dc_link->type == dc_connection_mst_branch && 3294 aconnector->mst_mgr.aux) { 3295 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3296 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3297 } 3298 } 3299 } else if (val == 0) { 3300 drm_connector_list_iter_begin(dev, &iter); 3301 drm_for_each_connector_iter(connector, &iter) { 3302 aconnector = to_amdgpu_dm_connector(connector); 3303 if (!aconnector->dc_link) 3304 continue; 3305 3306 if (!aconnector->mst_port) 3307 continue; 3308 3309 link = aconnector->dc_link; 3310 dp_receiver_power_ctrl(link, false); 3311 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3312 link->mst_stream_alloc_table.stream_count = 0; 3313 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3314 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3315 } 3316 } else { 3317 return 0; 3318 } 3319 drm_kms_helper_hotplug_event(dev); 3320 3321 return 0; 3322 } 3323 3324 /* 3325 * The interface doesn't need get function, so it will return the 3326 * value of zero 3327 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3328 */ 3329 static int trigger_hpd_mst_get(void *data, u64 *val) 3330 { 3331 *val = 0; 3332 return 0; 3333 } 3334 3335 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3336 trigger_hpd_mst_set, "%llu\n"); 3337 3338 3339 /* 3340 * Sets the force_timing_sync debug option from the given string. 3341 * All connected displays will be force synchronized immediately. 3342 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3343 */ 3344 static int force_timing_sync_set(void *data, u64 val) 3345 { 3346 struct amdgpu_device *adev = data; 3347 3348 adev->dm.force_timing_sync = (bool)val; 3349 3350 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3351 3352 return 0; 3353 } 3354 3355 /* 3356 * Gets the force_timing_sync debug option value into the given buffer. 3357 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3358 */ 3359 static int force_timing_sync_get(void *data, u64 *val) 3360 { 3361 struct amdgpu_device *adev = data; 3362 3363 *val = adev->dm.force_timing_sync; 3364 3365 return 0; 3366 } 3367 3368 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3369 force_timing_sync_set, "%llu\n"); 3370 3371 3372 /* 3373 * Disables all HPD and HPD RX interrupt handling in the 3374 * driver when set to 1. Default is 0. 3375 */ 3376 static int disable_hpd_set(void *data, u64 val) 3377 { 3378 struct amdgpu_device *adev = data; 3379 3380 adev->dm.disable_hpd_irq = (bool)val; 3381 3382 return 0; 3383 } 3384 3385 3386 /* 3387 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3388 * 0 otherwise. 3389 */ 3390 static int disable_hpd_get(void *data, u64 *val) 3391 { 3392 struct amdgpu_device *adev = data; 3393 3394 *val = adev->dm.disable_hpd_irq; 3395 3396 return 0; 3397 } 3398 3399 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3400 disable_hpd_set, "%llu\n"); 3401 3402 #if defined(CONFIG_DRM_AMD_DC_DCN) 3403 /* 3404 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3405 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3406 */ 3407 static int dp_force_sst_set(void *data, u64 val) 3408 { 3409 struct amdgpu_device *adev = data; 3410 3411 adev->dm.dc->debug.set_mst_en_for_sst = val; 3412 3413 return 0; 3414 } 3415 3416 static int dp_force_sst_get(void *data, u64 *val) 3417 { 3418 struct amdgpu_device *adev = data; 3419 3420 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3421 3422 return 0; 3423 } 3424 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3425 dp_force_sst_set, "%llu\n"); 3426 3427 /* 3428 * Force DP2 sequence without VESA certified cable. 3429 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3430 */ 3431 static int dp_ignore_cable_id_set(void *data, u64 val) 3432 { 3433 struct amdgpu_device *adev = data; 3434 3435 adev->dm.dc->debug.ignore_cable_id = val; 3436 3437 return 0; 3438 } 3439 3440 static int dp_ignore_cable_id_get(void *data, u64 *val) 3441 { 3442 struct amdgpu_device *adev = data; 3443 3444 *val = adev->dm.dc->debug.ignore_cable_id; 3445 3446 return 0; 3447 } 3448 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3449 dp_ignore_cable_id_set, "%llu\n"); 3450 #endif 3451 3452 /* 3453 * Sets the DC visual confirm debug option from the given string. 3454 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3455 */ 3456 static int visual_confirm_set(void *data, u64 val) 3457 { 3458 struct amdgpu_device *adev = data; 3459 3460 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3461 3462 return 0; 3463 } 3464 3465 /* 3466 * Reads the DC visual confirm debug option value into the given buffer. 3467 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3468 */ 3469 static int visual_confirm_get(void *data, u64 *val) 3470 { 3471 struct amdgpu_device *adev = data; 3472 3473 *val = adev->dm.dc->debug.visual_confirm; 3474 3475 return 0; 3476 } 3477 3478 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3479 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3480 visual_confirm_set, "%llu\n"); 3481 3482 3483 /* 3484 * Sets the DC skip_detection_link_training debug option from the given string. 3485 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3486 */ 3487 static int skip_detection_link_training_set(void *data, u64 val) 3488 { 3489 struct amdgpu_device *adev = data; 3490 3491 if (val == 0) 3492 adev->dm.dc->debug.skip_detection_link_training = false; 3493 else 3494 adev->dm.dc->debug.skip_detection_link_training = true; 3495 3496 return 0; 3497 } 3498 3499 /* 3500 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3501 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3502 */ 3503 static int skip_detection_link_training_get(void *data, u64 *val) 3504 { 3505 struct amdgpu_device *adev = data; 3506 3507 *val = adev->dm.dc->debug.skip_detection_link_training; 3508 3509 return 0; 3510 } 3511 3512 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3513 skip_detection_link_training_get, 3514 skip_detection_link_training_set, "%llu\n"); 3515 3516 /* 3517 * Dumps the DCC_EN bit for each pipe. 3518 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3519 */ 3520 static ssize_t dcc_en_bits_read( 3521 struct file *f, 3522 char __user *buf, 3523 size_t size, 3524 loff_t *pos) 3525 { 3526 struct amdgpu_device *adev = file_inode(f)->i_private; 3527 struct dc *dc = adev->dm.dc; 3528 char *rd_buf = NULL; 3529 const uint32_t rd_buf_size = 32; 3530 uint32_t result = 0; 3531 int offset = 0; 3532 int num_pipes = dc->res_pool->pipe_count; 3533 int *dcc_en_bits; 3534 int i, r; 3535 3536 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3537 if (!dcc_en_bits) 3538 return -ENOMEM; 3539 3540 if (!dc->hwss.get_dcc_en_bits) { 3541 kfree(dcc_en_bits); 3542 return 0; 3543 } 3544 3545 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3546 3547 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3548 if (!rd_buf) { 3549 kfree(dcc_en_bits); 3550 return -ENOMEM; 3551 } 3552 3553 for (i = 0; i < num_pipes; i++) 3554 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3555 "%d ", dcc_en_bits[i]); 3556 rd_buf[strlen(rd_buf)] = '\n'; 3557 3558 kfree(dcc_en_bits); 3559 3560 while (size) { 3561 if (*pos >= rd_buf_size) 3562 break; 3563 r = put_user(*(rd_buf + result), buf); 3564 if (r) { 3565 kfree(rd_buf); 3566 return r; /* r = -EFAULT */ 3567 } 3568 buf += 1; 3569 size -= 1; 3570 *pos += 1; 3571 result += 1; 3572 } 3573 3574 kfree(rd_buf); 3575 return result; 3576 } 3577 3578 void dtn_debugfs_init(struct amdgpu_device *adev) 3579 { 3580 static const struct file_operations dtn_log_fops = { 3581 .owner = THIS_MODULE, 3582 .read = dtn_log_read, 3583 .write = dtn_log_write, 3584 .llseek = default_llseek 3585 }; 3586 static const struct file_operations dcc_en_bits_fops = { 3587 .owner = THIS_MODULE, 3588 .read = dcc_en_bits_read, 3589 .llseek = default_llseek 3590 }; 3591 3592 struct drm_minor *minor = adev_to_drm(adev)->primary; 3593 struct dentry *root = minor->debugfs_root; 3594 3595 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3596 adev, &mst_topo_fops); 3597 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3598 &dtn_log_fops); 3599 #if defined(CONFIG_DRM_AMD_DC_DCN) 3600 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3601 &dp_set_mst_en_for_sst_ops); 3602 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3603 &dp_ignore_cable_id_ops); 3604 #endif 3605 3606 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3607 &visual_confirm_fops); 3608 3609 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3610 &skip_detection_link_training_fops); 3611 3612 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3613 adev, &dmub_tracebuffer_fops); 3614 3615 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3616 adev, &dmub_fw_state_fops); 3617 3618 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3619 adev, &force_timing_sync_ops); 3620 3621 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3622 adev, &dmcub_trace_event_state_fops); 3623 3624 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3625 adev, &trigger_hpd_mst_ops); 3626 3627 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3628 &dcc_en_bits_fops); 3629 3630 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3631 &disable_hpd_ops); 3632 3633 } 3634