1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 41 struct dmub_debugfs_trace_header { 42 uint32_t entry_count; 43 uint32_t reserved[3]; 44 }; 45 46 struct dmub_debugfs_trace_entry { 47 uint32_t trace_code; 48 uint32_t tick_count; 49 uint32_t param0; 50 uint32_t param1; 51 }; 52 53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 54 * 55 * Function takes in attributes passed to debugfs write entry 56 * and writes into param array. 57 * The user passes max_param_num to identify maximum number of 58 * parameters that could be parsed. 59 * 60 */ 61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 62 long *param, const char __user *buf, 63 int max_param_num, 64 uint8_t *param_nums) 65 { 66 char *wr_buf_ptr = NULL; 67 uint32_t wr_buf_count = 0; 68 int r; 69 char *sub_str = NULL; 70 const char delimiter[3] = {' ', '\n', '\0'}; 71 uint8_t param_index = 0; 72 73 *param_nums = 0; 74 75 wr_buf_ptr = wr_buf; 76 77 /* r is bytes not be copied */ 78 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 79 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 80 return -EFAULT; 81 } 82 83 /* check number of parameters. isspace could not differ space and \n */ 84 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 85 /* skip space*/ 86 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 87 wr_buf_ptr++; 88 wr_buf_count++; 89 } 90 91 if (wr_buf_count == wr_buf_size) 92 break; 93 94 /* skip non-space*/ 95 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 96 wr_buf_ptr++; 97 wr_buf_count++; 98 } 99 100 (*param_nums)++; 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 } 105 106 if (*param_nums > max_param_num) 107 *param_nums = max_param_num; 108 109 wr_buf_ptr = wr_buf; /* reset buf pointer */ 110 wr_buf_count = 0; /* number of char already checked */ 111 112 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 113 wr_buf_ptr++; 114 wr_buf_count++; 115 } 116 117 while (param_index < *param_nums) { 118 /* after strsep, wr_buf_ptr will be moved to after space */ 119 sub_str = strsep(&wr_buf_ptr, delimiter); 120 121 r = kstrtol(sub_str, 16, &(param[param_index])); 122 123 if (r) 124 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 125 126 param_index++; 127 } 128 129 return 0; 130 } 131 132 /* function description 133 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 134 * 135 * valid lane count value: 1, 2, 4 136 * valid link rate value: 137 * 06h = 1.62Gbps per lane 138 * 0Ah = 2.7Gbps per lane 139 * 0Ch = 3.24Gbps per lane 140 * 14h = 5.4Gbps per lane 141 * 1Eh = 8.1Gbps per lane 142 * 143 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 144 * 145 * --- to get dp configuration 146 * 147 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 148 * 149 * It will list current, verified, reported, preferred dp configuration. 150 * current -- for current video mode 151 * verified --- maximum configuration which pass link training 152 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 153 * preferred --- user force settings 154 * 155 * --- set (or force) dp configuration 156 * 157 * echo <lane_count> <link_rate> > link_settings 158 * 159 * for example, to force to 2 lane, 2.7GHz, 160 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * spread_spectrum could not be changed dynamically. 163 * 164 * in case invalid lane count, link rate are force, no hw programming will be 165 * done. please check link settings after force operation to see if HW get 166 * programming. 167 * 168 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 169 * 170 * check current and preferred settings. 171 * 172 */ 173 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 174 size_t size, loff_t *pos) 175 { 176 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 177 struct dc_link *link = connector->dc_link; 178 char *rd_buf = NULL; 179 char *rd_buf_ptr = NULL; 180 const uint32_t rd_buf_size = 100; 181 uint32_t result = 0; 182 uint8_t str_len = 0; 183 int r; 184 185 if (*pos & 3 || size & 3) 186 return -EINVAL; 187 188 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 189 if (!rd_buf) 190 return 0; 191 192 rd_buf_ptr = rd_buf; 193 194 str_len = strlen("Current: %d 0x%x %d "); 195 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 196 link->cur_link_settings.lane_count, 197 link->cur_link_settings.link_rate, 198 link->cur_link_settings.link_spread); 199 rd_buf_ptr += str_len; 200 201 str_len = strlen("Verified: %d 0x%x %d "); 202 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 203 link->verified_link_cap.lane_count, 204 link->verified_link_cap.link_rate, 205 link->verified_link_cap.link_spread); 206 rd_buf_ptr += str_len; 207 208 str_len = strlen("Reported: %d 0x%x %d "); 209 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 210 link->reported_link_cap.lane_count, 211 link->reported_link_cap.link_rate, 212 link->reported_link_cap.link_spread); 213 rd_buf_ptr += str_len; 214 215 str_len = strlen("Preferred: %d 0x%x %d "); 216 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 217 link->preferred_link_setting.lane_count, 218 link->preferred_link_setting.link_rate, 219 link->preferred_link_setting.link_spread); 220 221 while (size) { 222 if (*pos >= rd_buf_size) 223 break; 224 225 r = put_user(*(rd_buf + result), buf); 226 if (r) 227 return r; /* r = -EFAULT */ 228 229 buf += 1; 230 size -= 1; 231 *pos += 1; 232 result += 1; 233 } 234 235 kfree(rd_buf); 236 return result; 237 } 238 239 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 240 size_t size, loff_t *pos) 241 { 242 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 243 struct dc_link *link = connector->dc_link; 244 struct dc *dc = (struct dc *)link->dc; 245 struct dc_link_settings prefer_link_settings; 246 char *wr_buf = NULL; 247 const uint32_t wr_buf_size = 40; 248 /* 0: lane_count; 1: link_rate */ 249 int max_param_num = 2; 250 uint8_t param_nums = 0; 251 long param[2]; 252 bool valid_input = true; 253 254 if (size == 0) 255 return -EINVAL; 256 257 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 258 if (!wr_buf) 259 return -ENOSPC; 260 261 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 262 (long *)param, buf, 263 max_param_num, 264 ¶m_nums)) { 265 kfree(wr_buf); 266 return -EINVAL; 267 } 268 269 if (param_nums <= 0) { 270 kfree(wr_buf); 271 DRM_DEBUG_DRIVER("user data not be read\n"); 272 return -EINVAL; 273 } 274 275 switch (param[0]) { 276 case LANE_COUNT_ONE: 277 case LANE_COUNT_TWO: 278 case LANE_COUNT_FOUR: 279 break; 280 default: 281 valid_input = false; 282 break; 283 } 284 285 switch (param[1]) { 286 case LINK_RATE_LOW: 287 case LINK_RATE_HIGH: 288 case LINK_RATE_RBR2: 289 case LINK_RATE_HIGH2: 290 case LINK_RATE_HIGH3: 291 #if defined(CONFIG_DRM_AMD_DC_DCN) 292 case LINK_RATE_UHBR10: 293 #endif 294 break; 295 default: 296 valid_input = false; 297 break; 298 } 299 300 if (!valid_input) { 301 kfree(wr_buf); 302 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 303 return size; 304 } 305 306 /* save user force lane_count, link_rate to preferred settings 307 * spread spectrum will not be changed 308 */ 309 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 310 prefer_link_settings.use_link_rate_set = false; 311 prefer_link_settings.lane_count = param[0]; 312 prefer_link_settings.link_rate = param[1]; 313 314 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 315 316 kfree(wr_buf); 317 return size; 318 } 319 320 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 321 * post-cursor2 (defined by VESA DP specification) 322 * 323 * valid values 324 * voltage swing: 0,1,2,3 325 * pre-emphasis : 0,1,2,3 326 * post cursor2 : 0,1,2,3 327 * 328 * 329 * how to use this debugfs 330 * 331 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 332 * 333 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 334 * 335 * To figure out which DP-x is the display for DP to be check, 336 * cd DP-x 337 * ls -ll 338 * There should be debugfs file, like link_settings, phy_settings. 339 * cat link_settings 340 * from lane_count, link_rate to figure which DP-x is for display to be worked 341 * on 342 * 343 * To get current DP PHY settings, 344 * cat phy_settings 345 * 346 * To change DP PHY settings, 347 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 348 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 349 * 0, 350 * echo 2 3 0 > phy_settings 351 * 352 * To check if change be applied, get current phy settings by 353 * cat phy_settings 354 * 355 * In case invalid values are set by user, like 356 * echo 1 4 0 > phy_settings 357 * 358 * HW will NOT be programmed by these settings. 359 * cat phy_settings will show the previous valid settings. 360 */ 361 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 362 size_t size, loff_t *pos) 363 { 364 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 365 struct dc_link *link = connector->dc_link; 366 char *rd_buf = NULL; 367 const uint32_t rd_buf_size = 20; 368 uint32_t result = 0; 369 int r; 370 371 if (*pos & 3 || size & 3) 372 return -EINVAL; 373 374 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 375 if (!rd_buf) 376 return -EINVAL; 377 378 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 379 link->cur_lane_setting[0].VOLTAGE_SWING, 380 link->cur_lane_setting[0].PRE_EMPHASIS, 381 link->cur_lane_setting[0].POST_CURSOR2); 382 383 while (size) { 384 if (*pos >= rd_buf_size) 385 break; 386 387 r = put_user((*(rd_buf + result)), buf); 388 if (r) 389 return r; /* r = -EFAULT */ 390 391 buf += 1; 392 size -= 1; 393 *pos += 1; 394 result += 1; 395 } 396 397 kfree(rd_buf); 398 return result; 399 } 400 401 static int dp_lttpr_status_show(struct seq_file *m, void *d) 402 { 403 char *data; 404 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 405 struct dc_link *link = connector->dc_link; 406 uint32_t read_size = 1; 407 uint8_t repeater_count = 0; 408 409 data = kzalloc(read_size, GFP_KERNEL); 410 if (!data) 411 return 0; 412 413 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 414 415 switch ((uint8_t)*data) { 416 case 0x80: 417 repeater_count = 1; 418 break; 419 case 0x40: 420 repeater_count = 2; 421 break; 422 case 0x20: 423 repeater_count = 3; 424 break; 425 case 0x10: 426 repeater_count = 4; 427 break; 428 case 0x8: 429 repeater_count = 5; 430 break; 431 case 0x4: 432 repeater_count = 6; 433 break; 434 case 0x2: 435 repeater_count = 7; 436 break; 437 case 0x1: 438 repeater_count = 8; 439 break; 440 case 0x0: 441 repeater_count = 0; 442 break; 443 default: 444 repeater_count = (uint8_t)*data; 445 break; 446 } 447 448 seq_printf(m, "phy repeater count: %d\n", repeater_count); 449 450 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 451 452 if ((uint8_t)*data == 0x55) 453 seq_printf(m, "phy repeater mode: transparent\n"); 454 else if ((uint8_t)*data == 0xAA) 455 seq_printf(m, "phy repeater mode: non-transparent\n"); 456 else if ((uint8_t)*data == 0x00) 457 seq_printf(m, "phy repeater mode: non lttpr\n"); 458 else 459 seq_printf(m, "phy repeater mode: read error\n"); 460 461 kfree(data); 462 return 0; 463 } 464 465 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 466 size_t size, loff_t *pos) 467 { 468 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 469 struct dc_link *link = connector->dc_link; 470 struct dc *dc = (struct dc *)link->dc; 471 char *wr_buf = NULL; 472 uint32_t wr_buf_size = 40; 473 long param[3]; 474 bool use_prefer_link_setting; 475 struct link_training_settings link_lane_settings; 476 int max_param_num = 3; 477 uint8_t param_nums = 0; 478 int r = 0; 479 480 481 if (size == 0) 482 return -EINVAL; 483 484 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 485 if (!wr_buf) 486 return -ENOSPC; 487 488 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 489 (long *)param, buf, 490 max_param_num, 491 ¶m_nums)) { 492 kfree(wr_buf); 493 return -EINVAL; 494 } 495 496 if (param_nums <= 0) { 497 kfree(wr_buf); 498 DRM_DEBUG_DRIVER("user data not be read\n"); 499 return -EINVAL; 500 } 501 502 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 503 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 504 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 505 kfree(wr_buf); 506 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 507 return size; 508 } 509 510 /* get link settings: lane count, link rate */ 511 use_prefer_link_setting = 512 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 513 (link->test_pattern_enabled)); 514 515 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 516 517 if (use_prefer_link_setting) { 518 link_lane_settings.link_settings.lane_count = 519 link->preferred_link_setting.lane_count; 520 link_lane_settings.link_settings.link_rate = 521 link->preferred_link_setting.link_rate; 522 link_lane_settings.link_settings.link_spread = 523 link->preferred_link_setting.link_spread; 524 } else { 525 link_lane_settings.link_settings.lane_count = 526 link->cur_link_settings.lane_count; 527 link_lane_settings.link_settings.link_rate = 528 link->cur_link_settings.link_rate; 529 link_lane_settings.link_settings.link_spread = 530 link->cur_link_settings.link_spread; 531 } 532 533 /* apply phy settings from user */ 534 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 535 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 536 (enum dc_voltage_swing) (param[0]); 537 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 538 (enum dc_pre_emphasis) (param[1]); 539 link_lane_settings.lane_settings[r].POST_CURSOR2 = 540 (enum dc_post_cursor2) (param[2]); 541 } 542 543 /* program ASIC registers and DPCD registers */ 544 dc_link_set_drive_settings(dc, &link_lane_settings, link); 545 546 kfree(wr_buf); 547 return size; 548 } 549 550 /* function description 551 * 552 * set PHY layer or Link layer test pattern 553 * PHY test pattern is used for PHY SI check. 554 * Link layer test will not affect PHY SI. 555 * 556 * Reset Test Pattern: 557 * 0 = DP_TEST_PATTERN_VIDEO_MODE 558 * 559 * PHY test pattern supported: 560 * 1 = DP_TEST_PATTERN_D102 561 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 562 * 3 = DP_TEST_PATTERN_PRBS7 563 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 564 * 5 = DP_TEST_PATTERN_CP2520_1 565 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 566 * 7 = DP_TEST_PATTERN_CP2520_3 567 * 568 * DP PHY Link Training Patterns 569 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 570 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 571 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 572 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 573 * 574 * DP Link Layer Test pattern 575 * c = DP_TEST_PATTERN_COLOR_SQUARES 576 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 577 * e = DP_TEST_PATTERN_VERTICAL_BARS 578 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 579 * 10= DP_TEST_PATTERN_COLOR_RAMP 580 * 581 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 582 * 583 * --- set test pattern 584 * echo <test pattern #> > test_pattern 585 * 586 * If test pattern # is not supported, NO HW programming will be done. 587 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 588 * for the user pattern. input 10 bytes data are separated by space 589 * 590 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 591 * 592 * --- reset test pattern 593 * echo 0 > test_pattern 594 * 595 * --- HPD detection is disabled when set PHY test pattern 596 * 597 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 598 * is disable. User could unplug DP display from DP connected and plug scope to 599 * check test pattern PHY SI. 600 * If there is need unplug scope and plug DP display back, do steps below: 601 * echo 0 > phy_test_pattern 602 * unplug scope 603 * plug DP display. 604 * 605 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 606 * driver could detect "unplug scope" and "plug DP display" 607 */ 608 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 609 size_t size, loff_t *pos) 610 { 611 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 612 struct dc_link *link = connector->dc_link; 613 char *wr_buf = NULL; 614 uint32_t wr_buf_size = 100; 615 long param[11] = {0x0}; 616 int max_param_num = 11; 617 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 618 bool disable_hpd = false; 619 bool valid_test_pattern = false; 620 uint8_t param_nums = 0; 621 /* init with default 80bit custom pattern */ 622 uint8_t custom_pattern[10] = { 623 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 624 0x1f, 0x7c, 0xf0, 0xc1, 0x07 625 }; 626 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 627 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 628 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 629 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 630 struct link_training_settings link_training_settings; 631 int i; 632 633 if (size == 0) 634 return -EINVAL; 635 636 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 637 if (!wr_buf) 638 return -ENOSPC; 639 640 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 641 (long *)param, buf, 642 max_param_num, 643 ¶m_nums)) { 644 kfree(wr_buf); 645 return -EINVAL; 646 } 647 648 if (param_nums <= 0) { 649 kfree(wr_buf); 650 DRM_DEBUG_DRIVER("user data not be read\n"); 651 return -EINVAL; 652 } 653 654 655 test_pattern = param[0]; 656 657 switch (test_pattern) { 658 case DP_TEST_PATTERN_VIDEO_MODE: 659 case DP_TEST_PATTERN_COLOR_SQUARES: 660 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 661 case DP_TEST_PATTERN_VERTICAL_BARS: 662 case DP_TEST_PATTERN_HORIZONTAL_BARS: 663 case DP_TEST_PATTERN_COLOR_RAMP: 664 valid_test_pattern = true; 665 break; 666 667 case DP_TEST_PATTERN_D102: 668 case DP_TEST_PATTERN_SYMBOL_ERROR: 669 case DP_TEST_PATTERN_PRBS7: 670 case DP_TEST_PATTERN_80BIT_CUSTOM: 671 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 672 case DP_TEST_PATTERN_TRAINING_PATTERN4: 673 disable_hpd = true; 674 valid_test_pattern = true; 675 break; 676 677 default: 678 valid_test_pattern = false; 679 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 680 break; 681 } 682 683 if (!valid_test_pattern) { 684 kfree(wr_buf); 685 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 686 return size; 687 } 688 689 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 690 for (i = 0; i < 10; i++) { 691 if ((uint8_t) param[i + 1] != 0x0) 692 break; 693 } 694 695 if (i < 10) { 696 /* not use default value */ 697 for (i = 0; i < 10; i++) 698 custom_pattern[i] = (uint8_t) param[i + 1]; 699 } 700 } 701 702 /* Usage: set DP physical test pattern using debugfs with normal DP 703 * panel. Then plug out DP panel and connect a scope to measure 704 * For normal video mode and test pattern generated from CRCT, 705 * they are visibile to user. So do not disable HPD. 706 * Video Mode is also set to clear the test pattern, so enable HPD 707 * because it might have been disabled after a test pattern was set. 708 * AUX depends on HPD * sequence dependent, do not move! 709 */ 710 if (!disable_hpd) 711 dc_link_enable_hpd(link); 712 713 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 714 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 715 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 716 717 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 718 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 719 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 720 721 link_training_settings.link_settings = cur_link_settings; 722 723 724 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 725 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 726 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 727 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 728 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 729 link_training_settings.link_settings = prefer_link_settings; 730 } 731 732 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 733 link_training_settings.lane_settings[i] = link->cur_lane_setting[i]; 734 735 dc_link_set_test_pattern( 736 link, 737 test_pattern, 738 DP_TEST_PATTERN_COLOR_SPACE_RGB, 739 &link_training_settings, 740 custom_pattern, 741 10); 742 743 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 744 * Then plug out DP panel and connect a scope to measure DP PHY signal. 745 * Need disable interrupt to avoid SW driver disable DP output. This is 746 * done after the test pattern is set. 747 */ 748 if (valid_test_pattern && disable_hpd) 749 dc_link_disable_hpd(link); 750 751 kfree(wr_buf); 752 753 return size; 754 } 755 756 /* 757 * Returns the DMCUB tracebuffer contents. 758 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 759 */ 760 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 761 { 762 struct amdgpu_device *adev = m->private; 763 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 764 struct dmub_debugfs_trace_entry *entries; 765 uint8_t *tbuf_base; 766 uint32_t tbuf_size, max_entries, num_entries, i; 767 768 if (!fb_info) 769 return 0; 770 771 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 772 if (!tbuf_base) 773 return 0; 774 775 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 776 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 777 sizeof(struct dmub_debugfs_trace_entry); 778 779 num_entries = 780 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 781 782 num_entries = min(num_entries, max_entries); 783 784 entries = (struct dmub_debugfs_trace_entry 785 *)(tbuf_base + 786 sizeof(struct dmub_debugfs_trace_header)); 787 788 for (i = 0; i < num_entries; ++i) { 789 struct dmub_debugfs_trace_entry *entry = &entries[i]; 790 791 seq_printf(m, 792 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 793 entry->trace_code, entry->tick_count, entry->param0, 794 entry->param1); 795 } 796 797 return 0; 798 } 799 800 /* 801 * Returns the DMCUB firmware state contents. 802 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 803 */ 804 static int dmub_fw_state_show(struct seq_file *m, void *data) 805 { 806 struct amdgpu_device *adev = m->private; 807 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 808 uint8_t *state_base; 809 uint32_t state_size; 810 811 if (!fb_info) 812 return 0; 813 814 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 815 if (!state_base) 816 return 0; 817 818 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 819 820 return seq_write(m, state_base, state_size); 821 } 822 823 /* psr_capability_show() - show eDP panel PSR capability 824 * 825 * The read function: sink_psr_capability_show 826 * Shows if sink has PSR capability or not. 827 * If yes - the PSR version is appended 828 * 829 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 830 * 831 * Expected output: 832 * "Sink support: no\n" - if panel doesn't support PSR 833 * "Sink support: yes [0x01]\n" - if panel supports PSR1 834 * "Driver support: no\n" - if driver doesn't support PSR 835 * "Driver support: yes [0x01]\n" - if driver supports PSR1 836 */ 837 static int psr_capability_show(struct seq_file *m, void *data) 838 { 839 struct drm_connector *connector = m->private; 840 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 841 struct dc_link *link = aconnector->dc_link; 842 843 if (!link) 844 return -ENODEV; 845 846 if (link->type == dc_connection_none) 847 return -ENODEV; 848 849 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 850 return -ENODEV; 851 852 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_caps.psr_version != 0)); 853 if (link->dpcd_caps.psr_caps.psr_version) 854 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_caps.psr_version); 855 seq_puts(m, "\n"); 856 857 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 858 if (link->psr_settings.psr_version) 859 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 860 seq_puts(m, "\n"); 861 862 return 0; 863 } 864 865 /* 866 * Returns the current and maximum output bpc for the connector. 867 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 868 */ 869 static int output_bpc_show(struct seq_file *m, void *data) 870 { 871 struct drm_connector *connector = m->private; 872 struct drm_device *dev = connector->dev; 873 struct drm_crtc *crtc = NULL; 874 struct dm_crtc_state *dm_crtc_state = NULL; 875 int res = -ENODEV; 876 unsigned int bpc; 877 878 mutex_lock(&dev->mode_config.mutex); 879 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 880 881 if (connector->state == NULL) 882 goto unlock; 883 884 crtc = connector->state->crtc; 885 if (crtc == NULL) 886 goto unlock; 887 888 drm_modeset_lock(&crtc->mutex, NULL); 889 if (crtc->state == NULL) 890 goto unlock; 891 892 dm_crtc_state = to_dm_crtc_state(crtc->state); 893 if (dm_crtc_state->stream == NULL) 894 goto unlock; 895 896 switch (dm_crtc_state->stream->timing.display_color_depth) { 897 case COLOR_DEPTH_666: 898 bpc = 6; 899 break; 900 case COLOR_DEPTH_888: 901 bpc = 8; 902 break; 903 case COLOR_DEPTH_101010: 904 bpc = 10; 905 break; 906 case COLOR_DEPTH_121212: 907 bpc = 12; 908 break; 909 case COLOR_DEPTH_161616: 910 bpc = 16; 911 break; 912 default: 913 goto unlock; 914 } 915 916 seq_printf(m, "Current: %u\n", bpc); 917 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 918 res = 0; 919 920 unlock: 921 if (crtc) 922 drm_modeset_unlock(&crtc->mutex); 923 924 drm_modeset_unlock(&dev->mode_config.connection_mutex); 925 mutex_unlock(&dev->mode_config.mutex); 926 927 return res; 928 } 929 930 /* 931 * Example usage: 932 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 933 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 934 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 935 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 936 */ 937 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 938 size_t size, loff_t *pos) 939 { 940 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 941 char *wr_buf = NULL; 942 uint32_t wr_buf_size = 42; 943 int max_param_num = 1; 944 long param; 945 uint8_t param_nums = 0; 946 947 if (size == 0) 948 return -EINVAL; 949 950 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 951 952 if (!wr_buf) { 953 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 954 return -ENOSPC; 955 } 956 957 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 958 ¶m, buf, 959 max_param_num, 960 ¶m_nums)) { 961 kfree(wr_buf); 962 return -EINVAL; 963 } 964 965 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 966 967 kfree(wr_buf); 968 return 0; 969 } 970 971 #ifdef CONFIG_DRM_AMD_DC_HDCP 972 /* 973 * Returns the HDCP capability of the Display (1.4 for now). 974 * 975 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 976 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 977 * 978 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 979 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 980 */ 981 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 982 { 983 struct drm_connector *connector = m->private; 984 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 985 bool hdcp_cap, hdcp2_cap; 986 987 if (connector->status != connector_status_connected) 988 return -ENODEV; 989 990 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 991 992 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 993 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 994 995 996 if (hdcp_cap) 997 seq_printf(m, "%s ", "HDCP1.4"); 998 if (hdcp2_cap) 999 seq_printf(m, "%s ", "HDCP2.2"); 1000 1001 if (!hdcp_cap && !hdcp2_cap) 1002 seq_printf(m, "%s ", "None"); 1003 1004 seq_puts(m, "\n"); 1005 1006 return 0; 1007 } 1008 #endif 1009 1010 /* 1011 * Returns whether the connected display is internal and not hotpluggable. 1012 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1013 */ 1014 static int internal_display_show(struct seq_file *m, void *data) 1015 { 1016 struct drm_connector *connector = m->private; 1017 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1018 struct dc_link *link = aconnector->dc_link; 1019 1020 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1021 1022 return 0; 1023 } 1024 1025 /* function description 1026 * 1027 * generic SDP message access for testing 1028 * 1029 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1030 * 1031 * SDP header 1032 * Hb0 : Secondary-Data Packet ID 1033 * Hb1 : Secondary-Data Packet type 1034 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1035 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1036 * 1037 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1038 */ 1039 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1040 size_t size, loff_t *pos) 1041 { 1042 int r; 1043 uint8_t data[36]; 1044 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1045 struct dm_crtc_state *acrtc_state; 1046 uint32_t write_size = 36; 1047 1048 if (connector->base.status != connector_status_connected) 1049 return -ENODEV; 1050 1051 if (size == 0) 1052 return 0; 1053 1054 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1055 1056 r = copy_from_user(data, buf, write_size); 1057 1058 write_size -= r; 1059 1060 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1061 1062 return write_size; 1063 } 1064 1065 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1066 size_t size, loff_t *pos) 1067 { 1068 int r; 1069 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1070 1071 if (size < sizeof(connector->debugfs_dpcd_address)) 1072 return -EINVAL; 1073 1074 r = copy_from_user(&connector->debugfs_dpcd_address, 1075 buf, sizeof(connector->debugfs_dpcd_address)); 1076 1077 return size - r; 1078 } 1079 1080 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1081 size_t size, loff_t *pos) 1082 { 1083 int r; 1084 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1085 1086 if (size < sizeof(connector->debugfs_dpcd_size)) 1087 return -EINVAL; 1088 1089 r = copy_from_user(&connector->debugfs_dpcd_size, 1090 buf, sizeof(connector->debugfs_dpcd_size)); 1091 1092 if (connector->debugfs_dpcd_size > 256) 1093 connector->debugfs_dpcd_size = 0; 1094 1095 return size - r; 1096 } 1097 1098 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1099 size_t size, loff_t *pos) 1100 { 1101 int r; 1102 char *data; 1103 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1104 struct dc_link *link = connector->dc_link; 1105 uint32_t write_size = connector->debugfs_dpcd_size; 1106 1107 if (!write_size || size < write_size) 1108 return -EINVAL; 1109 1110 data = kzalloc(write_size, GFP_KERNEL); 1111 if (!data) 1112 return 0; 1113 1114 r = copy_from_user(data, buf, write_size); 1115 1116 dm_helpers_dp_write_dpcd(link->ctx, link, 1117 connector->debugfs_dpcd_address, data, write_size - r); 1118 kfree(data); 1119 return write_size - r; 1120 } 1121 1122 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1123 size_t size, loff_t *pos) 1124 { 1125 int r; 1126 char *data; 1127 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1128 struct dc_link *link = connector->dc_link; 1129 uint32_t read_size = connector->debugfs_dpcd_size; 1130 1131 if (!read_size || size < read_size) 1132 return 0; 1133 1134 data = kzalloc(read_size, GFP_KERNEL); 1135 if (!data) 1136 return 0; 1137 1138 dm_helpers_dp_read_dpcd(link->ctx, link, 1139 connector->debugfs_dpcd_address, data, read_size); 1140 1141 r = copy_to_user(buf, data, read_size); 1142 1143 kfree(data); 1144 return read_size - r; 1145 } 1146 1147 /* function: Read link's DSC & FEC capabilities 1148 * 1149 * 1150 * Access it with the following command (you need to specify 1151 * connector like DP-1): 1152 * 1153 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1154 * 1155 */ 1156 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1157 { 1158 struct drm_connector *connector = m->private; 1159 struct drm_modeset_acquire_ctx ctx; 1160 struct drm_device *dev = connector->dev; 1161 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1162 int ret = 0; 1163 bool try_again = false; 1164 bool is_fec_supported = false; 1165 bool is_dsc_supported = false; 1166 struct dpcd_caps dpcd_caps; 1167 1168 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1169 do { 1170 try_again = false; 1171 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1172 if (ret) { 1173 if (ret == -EDEADLK) { 1174 ret = drm_modeset_backoff(&ctx); 1175 if (!ret) { 1176 try_again = true; 1177 continue; 1178 } 1179 } 1180 break; 1181 } 1182 if (connector->status != connector_status_connected) { 1183 ret = -ENODEV; 1184 break; 1185 } 1186 dpcd_caps = aconnector->dc_link->dpcd_caps; 1187 if (aconnector->port) { 1188 /* aconnector sets dsc_aux during get_modes call 1189 * if MST connector has it means it can either 1190 * enable DSC on the sink device or on MST branch 1191 * its connected to. 1192 */ 1193 if (aconnector->dsc_aux) { 1194 is_fec_supported = true; 1195 is_dsc_supported = true; 1196 } 1197 } else { 1198 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1199 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1200 } 1201 } while (try_again); 1202 1203 drm_modeset_drop_locks(&ctx); 1204 drm_modeset_acquire_fini(&ctx); 1205 1206 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1207 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1208 1209 return ret; 1210 } 1211 1212 /* function: Trigger virtual HPD redetection on connector 1213 * 1214 * This function will perform link rediscovery, link disable 1215 * and enable, and dm connector state update. 1216 * 1217 * Retrigger HPD on an existing connector by echoing 1 into 1218 * its respectful "trigger_hotplug" debugfs entry: 1219 * 1220 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1221 * 1222 * This function can perform HPD unplug: 1223 * 1224 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1225 * 1226 */ 1227 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1228 size_t size, loff_t *pos) 1229 { 1230 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1231 struct drm_connector *connector = &aconnector->base; 1232 struct dc_link *link = NULL; 1233 struct drm_device *dev = connector->dev; 1234 enum dc_connection_type new_connection_type = dc_connection_none; 1235 char *wr_buf = NULL; 1236 uint32_t wr_buf_size = 42; 1237 int max_param_num = 1; 1238 long param[1] = {0}; 1239 uint8_t param_nums = 0; 1240 1241 if (!aconnector || !aconnector->dc_link) 1242 return -EINVAL; 1243 1244 if (size == 0) 1245 return -EINVAL; 1246 1247 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1248 1249 if (!wr_buf) { 1250 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1251 return -ENOSPC; 1252 } 1253 1254 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1255 (long *)param, buf, 1256 max_param_num, 1257 ¶m_nums)) { 1258 kfree(wr_buf); 1259 return -EINVAL; 1260 } 1261 1262 if (param_nums <= 0) { 1263 DRM_DEBUG_DRIVER("user data not be read\n"); 1264 kfree(wr_buf); 1265 return -EINVAL; 1266 } 1267 1268 if (param[0] == 1) { 1269 mutex_lock(&aconnector->hpd_lock); 1270 1271 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1272 new_connection_type != dc_connection_none) 1273 goto unlock; 1274 1275 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1276 goto unlock; 1277 1278 amdgpu_dm_update_connector_after_detect(aconnector); 1279 1280 drm_modeset_lock_all(dev); 1281 dm_restore_drm_connector_state(dev, connector); 1282 drm_modeset_unlock_all(dev); 1283 1284 drm_kms_helper_connector_hotplug_event(connector); 1285 } else if (param[0] == 0) { 1286 if (!aconnector->dc_link) 1287 goto unlock; 1288 1289 link = aconnector->dc_link; 1290 1291 if (link->local_sink) { 1292 dc_sink_release(link->local_sink); 1293 link->local_sink = NULL; 1294 } 1295 1296 link->dpcd_sink_count = 0; 1297 link->type = dc_connection_none; 1298 link->dongle_max_pix_clk = 0; 1299 1300 amdgpu_dm_update_connector_after_detect(aconnector); 1301 1302 drm_modeset_lock_all(dev); 1303 dm_restore_drm_connector_state(dev, connector); 1304 drm_modeset_unlock_all(dev); 1305 1306 drm_kms_helper_connector_hotplug_event(connector); 1307 } 1308 1309 unlock: 1310 mutex_unlock(&aconnector->hpd_lock); 1311 1312 kfree(wr_buf); 1313 return size; 1314 } 1315 1316 /* function: read DSC status on the connector 1317 * 1318 * The read function: dp_dsc_clock_en_read 1319 * returns current status of DSC clock on the connector. 1320 * The return is a boolean flag: 1 or 0. 1321 * 1322 * Access it with the following command (you need to specify 1323 * connector like DP-1): 1324 * 1325 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1326 * 1327 * Expected output: 1328 * 1 - means that DSC is currently enabled 1329 * 0 - means that DSC is disabled 1330 */ 1331 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1332 size_t size, loff_t *pos) 1333 { 1334 char *rd_buf = NULL; 1335 char *rd_buf_ptr = NULL; 1336 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1337 struct display_stream_compressor *dsc; 1338 struct dcn_dsc_state dsc_state = {0}; 1339 const uint32_t rd_buf_size = 10; 1340 struct pipe_ctx *pipe_ctx; 1341 ssize_t result = 0; 1342 int i, r, str_len = 30; 1343 1344 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1345 1346 if (!rd_buf) 1347 return -ENOMEM; 1348 1349 rd_buf_ptr = rd_buf; 1350 1351 for (i = 0; i < MAX_PIPES; i++) { 1352 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1353 if (pipe_ctx && pipe_ctx->stream && 1354 pipe_ctx->stream->link == aconnector->dc_link) 1355 break; 1356 } 1357 1358 if (!pipe_ctx) 1359 return -ENXIO; 1360 1361 dsc = pipe_ctx->stream_res.dsc; 1362 if (dsc) 1363 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1364 1365 snprintf(rd_buf_ptr, str_len, 1366 "%d\n", 1367 dsc_state.dsc_clock_en); 1368 rd_buf_ptr += str_len; 1369 1370 while (size) { 1371 if (*pos >= rd_buf_size) 1372 break; 1373 1374 r = put_user(*(rd_buf + result), buf); 1375 if (r) 1376 return r; /* r = -EFAULT */ 1377 1378 buf += 1; 1379 size -= 1; 1380 *pos += 1; 1381 result += 1; 1382 } 1383 1384 kfree(rd_buf); 1385 return result; 1386 } 1387 1388 /* function: write force DSC on the connector 1389 * 1390 * The write function: dp_dsc_clock_en_write 1391 * enables to force DSC on the connector. 1392 * User can write to either force enable or force disable DSC 1393 * on the next modeset or set it to driver default 1394 * 1395 * Accepted inputs: 1396 * 0 - default DSC enablement policy 1397 * 1 - force enable DSC on the connector 1398 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1399 * 1400 * Writing DSC settings is done with the following command: 1401 * - To force enable DSC (you need to specify 1402 * connector like DP-1): 1403 * 1404 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1405 * 1406 * - To return to default state set the flag to zero and 1407 * let driver deal with DSC automatically 1408 * (you need to specify connector like DP-1): 1409 * 1410 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1411 * 1412 */ 1413 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1414 size_t size, loff_t *pos) 1415 { 1416 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1417 struct drm_connector *connector = &aconnector->base; 1418 struct drm_device *dev = connector->dev; 1419 struct drm_crtc *crtc = NULL; 1420 struct dm_crtc_state *dm_crtc_state = NULL; 1421 struct pipe_ctx *pipe_ctx; 1422 int i; 1423 char *wr_buf = NULL; 1424 uint32_t wr_buf_size = 42; 1425 int max_param_num = 1; 1426 long param[1] = {0}; 1427 uint8_t param_nums = 0; 1428 1429 if (size == 0) 1430 return -EINVAL; 1431 1432 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1433 1434 if (!wr_buf) { 1435 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1436 return -ENOSPC; 1437 } 1438 1439 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1440 (long *)param, buf, 1441 max_param_num, 1442 ¶m_nums)) { 1443 kfree(wr_buf); 1444 return -EINVAL; 1445 } 1446 1447 if (param_nums <= 0) { 1448 DRM_DEBUG_DRIVER("user data not be read\n"); 1449 kfree(wr_buf); 1450 return -EINVAL; 1451 } 1452 1453 for (i = 0; i < MAX_PIPES; i++) { 1454 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1455 if (pipe_ctx && pipe_ctx->stream && 1456 pipe_ctx->stream->link == aconnector->dc_link) 1457 break; 1458 } 1459 1460 if (!pipe_ctx || !pipe_ctx->stream) 1461 goto done; 1462 1463 // Get CRTC state 1464 mutex_lock(&dev->mode_config.mutex); 1465 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1466 1467 if (connector->state == NULL) 1468 goto unlock; 1469 1470 crtc = connector->state->crtc; 1471 if (crtc == NULL) 1472 goto unlock; 1473 1474 drm_modeset_lock(&crtc->mutex, NULL); 1475 if (crtc->state == NULL) 1476 goto unlock; 1477 1478 dm_crtc_state = to_dm_crtc_state(crtc->state); 1479 if (dm_crtc_state->stream == NULL) 1480 goto unlock; 1481 1482 if (param[0] == 1) 1483 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1484 else if (param[0] == 2) 1485 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1486 else 1487 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1488 1489 dm_crtc_state->dsc_force_changed = true; 1490 1491 unlock: 1492 if (crtc) 1493 drm_modeset_unlock(&crtc->mutex); 1494 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1495 mutex_unlock(&dev->mode_config.mutex); 1496 1497 done: 1498 kfree(wr_buf); 1499 return size; 1500 } 1501 1502 /* function: read DSC slice width parameter on the connector 1503 * 1504 * The read function: dp_dsc_slice_width_read 1505 * returns dsc slice width used in the current configuration 1506 * The return is an integer: 0 or other positive number 1507 * 1508 * Access the status with the following command: 1509 * 1510 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1511 * 1512 * 0 - means that DSC is disabled 1513 * 1514 * Any other number more than zero represents the 1515 * slice width currently used by DSC in pixels 1516 * 1517 */ 1518 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1519 size_t size, loff_t *pos) 1520 { 1521 char *rd_buf = NULL; 1522 char *rd_buf_ptr = NULL; 1523 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1524 struct display_stream_compressor *dsc; 1525 struct dcn_dsc_state dsc_state = {0}; 1526 const uint32_t rd_buf_size = 100; 1527 struct pipe_ctx *pipe_ctx; 1528 ssize_t result = 0; 1529 int i, r, str_len = 30; 1530 1531 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1532 1533 if (!rd_buf) 1534 return -ENOMEM; 1535 1536 rd_buf_ptr = rd_buf; 1537 1538 for (i = 0; i < MAX_PIPES; i++) { 1539 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1540 if (pipe_ctx && pipe_ctx->stream && 1541 pipe_ctx->stream->link == aconnector->dc_link) 1542 break; 1543 } 1544 1545 if (!pipe_ctx) 1546 return -ENXIO; 1547 1548 dsc = pipe_ctx->stream_res.dsc; 1549 if (dsc) 1550 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1551 1552 snprintf(rd_buf_ptr, str_len, 1553 "%d\n", 1554 dsc_state.dsc_slice_width); 1555 rd_buf_ptr += str_len; 1556 1557 while (size) { 1558 if (*pos >= rd_buf_size) 1559 break; 1560 1561 r = put_user(*(rd_buf + result), buf); 1562 if (r) 1563 return r; /* r = -EFAULT */ 1564 1565 buf += 1; 1566 size -= 1; 1567 *pos += 1; 1568 result += 1; 1569 } 1570 1571 kfree(rd_buf); 1572 return result; 1573 } 1574 1575 /* function: write DSC slice width parameter 1576 * 1577 * The write function: dp_dsc_slice_width_write 1578 * overwrites automatically generated DSC configuration 1579 * of slice width. 1580 * 1581 * The user has to write the slice width divisible by the 1582 * picture width. 1583 * 1584 * Also the user has to write width in hexidecimal 1585 * rather than in decimal. 1586 * 1587 * Writing DSC settings is done with the following command: 1588 * - To force overwrite slice width: (example sets to 1920 pixels) 1589 * 1590 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1591 * 1592 * - To stop overwriting and let driver find the optimal size, 1593 * set the width to zero: 1594 * 1595 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1596 * 1597 */ 1598 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1599 size_t size, loff_t *pos) 1600 { 1601 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1602 struct pipe_ctx *pipe_ctx; 1603 struct drm_connector *connector = &aconnector->base; 1604 struct drm_device *dev = connector->dev; 1605 struct drm_crtc *crtc = NULL; 1606 struct dm_crtc_state *dm_crtc_state = NULL; 1607 int i; 1608 char *wr_buf = NULL; 1609 uint32_t wr_buf_size = 42; 1610 int max_param_num = 1; 1611 long param[1] = {0}; 1612 uint8_t param_nums = 0; 1613 1614 if (size == 0) 1615 return -EINVAL; 1616 1617 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1618 1619 if (!wr_buf) { 1620 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1621 return -ENOSPC; 1622 } 1623 1624 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1625 (long *)param, buf, 1626 max_param_num, 1627 ¶m_nums)) { 1628 kfree(wr_buf); 1629 return -EINVAL; 1630 } 1631 1632 if (param_nums <= 0) { 1633 DRM_DEBUG_DRIVER("user data not be read\n"); 1634 kfree(wr_buf); 1635 return -EINVAL; 1636 } 1637 1638 for (i = 0; i < MAX_PIPES; i++) { 1639 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1640 if (pipe_ctx && pipe_ctx->stream && 1641 pipe_ctx->stream->link == aconnector->dc_link) 1642 break; 1643 } 1644 1645 if (!pipe_ctx || !pipe_ctx->stream) 1646 goto done; 1647 1648 // Safely get CRTC state 1649 mutex_lock(&dev->mode_config.mutex); 1650 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1651 1652 if (connector->state == NULL) 1653 goto unlock; 1654 1655 crtc = connector->state->crtc; 1656 if (crtc == NULL) 1657 goto unlock; 1658 1659 drm_modeset_lock(&crtc->mutex, NULL); 1660 if (crtc->state == NULL) 1661 goto unlock; 1662 1663 dm_crtc_state = to_dm_crtc_state(crtc->state); 1664 if (dm_crtc_state->stream == NULL) 1665 goto unlock; 1666 1667 if (param[0] > 0) 1668 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1669 pipe_ctx->stream->timing.h_addressable, 1670 param[0]); 1671 else 1672 aconnector->dsc_settings.dsc_num_slices_h = 0; 1673 1674 dm_crtc_state->dsc_force_changed = true; 1675 1676 unlock: 1677 if (crtc) 1678 drm_modeset_unlock(&crtc->mutex); 1679 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1680 mutex_unlock(&dev->mode_config.mutex); 1681 1682 done: 1683 kfree(wr_buf); 1684 return size; 1685 } 1686 1687 /* function: read DSC slice height parameter on the connector 1688 * 1689 * The read function: dp_dsc_slice_height_read 1690 * returns dsc slice height used in the current configuration 1691 * The return is an integer: 0 or other positive number 1692 * 1693 * Access the status with the following command: 1694 * 1695 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1696 * 1697 * 0 - means that DSC is disabled 1698 * 1699 * Any other number more than zero represents the 1700 * slice height currently used by DSC in pixels 1701 * 1702 */ 1703 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1704 size_t size, loff_t *pos) 1705 { 1706 char *rd_buf = NULL; 1707 char *rd_buf_ptr = NULL; 1708 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1709 struct display_stream_compressor *dsc; 1710 struct dcn_dsc_state dsc_state = {0}; 1711 const uint32_t rd_buf_size = 100; 1712 struct pipe_ctx *pipe_ctx; 1713 ssize_t result = 0; 1714 int i, r, str_len = 30; 1715 1716 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1717 1718 if (!rd_buf) 1719 return -ENOMEM; 1720 1721 rd_buf_ptr = rd_buf; 1722 1723 for (i = 0; i < MAX_PIPES; i++) { 1724 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1725 if (pipe_ctx && pipe_ctx->stream && 1726 pipe_ctx->stream->link == aconnector->dc_link) 1727 break; 1728 } 1729 1730 if (!pipe_ctx) 1731 return -ENXIO; 1732 1733 dsc = pipe_ctx->stream_res.dsc; 1734 if (dsc) 1735 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1736 1737 snprintf(rd_buf_ptr, str_len, 1738 "%d\n", 1739 dsc_state.dsc_slice_height); 1740 rd_buf_ptr += str_len; 1741 1742 while (size) { 1743 if (*pos >= rd_buf_size) 1744 break; 1745 1746 r = put_user(*(rd_buf + result), buf); 1747 if (r) 1748 return r; /* r = -EFAULT */ 1749 1750 buf += 1; 1751 size -= 1; 1752 *pos += 1; 1753 result += 1; 1754 } 1755 1756 kfree(rd_buf); 1757 return result; 1758 } 1759 1760 /* function: write DSC slice height parameter 1761 * 1762 * The write function: dp_dsc_slice_height_write 1763 * overwrites automatically generated DSC configuration 1764 * of slice height. 1765 * 1766 * The user has to write the slice height divisible by the 1767 * picture height. 1768 * 1769 * Also the user has to write height in hexidecimal 1770 * rather than in decimal. 1771 * 1772 * Writing DSC settings is done with the following command: 1773 * - To force overwrite slice height (example sets to 128 pixels): 1774 * 1775 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1776 * 1777 * - To stop overwriting and let driver find the optimal size, 1778 * set the height to zero: 1779 * 1780 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1781 * 1782 */ 1783 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1784 size_t size, loff_t *pos) 1785 { 1786 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1787 struct drm_connector *connector = &aconnector->base; 1788 struct drm_device *dev = connector->dev; 1789 struct drm_crtc *crtc = NULL; 1790 struct dm_crtc_state *dm_crtc_state = NULL; 1791 struct pipe_ctx *pipe_ctx; 1792 int i; 1793 char *wr_buf = NULL; 1794 uint32_t wr_buf_size = 42; 1795 int max_param_num = 1; 1796 uint8_t param_nums = 0; 1797 long param[1] = {0}; 1798 1799 if (size == 0) 1800 return -EINVAL; 1801 1802 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1803 1804 if (!wr_buf) { 1805 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1806 return -ENOSPC; 1807 } 1808 1809 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1810 (long *)param, buf, 1811 max_param_num, 1812 ¶m_nums)) { 1813 kfree(wr_buf); 1814 return -EINVAL; 1815 } 1816 1817 if (param_nums <= 0) { 1818 DRM_DEBUG_DRIVER("user data not be read\n"); 1819 kfree(wr_buf); 1820 return -EINVAL; 1821 } 1822 1823 for (i = 0; i < MAX_PIPES; i++) { 1824 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1825 if (pipe_ctx && pipe_ctx->stream && 1826 pipe_ctx->stream->link == aconnector->dc_link) 1827 break; 1828 } 1829 1830 if (!pipe_ctx || !pipe_ctx->stream) 1831 goto done; 1832 1833 // Get CRTC state 1834 mutex_lock(&dev->mode_config.mutex); 1835 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1836 1837 if (connector->state == NULL) 1838 goto unlock; 1839 1840 crtc = connector->state->crtc; 1841 if (crtc == NULL) 1842 goto unlock; 1843 1844 drm_modeset_lock(&crtc->mutex, NULL); 1845 if (crtc->state == NULL) 1846 goto unlock; 1847 1848 dm_crtc_state = to_dm_crtc_state(crtc->state); 1849 if (dm_crtc_state->stream == NULL) 1850 goto unlock; 1851 1852 if (param[0] > 0) 1853 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1854 pipe_ctx->stream->timing.v_addressable, 1855 param[0]); 1856 else 1857 aconnector->dsc_settings.dsc_num_slices_v = 0; 1858 1859 dm_crtc_state->dsc_force_changed = true; 1860 1861 unlock: 1862 if (crtc) 1863 drm_modeset_unlock(&crtc->mutex); 1864 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1865 mutex_unlock(&dev->mode_config.mutex); 1866 1867 done: 1868 kfree(wr_buf); 1869 return size; 1870 } 1871 1872 /* function: read DSC target rate on the connector in bits per pixel 1873 * 1874 * The read function: dp_dsc_bits_per_pixel_read 1875 * returns target rate of compression in bits per pixel 1876 * The return is an integer: 0 or other positive integer 1877 * 1878 * Access it with the following command: 1879 * 1880 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1881 * 1882 * 0 - means that DSC is disabled 1883 */ 1884 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1885 size_t size, loff_t *pos) 1886 { 1887 char *rd_buf = NULL; 1888 char *rd_buf_ptr = NULL; 1889 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1890 struct display_stream_compressor *dsc; 1891 struct dcn_dsc_state dsc_state = {0}; 1892 const uint32_t rd_buf_size = 100; 1893 struct pipe_ctx *pipe_ctx; 1894 ssize_t result = 0; 1895 int i, r, str_len = 30; 1896 1897 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1898 1899 if (!rd_buf) 1900 return -ENOMEM; 1901 1902 rd_buf_ptr = rd_buf; 1903 1904 for (i = 0; i < MAX_PIPES; i++) { 1905 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1906 if (pipe_ctx && pipe_ctx->stream && 1907 pipe_ctx->stream->link == aconnector->dc_link) 1908 break; 1909 } 1910 1911 if (!pipe_ctx) 1912 return -ENXIO; 1913 1914 dsc = pipe_ctx->stream_res.dsc; 1915 if (dsc) 1916 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1917 1918 snprintf(rd_buf_ptr, str_len, 1919 "%d\n", 1920 dsc_state.dsc_bits_per_pixel); 1921 rd_buf_ptr += str_len; 1922 1923 while (size) { 1924 if (*pos >= rd_buf_size) 1925 break; 1926 1927 r = put_user(*(rd_buf + result), buf); 1928 if (r) 1929 return r; /* r = -EFAULT */ 1930 1931 buf += 1; 1932 size -= 1; 1933 *pos += 1; 1934 result += 1; 1935 } 1936 1937 kfree(rd_buf); 1938 return result; 1939 } 1940 1941 /* function: write DSC target rate in bits per pixel 1942 * 1943 * The write function: dp_dsc_bits_per_pixel_write 1944 * overwrites automatically generated DSC configuration 1945 * of DSC target bit rate. 1946 * 1947 * Also the user has to write bpp in hexidecimal 1948 * rather than in decimal. 1949 * 1950 * Writing DSC settings is done with the following command: 1951 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1952 * 1953 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1954 * 1955 * - To stop overwriting and let driver find the optimal rate, 1956 * set the rate to zero: 1957 * 1958 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1959 * 1960 */ 1961 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1962 size_t size, loff_t *pos) 1963 { 1964 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1965 struct drm_connector *connector = &aconnector->base; 1966 struct drm_device *dev = connector->dev; 1967 struct drm_crtc *crtc = NULL; 1968 struct dm_crtc_state *dm_crtc_state = NULL; 1969 struct pipe_ctx *pipe_ctx; 1970 int i; 1971 char *wr_buf = NULL; 1972 uint32_t wr_buf_size = 42; 1973 int max_param_num = 1; 1974 uint8_t param_nums = 0; 1975 long param[1] = {0}; 1976 1977 if (size == 0) 1978 return -EINVAL; 1979 1980 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1981 1982 if (!wr_buf) { 1983 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1984 return -ENOSPC; 1985 } 1986 1987 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1988 (long *)param, buf, 1989 max_param_num, 1990 ¶m_nums)) { 1991 kfree(wr_buf); 1992 return -EINVAL; 1993 } 1994 1995 if (param_nums <= 0) { 1996 DRM_DEBUG_DRIVER("user data not be read\n"); 1997 kfree(wr_buf); 1998 return -EINVAL; 1999 } 2000 2001 for (i = 0; i < MAX_PIPES; i++) { 2002 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2003 if (pipe_ctx && pipe_ctx->stream && 2004 pipe_ctx->stream->link == aconnector->dc_link) 2005 break; 2006 } 2007 2008 if (!pipe_ctx || !pipe_ctx->stream) 2009 goto done; 2010 2011 // Get CRTC state 2012 mutex_lock(&dev->mode_config.mutex); 2013 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2014 2015 if (connector->state == NULL) 2016 goto unlock; 2017 2018 crtc = connector->state->crtc; 2019 if (crtc == NULL) 2020 goto unlock; 2021 2022 drm_modeset_lock(&crtc->mutex, NULL); 2023 if (crtc->state == NULL) 2024 goto unlock; 2025 2026 dm_crtc_state = to_dm_crtc_state(crtc->state); 2027 if (dm_crtc_state->stream == NULL) 2028 goto unlock; 2029 2030 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2031 2032 dm_crtc_state->dsc_force_changed = true; 2033 2034 unlock: 2035 if (crtc) 2036 drm_modeset_unlock(&crtc->mutex); 2037 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2038 mutex_unlock(&dev->mode_config.mutex); 2039 2040 done: 2041 kfree(wr_buf); 2042 return size; 2043 } 2044 2045 /* function: read DSC picture width parameter on the connector 2046 * 2047 * The read function: dp_dsc_pic_width_read 2048 * returns dsc picture width used in the current configuration 2049 * It is the same as h_addressable of the current 2050 * display's timing 2051 * The return is an integer: 0 or other positive integer 2052 * If 0 then DSC is disabled. 2053 * 2054 * Access it with the following command: 2055 * 2056 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2057 * 2058 * 0 - means that DSC is disabled 2059 */ 2060 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2061 size_t size, loff_t *pos) 2062 { 2063 char *rd_buf = NULL; 2064 char *rd_buf_ptr = NULL; 2065 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2066 struct display_stream_compressor *dsc; 2067 struct dcn_dsc_state dsc_state = {0}; 2068 const uint32_t rd_buf_size = 100; 2069 struct pipe_ctx *pipe_ctx; 2070 ssize_t result = 0; 2071 int i, r, str_len = 30; 2072 2073 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2074 2075 if (!rd_buf) 2076 return -ENOMEM; 2077 2078 rd_buf_ptr = rd_buf; 2079 2080 for (i = 0; i < MAX_PIPES; i++) { 2081 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2082 if (pipe_ctx && pipe_ctx->stream && 2083 pipe_ctx->stream->link == aconnector->dc_link) 2084 break; 2085 } 2086 2087 if (!pipe_ctx) 2088 return -ENXIO; 2089 2090 dsc = pipe_ctx->stream_res.dsc; 2091 if (dsc) 2092 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2093 2094 snprintf(rd_buf_ptr, str_len, 2095 "%d\n", 2096 dsc_state.dsc_pic_width); 2097 rd_buf_ptr += str_len; 2098 2099 while (size) { 2100 if (*pos >= rd_buf_size) 2101 break; 2102 2103 r = put_user(*(rd_buf + result), buf); 2104 if (r) 2105 return r; /* r = -EFAULT */ 2106 2107 buf += 1; 2108 size -= 1; 2109 *pos += 1; 2110 result += 1; 2111 } 2112 2113 kfree(rd_buf); 2114 return result; 2115 } 2116 2117 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2118 size_t size, loff_t *pos) 2119 { 2120 char *rd_buf = NULL; 2121 char *rd_buf_ptr = NULL; 2122 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2123 struct display_stream_compressor *dsc; 2124 struct dcn_dsc_state dsc_state = {0}; 2125 const uint32_t rd_buf_size = 100; 2126 struct pipe_ctx *pipe_ctx; 2127 ssize_t result = 0; 2128 int i, r, str_len = 30; 2129 2130 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2131 2132 if (!rd_buf) 2133 return -ENOMEM; 2134 2135 rd_buf_ptr = rd_buf; 2136 2137 for (i = 0; i < MAX_PIPES; i++) { 2138 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2139 if (pipe_ctx && pipe_ctx->stream && 2140 pipe_ctx->stream->link == aconnector->dc_link) 2141 break; 2142 } 2143 2144 if (!pipe_ctx) 2145 return -ENXIO; 2146 2147 dsc = pipe_ctx->stream_res.dsc; 2148 if (dsc) 2149 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2150 2151 snprintf(rd_buf_ptr, str_len, 2152 "%d\n", 2153 dsc_state.dsc_pic_height); 2154 rd_buf_ptr += str_len; 2155 2156 while (size) { 2157 if (*pos >= rd_buf_size) 2158 break; 2159 2160 r = put_user(*(rd_buf + result), buf); 2161 if (r) 2162 return r; /* r = -EFAULT */ 2163 2164 buf += 1; 2165 size -= 1; 2166 *pos += 1; 2167 result += 1; 2168 } 2169 2170 kfree(rd_buf); 2171 return result; 2172 } 2173 2174 /* function: read DSC chunk size parameter on the connector 2175 * 2176 * The read function: dp_dsc_chunk_size_read 2177 * returns dsc chunk size set in the current configuration 2178 * The value is calculated automatically by DSC code 2179 * and depends on slice parameters and bpp target rate 2180 * The return is an integer: 0 or other positive integer 2181 * If 0 then DSC is disabled. 2182 * 2183 * Access it with the following command: 2184 * 2185 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2186 * 2187 * 0 - means that DSC is disabled 2188 */ 2189 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2190 size_t size, loff_t *pos) 2191 { 2192 char *rd_buf = NULL; 2193 char *rd_buf_ptr = NULL; 2194 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2195 struct display_stream_compressor *dsc; 2196 struct dcn_dsc_state dsc_state = {0}; 2197 const uint32_t rd_buf_size = 100; 2198 struct pipe_ctx *pipe_ctx; 2199 ssize_t result = 0; 2200 int i, r, str_len = 30; 2201 2202 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2203 2204 if (!rd_buf) 2205 return -ENOMEM; 2206 2207 rd_buf_ptr = rd_buf; 2208 2209 for (i = 0; i < MAX_PIPES; i++) { 2210 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2211 if (pipe_ctx && pipe_ctx->stream && 2212 pipe_ctx->stream->link == aconnector->dc_link) 2213 break; 2214 } 2215 2216 if (!pipe_ctx) 2217 return -ENXIO; 2218 2219 dsc = pipe_ctx->stream_res.dsc; 2220 if (dsc) 2221 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2222 2223 snprintf(rd_buf_ptr, str_len, 2224 "%d\n", 2225 dsc_state.dsc_chunk_size); 2226 rd_buf_ptr += str_len; 2227 2228 while (size) { 2229 if (*pos >= rd_buf_size) 2230 break; 2231 2232 r = put_user(*(rd_buf + result), buf); 2233 if (r) 2234 return r; /* r = -EFAULT */ 2235 2236 buf += 1; 2237 size -= 1; 2238 *pos += 1; 2239 result += 1; 2240 } 2241 2242 kfree(rd_buf); 2243 return result; 2244 } 2245 2246 /* function: read DSC slice bpg offset on the connector 2247 * 2248 * The read function: dp_dsc_slice_bpg_offset_read 2249 * returns dsc bpg slice offset set in the current configuration 2250 * The value is calculated automatically by DSC code 2251 * and depends on slice parameters and bpp target rate 2252 * The return is an integer: 0 or other positive integer 2253 * If 0 then DSC is disabled. 2254 * 2255 * Access it with the following command: 2256 * 2257 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2258 * 2259 * 0 - means that DSC is disabled 2260 */ 2261 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2262 size_t size, loff_t *pos) 2263 { 2264 char *rd_buf = NULL; 2265 char *rd_buf_ptr = NULL; 2266 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2267 struct display_stream_compressor *dsc; 2268 struct dcn_dsc_state dsc_state = {0}; 2269 const uint32_t rd_buf_size = 100; 2270 struct pipe_ctx *pipe_ctx; 2271 ssize_t result = 0; 2272 int i, r, str_len = 30; 2273 2274 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2275 2276 if (!rd_buf) 2277 return -ENOMEM; 2278 2279 rd_buf_ptr = rd_buf; 2280 2281 for (i = 0; i < MAX_PIPES; i++) { 2282 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2283 if (pipe_ctx && pipe_ctx->stream && 2284 pipe_ctx->stream->link == aconnector->dc_link) 2285 break; 2286 } 2287 2288 if (!pipe_ctx) 2289 return -ENXIO; 2290 2291 dsc = pipe_ctx->stream_res.dsc; 2292 if (dsc) 2293 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2294 2295 snprintf(rd_buf_ptr, str_len, 2296 "%d\n", 2297 dsc_state.dsc_slice_bpg_offset); 2298 rd_buf_ptr += str_len; 2299 2300 while (size) { 2301 if (*pos >= rd_buf_size) 2302 break; 2303 2304 r = put_user(*(rd_buf + result), buf); 2305 if (r) 2306 return r; /* r = -EFAULT */ 2307 2308 buf += 1; 2309 size -= 1; 2310 *pos += 1; 2311 result += 1; 2312 } 2313 2314 kfree(rd_buf); 2315 return result; 2316 } 2317 2318 2319 /* 2320 * function description: Read max_requested_bpc property from the connector 2321 * 2322 * Access it with the following command: 2323 * 2324 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2325 * 2326 */ 2327 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2328 size_t size, loff_t *pos) 2329 { 2330 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2331 struct drm_connector *connector = &aconnector->base; 2332 struct drm_device *dev = connector->dev; 2333 struct dm_connector_state *state; 2334 ssize_t result = 0; 2335 char *rd_buf = NULL; 2336 char *rd_buf_ptr = NULL; 2337 const uint32_t rd_buf_size = 10; 2338 int r; 2339 2340 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2341 2342 if (!rd_buf) 2343 return -ENOMEM; 2344 2345 mutex_lock(&dev->mode_config.mutex); 2346 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2347 2348 if (connector->state == NULL) 2349 goto unlock; 2350 2351 state = to_dm_connector_state(connector->state); 2352 2353 rd_buf_ptr = rd_buf; 2354 snprintf(rd_buf_ptr, rd_buf_size, 2355 "%u\n", 2356 state->base.max_requested_bpc); 2357 2358 while (size) { 2359 if (*pos >= rd_buf_size) 2360 break; 2361 2362 r = put_user(*(rd_buf + result), buf); 2363 if (r) { 2364 result = r; /* r = -EFAULT */ 2365 goto unlock; 2366 } 2367 buf += 1; 2368 size -= 1; 2369 *pos += 1; 2370 result += 1; 2371 } 2372 unlock: 2373 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2374 mutex_unlock(&dev->mode_config.mutex); 2375 kfree(rd_buf); 2376 return result; 2377 } 2378 2379 2380 /* 2381 * function description: Set max_requested_bpc property on the connector 2382 * 2383 * This function will not force the input BPC on connector, it will only 2384 * change the max value. This is equivalent to setting max_bpc through 2385 * xrandr. 2386 * 2387 * The BPC value written must be >= 6 and <= 16. Values outside of this 2388 * range will result in errors. 2389 * 2390 * BPC values: 2391 * 0x6 - 6 BPC 2392 * 0x8 - 8 BPC 2393 * 0xa - 10 BPC 2394 * 0xc - 12 BPC 2395 * 0x10 - 16 BPC 2396 * 2397 * Write the max_bpc in the following way: 2398 * 2399 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2400 * 2401 */ 2402 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2403 size_t size, loff_t *pos) 2404 { 2405 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2406 struct drm_connector *connector = &aconnector->base; 2407 struct dm_connector_state *state; 2408 struct drm_device *dev = connector->dev; 2409 char *wr_buf = NULL; 2410 uint32_t wr_buf_size = 42; 2411 int max_param_num = 1; 2412 long param[1] = {0}; 2413 uint8_t param_nums = 0; 2414 2415 if (size == 0) 2416 return -EINVAL; 2417 2418 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2419 2420 if (!wr_buf) { 2421 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2422 return -ENOSPC; 2423 } 2424 2425 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2426 (long *)param, buf, 2427 max_param_num, 2428 ¶m_nums)) { 2429 kfree(wr_buf); 2430 return -EINVAL; 2431 } 2432 2433 if (param_nums <= 0) { 2434 DRM_DEBUG_DRIVER("user data not be read\n"); 2435 kfree(wr_buf); 2436 return -EINVAL; 2437 } 2438 2439 if (param[0] < 6 || param[0] > 16) { 2440 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2441 kfree(wr_buf); 2442 return -EINVAL; 2443 } 2444 2445 mutex_lock(&dev->mode_config.mutex); 2446 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2447 2448 if (connector->state == NULL) 2449 goto unlock; 2450 2451 state = to_dm_connector_state(connector->state); 2452 state->base.max_requested_bpc = param[0]; 2453 unlock: 2454 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2455 mutex_unlock(&dev->mode_config.mutex); 2456 2457 kfree(wr_buf); 2458 return size; 2459 } 2460 2461 /* 2462 * Backlight at this moment. Read only. 2463 * As written to display, taking ABM and backlight lut into account. 2464 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2465 * 2466 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2467 */ 2468 static int current_backlight_show(struct seq_file *m, void *unused) 2469 { 2470 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2471 struct dc_link *link = aconnector->dc_link; 2472 unsigned int backlight; 2473 2474 backlight = dc_link_get_backlight_level(link); 2475 seq_printf(m, "0x%x\n", backlight); 2476 2477 return 0; 2478 } 2479 2480 /* 2481 * Backlight value that is being approached. Read only. 2482 * As written to display, taking ABM and backlight lut into account. 2483 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2484 * 2485 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2486 */ 2487 static int target_backlight_show(struct seq_file *m, void *unused) 2488 { 2489 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2490 struct dc_link *link = aconnector->dc_link; 2491 unsigned int backlight; 2492 2493 backlight = dc_link_get_target_backlight_pwm(link); 2494 seq_printf(m, "0x%x\n", backlight); 2495 2496 return 0; 2497 } 2498 2499 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2500 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2501 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2502 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2503 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2504 #ifdef CONFIG_DRM_AMD_DC_HDCP 2505 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2506 #endif 2507 DEFINE_SHOW_ATTRIBUTE(internal_display); 2508 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2509 2510 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2511 .owner = THIS_MODULE, 2512 .read = dp_dsc_clock_en_read, 2513 .write = dp_dsc_clock_en_write, 2514 .llseek = default_llseek 2515 }; 2516 2517 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2518 .owner = THIS_MODULE, 2519 .read = dp_dsc_slice_width_read, 2520 .write = dp_dsc_slice_width_write, 2521 .llseek = default_llseek 2522 }; 2523 2524 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2525 .owner = THIS_MODULE, 2526 .read = dp_dsc_slice_height_read, 2527 .write = dp_dsc_slice_height_write, 2528 .llseek = default_llseek 2529 }; 2530 2531 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2532 .owner = THIS_MODULE, 2533 .read = dp_dsc_bits_per_pixel_read, 2534 .write = dp_dsc_bits_per_pixel_write, 2535 .llseek = default_llseek 2536 }; 2537 2538 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2539 .owner = THIS_MODULE, 2540 .read = dp_dsc_pic_width_read, 2541 .llseek = default_llseek 2542 }; 2543 2544 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2545 .owner = THIS_MODULE, 2546 .read = dp_dsc_pic_height_read, 2547 .llseek = default_llseek 2548 }; 2549 2550 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2551 .owner = THIS_MODULE, 2552 .read = dp_dsc_chunk_size_read, 2553 .llseek = default_llseek 2554 }; 2555 2556 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2557 .owner = THIS_MODULE, 2558 .read = dp_dsc_slice_bpg_offset_read, 2559 .llseek = default_llseek 2560 }; 2561 2562 static const struct file_operations trigger_hotplug_debugfs_fops = { 2563 .owner = THIS_MODULE, 2564 .write = trigger_hotplug, 2565 .llseek = default_llseek 2566 }; 2567 2568 static const struct file_operations dp_link_settings_debugfs_fops = { 2569 .owner = THIS_MODULE, 2570 .read = dp_link_settings_read, 2571 .write = dp_link_settings_write, 2572 .llseek = default_llseek 2573 }; 2574 2575 static const struct file_operations dp_phy_settings_debugfs_fop = { 2576 .owner = THIS_MODULE, 2577 .read = dp_phy_settings_read, 2578 .write = dp_phy_settings_write, 2579 .llseek = default_llseek 2580 }; 2581 2582 static const struct file_operations dp_phy_test_pattern_fops = { 2583 .owner = THIS_MODULE, 2584 .write = dp_phy_test_pattern_debugfs_write, 2585 .llseek = default_llseek 2586 }; 2587 2588 static const struct file_operations sdp_message_fops = { 2589 .owner = THIS_MODULE, 2590 .write = dp_sdp_message_debugfs_write, 2591 .llseek = default_llseek 2592 }; 2593 2594 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2595 .owner = THIS_MODULE, 2596 .write = dp_dpcd_address_write, 2597 .llseek = default_llseek 2598 }; 2599 2600 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2601 .owner = THIS_MODULE, 2602 .write = dp_dpcd_size_write, 2603 .llseek = default_llseek 2604 }; 2605 2606 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2607 .owner = THIS_MODULE, 2608 .read = dp_dpcd_data_read, 2609 .write = dp_dpcd_data_write, 2610 .llseek = default_llseek 2611 }; 2612 2613 static const struct file_operations dp_max_bpc_debugfs_fops = { 2614 .owner = THIS_MODULE, 2615 .read = dp_max_bpc_read, 2616 .write = dp_max_bpc_write, 2617 .llseek = default_llseek 2618 }; 2619 2620 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2621 .owner = THIS_MODULE, 2622 .write = dp_dsc_passthrough_set, 2623 .llseek = default_llseek 2624 }; 2625 2626 static const struct { 2627 char *name; 2628 const struct file_operations *fops; 2629 } dp_debugfs_entries[] = { 2630 {"link_settings", &dp_link_settings_debugfs_fops}, 2631 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2632 {"lttpr_status", &dp_lttpr_status_fops}, 2633 {"test_pattern", &dp_phy_test_pattern_fops}, 2634 #ifdef CONFIG_DRM_AMD_DC_HDCP 2635 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2636 #endif 2637 {"sdp_message", &sdp_message_fops}, 2638 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2639 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2640 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2641 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2642 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2643 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2644 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2645 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2646 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2647 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2648 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2649 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2650 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2651 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2652 }; 2653 2654 #ifdef CONFIG_DRM_AMD_DC_HDCP 2655 static const struct { 2656 char *name; 2657 const struct file_operations *fops; 2658 } hdmi_debugfs_entries[] = { 2659 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2660 }; 2661 #endif 2662 /* 2663 * Force YUV420 output if available from the given mode 2664 */ 2665 static int force_yuv420_output_set(void *data, u64 val) 2666 { 2667 struct amdgpu_dm_connector *connector = data; 2668 2669 connector->force_yuv420_output = (bool)val; 2670 2671 return 0; 2672 } 2673 2674 /* 2675 * Check if YUV420 is forced when available from the given mode 2676 */ 2677 static int force_yuv420_output_get(void *data, u64 *val) 2678 { 2679 struct amdgpu_dm_connector *connector = data; 2680 2681 *val = connector->force_yuv420_output; 2682 2683 return 0; 2684 } 2685 2686 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2687 force_yuv420_output_set, "%llu\n"); 2688 2689 /* 2690 * Read PSR state 2691 */ 2692 static int psr_get(void *data, u64 *val) 2693 { 2694 struct amdgpu_dm_connector *connector = data; 2695 struct dc_link *link = connector->dc_link; 2696 enum dc_psr_state state = PSR_STATE0; 2697 2698 dc_link_get_psr_state(link, &state); 2699 2700 *val = state; 2701 2702 return 0; 2703 } 2704 2705 /* 2706 * Set dmcub trace event IRQ enable or disable. 2707 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2708 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2709 */ 2710 static int dmcub_trace_event_state_set(void *data, u64 val) 2711 { 2712 struct amdgpu_device *adev = data; 2713 2714 if (val == 1 || val == 0) { 2715 dc_dmub_trace_event_control(adev->dm.dc, val); 2716 adev->dm.dmcub_trace_event_en = (bool)val; 2717 } else 2718 return 0; 2719 2720 return 0; 2721 } 2722 2723 /* 2724 * The interface doesn't need get function, so it will return the 2725 * value of zero 2726 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2727 */ 2728 static int dmcub_trace_event_state_get(void *data, u64 *val) 2729 { 2730 struct amdgpu_device *adev = data; 2731 2732 *val = adev->dm.dmcub_trace_event_en; 2733 return 0; 2734 } 2735 2736 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2737 dmcub_trace_event_state_set, "%llu\n"); 2738 2739 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2740 2741 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2742 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2743 2744 static const struct { 2745 char *name; 2746 const struct file_operations *fops; 2747 } connector_debugfs_entries[] = { 2748 {"force_yuv420_output", &force_yuv420_output_fops}, 2749 {"output_bpc", &output_bpc_fops}, 2750 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2751 {"internal_display", &internal_display_fops} 2752 }; 2753 2754 /* 2755 * Returns supported customized link rates by this eDP panel. 2756 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2757 */ 2758 static int edp_ilr_show(struct seq_file *m, void *unused) 2759 { 2760 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2761 struct dc_link *link = aconnector->dc_link; 2762 uint8_t supported_link_rates[16]; 2763 uint32_t link_rate_in_khz; 2764 uint32_t entry = 0; 2765 uint8_t dpcd_rev; 2766 2767 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2768 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2769 supported_link_rates, sizeof(supported_link_rates)); 2770 2771 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2772 2773 if (dpcd_rev >= DP_DPCD_REV_13 && 2774 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2775 2776 for (entry = 0; entry < 16; entry += 2) { 2777 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2778 supported_link_rates[entry]) * 200; 2779 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2780 } 2781 } else { 2782 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2783 } 2784 2785 return 0; 2786 } 2787 2788 /* 2789 * Set supported customized link rate to eDP panel. 2790 * 2791 * echo <lane_count> <link_rate option> > ilr_setting 2792 * 2793 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2794 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2795 * to set 4 lanes and 2.16 GHz 2796 */ 2797 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2798 size_t size, loff_t *pos) 2799 { 2800 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2801 struct dc_link *link = connector->dc_link; 2802 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2803 struct dc *dc = (struct dc *)link->dc; 2804 struct dc_link_settings prefer_link_settings; 2805 char *wr_buf = NULL; 2806 const uint32_t wr_buf_size = 40; 2807 /* 0: lane_count; 1: link_rate */ 2808 int max_param_num = 2; 2809 uint8_t param_nums = 0; 2810 long param[2]; 2811 bool valid_input = true; 2812 2813 if (size == 0) 2814 return -EINVAL; 2815 2816 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2817 if (!wr_buf) 2818 return -ENOMEM; 2819 2820 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2821 (long *)param, buf, 2822 max_param_num, 2823 ¶m_nums)) { 2824 kfree(wr_buf); 2825 return -EINVAL; 2826 } 2827 2828 if (param_nums <= 0) { 2829 kfree(wr_buf); 2830 return -EINVAL; 2831 } 2832 2833 switch (param[0]) { 2834 case LANE_COUNT_ONE: 2835 case LANE_COUNT_TWO: 2836 case LANE_COUNT_FOUR: 2837 break; 2838 default: 2839 valid_input = false; 2840 break; 2841 } 2842 2843 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2844 valid_input = false; 2845 2846 if (!valid_input) { 2847 kfree(wr_buf); 2848 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2849 prefer_link_settings.use_link_rate_set = false; 2850 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, true); 2851 return size; 2852 } 2853 2854 /* save user force lane_count, link_rate to preferred settings 2855 * spread spectrum will not be changed 2856 */ 2857 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2858 prefer_link_settings.lane_count = param[0]; 2859 prefer_link_settings.use_link_rate_set = true; 2860 prefer_link_settings.link_rate_set = param[1]; 2861 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2862 2863 mutex_lock(&adev->dm.dc_lock); 2864 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2865 NULL, link, false); 2866 mutex_unlock(&adev->dm.dc_lock); 2867 2868 kfree(wr_buf); 2869 return size; 2870 } 2871 2872 static int edp_ilr_open(struct inode *inode, struct file *file) 2873 { 2874 return single_open(file, edp_ilr_show, inode->i_private); 2875 } 2876 2877 static const struct file_operations edp_ilr_debugfs_fops = { 2878 .owner = THIS_MODULE, 2879 .open = edp_ilr_open, 2880 .read = seq_read, 2881 .llseek = seq_lseek, 2882 .release = single_release, 2883 .write = edp_ilr_write 2884 }; 2885 2886 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2887 { 2888 int i; 2889 struct dentry *dir = connector->base.debugfs_entry; 2890 2891 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2892 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2893 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2894 debugfs_create_file(dp_debugfs_entries[i].name, 2895 0644, dir, connector, 2896 dp_debugfs_entries[i].fops); 2897 } 2898 } 2899 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2900 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 2901 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2902 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2903 ¤t_backlight_fops); 2904 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2905 &target_backlight_fops); 2906 debugfs_create_file("ilr_setting", 0644, dir, connector, 2907 &edp_ilr_debugfs_fops); 2908 } 2909 2910 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2911 debugfs_create_file(connector_debugfs_entries[i].name, 2912 0644, dir, connector, 2913 connector_debugfs_entries[i].fops); 2914 } 2915 2916 connector->debugfs_dpcd_address = 0; 2917 connector->debugfs_dpcd_size = 0; 2918 2919 #ifdef CONFIG_DRM_AMD_DC_HDCP 2920 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2921 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2922 debugfs_create_file(hdmi_debugfs_entries[i].name, 2923 0644, dir, connector, 2924 hdmi_debugfs_entries[i].fops); 2925 } 2926 } 2927 #endif 2928 } 2929 2930 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2931 /* 2932 * Set crc window coordinate x start 2933 */ 2934 static int crc_win_x_start_set(void *data, u64 val) 2935 { 2936 struct drm_crtc *crtc = data; 2937 struct drm_device *drm_dev = crtc->dev; 2938 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2939 2940 spin_lock_irq(&drm_dev->event_lock); 2941 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2942 acrtc->dm_irq_params.crc_window.update_win = false; 2943 spin_unlock_irq(&drm_dev->event_lock); 2944 2945 return 0; 2946 } 2947 2948 /* 2949 * Get crc window coordinate x start 2950 */ 2951 static int crc_win_x_start_get(void *data, u64 *val) 2952 { 2953 struct drm_crtc *crtc = data; 2954 struct drm_device *drm_dev = crtc->dev; 2955 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2956 2957 spin_lock_irq(&drm_dev->event_lock); 2958 *val = acrtc->dm_irq_params.crc_window.x_start; 2959 spin_unlock_irq(&drm_dev->event_lock); 2960 2961 return 0; 2962 } 2963 2964 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 2965 crc_win_x_start_set, "%llu\n"); 2966 2967 2968 /* 2969 * Set crc window coordinate y start 2970 */ 2971 static int crc_win_y_start_set(void *data, u64 val) 2972 { 2973 struct drm_crtc *crtc = data; 2974 struct drm_device *drm_dev = crtc->dev; 2975 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2976 2977 spin_lock_irq(&drm_dev->event_lock); 2978 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 2979 acrtc->dm_irq_params.crc_window.update_win = false; 2980 spin_unlock_irq(&drm_dev->event_lock); 2981 2982 return 0; 2983 } 2984 2985 /* 2986 * Get crc window coordinate y start 2987 */ 2988 static int crc_win_y_start_get(void *data, u64 *val) 2989 { 2990 struct drm_crtc *crtc = data; 2991 struct drm_device *drm_dev = crtc->dev; 2992 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2993 2994 spin_lock_irq(&drm_dev->event_lock); 2995 *val = acrtc->dm_irq_params.crc_window.y_start; 2996 spin_unlock_irq(&drm_dev->event_lock); 2997 2998 return 0; 2999 } 3000 3001 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3002 crc_win_y_start_set, "%llu\n"); 3003 3004 /* 3005 * Set crc window coordinate x end 3006 */ 3007 static int crc_win_x_end_set(void *data, u64 val) 3008 { 3009 struct drm_crtc *crtc = data; 3010 struct drm_device *drm_dev = crtc->dev; 3011 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3012 3013 spin_lock_irq(&drm_dev->event_lock); 3014 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 3015 acrtc->dm_irq_params.crc_window.update_win = false; 3016 spin_unlock_irq(&drm_dev->event_lock); 3017 3018 return 0; 3019 } 3020 3021 /* 3022 * Get crc window coordinate x end 3023 */ 3024 static int crc_win_x_end_get(void *data, u64 *val) 3025 { 3026 struct drm_crtc *crtc = data; 3027 struct drm_device *drm_dev = crtc->dev; 3028 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3029 3030 spin_lock_irq(&drm_dev->event_lock); 3031 *val = acrtc->dm_irq_params.crc_window.x_end; 3032 spin_unlock_irq(&drm_dev->event_lock); 3033 3034 return 0; 3035 } 3036 3037 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3038 crc_win_x_end_set, "%llu\n"); 3039 3040 /* 3041 * Set crc window coordinate y end 3042 */ 3043 static int crc_win_y_end_set(void *data, u64 val) 3044 { 3045 struct drm_crtc *crtc = data; 3046 struct drm_device *drm_dev = crtc->dev; 3047 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3048 3049 spin_lock_irq(&drm_dev->event_lock); 3050 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 3051 acrtc->dm_irq_params.crc_window.update_win = false; 3052 spin_unlock_irq(&drm_dev->event_lock); 3053 3054 return 0; 3055 } 3056 3057 /* 3058 * Get crc window coordinate y end 3059 */ 3060 static int crc_win_y_end_get(void *data, u64 *val) 3061 { 3062 struct drm_crtc *crtc = data; 3063 struct drm_device *drm_dev = crtc->dev; 3064 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3065 3066 spin_lock_irq(&drm_dev->event_lock); 3067 *val = acrtc->dm_irq_params.crc_window.y_end; 3068 spin_unlock_irq(&drm_dev->event_lock); 3069 3070 return 0; 3071 } 3072 3073 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3074 crc_win_y_end_set, "%llu\n"); 3075 /* 3076 * Trigger to commit crc window 3077 */ 3078 static int crc_win_update_set(void *data, u64 val) 3079 { 3080 struct drm_crtc *new_crtc = data; 3081 struct drm_crtc *old_crtc = NULL; 3082 struct amdgpu_crtc *new_acrtc, *old_acrtc; 3083 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 3084 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 3085 3086 if (!crc_rd_wrk) 3087 return 0; 3088 3089 if (val) { 3090 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3091 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 3092 if (crc_rd_wrk->crtc) { 3093 old_crtc = crc_rd_wrk->crtc; 3094 old_acrtc = to_amdgpu_crtc(old_crtc); 3095 } 3096 new_acrtc = to_amdgpu_crtc(new_crtc); 3097 3098 if (old_crtc && old_crtc != new_crtc) { 3099 old_acrtc->dm_irq_params.crc_window.activated = false; 3100 old_acrtc->dm_irq_params.crc_window.update_win = false; 3101 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3102 3103 new_acrtc->dm_irq_params.crc_window.activated = true; 3104 new_acrtc->dm_irq_params.crc_window.update_win = true; 3105 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3106 crc_rd_wrk->crtc = new_crtc; 3107 } else { 3108 new_acrtc->dm_irq_params.crc_window.activated = true; 3109 new_acrtc->dm_irq_params.crc_window.update_win = true; 3110 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3111 crc_rd_wrk->crtc = new_crtc; 3112 } 3113 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 3114 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3115 } 3116 3117 return 0; 3118 } 3119 3120 /* 3121 * Get crc window update flag 3122 */ 3123 static int crc_win_update_get(void *data, u64 *val) 3124 { 3125 *val = 0; 3126 return 0; 3127 } 3128 3129 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3130 crc_win_update_set, "%llu\n"); 3131 3132 void crtc_debugfs_init(struct drm_crtc *crtc) 3133 { 3134 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3135 3136 if (!dir) 3137 return; 3138 3139 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3140 &crc_win_x_start_fops); 3141 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3142 &crc_win_y_start_fops); 3143 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3144 &crc_win_x_end_fops); 3145 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3146 &crc_win_y_end_fops); 3147 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3148 &crc_win_update_fops); 3149 3150 } 3151 #endif 3152 /* 3153 * Writes DTN log state to the user supplied buffer. 3154 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3155 */ 3156 static ssize_t dtn_log_read( 3157 struct file *f, 3158 char __user *buf, 3159 size_t size, 3160 loff_t *pos) 3161 { 3162 struct amdgpu_device *adev = file_inode(f)->i_private; 3163 struct dc *dc = adev->dm.dc; 3164 struct dc_log_buffer_ctx log_ctx = { 0 }; 3165 ssize_t result = 0; 3166 3167 if (!buf || !size) 3168 return -EINVAL; 3169 3170 if (!dc->hwss.log_hw_state) 3171 return 0; 3172 3173 dc->hwss.log_hw_state(dc, &log_ctx); 3174 3175 if (*pos < log_ctx.pos) { 3176 size_t to_copy = log_ctx.pos - *pos; 3177 3178 to_copy = min(to_copy, size); 3179 3180 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3181 *pos += to_copy; 3182 result = to_copy; 3183 } 3184 } 3185 3186 kfree(log_ctx.buf); 3187 3188 return result; 3189 } 3190 3191 /* 3192 * Writes DTN log state to dmesg when triggered via a write. 3193 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3194 */ 3195 static ssize_t dtn_log_write( 3196 struct file *f, 3197 const char __user *buf, 3198 size_t size, 3199 loff_t *pos) 3200 { 3201 struct amdgpu_device *adev = file_inode(f)->i_private; 3202 struct dc *dc = adev->dm.dc; 3203 3204 /* Write triggers log output via dmesg. */ 3205 if (size == 0) 3206 return 0; 3207 3208 if (dc->hwss.log_hw_state) 3209 dc->hwss.log_hw_state(dc, NULL); 3210 3211 return size; 3212 } 3213 3214 static int mst_topo_show(struct seq_file *m, void *unused) 3215 { 3216 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3217 struct drm_device *dev = adev_to_drm(adev); 3218 struct drm_connector *connector; 3219 struct drm_connector_list_iter conn_iter; 3220 struct amdgpu_dm_connector *aconnector; 3221 3222 drm_connector_list_iter_begin(dev, &conn_iter); 3223 drm_for_each_connector_iter(connector, &conn_iter) { 3224 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3225 continue; 3226 3227 aconnector = to_amdgpu_dm_connector(connector); 3228 3229 /* Ensure we're only dumping the topology of a root mst node */ 3230 if (!aconnector->mst_mgr.mst_state) 3231 continue; 3232 3233 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3234 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3235 } 3236 drm_connector_list_iter_end(&conn_iter); 3237 3238 return 0; 3239 } 3240 3241 /* 3242 * Sets trigger hpd for MST topologies. 3243 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3244 * All topologies will be disconnected if val of 0 is set . 3245 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3246 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3247 */ 3248 static int trigger_hpd_mst_set(void *data, u64 val) 3249 { 3250 struct amdgpu_device *adev = data; 3251 struct drm_device *dev = adev_to_drm(adev); 3252 struct drm_connector_list_iter iter; 3253 struct amdgpu_dm_connector *aconnector; 3254 struct drm_connector *connector; 3255 struct dc_link *link = NULL; 3256 3257 if (val == 1) { 3258 drm_connector_list_iter_begin(dev, &iter); 3259 drm_for_each_connector_iter(connector, &iter) { 3260 aconnector = to_amdgpu_dm_connector(connector); 3261 if (aconnector->dc_link->type == dc_connection_mst_branch && 3262 aconnector->mst_mgr.aux) { 3263 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3264 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3265 } 3266 } 3267 } else if (val == 0) { 3268 drm_connector_list_iter_begin(dev, &iter); 3269 drm_for_each_connector_iter(connector, &iter) { 3270 aconnector = to_amdgpu_dm_connector(connector); 3271 if (!aconnector->dc_link) 3272 continue; 3273 3274 if (!aconnector->mst_port) 3275 continue; 3276 3277 link = aconnector->dc_link; 3278 dp_receiver_power_ctrl(link, false); 3279 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3280 link->mst_stream_alloc_table.stream_count = 0; 3281 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3282 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3283 } 3284 } else { 3285 return 0; 3286 } 3287 drm_kms_helper_hotplug_event(dev); 3288 3289 return 0; 3290 } 3291 3292 /* 3293 * The interface doesn't need get function, so it will return the 3294 * value of zero 3295 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3296 */ 3297 static int trigger_hpd_mst_get(void *data, u64 *val) 3298 { 3299 *val = 0; 3300 return 0; 3301 } 3302 3303 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3304 trigger_hpd_mst_set, "%llu\n"); 3305 3306 3307 /* 3308 * Sets the force_timing_sync debug option from the given string. 3309 * All connected displays will be force synchronized immediately. 3310 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3311 */ 3312 static int force_timing_sync_set(void *data, u64 val) 3313 { 3314 struct amdgpu_device *adev = data; 3315 3316 adev->dm.force_timing_sync = (bool)val; 3317 3318 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3319 3320 return 0; 3321 } 3322 3323 /* 3324 * Gets the force_timing_sync debug option value into the given buffer. 3325 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3326 */ 3327 static int force_timing_sync_get(void *data, u64 *val) 3328 { 3329 struct amdgpu_device *adev = data; 3330 3331 *val = adev->dm.force_timing_sync; 3332 3333 return 0; 3334 } 3335 3336 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3337 force_timing_sync_set, "%llu\n"); 3338 3339 3340 /* 3341 * Disables all HPD and HPD RX interrupt handling in the 3342 * driver when set to 1. Default is 0. 3343 */ 3344 static int disable_hpd_set(void *data, u64 val) 3345 { 3346 struct amdgpu_device *adev = data; 3347 3348 adev->dm.disable_hpd_irq = (bool)val; 3349 3350 return 0; 3351 } 3352 3353 3354 /* 3355 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3356 * 0 otherwise. 3357 */ 3358 static int disable_hpd_get(void *data, u64 *val) 3359 { 3360 struct amdgpu_device *adev = data; 3361 3362 *val = adev->dm.disable_hpd_irq; 3363 3364 return 0; 3365 } 3366 3367 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3368 disable_hpd_set, "%llu\n"); 3369 3370 #if defined(CONFIG_DRM_AMD_DC_DCN) 3371 /* 3372 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3373 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3374 */ 3375 static int dp_force_sst_set(void *data, u64 val) 3376 { 3377 struct amdgpu_device *adev = data; 3378 3379 adev->dm.dc->debug.set_mst_en_for_sst = val; 3380 3381 return 0; 3382 } 3383 3384 static int dp_force_sst_get(void *data, u64 *val) 3385 { 3386 struct amdgpu_device *adev = data; 3387 3388 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3389 3390 return 0; 3391 } 3392 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3393 dp_force_sst_set, "%llu\n"); 3394 #endif 3395 3396 /* 3397 * Sets the DC visual confirm debug option from the given string. 3398 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3399 */ 3400 static int visual_confirm_set(void *data, u64 val) 3401 { 3402 struct amdgpu_device *adev = data; 3403 3404 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3405 3406 return 0; 3407 } 3408 3409 /* 3410 * Reads the DC visual confirm debug option value into the given buffer. 3411 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3412 */ 3413 static int visual_confirm_get(void *data, u64 *val) 3414 { 3415 struct amdgpu_device *adev = data; 3416 3417 *val = adev->dm.dc->debug.visual_confirm; 3418 3419 return 0; 3420 } 3421 3422 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3423 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3424 visual_confirm_set, "%llu\n"); 3425 3426 /* 3427 * Dumps the DCC_EN bit for each pipe. 3428 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3429 */ 3430 static ssize_t dcc_en_bits_read( 3431 struct file *f, 3432 char __user *buf, 3433 size_t size, 3434 loff_t *pos) 3435 { 3436 struct amdgpu_device *adev = file_inode(f)->i_private; 3437 struct dc *dc = adev->dm.dc; 3438 char *rd_buf = NULL; 3439 const uint32_t rd_buf_size = 32; 3440 uint32_t result = 0; 3441 int offset = 0; 3442 int num_pipes = dc->res_pool->pipe_count; 3443 int *dcc_en_bits; 3444 int i, r; 3445 3446 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3447 if (!dcc_en_bits) 3448 return -ENOMEM; 3449 3450 if (!dc->hwss.get_dcc_en_bits) { 3451 kfree(dcc_en_bits); 3452 return 0; 3453 } 3454 3455 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3456 3457 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3458 if (!rd_buf) 3459 return -ENOMEM; 3460 3461 for (i = 0; i < num_pipes; i++) 3462 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3463 "%d ", dcc_en_bits[i]); 3464 rd_buf[strlen(rd_buf)] = '\n'; 3465 3466 kfree(dcc_en_bits); 3467 3468 while (size) { 3469 if (*pos >= rd_buf_size) 3470 break; 3471 r = put_user(*(rd_buf + result), buf); 3472 if (r) 3473 return r; /* r = -EFAULT */ 3474 buf += 1; 3475 size -= 1; 3476 *pos += 1; 3477 result += 1; 3478 } 3479 3480 kfree(rd_buf); 3481 return result; 3482 } 3483 3484 void dtn_debugfs_init(struct amdgpu_device *adev) 3485 { 3486 static const struct file_operations dtn_log_fops = { 3487 .owner = THIS_MODULE, 3488 .read = dtn_log_read, 3489 .write = dtn_log_write, 3490 .llseek = default_llseek 3491 }; 3492 static const struct file_operations dcc_en_bits_fops = { 3493 .owner = THIS_MODULE, 3494 .read = dcc_en_bits_read, 3495 .llseek = default_llseek 3496 }; 3497 3498 struct drm_minor *minor = adev_to_drm(adev)->primary; 3499 struct dentry *root = minor->debugfs_root; 3500 3501 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3502 adev, &mst_topo_fops); 3503 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3504 &dtn_log_fops); 3505 #if defined(CONFIG_DRM_AMD_DC_DCN) 3506 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3507 &dp_set_mst_en_for_sst_ops); 3508 #endif 3509 3510 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3511 &visual_confirm_fops); 3512 3513 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3514 adev, &dmub_tracebuffer_fops); 3515 3516 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3517 adev, &dmub_fw_state_fops); 3518 3519 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3520 adev, &force_timing_sync_ops); 3521 3522 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3523 adev, &dmcub_trace_event_state_fops); 3524 3525 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3526 adev, &trigger_hpd_mst_ops); 3527 3528 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3529 &dcc_en_bits_fops); 3530 3531 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3532 &disable_hpd_ops); 3533 3534 } 3535