1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "amdgpu_dm_replay.h" 34 #include "dm_helpers.h" 35 #include "dmub/dmub_srv.h" 36 #include "resource.h" 37 #include "dsc.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 #include "link/protocols/link_dp_capability.h" 41 #include "inc/hw/dchubbub.h" 42 43 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 44 #include "amdgpu_dm_psr.h" 45 #endif 46 47 struct dmub_debugfs_trace_header { 48 uint32_t entry_count; 49 uint32_t reserved[3]; 50 }; 51 52 struct dmub_debugfs_trace_entry { 53 uint32_t trace_code; 54 uint32_t tick_count; 55 uint32_t param0; 56 uint32_t param1; 57 }; 58 59 static const char *const mst_progress_status[] = { 60 "probe", 61 "remote_edid", 62 "allocate_new_payload", 63 "clear_allocated_payload", 64 }; 65 66 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 67 * 68 * Function takes in attributes passed to debugfs write entry 69 * and writes into param array. 70 * The user passes max_param_num to identify maximum number of 71 * parameters that could be parsed. 72 * 73 */ 74 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 75 long *param, const char __user *buf, 76 int max_param_num, 77 uint8_t *param_nums) 78 { 79 char *wr_buf_ptr = NULL; 80 uint32_t wr_buf_count = 0; 81 int r; 82 char *sub_str = NULL; 83 const char delimiter[3] = {' ', '\n', '\0'}; 84 uint8_t param_index = 0; 85 86 *param_nums = 0; 87 88 wr_buf_ptr = wr_buf; 89 90 /* r is bytes not be copied */ 91 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 92 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 93 return -EFAULT; 94 } 95 96 /* check number of parameters. isspace could not differ space and \n */ 97 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 98 /* skip space*/ 99 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 100 wr_buf_ptr++; 101 wr_buf_count++; 102 } 103 104 if (wr_buf_count == wr_buf_size) 105 break; 106 107 /* skip non-space*/ 108 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 109 wr_buf_ptr++; 110 wr_buf_count++; 111 } 112 113 (*param_nums)++; 114 115 if (wr_buf_count == wr_buf_size) 116 break; 117 } 118 119 if (*param_nums > max_param_num) 120 *param_nums = max_param_num; 121 122 wr_buf_ptr = wr_buf; /* reset buf pointer */ 123 wr_buf_count = 0; /* number of char already checked */ 124 125 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 126 wr_buf_ptr++; 127 wr_buf_count++; 128 } 129 130 while (param_index < *param_nums) { 131 /* after strsep, wr_buf_ptr will be moved to after space */ 132 sub_str = strsep(&wr_buf_ptr, delimiter); 133 134 r = kstrtol(sub_str, 16, &(param[param_index])); 135 136 if (r) 137 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 138 139 param_index++; 140 } 141 142 return 0; 143 } 144 145 /* function description 146 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 147 * 148 * valid lane count value: 1, 2, 4 149 * valid link rate value: 150 * 06h = 1.62Gbps per lane 151 * 0Ah = 2.7Gbps per lane 152 * 0Ch = 3.24Gbps per lane 153 * 14h = 5.4Gbps per lane 154 * 1Eh = 8.1Gbps per lane 155 * 156 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 157 * 158 * --- to get dp configuration 159 * 160 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * It will list current, verified, reported, preferred dp configuration. 163 * current -- for current video mode 164 * verified --- maximum configuration which pass link training 165 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 166 * preferred --- user force settings 167 * 168 * --- set (or force) dp configuration 169 * 170 * echo <lane_count> <link_rate> > link_settings 171 * 172 * for example, to force to 2 lane, 2.7GHz, 173 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 174 * 175 * spread_spectrum could not be changed dynamically. 176 * 177 * in case invalid lane count, link rate are force, no hw programming will be 178 * done. please check link settings after force operation to see if HW get 179 * programming. 180 * 181 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 182 * 183 * check current and preferred settings. 184 * 185 */ 186 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 187 size_t size, loff_t *pos) 188 { 189 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 190 struct dc_link *link = connector->dc_link; 191 char *rd_buf = NULL; 192 char *rd_buf_ptr = NULL; 193 const uint32_t rd_buf_size = 100; 194 uint32_t result = 0; 195 uint8_t str_len = 0; 196 int r; 197 198 if (*pos & 3 || size & 3) 199 return -EINVAL; 200 201 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 202 if (!rd_buf) 203 return 0; 204 205 rd_buf_ptr = rd_buf; 206 207 str_len = strlen("Current: %d 0x%x %d "); 208 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 209 link->cur_link_settings.lane_count, 210 link->cur_link_settings.link_rate, 211 link->cur_link_settings.link_spread); 212 rd_buf_ptr += str_len; 213 214 str_len = strlen("Verified: %d 0x%x %d "); 215 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 216 link->verified_link_cap.lane_count, 217 link->verified_link_cap.link_rate, 218 link->verified_link_cap.link_spread); 219 rd_buf_ptr += str_len; 220 221 str_len = strlen("Reported: %d 0x%x %d "); 222 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 223 link->reported_link_cap.lane_count, 224 link->reported_link_cap.link_rate, 225 link->reported_link_cap.link_spread); 226 rd_buf_ptr += str_len; 227 228 str_len = strlen("Preferred: %d 0x%x %d "); 229 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 230 link->preferred_link_setting.lane_count, 231 link->preferred_link_setting.link_rate, 232 link->preferred_link_setting.link_spread); 233 234 while (size) { 235 if (*pos >= rd_buf_size) 236 break; 237 238 r = put_user(*(rd_buf + result), buf); 239 if (r) { 240 kfree(rd_buf); 241 return r; /* r = -EFAULT */ 242 } 243 244 buf += 1; 245 size -= 1; 246 *pos += 1; 247 result += 1; 248 } 249 250 kfree(rd_buf); 251 return result; 252 } 253 254 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 255 size_t size, loff_t *pos) 256 { 257 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 258 struct dc_link *link = connector->dc_link; 259 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 260 struct dc *dc = (struct dc *)link->dc; 261 struct dc_link_settings prefer_link_settings = {0}; 262 char *wr_buf = NULL; 263 const uint32_t wr_buf_size = 40; 264 /* 0: lane_count; 1: link_rate */ 265 int max_param_num = 2; 266 uint8_t param_nums = 0; 267 long param[2]; 268 bool valid_input = true; 269 270 if (size == 0) 271 return -EINVAL; 272 273 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 274 if (!wr_buf) 275 return -ENOSPC; 276 277 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 278 (long *)param, buf, 279 max_param_num, 280 ¶m_nums)) { 281 kfree(wr_buf); 282 return -EINVAL; 283 } 284 285 if (param_nums <= 0) { 286 kfree(wr_buf); 287 DRM_DEBUG_DRIVER("user data not be read\n"); 288 return -EINVAL; 289 } 290 291 switch (param[0]) { 292 case LANE_COUNT_ONE: 293 case LANE_COUNT_TWO: 294 case LANE_COUNT_FOUR: 295 break; 296 default: 297 valid_input = false; 298 break; 299 } 300 301 switch (param[1]) { 302 case LINK_RATE_LOW: 303 case LINK_RATE_HIGH: 304 case LINK_RATE_RBR2: 305 case LINK_RATE_HIGH2: 306 case LINK_RATE_HIGH3: 307 case LINK_RATE_UHBR10: 308 case LINK_RATE_UHBR13_5: 309 case LINK_RATE_UHBR20: 310 break; 311 default: 312 valid_input = false; 313 break; 314 } 315 316 if (!valid_input) { 317 kfree(wr_buf); 318 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 319 mutex_lock(&adev->dm.dc_lock); 320 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 321 mutex_unlock(&adev->dm.dc_lock); 322 return size; 323 } 324 325 /* save user force lane_count, link_rate to preferred settings 326 * spread spectrum will not be changed 327 */ 328 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 329 prefer_link_settings.use_link_rate_set = false; 330 prefer_link_settings.lane_count = param[0]; 331 prefer_link_settings.link_rate = param[1]; 332 333 mutex_lock(&adev->dm.dc_lock); 334 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 335 mutex_unlock(&adev->dm.dc_lock); 336 337 kfree(wr_buf); 338 return size; 339 } 340 341 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) 342 { 343 bool is_end_device = false; 344 struct drm_dp_mst_topology_mgr *mgr = NULL; 345 struct drm_dp_mst_port *port = NULL; 346 347 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) { 348 mgr = &aconnector->mst_root->mst_mgr; 349 port = aconnector->mst_output_port; 350 351 drm_modeset_lock(&mgr->base.lock, NULL); 352 if (port->pdt == DP_PEER_DEVICE_SST_SINK || 353 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) 354 is_end_device = true; 355 drm_modeset_unlock(&mgr->base.lock); 356 } 357 358 return is_end_device; 359 } 360 361 /* Change MST link setting 362 * 363 * valid lane count value: 1, 2, 4 364 * valid link rate value: 365 * 06h = 1.62Gbps per lane 366 * 0Ah = 2.7Gbps per lane 367 * 0Ch = 3.24Gbps per lane 368 * 14h = 5.4Gbps per lane 369 * 1Eh = 8.1Gbps per lane 370 * 3E8h = 10.0Gbps per lane 371 * 546h = 13.5Gbps per lane 372 * 7D0h = 20.0Gbps per lane 373 * 374 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings 375 * 376 * for example, to force to 2 lane, 10.0GHz, 377 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings 378 * 379 * Valid input will trigger hotplug event to get new link setting applied 380 * Invalid input will trigger training setting reset 381 * 382 * The usage can be referred to link_settings entry 383 * 384 */ 385 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, 386 size_t size, loff_t *pos) 387 { 388 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 389 struct dc_link *link = aconnector->dc_link; 390 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 391 struct dc *dc = (struct dc *)link->dc; 392 struct dc_link_settings prefer_link_settings = {0}; 393 char *wr_buf = NULL; 394 const uint32_t wr_buf_size = 40; 395 /* 0: lane_count; 1: link_rate */ 396 int max_param_num = 2; 397 uint8_t param_nums = 0; 398 long param[2]; 399 bool valid_input = true; 400 401 if (!dp_mst_is_end_device(aconnector)) 402 return -EINVAL; 403 404 if (size == 0) 405 return -EINVAL; 406 407 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 408 if (!wr_buf) 409 return -ENOSPC; 410 411 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 412 (long *)param, buf, 413 max_param_num, 414 ¶m_nums)) { 415 kfree(wr_buf); 416 return -EINVAL; 417 } 418 419 if (param_nums <= 0) { 420 kfree(wr_buf); 421 DRM_DEBUG_DRIVER("user data not be read\n"); 422 return -EINVAL; 423 } 424 425 switch (param[0]) { 426 case LANE_COUNT_ONE: 427 case LANE_COUNT_TWO: 428 case LANE_COUNT_FOUR: 429 break; 430 default: 431 valid_input = false; 432 break; 433 } 434 435 switch (param[1]) { 436 case LINK_RATE_LOW: 437 case LINK_RATE_HIGH: 438 case LINK_RATE_RBR2: 439 case LINK_RATE_HIGH2: 440 case LINK_RATE_HIGH3: 441 case LINK_RATE_UHBR10: 442 case LINK_RATE_UHBR13_5: 443 case LINK_RATE_UHBR20: 444 break; 445 default: 446 valid_input = false; 447 break; 448 } 449 450 if (!valid_input) { 451 kfree(wr_buf); 452 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 453 mutex_lock(&adev->dm.dc_lock); 454 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 455 mutex_unlock(&adev->dm.dc_lock); 456 return -EINVAL; 457 } 458 459 /* save user force lane_count, link_rate to preferred settings 460 * spread spectrum will not be changed 461 */ 462 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 463 prefer_link_settings.use_link_rate_set = false; 464 prefer_link_settings.lane_count = param[0]; 465 prefer_link_settings.link_rate = param[1]; 466 467 /* skip immediate retrain, and train to new link setting after hotplug event triggered */ 468 mutex_lock(&adev->dm.dc_lock); 469 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 470 mutex_unlock(&adev->dm.dc_lock); 471 472 mutex_lock(&aconnector->base.dev->mode_config.mutex); 473 aconnector->base.force = DRM_FORCE_OFF; 474 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 475 drm_kms_helper_hotplug_event(aconnector->base.dev); 476 477 msleep(100); 478 479 mutex_lock(&aconnector->base.dev->mode_config.mutex); 480 aconnector->base.force = DRM_FORCE_UNSPECIFIED; 481 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 482 drm_kms_helper_hotplug_event(aconnector->base.dev); 483 484 kfree(wr_buf); 485 return size; 486 } 487 488 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 489 * post-cursor2 (defined by VESA DP specification) 490 * 491 * valid values 492 * voltage swing: 0,1,2,3 493 * pre-emphasis : 0,1,2,3 494 * post cursor2 : 0,1,2,3 495 * 496 * 497 * how to use this debugfs 498 * 499 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 500 * 501 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 502 * 503 * To figure out which DP-x is the display for DP to be check, 504 * cd DP-x 505 * ls -ll 506 * There should be debugfs file, like link_settings, phy_settings. 507 * cat link_settings 508 * from lane_count, link_rate to figure which DP-x is for display to be worked 509 * on 510 * 511 * To get current DP PHY settings, 512 * cat phy_settings 513 * 514 * To change DP PHY settings, 515 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 516 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 517 * 0, 518 * echo 2 3 0 > phy_settings 519 * 520 * To check if change be applied, get current phy settings by 521 * cat phy_settings 522 * 523 * In case invalid values are set by user, like 524 * echo 1 4 0 > phy_settings 525 * 526 * HW will NOT be programmed by these settings. 527 * cat phy_settings will show the previous valid settings. 528 */ 529 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 530 size_t size, loff_t *pos) 531 { 532 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 533 struct dc_link *link = connector->dc_link; 534 char *rd_buf = NULL; 535 const uint32_t rd_buf_size = 20; 536 uint32_t result = 0; 537 int r; 538 539 if (*pos & 3 || size & 3) 540 return -EINVAL; 541 542 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 543 if (!rd_buf) 544 return -EINVAL; 545 546 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 547 link->cur_lane_setting[0].VOLTAGE_SWING, 548 link->cur_lane_setting[0].PRE_EMPHASIS, 549 link->cur_lane_setting[0].POST_CURSOR2); 550 551 while (size) { 552 if (*pos >= rd_buf_size) 553 break; 554 555 r = put_user((*(rd_buf + result)), buf); 556 if (r) { 557 kfree(rd_buf); 558 return r; /* r = -EFAULT */ 559 } 560 561 buf += 1; 562 size -= 1; 563 *pos += 1; 564 result += 1; 565 } 566 567 kfree(rd_buf); 568 return result; 569 } 570 571 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 572 { 573 struct drm_connector *connector = m->private; 574 struct amdgpu_dm_connector *aconnector = 575 to_amdgpu_dm_connector(connector); 576 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 577 578 if (connector->status != connector_status_connected) 579 return -ENODEV; 580 581 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 582 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 583 caps.phy_repeater_cnt); 584 585 seq_puts(m, "phy repeater mode: "); 586 587 switch (caps.mode) { 588 case DP_PHY_REPEATER_MODE_TRANSPARENT: 589 seq_puts(m, "transparent"); 590 break; 591 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 592 seq_puts(m, "non-transparent"); 593 break; 594 case 0x00: 595 seq_puts(m, "non lttpr"); 596 break; 597 default: 598 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 599 break; 600 } 601 602 seq_puts(m, "\n"); 603 return 0; 604 } 605 606 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 607 size_t size, loff_t *pos) 608 { 609 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 610 struct dc_link *link = connector->dc_link; 611 struct dc *dc = (struct dc *)link->dc; 612 char *wr_buf = NULL; 613 uint32_t wr_buf_size = 40; 614 long param[3]; 615 bool use_prefer_link_setting; 616 struct link_training_settings link_lane_settings = {0}; 617 int max_param_num = 3; 618 uint8_t param_nums = 0; 619 int r = 0; 620 621 622 if (size == 0) 623 return -EINVAL; 624 625 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 626 if (!wr_buf) 627 return -ENOSPC; 628 629 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 630 (long *)param, buf, 631 max_param_num, 632 ¶m_nums)) { 633 kfree(wr_buf); 634 return -EINVAL; 635 } 636 637 if (param_nums <= 0) { 638 kfree(wr_buf); 639 DRM_DEBUG_DRIVER("user data not be read\n"); 640 return -EINVAL; 641 } 642 643 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 644 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 645 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 646 kfree(wr_buf); 647 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 648 return size; 649 } 650 651 /* get link settings: lane count, link rate */ 652 use_prefer_link_setting = 653 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 654 (link->test_pattern_enabled)); 655 656 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 657 658 if (use_prefer_link_setting) { 659 link_lane_settings.link_settings.lane_count = 660 link->preferred_link_setting.lane_count; 661 link_lane_settings.link_settings.link_rate = 662 link->preferred_link_setting.link_rate; 663 link_lane_settings.link_settings.link_spread = 664 link->preferred_link_setting.link_spread; 665 } else { 666 link_lane_settings.link_settings.lane_count = 667 link->cur_link_settings.lane_count; 668 link_lane_settings.link_settings.link_rate = 669 link->cur_link_settings.link_rate; 670 link_lane_settings.link_settings.link_spread = 671 link->cur_link_settings.link_spread; 672 } 673 674 /* apply phy settings from user */ 675 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 676 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 677 (enum dc_voltage_swing) (param[0]); 678 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 679 (enum dc_pre_emphasis) (param[1]); 680 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 681 (enum dc_post_cursor2) (param[2]); 682 } 683 684 /* program ASIC registers and DPCD registers */ 685 dc_link_set_drive_settings(dc, &link_lane_settings, link); 686 687 kfree(wr_buf); 688 return size; 689 } 690 691 /* function description 692 * 693 * set PHY layer or Link layer test pattern 694 * PHY test pattern is used for PHY SI check. 695 * Link layer test will not affect PHY SI. 696 * 697 * Reset Test Pattern: 698 * 0 = DP_TEST_PATTERN_VIDEO_MODE 699 * 700 * PHY test pattern supported: 701 * 1 = DP_TEST_PATTERN_D102 702 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 703 * 3 = DP_TEST_PATTERN_PRBS7 704 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 705 * 5 = DP_TEST_PATTERN_CP2520_1 706 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 707 * 7 = DP_TEST_PATTERN_CP2520_3 708 * 709 * DP PHY Link Training Patterns 710 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 711 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 712 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 713 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 714 * 715 * DP Link Layer Test pattern 716 * c = DP_TEST_PATTERN_COLOR_SQUARES 717 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 718 * e = DP_TEST_PATTERN_VERTICAL_BARS 719 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 720 * 10= DP_TEST_PATTERN_COLOR_RAMP 721 * 722 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 723 * 724 * --- set test pattern 725 * echo <test pattern #> > test_pattern 726 * 727 * If test pattern # is not supported, NO HW programming will be done. 728 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 729 * for the user pattern. input 10 bytes data are separated by space 730 * 731 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 732 * 733 * --- reset test pattern 734 * echo 0 > test_pattern 735 * 736 * --- HPD detection is disabled when set PHY test pattern 737 * 738 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 739 * is disable. User could unplug DP display from DP connected and plug scope to 740 * check test pattern PHY SI. 741 * If there is need unplug scope and plug DP display back, do steps below: 742 * echo 0 > phy_test_pattern 743 * unplug scope 744 * plug DP display. 745 * 746 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 747 * driver could detect "unplug scope" and "plug DP display" 748 */ 749 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 750 size_t size, loff_t *pos) 751 { 752 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 753 struct dc_link *link = connector->dc_link; 754 char *wr_buf = NULL; 755 uint32_t wr_buf_size = 100; 756 long param[11] = {0x0}; 757 int max_param_num = 11; 758 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 759 bool disable_hpd = false; 760 bool valid_test_pattern = false; 761 uint8_t param_nums = 0; 762 /* init with default 80bit custom pattern */ 763 uint8_t custom_pattern[10] = { 764 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 765 0x1f, 0x7c, 0xf0, 0xc1, 0x07 766 }; 767 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 768 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 769 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 770 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 771 struct link_training_settings link_training_settings = {0}; 772 int i; 773 774 if (size == 0) 775 return -EINVAL; 776 777 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 778 if (!wr_buf) 779 return -ENOSPC; 780 781 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 782 (long *)param, buf, 783 max_param_num, 784 ¶m_nums)) { 785 kfree(wr_buf); 786 return -EINVAL; 787 } 788 789 if (param_nums <= 0) { 790 kfree(wr_buf); 791 DRM_DEBUG_DRIVER("user data not be read\n"); 792 return -EINVAL; 793 } 794 795 796 test_pattern = param[0]; 797 798 switch (test_pattern) { 799 case DP_TEST_PATTERN_VIDEO_MODE: 800 case DP_TEST_PATTERN_COLOR_SQUARES: 801 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 802 case DP_TEST_PATTERN_VERTICAL_BARS: 803 case DP_TEST_PATTERN_HORIZONTAL_BARS: 804 case DP_TEST_PATTERN_COLOR_RAMP: 805 valid_test_pattern = true; 806 break; 807 808 case DP_TEST_PATTERN_D102: 809 case DP_TEST_PATTERN_SYMBOL_ERROR: 810 case DP_TEST_PATTERN_PRBS7: 811 case DP_TEST_PATTERN_80BIT_CUSTOM: 812 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 813 case DP_TEST_PATTERN_TRAINING_PATTERN4: 814 disable_hpd = true; 815 valid_test_pattern = true; 816 break; 817 818 default: 819 valid_test_pattern = false; 820 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 821 break; 822 } 823 824 if (!valid_test_pattern) { 825 kfree(wr_buf); 826 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 827 return size; 828 } 829 830 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 831 for (i = 0; i < 10; i++) { 832 if ((uint8_t) param[i + 1] != 0x0) 833 break; 834 } 835 836 if (i < 10) { 837 /* not use default value */ 838 for (i = 0; i < 10; i++) 839 custom_pattern[i] = (uint8_t) param[i + 1]; 840 } 841 } 842 843 /* Usage: set DP physical test pattern using debugfs with normal DP 844 * panel. Then plug out DP panel and connect a scope to measure 845 * For normal video mode and test pattern generated from CRCT, 846 * they are visibile to user. So do not disable HPD. 847 * Video Mode is also set to clear the test pattern, so enable HPD 848 * because it might have been disabled after a test pattern was set. 849 * AUX depends on HPD * sequence dependent, do not move! 850 */ 851 if (!disable_hpd) 852 dc_link_enable_hpd(link); 853 854 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 855 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 856 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 857 858 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 859 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 860 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 861 862 link_training_settings.link_settings = cur_link_settings; 863 864 865 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 866 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 867 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 868 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 869 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 870 link_training_settings.link_settings = prefer_link_settings; 871 } 872 873 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 874 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 875 876 dc_link_dp_set_test_pattern( 877 link, 878 test_pattern, 879 DP_TEST_PATTERN_COLOR_SPACE_RGB, 880 &link_training_settings, 881 custom_pattern, 882 10); 883 884 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 885 * Then plug out DP panel and connect a scope to measure DP PHY signal. 886 * Need disable interrupt to avoid SW driver disable DP output. This is 887 * done after the test pattern is set. 888 */ 889 if (valid_test_pattern && disable_hpd) 890 dc_link_disable_hpd(link); 891 892 kfree(wr_buf); 893 894 return size; 895 } 896 897 /* 898 * Returns the DMCUB tracebuffer contents. 899 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 900 */ 901 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 902 { 903 struct amdgpu_device *adev = m->private; 904 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 905 struct dmub_fw_meta_info *fw_meta_info = NULL; 906 struct dmub_debugfs_trace_entry *entries; 907 uint8_t *tbuf_base; 908 uint32_t tbuf_size, max_entries, num_entries, first_entry, i; 909 910 if (!fb_info) 911 return 0; 912 913 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 914 if (!tbuf_base) 915 return 0; 916 917 if (adev->dm.dmub_srv) 918 fw_meta_info = &adev->dm.dmub_srv->meta_info; 919 920 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size : 921 DMUB_TRACE_BUFFER_SIZE; 922 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 923 sizeof(struct dmub_debugfs_trace_entry); 924 925 num_entries = 926 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 927 928 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that 929 * entries are being overwritten. 930 */ 931 if (num_entries > max_entries) 932 seq_printf(m, "...\n"); 933 934 first_entry = num_entries % max_entries; 935 num_entries = min(num_entries, max_entries); 936 937 entries = (struct dmub_debugfs_trace_entry 938 *)(tbuf_base + 939 sizeof(struct dmub_debugfs_trace_header)); 940 941 /* To print entries chronologically, start from the first entry till the 942 * top of buffer, then from base of buffer to first entry. 943 */ 944 for (i = first_entry; i < num_entries; ++i) { 945 struct dmub_debugfs_trace_entry *entry = &entries[i]; 946 947 seq_printf(m, 948 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 949 entry->trace_code, entry->tick_count, entry->param0, 950 entry->param1); 951 } 952 for (i = 0; i < first_entry; ++i) { 953 struct dmub_debugfs_trace_entry *entry = &entries[i]; 954 955 seq_printf(m, 956 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 957 entry->trace_code, entry->tick_count, entry->param0, 958 entry->param1); 959 } 960 961 return 0; 962 } 963 964 /* 965 * Returns the DMCUB firmware state contents. 966 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 967 */ 968 static int dmub_fw_state_show(struct seq_file *m, void *data) 969 { 970 struct amdgpu_device *adev = m->private; 971 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 972 uint8_t *state_base; 973 uint32_t state_size; 974 975 if (!fb_info) 976 return 0; 977 978 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 979 if (!state_base) 980 return 0; 981 982 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 983 984 return seq_write(m, state_base, state_size); 985 } 986 987 /* replay_capability_show() - show eDP panel replay capability 988 * 989 * The read function: replay_capability_show 990 * Shows if sink and driver has Replay capability or not. 991 * 992 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability 993 * 994 * Expected output: 995 * "Sink support: no\n" - if panel doesn't support Replay 996 * "Sink support: yes\n" - if panel supports Replay 997 * "Driver support: no\n" - if driver doesn't support Replay 998 * "Driver support: yes\n" - if driver supports Replay 999 */ 1000 static int replay_capability_show(struct seq_file *m, void *data) 1001 { 1002 struct drm_connector *connector = m->private; 1003 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1004 struct dc_link *link = aconnector->dc_link; 1005 bool sink_support_replay = false; 1006 bool driver_support_replay = false; 1007 1008 if (!link) 1009 return -ENODEV; 1010 1011 if (link->type == dc_connection_none) 1012 return -ENODEV; 1013 1014 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1015 return -ENODEV; 1016 1017 /* If Replay is already set to support, skip the checks */ 1018 if (link->replay_settings.config.replay_supported) { 1019 sink_support_replay = true; 1020 driver_support_replay = true; 1021 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 1022 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1023 } else { 1024 struct dc *dc = link->ctx->dc; 1025 1026 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1027 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub) 1028 driver_support_replay = 1029 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported; 1030 } 1031 1032 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay)); 1033 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay)); 1034 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported)); 1035 1036 return 0; 1037 } 1038 1039 /* psr_capability_show() - show eDP panel PSR capability 1040 * 1041 * The read function: sink_psr_capability_show 1042 * Shows if sink has PSR capability or not. 1043 * If yes - the PSR version is appended 1044 * 1045 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 1046 * 1047 * Expected output: 1048 * "Sink support: no\n" - if panel doesn't support PSR 1049 * "Sink support: yes [0x01]\n" - if panel supports PSR1 1050 * "Driver support: no\n" - if driver doesn't support PSR 1051 * "Driver support: yes [0x01]\n" - if driver supports PSR1 1052 */ 1053 static int psr_capability_show(struct seq_file *m, void *data) 1054 { 1055 struct drm_connector *connector = m->private; 1056 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1057 struct dc_link *link = aconnector->dc_link; 1058 1059 if (!link) 1060 return -ENODEV; 1061 1062 if (link->type == dc_connection_none) 1063 return -ENODEV; 1064 1065 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1066 return -ENODEV; 1067 1068 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 1069 if (link->dpcd_caps.psr_info.psr_version) 1070 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 1071 seq_puts(m, "\n"); 1072 1073 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 1074 if (link->psr_settings.psr_version) 1075 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 1076 seq_puts(m, "\n"); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * Returns the current bpc for the crtc. 1083 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 1084 */ 1085 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 1086 { 1087 struct drm_crtc *crtc = m->private; 1088 struct drm_device *dev = crtc->dev; 1089 struct dm_crtc_state *dm_crtc_state = NULL; 1090 int res = -ENODEV; 1091 unsigned int bpc; 1092 1093 mutex_lock(&dev->mode_config.mutex); 1094 drm_modeset_lock(&crtc->mutex, NULL); 1095 if (crtc->state == NULL) 1096 goto unlock; 1097 1098 dm_crtc_state = to_dm_crtc_state(crtc->state); 1099 if (dm_crtc_state->stream == NULL) 1100 goto unlock; 1101 1102 switch (dm_crtc_state->stream->timing.display_color_depth) { 1103 case COLOR_DEPTH_666: 1104 bpc = 6; 1105 break; 1106 case COLOR_DEPTH_888: 1107 bpc = 8; 1108 break; 1109 case COLOR_DEPTH_101010: 1110 bpc = 10; 1111 break; 1112 case COLOR_DEPTH_121212: 1113 bpc = 12; 1114 break; 1115 case COLOR_DEPTH_161616: 1116 bpc = 16; 1117 break; 1118 default: 1119 goto unlock; 1120 } 1121 1122 seq_printf(m, "Current: %u\n", bpc); 1123 res = 0; 1124 1125 unlock: 1126 drm_modeset_unlock(&crtc->mutex); 1127 mutex_unlock(&dev->mode_config.mutex); 1128 1129 return res; 1130 } 1131 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 1132 1133 /* 1134 * Returns the current colorspace for the crtc. 1135 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 1136 */ 1137 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 1138 { 1139 struct drm_crtc *crtc = m->private; 1140 struct drm_device *dev = crtc->dev; 1141 struct dm_crtc_state *dm_crtc_state = NULL; 1142 int res = -ENODEV; 1143 1144 mutex_lock(&dev->mode_config.mutex); 1145 drm_modeset_lock(&crtc->mutex, NULL); 1146 if (crtc->state == NULL) 1147 goto unlock; 1148 1149 dm_crtc_state = to_dm_crtc_state(crtc->state); 1150 if (dm_crtc_state->stream == NULL) 1151 goto unlock; 1152 1153 switch (dm_crtc_state->stream->output_color_space) { 1154 case COLOR_SPACE_SRGB: 1155 seq_puts(m, "sRGB"); 1156 break; 1157 case COLOR_SPACE_YCBCR601: 1158 case COLOR_SPACE_YCBCR601_LIMITED: 1159 seq_puts(m, "BT601_YCC"); 1160 break; 1161 case COLOR_SPACE_YCBCR709: 1162 case COLOR_SPACE_YCBCR709_LIMITED: 1163 seq_puts(m, "BT709_YCC"); 1164 break; 1165 case COLOR_SPACE_ADOBERGB: 1166 seq_puts(m, "opRGB"); 1167 break; 1168 case COLOR_SPACE_2020_RGB_FULLRANGE: 1169 seq_puts(m, "BT2020_RGB"); 1170 break; 1171 case COLOR_SPACE_2020_YCBCR: 1172 seq_puts(m, "BT2020_YCC"); 1173 break; 1174 default: 1175 goto unlock; 1176 } 1177 res = 0; 1178 1179 unlock: 1180 drm_modeset_unlock(&crtc->mutex); 1181 mutex_unlock(&dev->mode_config.mutex); 1182 1183 return res; 1184 } 1185 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 1186 1187 1188 /* 1189 * Example usage: 1190 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 1191 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1192 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 1193 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1194 */ 1195 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 1196 size_t size, loff_t *pos) 1197 { 1198 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1199 char *wr_buf = NULL; 1200 uint32_t wr_buf_size = 42; 1201 int max_param_num = 1; 1202 long param; 1203 uint8_t param_nums = 0; 1204 1205 if (size == 0) 1206 return -EINVAL; 1207 1208 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1209 1210 if (!wr_buf) { 1211 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1212 return -ENOSPC; 1213 } 1214 1215 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1216 ¶m, buf, 1217 max_param_num, 1218 ¶m_nums)) { 1219 kfree(wr_buf); 1220 return -EINVAL; 1221 } 1222 1223 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1224 1225 kfree(wr_buf); 1226 return 0; 1227 } 1228 1229 /* 1230 * Returns the HDCP capability of the Display (1.4 for now). 1231 * 1232 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1233 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1234 * 1235 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1236 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1237 */ 1238 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1239 { 1240 struct drm_connector *connector = m->private; 1241 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1242 bool hdcp_cap, hdcp2_cap; 1243 1244 if (connector->status != connector_status_connected) 1245 return -ENODEV; 1246 1247 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1248 1249 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1250 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1251 1252 1253 if (hdcp_cap) 1254 seq_printf(m, "%s ", "HDCP1.4"); 1255 if (hdcp2_cap) 1256 seq_printf(m, "%s ", "HDCP2.2"); 1257 1258 if (!hdcp_cap && !hdcp2_cap) 1259 seq_printf(m, "%s ", "None"); 1260 1261 seq_puts(m, "\n"); 1262 1263 return 0; 1264 } 1265 1266 /* 1267 * Returns whether the connected display is internal and not hotpluggable. 1268 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1269 */ 1270 static int internal_display_show(struct seq_file *m, void *data) 1271 { 1272 struct drm_connector *connector = m->private; 1273 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1274 struct dc_link *link = aconnector->dc_link; 1275 1276 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1277 1278 return 0; 1279 } 1280 1281 /* 1282 * Returns the number of segments used if ODM Combine mode is enabled. 1283 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments 1284 */ 1285 static int odm_combine_segments_show(struct seq_file *m, void *unused) 1286 { 1287 struct drm_connector *connector = m->private; 1288 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1289 struct dc_link *link = aconnector->dc_link; 1290 struct pipe_ctx *pipe_ctx = NULL; 1291 int i, segments = -EOPNOTSUPP; 1292 1293 for (i = 0; i < MAX_PIPES; i++) { 1294 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 1295 if (pipe_ctx->stream && 1296 pipe_ctx->stream->link == link) 1297 break; 1298 } 1299 1300 if (connector->status != connector_status_connected) 1301 return -ENODEV; 1302 1303 if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1304 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1305 1306 seq_printf(m, "%d\n", segments); 1307 return 0; 1308 } 1309 1310 /* function description 1311 * 1312 * generic SDP message access for testing 1313 * 1314 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1315 * 1316 * SDP header 1317 * Hb0 : Secondary-Data Packet ID 1318 * Hb1 : Secondary-Data Packet type 1319 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1320 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1321 * 1322 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1323 */ 1324 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1325 size_t size, loff_t *pos) 1326 { 1327 int r; 1328 uint8_t data[36] = {0}; 1329 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1330 struct dm_crtc_state *acrtc_state; 1331 uint32_t write_size = 36; 1332 1333 if (connector->base.status != connector_status_connected) 1334 return -ENODEV; 1335 1336 if (size == 0) 1337 return 0; 1338 1339 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1340 1341 r = copy_from_user(data, buf, write_size); 1342 1343 write_size -= r; 1344 1345 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1346 1347 return write_size; 1348 } 1349 1350 /* function: Read link's DSC & FEC capabilities 1351 * 1352 * 1353 * Access it with the following command (you need to specify 1354 * connector like DP-1): 1355 * 1356 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1357 * 1358 */ 1359 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1360 { 1361 struct drm_connector *connector = m->private; 1362 struct drm_modeset_acquire_ctx ctx; 1363 struct drm_device *dev = connector->dev; 1364 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1365 int ret = 0; 1366 bool try_again = false; 1367 bool is_fec_supported = false; 1368 bool is_dsc_supported = false; 1369 struct dpcd_caps dpcd_caps; 1370 1371 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1372 do { 1373 try_again = false; 1374 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1375 if (ret) { 1376 if (ret == -EDEADLK) { 1377 ret = drm_modeset_backoff(&ctx); 1378 if (!ret) { 1379 try_again = true; 1380 continue; 1381 } 1382 } 1383 break; 1384 } 1385 if (connector->status != connector_status_connected) { 1386 ret = -ENODEV; 1387 break; 1388 } 1389 dpcd_caps = aconnector->dc_link->dpcd_caps; 1390 if (aconnector->mst_output_port) { 1391 /* aconnector sets dsc_aux during get_modes call 1392 * if MST connector has it means it can either 1393 * enable DSC on the sink device or on MST branch 1394 * its connected to. 1395 */ 1396 if (aconnector->dsc_aux) { 1397 is_fec_supported = true; 1398 is_dsc_supported = true; 1399 } 1400 } else { 1401 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1402 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1403 } 1404 } while (try_again); 1405 1406 drm_modeset_drop_locks(&ctx); 1407 drm_modeset_acquire_fini(&ctx); 1408 1409 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1410 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1411 1412 return ret; 1413 } 1414 1415 /* function: Trigger virtual HPD redetection on connector 1416 * 1417 * This function will perform link rediscovery, link disable 1418 * and enable, and dm connector state update. 1419 * 1420 * Retrigger HPD on an existing connector by echoing 1 into 1421 * its respectful "trigger_hotplug" debugfs entry: 1422 * 1423 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1424 * 1425 * This function can perform HPD unplug: 1426 * 1427 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1428 * 1429 */ 1430 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1431 size_t size, loff_t *pos) 1432 { 1433 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1434 struct drm_connector *connector = &aconnector->base; 1435 struct dc_link *link = NULL; 1436 struct drm_device *dev = connector->dev; 1437 struct amdgpu_device *adev = drm_to_adev(dev); 1438 enum dc_connection_type new_connection_type = dc_connection_none; 1439 char *wr_buf = NULL; 1440 uint32_t wr_buf_size = 42; 1441 int max_param_num = 1; 1442 long param[1] = {0}; 1443 uint8_t param_nums = 0; 1444 bool ret = false; 1445 1446 if (!aconnector->dc_link) 1447 return -EINVAL; 1448 1449 if (size == 0) 1450 return -EINVAL; 1451 1452 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1453 1454 if (!wr_buf) { 1455 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1456 return -ENOSPC; 1457 } 1458 1459 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1460 (long *)param, buf, 1461 max_param_num, 1462 ¶m_nums)) { 1463 kfree(wr_buf); 1464 return -EINVAL; 1465 } 1466 1467 kfree(wr_buf); 1468 1469 if (param_nums <= 0) { 1470 DRM_DEBUG_DRIVER("user data not be read\n"); 1471 return -EINVAL; 1472 } 1473 1474 mutex_lock(&aconnector->hpd_lock); 1475 1476 /* Don't support for mst end device*/ 1477 if (aconnector->mst_root) { 1478 mutex_unlock(&aconnector->hpd_lock); 1479 return -EINVAL; 1480 } 1481 1482 if (param[0] == 1) { 1483 1484 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1485 new_connection_type != dc_connection_none) 1486 goto unlock; 1487 1488 mutex_lock(&adev->dm.dc_lock); 1489 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1490 mutex_unlock(&adev->dm.dc_lock); 1491 1492 if (!ret) 1493 goto unlock; 1494 1495 amdgpu_dm_update_connector_after_detect(aconnector); 1496 1497 drm_modeset_lock_all(dev); 1498 dm_restore_drm_connector_state(dev, connector); 1499 drm_modeset_unlock_all(dev); 1500 1501 drm_kms_helper_connector_hotplug_event(connector); 1502 } else if (param[0] == 0) { 1503 if (!aconnector->dc_link) 1504 goto unlock; 1505 1506 link = aconnector->dc_link; 1507 1508 if (link->local_sink) { 1509 dc_sink_release(link->local_sink); 1510 link->local_sink = NULL; 1511 } 1512 1513 link->dpcd_sink_count = 0; 1514 link->type = dc_connection_none; 1515 link->dongle_max_pix_clk = 0; 1516 1517 amdgpu_dm_update_connector_after_detect(aconnector); 1518 1519 /* If the aconnector is the root node in mst topology */ 1520 if (aconnector->mst_mgr.mst_state == true) 1521 dc_link_reset_cur_dp_mst_topology(link); 1522 1523 drm_modeset_lock_all(dev); 1524 dm_restore_drm_connector_state(dev, connector); 1525 drm_modeset_unlock_all(dev); 1526 1527 drm_kms_helper_connector_hotplug_event(connector); 1528 } 1529 1530 unlock: 1531 mutex_unlock(&aconnector->hpd_lock); 1532 1533 return size; 1534 } 1535 1536 /* function: read DSC status on the connector 1537 * 1538 * The read function: dp_dsc_clock_en_read 1539 * returns current status of DSC clock on the connector. 1540 * The return is a boolean flag: 1 or 0. 1541 * 1542 * Access it with the following command (you need to specify 1543 * connector like DP-1): 1544 * 1545 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1546 * 1547 * Expected output: 1548 * 1 - means that DSC is currently enabled 1549 * 0 - means that DSC is disabled 1550 */ 1551 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1552 size_t size, loff_t *pos) 1553 { 1554 char *rd_buf = NULL; 1555 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1556 struct display_stream_compressor *dsc; 1557 struct dcn_dsc_state dsc_state = {0}; 1558 const uint32_t rd_buf_size = 10; 1559 struct pipe_ctx *pipe_ctx; 1560 ssize_t result = 0; 1561 int i, r, str_len = 10; 1562 1563 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1564 1565 if (!rd_buf) 1566 return -ENOMEM; 1567 1568 for (i = 0; i < MAX_PIPES; i++) { 1569 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1570 if (pipe_ctx->stream && 1571 pipe_ctx->stream->link == aconnector->dc_link && 1572 pipe_ctx->stream->sink && 1573 pipe_ctx->stream->sink == aconnector->dc_sink) 1574 break; 1575 } 1576 1577 dsc = pipe_ctx->stream_res.dsc; 1578 if (dsc) 1579 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1580 1581 snprintf(rd_buf, str_len, 1582 "%d\n", 1583 dsc_state.dsc_clock_en); 1584 1585 while (size) { 1586 if (*pos >= rd_buf_size) 1587 break; 1588 1589 r = put_user(*(rd_buf + result), buf); 1590 if (r) { 1591 kfree(rd_buf); 1592 return r; /* r = -EFAULT */ 1593 } 1594 1595 buf += 1; 1596 size -= 1; 1597 *pos += 1; 1598 result += 1; 1599 } 1600 1601 kfree(rd_buf); 1602 return result; 1603 } 1604 1605 /* function: write force DSC on the connector 1606 * 1607 * The write function: dp_dsc_clock_en_write 1608 * enables to force DSC on the connector. 1609 * User can write to either force enable or force disable DSC 1610 * on the next modeset or set it to driver default 1611 * 1612 * Accepted inputs: 1613 * 0 - default DSC enablement policy 1614 * 1 - force enable DSC on the connector 1615 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1616 * 1617 * Writing DSC settings is done with the following command: 1618 * - To force enable DSC (you need to specify 1619 * connector like DP-1): 1620 * 1621 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1622 * 1623 * - To return to default state set the flag to zero and 1624 * let driver deal with DSC automatically 1625 * (you need to specify connector like DP-1): 1626 * 1627 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1628 * 1629 */ 1630 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1631 size_t size, loff_t *pos) 1632 { 1633 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1634 struct drm_connector *connector = &aconnector->base; 1635 struct drm_device *dev = connector->dev; 1636 struct drm_crtc *crtc = NULL; 1637 struct dm_crtc_state *dm_crtc_state = NULL; 1638 struct pipe_ctx *pipe_ctx; 1639 int i; 1640 char *wr_buf = NULL; 1641 uint32_t wr_buf_size = 42; 1642 int max_param_num = 1; 1643 long param[1] = {0}; 1644 uint8_t param_nums = 0; 1645 1646 if (size == 0) 1647 return -EINVAL; 1648 1649 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1650 1651 if (!wr_buf) { 1652 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1653 return -ENOSPC; 1654 } 1655 1656 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1657 (long *)param, buf, 1658 max_param_num, 1659 ¶m_nums)) { 1660 kfree(wr_buf); 1661 return -EINVAL; 1662 } 1663 1664 if (param_nums <= 0) { 1665 DRM_DEBUG_DRIVER("user data not be read\n"); 1666 kfree(wr_buf); 1667 return -EINVAL; 1668 } 1669 1670 for (i = 0; i < MAX_PIPES; i++) { 1671 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1672 if (pipe_ctx->stream && 1673 pipe_ctx->stream->link == aconnector->dc_link && 1674 pipe_ctx->stream->sink && 1675 pipe_ctx->stream->sink == aconnector->dc_sink) 1676 break; 1677 } 1678 1679 if (!pipe_ctx->stream) 1680 goto done; 1681 1682 // Get CRTC state 1683 mutex_lock(&dev->mode_config.mutex); 1684 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1685 1686 if (connector->state == NULL) 1687 goto unlock; 1688 1689 crtc = connector->state->crtc; 1690 if (crtc == NULL) 1691 goto unlock; 1692 1693 drm_modeset_lock(&crtc->mutex, NULL); 1694 if (crtc->state == NULL) 1695 goto unlock; 1696 1697 dm_crtc_state = to_dm_crtc_state(crtc->state); 1698 if (dm_crtc_state->stream == NULL) 1699 goto unlock; 1700 1701 if (param[0] == 1) 1702 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1703 else if (param[0] == 2) 1704 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1705 else 1706 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1707 1708 dm_crtc_state->dsc_force_changed = true; 1709 1710 unlock: 1711 if (crtc) 1712 drm_modeset_unlock(&crtc->mutex); 1713 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1714 mutex_unlock(&dev->mode_config.mutex); 1715 1716 done: 1717 kfree(wr_buf); 1718 return size; 1719 } 1720 1721 /* function: read DSC slice width parameter on the connector 1722 * 1723 * The read function: dp_dsc_slice_width_read 1724 * returns dsc slice width used in the current configuration 1725 * The return is an integer: 0 or other positive number 1726 * 1727 * Access the status with the following command: 1728 * 1729 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1730 * 1731 * 0 - means that DSC is disabled 1732 * 1733 * Any other number more than zero represents the 1734 * slice width currently used by DSC in pixels 1735 * 1736 */ 1737 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1738 size_t size, loff_t *pos) 1739 { 1740 char *rd_buf = NULL; 1741 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1742 struct display_stream_compressor *dsc; 1743 struct dcn_dsc_state dsc_state = {0}; 1744 const uint32_t rd_buf_size = 100; 1745 struct pipe_ctx *pipe_ctx; 1746 ssize_t result = 0; 1747 int i, r, str_len = 30; 1748 1749 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1750 1751 if (!rd_buf) 1752 return -ENOMEM; 1753 1754 for (i = 0; i < MAX_PIPES; i++) { 1755 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1756 if (pipe_ctx->stream && 1757 pipe_ctx->stream->link == aconnector->dc_link && 1758 pipe_ctx->stream->sink && 1759 pipe_ctx->stream->sink == aconnector->dc_sink) 1760 break; 1761 } 1762 1763 dsc = pipe_ctx->stream_res.dsc; 1764 if (dsc) 1765 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1766 1767 snprintf(rd_buf, str_len, 1768 "%d\n", 1769 dsc_state.dsc_slice_width); 1770 1771 while (size) { 1772 if (*pos >= rd_buf_size) 1773 break; 1774 1775 r = put_user(*(rd_buf + result), buf); 1776 if (r) { 1777 kfree(rd_buf); 1778 return r; /* r = -EFAULT */ 1779 } 1780 1781 buf += 1; 1782 size -= 1; 1783 *pos += 1; 1784 result += 1; 1785 } 1786 1787 kfree(rd_buf); 1788 return result; 1789 } 1790 1791 /* function: write DSC slice width parameter 1792 * 1793 * The write function: dp_dsc_slice_width_write 1794 * overwrites automatically generated DSC configuration 1795 * of slice width. 1796 * 1797 * The user has to write the slice width divisible by the 1798 * picture width. 1799 * 1800 * Also the user has to write width in hexidecimal 1801 * rather than in decimal. 1802 * 1803 * Writing DSC settings is done with the following command: 1804 * - To force overwrite slice width: (example sets to 1920 pixels) 1805 * 1806 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1807 * 1808 * - To stop overwriting and let driver find the optimal size, 1809 * set the width to zero: 1810 * 1811 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1812 * 1813 */ 1814 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1815 size_t size, loff_t *pos) 1816 { 1817 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1818 struct pipe_ctx *pipe_ctx; 1819 struct drm_connector *connector = &aconnector->base; 1820 struct drm_device *dev = connector->dev; 1821 struct drm_crtc *crtc = NULL; 1822 struct dm_crtc_state *dm_crtc_state = NULL; 1823 int i; 1824 char *wr_buf = NULL; 1825 uint32_t wr_buf_size = 42; 1826 int max_param_num = 1; 1827 long param[1] = {0}; 1828 uint8_t param_nums = 0; 1829 1830 if (size == 0) 1831 return -EINVAL; 1832 1833 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1834 1835 if (!wr_buf) { 1836 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1837 return -ENOSPC; 1838 } 1839 1840 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1841 (long *)param, buf, 1842 max_param_num, 1843 ¶m_nums)) { 1844 kfree(wr_buf); 1845 return -EINVAL; 1846 } 1847 1848 if (param_nums <= 0) { 1849 DRM_DEBUG_DRIVER("user data not be read\n"); 1850 kfree(wr_buf); 1851 return -EINVAL; 1852 } 1853 1854 for (i = 0; i < MAX_PIPES; i++) { 1855 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1856 if (pipe_ctx->stream && 1857 pipe_ctx->stream->link == aconnector->dc_link && 1858 pipe_ctx->stream->sink && 1859 pipe_ctx->stream->sink == aconnector->dc_sink) 1860 break; 1861 } 1862 1863 if (!pipe_ctx->stream) 1864 goto done; 1865 1866 // Safely get CRTC state 1867 mutex_lock(&dev->mode_config.mutex); 1868 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1869 1870 if (connector->state == NULL) 1871 goto unlock; 1872 1873 crtc = connector->state->crtc; 1874 if (crtc == NULL) 1875 goto unlock; 1876 1877 drm_modeset_lock(&crtc->mutex, NULL); 1878 if (crtc->state == NULL) 1879 goto unlock; 1880 1881 dm_crtc_state = to_dm_crtc_state(crtc->state); 1882 if (dm_crtc_state->stream == NULL) 1883 goto unlock; 1884 1885 if (param[0] > 0) 1886 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1887 pipe_ctx->stream->timing.h_addressable, 1888 param[0]); 1889 else 1890 aconnector->dsc_settings.dsc_num_slices_h = 0; 1891 1892 dm_crtc_state->dsc_force_changed = true; 1893 1894 unlock: 1895 if (crtc) 1896 drm_modeset_unlock(&crtc->mutex); 1897 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1898 mutex_unlock(&dev->mode_config.mutex); 1899 1900 done: 1901 kfree(wr_buf); 1902 return size; 1903 } 1904 1905 /* function: read DSC slice height parameter on the connector 1906 * 1907 * The read function: dp_dsc_slice_height_read 1908 * returns dsc slice height used in the current configuration 1909 * The return is an integer: 0 or other positive number 1910 * 1911 * Access the status with the following command: 1912 * 1913 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1914 * 1915 * 0 - means that DSC is disabled 1916 * 1917 * Any other number more than zero represents the 1918 * slice height currently used by DSC in pixels 1919 * 1920 */ 1921 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1922 size_t size, loff_t *pos) 1923 { 1924 char *rd_buf = NULL; 1925 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1926 struct display_stream_compressor *dsc; 1927 struct dcn_dsc_state dsc_state = {0}; 1928 const uint32_t rd_buf_size = 100; 1929 struct pipe_ctx *pipe_ctx; 1930 ssize_t result = 0; 1931 int i, r, str_len = 30; 1932 1933 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1934 1935 if (!rd_buf) 1936 return -ENOMEM; 1937 1938 for (i = 0; i < MAX_PIPES; i++) { 1939 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1940 if (pipe_ctx->stream && 1941 pipe_ctx->stream->link == aconnector->dc_link && 1942 pipe_ctx->stream->sink && 1943 pipe_ctx->stream->sink == aconnector->dc_sink) 1944 break; 1945 } 1946 1947 dsc = pipe_ctx->stream_res.dsc; 1948 if (dsc) 1949 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1950 1951 snprintf(rd_buf, str_len, 1952 "%d\n", 1953 dsc_state.dsc_slice_height); 1954 1955 while (size) { 1956 if (*pos >= rd_buf_size) 1957 break; 1958 1959 r = put_user(*(rd_buf + result), buf); 1960 if (r) { 1961 kfree(rd_buf); 1962 return r; /* r = -EFAULT */ 1963 } 1964 1965 buf += 1; 1966 size -= 1; 1967 *pos += 1; 1968 result += 1; 1969 } 1970 1971 kfree(rd_buf); 1972 return result; 1973 } 1974 1975 /* function: write DSC slice height parameter 1976 * 1977 * The write function: dp_dsc_slice_height_write 1978 * overwrites automatically generated DSC configuration 1979 * of slice height. 1980 * 1981 * The user has to write the slice height divisible by the 1982 * picture height. 1983 * 1984 * Also the user has to write height in hexidecimal 1985 * rather than in decimal. 1986 * 1987 * Writing DSC settings is done with the following command: 1988 * - To force overwrite slice height (example sets to 128 pixels): 1989 * 1990 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1991 * 1992 * - To stop overwriting and let driver find the optimal size, 1993 * set the height to zero: 1994 * 1995 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1996 * 1997 */ 1998 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1999 size_t size, loff_t *pos) 2000 { 2001 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2002 struct drm_connector *connector = &aconnector->base; 2003 struct drm_device *dev = connector->dev; 2004 struct drm_crtc *crtc = NULL; 2005 struct dm_crtc_state *dm_crtc_state = NULL; 2006 struct pipe_ctx *pipe_ctx; 2007 int i; 2008 char *wr_buf = NULL; 2009 uint32_t wr_buf_size = 42; 2010 int max_param_num = 1; 2011 uint8_t param_nums = 0; 2012 long param[1] = {0}; 2013 2014 if (size == 0) 2015 return -EINVAL; 2016 2017 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2018 2019 if (!wr_buf) { 2020 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2021 return -ENOSPC; 2022 } 2023 2024 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2025 (long *)param, buf, 2026 max_param_num, 2027 ¶m_nums)) { 2028 kfree(wr_buf); 2029 return -EINVAL; 2030 } 2031 2032 if (param_nums <= 0) { 2033 DRM_DEBUG_DRIVER("user data not be read\n"); 2034 kfree(wr_buf); 2035 return -EINVAL; 2036 } 2037 2038 for (i = 0; i < MAX_PIPES; i++) { 2039 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2040 if (pipe_ctx->stream && 2041 pipe_ctx->stream->link == aconnector->dc_link && 2042 pipe_ctx->stream->sink && 2043 pipe_ctx->stream->sink == aconnector->dc_sink) 2044 break; 2045 } 2046 2047 if (!pipe_ctx->stream) 2048 goto done; 2049 2050 // Get CRTC state 2051 mutex_lock(&dev->mode_config.mutex); 2052 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2053 2054 if (connector->state == NULL) 2055 goto unlock; 2056 2057 crtc = connector->state->crtc; 2058 if (crtc == NULL) 2059 goto unlock; 2060 2061 drm_modeset_lock(&crtc->mutex, NULL); 2062 if (crtc->state == NULL) 2063 goto unlock; 2064 2065 dm_crtc_state = to_dm_crtc_state(crtc->state); 2066 if (dm_crtc_state->stream == NULL) 2067 goto unlock; 2068 2069 if (param[0] > 0) 2070 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 2071 pipe_ctx->stream->timing.v_addressable, 2072 param[0]); 2073 else 2074 aconnector->dsc_settings.dsc_num_slices_v = 0; 2075 2076 dm_crtc_state->dsc_force_changed = true; 2077 2078 unlock: 2079 if (crtc) 2080 drm_modeset_unlock(&crtc->mutex); 2081 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2082 mutex_unlock(&dev->mode_config.mutex); 2083 2084 done: 2085 kfree(wr_buf); 2086 return size; 2087 } 2088 2089 /* function: read DSC target rate on the connector in bits per pixel 2090 * 2091 * The read function: dp_dsc_bits_per_pixel_read 2092 * returns target rate of compression in bits per pixel 2093 * The return is an integer: 0 or other positive integer 2094 * 2095 * Access it with the following command: 2096 * 2097 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2098 * 2099 * 0 - means that DSC is disabled 2100 */ 2101 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 2102 size_t size, loff_t *pos) 2103 { 2104 char *rd_buf = NULL; 2105 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2106 struct display_stream_compressor *dsc; 2107 struct dcn_dsc_state dsc_state = {0}; 2108 const uint32_t rd_buf_size = 100; 2109 struct pipe_ctx *pipe_ctx; 2110 ssize_t result = 0; 2111 int i, r, str_len = 30; 2112 2113 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2114 2115 if (!rd_buf) 2116 return -ENOMEM; 2117 2118 for (i = 0; i < MAX_PIPES; i++) { 2119 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2120 if (pipe_ctx->stream && 2121 pipe_ctx->stream->link == aconnector->dc_link && 2122 pipe_ctx->stream->sink && 2123 pipe_ctx->stream->sink == aconnector->dc_sink) 2124 break; 2125 } 2126 2127 dsc = pipe_ctx->stream_res.dsc; 2128 if (dsc) 2129 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2130 2131 snprintf(rd_buf, str_len, 2132 "%d\n", 2133 dsc_state.dsc_bits_per_pixel); 2134 2135 while (size) { 2136 if (*pos >= rd_buf_size) 2137 break; 2138 2139 r = put_user(*(rd_buf + result), buf); 2140 if (r) { 2141 kfree(rd_buf); 2142 return r; /* r = -EFAULT */ 2143 } 2144 2145 buf += 1; 2146 size -= 1; 2147 *pos += 1; 2148 result += 1; 2149 } 2150 2151 kfree(rd_buf); 2152 return result; 2153 } 2154 2155 /* function: write DSC target rate in bits per pixel 2156 * 2157 * The write function: dp_dsc_bits_per_pixel_write 2158 * overwrites automatically generated DSC configuration 2159 * of DSC target bit rate. 2160 * 2161 * Also the user has to write bpp in hexidecimal 2162 * rather than in decimal. 2163 * 2164 * Writing DSC settings is done with the following command: 2165 * - To force overwrite rate (example sets to 256 bpp x 1/16): 2166 * 2167 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2168 * 2169 * - To stop overwriting and let driver find the optimal rate, 2170 * set the rate to zero: 2171 * 2172 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2173 * 2174 */ 2175 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2176 size_t size, loff_t *pos) 2177 { 2178 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2179 struct drm_connector *connector = &aconnector->base; 2180 struct drm_device *dev = connector->dev; 2181 struct drm_crtc *crtc = NULL; 2182 struct dm_crtc_state *dm_crtc_state = NULL; 2183 struct pipe_ctx *pipe_ctx; 2184 int i; 2185 char *wr_buf = NULL; 2186 uint32_t wr_buf_size = 42; 2187 int max_param_num = 1; 2188 uint8_t param_nums = 0; 2189 long param[1] = {0}; 2190 2191 if (size == 0) 2192 return -EINVAL; 2193 2194 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2195 2196 if (!wr_buf) { 2197 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2198 return -ENOSPC; 2199 } 2200 2201 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2202 (long *)param, buf, 2203 max_param_num, 2204 ¶m_nums)) { 2205 kfree(wr_buf); 2206 return -EINVAL; 2207 } 2208 2209 if (param_nums <= 0) { 2210 DRM_DEBUG_DRIVER("user data not be read\n"); 2211 kfree(wr_buf); 2212 return -EINVAL; 2213 } 2214 2215 for (i = 0; i < MAX_PIPES; i++) { 2216 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2217 if (pipe_ctx->stream && 2218 pipe_ctx->stream->link == aconnector->dc_link && 2219 pipe_ctx->stream->sink && 2220 pipe_ctx->stream->sink == aconnector->dc_sink) 2221 break; 2222 } 2223 2224 if (!pipe_ctx->stream) 2225 goto done; 2226 2227 // Get CRTC state 2228 mutex_lock(&dev->mode_config.mutex); 2229 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2230 2231 if (connector->state == NULL) 2232 goto unlock; 2233 2234 crtc = connector->state->crtc; 2235 if (crtc == NULL) 2236 goto unlock; 2237 2238 drm_modeset_lock(&crtc->mutex, NULL); 2239 if (crtc->state == NULL) 2240 goto unlock; 2241 2242 dm_crtc_state = to_dm_crtc_state(crtc->state); 2243 if (dm_crtc_state->stream == NULL) 2244 goto unlock; 2245 2246 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2247 2248 dm_crtc_state->dsc_force_changed = true; 2249 2250 unlock: 2251 if (crtc) 2252 drm_modeset_unlock(&crtc->mutex); 2253 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2254 mutex_unlock(&dev->mode_config.mutex); 2255 2256 done: 2257 kfree(wr_buf); 2258 return size; 2259 } 2260 2261 /* function: read DSC picture width parameter on the connector 2262 * 2263 * The read function: dp_dsc_pic_width_read 2264 * returns dsc picture width used in the current configuration 2265 * It is the same as h_addressable of the current 2266 * display's timing 2267 * The return is an integer: 0 or other positive integer 2268 * If 0 then DSC is disabled. 2269 * 2270 * Access it with the following command: 2271 * 2272 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2273 * 2274 * 0 - means that DSC is disabled 2275 */ 2276 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2277 size_t size, loff_t *pos) 2278 { 2279 char *rd_buf = NULL; 2280 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2281 struct display_stream_compressor *dsc; 2282 struct dcn_dsc_state dsc_state = {0}; 2283 const uint32_t rd_buf_size = 100; 2284 struct pipe_ctx *pipe_ctx; 2285 ssize_t result = 0; 2286 int i, r, str_len = 30; 2287 2288 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2289 2290 if (!rd_buf) 2291 return -ENOMEM; 2292 2293 for (i = 0; i < MAX_PIPES; i++) { 2294 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2295 if (pipe_ctx->stream && 2296 pipe_ctx->stream->link == aconnector->dc_link && 2297 pipe_ctx->stream->sink && 2298 pipe_ctx->stream->sink == aconnector->dc_sink) 2299 break; 2300 } 2301 2302 dsc = pipe_ctx->stream_res.dsc; 2303 if (dsc) 2304 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2305 2306 snprintf(rd_buf, str_len, 2307 "%d\n", 2308 dsc_state.dsc_pic_width); 2309 2310 while (size) { 2311 if (*pos >= rd_buf_size) 2312 break; 2313 2314 r = put_user(*(rd_buf + result), buf); 2315 if (r) { 2316 kfree(rd_buf); 2317 return r; /* r = -EFAULT */ 2318 } 2319 2320 buf += 1; 2321 size -= 1; 2322 *pos += 1; 2323 result += 1; 2324 } 2325 2326 kfree(rd_buf); 2327 return result; 2328 } 2329 2330 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2331 size_t size, loff_t *pos) 2332 { 2333 char *rd_buf = NULL; 2334 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2335 struct display_stream_compressor *dsc; 2336 struct dcn_dsc_state dsc_state = {0}; 2337 const uint32_t rd_buf_size = 100; 2338 struct pipe_ctx *pipe_ctx; 2339 ssize_t result = 0; 2340 int i, r, str_len = 30; 2341 2342 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2343 2344 if (!rd_buf) 2345 return -ENOMEM; 2346 2347 for (i = 0; i < MAX_PIPES; i++) { 2348 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2349 if (pipe_ctx->stream && 2350 pipe_ctx->stream->link == aconnector->dc_link && 2351 pipe_ctx->stream->sink && 2352 pipe_ctx->stream->sink == aconnector->dc_sink) 2353 break; 2354 } 2355 2356 dsc = pipe_ctx->stream_res.dsc; 2357 if (dsc) 2358 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2359 2360 snprintf(rd_buf, str_len, 2361 "%d\n", 2362 dsc_state.dsc_pic_height); 2363 2364 while (size) { 2365 if (*pos >= rd_buf_size) 2366 break; 2367 2368 r = put_user(*(rd_buf + result), buf); 2369 if (r) { 2370 kfree(rd_buf); 2371 return r; /* r = -EFAULT */ 2372 } 2373 2374 buf += 1; 2375 size -= 1; 2376 *pos += 1; 2377 result += 1; 2378 } 2379 2380 kfree(rd_buf); 2381 return result; 2382 } 2383 2384 /* function: read DSC chunk size parameter on the connector 2385 * 2386 * The read function: dp_dsc_chunk_size_read 2387 * returns dsc chunk size set in the current configuration 2388 * The value is calculated automatically by DSC code 2389 * and depends on slice parameters and bpp target rate 2390 * The return is an integer: 0 or other positive integer 2391 * If 0 then DSC is disabled. 2392 * 2393 * Access it with the following command: 2394 * 2395 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2396 * 2397 * 0 - means that DSC is disabled 2398 */ 2399 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2400 size_t size, loff_t *pos) 2401 { 2402 char *rd_buf = NULL; 2403 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2404 struct display_stream_compressor *dsc; 2405 struct dcn_dsc_state dsc_state = {0}; 2406 const uint32_t rd_buf_size = 100; 2407 struct pipe_ctx *pipe_ctx; 2408 ssize_t result = 0; 2409 int i, r, str_len = 30; 2410 2411 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2412 2413 if (!rd_buf) 2414 return -ENOMEM; 2415 2416 for (i = 0; i < MAX_PIPES; i++) { 2417 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2418 if (pipe_ctx->stream && 2419 pipe_ctx->stream->link == aconnector->dc_link && 2420 pipe_ctx->stream->sink && 2421 pipe_ctx->stream->sink == aconnector->dc_sink) 2422 break; 2423 } 2424 2425 dsc = pipe_ctx->stream_res.dsc; 2426 if (dsc) 2427 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2428 2429 snprintf(rd_buf, str_len, 2430 "%d\n", 2431 dsc_state.dsc_chunk_size); 2432 2433 while (size) { 2434 if (*pos >= rd_buf_size) 2435 break; 2436 2437 r = put_user(*(rd_buf + result), buf); 2438 if (r) { 2439 kfree(rd_buf); 2440 return r; /* r = -EFAULT */ 2441 } 2442 2443 buf += 1; 2444 size -= 1; 2445 *pos += 1; 2446 result += 1; 2447 } 2448 2449 kfree(rd_buf); 2450 return result; 2451 } 2452 2453 /* function: read DSC slice bpg offset on the connector 2454 * 2455 * The read function: dp_dsc_slice_bpg_offset_read 2456 * returns dsc bpg slice offset set in the current configuration 2457 * The value is calculated automatically by DSC code 2458 * and depends on slice parameters and bpp target rate 2459 * The return is an integer: 0 or other positive integer 2460 * If 0 then DSC is disabled. 2461 * 2462 * Access it with the following command: 2463 * 2464 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2465 * 2466 * 0 - means that DSC is disabled 2467 */ 2468 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2469 size_t size, loff_t *pos) 2470 { 2471 char *rd_buf = NULL; 2472 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2473 struct display_stream_compressor *dsc; 2474 struct dcn_dsc_state dsc_state = {0}; 2475 const uint32_t rd_buf_size = 100; 2476 struct pipe_ctx *pipe_ctx; 2477 ssize_t result = 0; 2478 int i, r, str_len = 30; 2479 2480 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2481 2482 if (!rd_buf) 2483 return -ENOMEM; 2484 2485 for (i = 0; i < MAX_PIPES; i++) { 2486 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2487 if (pipe_ctx->stream && 2488 pipe_ctx->stream->link == aconnector->dc_link && 2489 pipe_ctx->stream->sink && 2490 pipe_ctx->stream->sink == aconnector->dc_sink) 2491 break; 2492 } 2493 2494 dsc = pipe_ctx->stream_res.dsc; 2495 if (dsc) 2496 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2497 2498 snprintf(rd_buf, str_len, 2499 "%d\n", 2500 dsc_state.dsc_slice_bpg_offset); 2501 2502 while (size) { 2503 if (*pos >= rd_buf_size) 2504 break; 2505 2506 r = put_user(*(rd_buf + result), buf); 2507 if (r) { 2508 kfree(rd_buf); 2509 return r; /* r = -EFAULT */ 2510 } 2511 2512 buf += 1; 2513 size -= 1; 2514 *pos += 1; 2515 result += 1; 2516 } 2517 2518 kfree(rd_buf); 2519 return result; 2520 } 2521 2522 2523 /* 2524 * function description: Read max_requested_bpc property from the connector 2525 * 2526 * Access it with the following command: 2527 * 2528 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2529 * 2530 */ 2531 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2532 size_t size, loff_t *pos) 2533 { 2534 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2535 struct drm_connector *connector = &aconnector->base; 2536 struct drm_device *dev = connector->dev; 2537 struct dm_connector_state *state; 2538 ssize_t result = 0; 2539 char *rd_buf = NULL; 2540 char *rd_buf_ptr = NULL; 2541 const uint32_t rd_buf_size = 10; 2542 int r; 2543 2544 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2545 2546 if (!rd_buf) 2547 return -ENOMEM; 2548 2549 mutex_lock(&dev->mode_config.mutex); 2550 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2551 2552 if (connector->state == NULL) 2553 goto unlock; 2554 2555 state = to_dm_connector_state(connector->state); 2556 2557 rd_buf_ptr = rd_buf; 2558 snprintf(rd_buf_ptr, rd_buf_size, 2559 "%u\n", 2560 state->base.max_requested_bpc); 2561 2562 while (size) { 2563 if (*pos >= rd_buf_size) 2564 break; 2565 2566 r = put_user(*(rd_buf + result), buf); 2567 if (r) { 2568 result = r; /* r = -EFAULT */ 2569 goto unlock; 2570 } 2571 buf += 1; 2572 size -= 1; 2573 *pos += 1; 2574 result += 1; 2575 } 2576 unlock: 2577 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2578 mutex_unlock(&dev->mode_config.mutex); 2579 kfree(rd_buf); 2580 return result; 2581 } 2582 2583 2584 /* 2585 * function description: Set max_requested_bpc property on the connector 2586 * 2587 * This function will not force the input BPC on connector, it will only 2588 * change the max value. This is equivalent to setting max_bpc through 2589 * xrandr. 2590 * 2591 * The BPC value written must be >= 6 and <= 16. Values outside of this 2592 * range will result in errors. 2593 * 2594 * BPC values: 2595 * 0x6 - 6 BPC 2596 * 0x8 - 8 BPC 2597 * 0xa - 10 BPC 2598 * 0xc - 12 BPC 2599 * 0x10 - 16 BPC 2600 * 2601 * Write the max_bpc in the following way: 2602 * 2603 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2604 * 2605 */ 2606 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2607 size_t size, loff_t *pos) 2608 { 2609 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2610 struct drm_connector *connector = &aconnector->base; 2611 struct dm_connector_state *state; 2612 struct drm_device *dev = connector->dev; 2613 char *wr_buf = NULL; 2614 uint32_t wr_buf_size = 42; 2615 int max_param_num = 1; 2616 long param[1] = {0}; 2617 uint8_t param_nums = 0; 2618 2619 if (size == 0) 2620 return -EINVAL; 2621 2622 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2623 2624 if (!wr_buf) { 2625 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2626 return -ENOSPC; 2627 } 2628 2629 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2630 (long *)param, buf, 2631 max_param_num, 2632 ¶m_nums)) { 2633 kfree(wr_buf); 2634 return -EINVAL; 2635 } 2636 2637 if (param_nums <= 0) { 2638 DRM_DEBUG_DRIVER("user data not be read\n"); 2639 kfree(wr_buf); 2640 return -EINVAL; 2641 } 2642 2643 if (param[0] < 6 || param[0] > 16) { 2644 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2645 kfree(wr_buf); 2646 return -EINVAL; 2647 } 2648 2649 mutex_lock(&dev->mode_config.mutex); 2650 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2651 2652 if (connector->state == NULL) 2653 goto unlock; 2654 2655 state = to_dm_connector_state(connector->state); 2656 state->base.max_requested_bpc = param[0]; 2657 unlock: 2658 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2659 mutex_unlock(&dev->mode_config.mutex); 2660 2661 kfree(wr_buf); 2662 return size; 2663 } 2664 2665 /* 2666 * IPS status. Read only. 2667 * 2668 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status 2669 */ 2670 static int ips_status_show(struct seq_file *m, void *unused) 2671 { 2672 struct amdgpu_device *adev = m->private; 2673 struct dc *dc = adev->dm.dc; 2674 struct dc_dmub_srv *dc_dmub_srv; 2675 2676 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips); 2677 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed); 2678 2679 if (adev->dm.idle_workqueue) { 2680 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable); 2681 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running); 2682 } 2683 2684 dc_dmub_srv = dc->ctx->dmub_srv; 2685 if (dc_dmub_srv && dc_dmub_srv->dmub) { 2686 uint32_t rcg_count, ips1_count, ips2_count; 2687 volatile const struct dmub_shared_state_ips_fw *ips_fw = 2688 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 2689 rcg_count = ips_fw->rcg_entry_count; 2690 ips1_count = ips_fw->ips1_entry_count; 2691 ips2_count = ips_fw->ips2_entry_count; 2692 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n", 2693 rcg_count, 2694 ips1_count, 2695 ips2_count); 2696 rcg_count = ips_fw->rcg_exit_count; 2697 ips1_count = ips_fw->ips1_exit_count; 2698 ips2_count = ips_fw->ips2_exit_count; 2699 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u", 2700 rcg_count, 2701 ips1_count, 2702 ips2_count); 2703 seq_puts(m, "\n"); 2704 } 2705 return 0; 2706 } 2707 2708 /* 2709 * Backlight at this moment. Read only. 2710 * As written to display, taking ABM and backlight lut into account. 2711 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2712 * 2713 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2714 */ 2715 static int current_backlight_show(struct seq_file *m, void *unused) 2716 { 2717 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2718 struct dc_link *link = aconnector->dc_link; 2719 unsigned int backlight; 2720 2721 backlight = dc_link_get_backlight_level(link); 2722 seq_printf(m, "0x%x\n", backlight); 2723 2724 return 0; 2725 } 2726 2727 /* 2728 * Backlight value that is being approached. Read only. 2729 * As written to display, taking ABM and backlight lut into account. 2730 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2731 * 2732 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2733 */ 2734 static int target_backlight_show(struct seq_file *m, void *unused) 2735 { 2736 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2737 struct dc_link *link = aconnector->dc_link; 2738 unsigned int backlight; 2739 2740 backlight = dc_link_get_target_backlight_pwm(link); 2741 seq_printf(m, "0x%x\n", backlight); 2742 2743 return 0; 2744 } 2745 2746 /* 2747 * function description: Determine if the connector is mst connector 2748 * 2749 * This function helps to determine whether a connector is a mst connector. 2750 * - "root" stands for the root connector of the topology 2751 * - "branch" stands for branch device of the topology 2752 * - "end" stands for leaf node connector of the topology 2753 * - "no" stands for the connector is not a device of a mst topology 2754 * Access it with the following command: 2755 * 2756 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2757 * 2758 */ 2759 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2760 { 2761 struct drm_connector *connector = m->private; 2762 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2763 struct drm_dp_mst_topology_mgr *mgr = NULL; 2764 struct drm_dp_mst_port *port = NULL; 2765 char *role = NULL; 2766 2767 mutex_lock(&aconnector->hpd_lock); 2768 2769 if (aconnector->mst_mgr.mst_state) { 2770 role = "root"; 2771 } else if (aconnector->mst_root && 2772 aconnector->mst_root->mst_mgr.mst_state) { 2773 2774 role = "end"; 2775 2776 mgr = &aconnector->mst_root->mst_mgr; 2777 port = aconnector->mst_output_port; 2778 2779 drm_modeset_lock(&mgr->base.lock, NULL); 2780 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2781 port->mcs) 2782 role = "branch"; 2783 drm_modeset_unlock(&mgr->base.lock); 2784 2785 } else { 2786 role = "no"; 2787 } 2788 2789 seq_printf(m, "%s\n", role); 2790 2791 mutex_unlock(&aconnector->hpd_lock); 2792 2793 return 0; 2794 } 2795 2796 /* 2797 * function description: Read out the mst progress status 2798 * 2799 * This function helps to determine the mst progress status of 2800 * a mst connector. 2801 * 2802 * Access it with the following command: 2803 * 2804 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2805 * 2806 */ 2807 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2808 { 2809 struct drm_connector *connector = m->private; 2810 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2811 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2812 int i; 2813 2814 mutex_lock(&aconnector->hpd_lock); 2815 mutex_lock(&adev->dm.dc_lock); 2816 2817 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2818 seq_puts(m, "disabled\n"); 2819 } else { 2820 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2821 seq_printf(m, "%s:%s\n", 2822 mst_progress_status[i], 2823 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2824 } 2825 2826 mutex_unlock(&adev->dm.dc_lock); 2827 mutex_unlock(&aconnector->hpd_lock); 2828 2829 return 0; 2830 } 2831 2832 /* 2833 * Reports whether the connected display is a USB4 DPIA tunneled display 2834 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2835 */ 2836 static int is_dpia_link_show(struct seq_file *m, void *data) 2837 { 2838 struct drm_connector *connector = m->private; 2839 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2840 struct dc_link *link = aconnector->dc_link; 2841 2842 if (connector->status != connector_status_connected) 2843 return -ENODEV; 2844 2845 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2846 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2847 2848 return 0; 2849 } 2850 2851 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2852 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2853 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2854 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2855 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2856 DEFINE_SHOW_ATTRIBUTE(internal_display); 2857 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); 2858 DEFINE_SHOW_ATTRIBUTE(replay_capability); 2859 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2860 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2861 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2862 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2863 2864 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2865 .owner = THIS_MODULE, 2866 .read = dp_dsc_clock_en_read, 2867 .write = dp_dsc_clock_en_write, 2868 .llseek = default_llseek 2869 }; 2870 2871 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2872 .owner = THIS_MODULE, 2873 .read = dp_dsc_slice_width_read, 2874 .write = dp_dsc_slice_width_write, 2875 .llseek = default_llseek 2876 }; 2877 2878 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2879 .owner = THIS_MODULE, 2880 .read = dp_dsc_slice_height_read, 2881 .write = dp_dsc_slice_height_write, 2882 .llseek = default_llseek 2883 }; 2884 2885 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2886 .owner = THIS_MODULE, 2887 .read = dp_dsc_bits_per_pixel_read, 2888 .write = dp_dsc_bits_per_pixel_write, 2889 .llseek = default_llseek 2890 }; 2891 2892 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2893 .owner = THIS_MODULE, 2894 .read = dp_dsc_pic_width_read, 2895 .llseek = default_llseek 2896 }; 2897 2898 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2899 .owner = THIS_MODULE, 2900 .read = dp_dsc_pic_height_read, 2901 .llseek = default_llseek 2902 }; 2903 2904 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2905 .owner = THIS_MODULE, 2906 .read = dp_dsc_chunk_size_read, 2907 .llseek = default_llseek 2908 }; 2909 2910 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2911 .owner = THIS_MODULE, 2912 .read = dp_dsc_slice_bpg_offset_read, 2913 .llseek = default_llseek 2914 }; 2915 2916 static const struct file_operations trigger_hotplug_debugfs_fops = { 2917 .owner = THIS_MODULE, 2918 .write = trigger_hotplug, 2919 .llseek = default_llseek 2920 }; 2921 2922 static const struct file_operations dp_link_settings_debugfs_fops = { 2923 .owner = THIS_MODULE, 2924 .read = dp_link_settings_read, 2925 .write = dp_link_settings_write, 2926 .llseek = default_llseek 2927 }; 2928 2929 static const struct file_operations dp_phy_settings_debugfs_fop = { 2930 .owner = THIS_MODULE, 2931 .read = dp_phy_settings_read, 2932 .write = dp_phy_settings_write, 2933 .llseek = default_llseek 2934 }; 2935 2936 static const struct file_operations dp_phy_test_pattern_fops = { 2937 .owner = THIS_MODULE, 2938 .write = dp_phy_test_pattern_debugfs_write, 2939 .llseek = default_llseek 2940 }; 2941 2942 static const struct file_operations sdp_message_fops = { 2943 .owner = THIS_MODULE, 2944 .write = dp_sdp_message_debugfs_write, 2945 .llseek = default_llseek 2946 }; 2947 2948 static const struct file_operations dp_max_bpc_debugfs_fops = { 2949 .owner = THIS_MODULE, 2950 .read = dp_max_bpc_read, 2951 .write = dp_max_bpc_write, 2952 .llseek = default_llseek 2953 }; 2954 2955 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2956 .owner = THIS_MODULE, 2957 .write = dp_dsc_passthrough_set, 2958 .llseek = default_llseek 2959 }; 2960 2961 static const struct file_operations dp_mst_link_settings_debugfs_fops = { 2962 .owner = THIS_MODULE, 2963 .write = dp_mst_link_setting, 2964 .llseek = default_llseek 2965 }; 2966 2967 static const struct { 2968 char *name; 2969 const struct file_operations *fops; 2970 } dp_debugfs_entries[] = { 2971 {"link_settings", &dp_link_settings_debugfs_fops}, 2972 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2973 {"lttpr_status", &dp_lttpr_status_fops}, 2974 {"test_pattern", &dp_phy_test_pattern_fops}, 2975 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2976 {"sdp_message", &sdp_message_fops}, 2977 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2978 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2979 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2980 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2981 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2982 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2983 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2984 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2985 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2986 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2987 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2988 {"is_mst_connector", &dp_is_mst_connector_fops}, 2989 {"mst_progress_status", &dp_mst_progress_status_fops}, 2990 {"is_dpia_link", &is_dpia_link_fops}, 2991 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} 2992 }; 2993 2994 static const struct { 2995 char *name; 2996 const struct file_operations *fops; 2997 } hdmi_debugfs_entries[] = { 2998 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2999 }; 3000 3001 /* 3002 * Force YUV420 output if available from the given mode 3003 */ 3004 static int force_yuv420_output_set(void *data, u64 val) 3005 { 3006 struct amdgpu_dm_connector *connector = data; 3007 3008 connector->force_yuv420_output = (bool)val; 3009 3010 return 0; 3011 } 3012 3013 /* 3014 * Check if YUV420 is forced when available from the given mode 3015 */ 3016 static int force_yuv420_output_get(void *data, u64 *val) 3017 { 3018 struct amdgpu_dm_connector *connector = data; 3019 3020 *val = connector->force_yuv420_output; 3021 3022 return 0; 3023 } 3024 3025 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 3026 force_yuv420_output_set, "%llu\n"); 3027 3028 /* 3029 * Read Replay state 3030 */ 3031 static int replay_get_state(void *data, u64 *val) 3032 { 3033 struct amdgpu_dm_connector *connector = data; 3034 struct dc_link *link = connector->dc_link; 3035 uint64_t state = REPLAY_STATE_INVALID; 3036 3037 dc_link_get_replay_state(link, &state); 3038 3039 *val = state; 3040 3041 return 0; 3042 } 3043 3044 /* 3045 * Read PSR state 3046 */ 3047 static int psr_get(void *data, u64 *val) 3048 { 3049 struct amdgpu_dm_connector *connector = data; 3050 struct dc_link *link = connector->dc_link; 3051 enum dc_psr_state state = PSR_STATE0; 3052 3053 dc_link_get_psr_state(link, &state); 3054 3055 *val = state; 3056 3057 return 0; 3058 } 3059 3060 /* 3061 * Read PSR state residency 3062 */ 3063 static int psr_read_residency(void *data, u64 *val) 3064 { 3065 struct amdgpu_dm_connector *connector = data; 3066 struct dc_link *link = connector->dc_link; 3067 u32 residency = 0; 3068 3069 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY); 3070 3071 *val = (u64)residency; 3072 3073 return 0; 3074 } 3075 3076 /* read allow_edp_hotplug_detection */ 3077 static int allow_edp_hotplug_detection_get(void *data, u64 *val) 3078 { 3079 struct amdgpu_dm_connector *aconnector = data; 3080 struct drm_connector *connector = &aconnector->base; 3081 struct drm_device *dev = connector->dev; 3082 struct amdgpu_device *adev = drm_to_adev(dev); 3083 3084 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 3085 3086 return 0; 3087 } 3088 3089 /* set allow_edp_hotplug_detection */ 3090 static int allow_edp_hotplug_detection_set(void *data, u64 val) 3091 { 3092 struct amdgpu_dm_connector *aconnector = data; 3093 struct drm_connector *connector = &aconnector->base; 3094 struct drm_device *dev = connector->dev; 3095 struct amdgpu_device *adev = drm_to_adev(dev); 3096 3097 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 3098 3099 return 0; 3100 } 3101 3102 /* check if kernel disallow eDP enter psr state 3103 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3104 * 0: allow edp enter psr; 1: disallow 3105 */ 3106 static int disallow_edp_enter_psr_get(void *data, u64 *val) 3107 { 3108 struct amdgpu_dm_connector *aconnector = data; 3109 3110 *val = (u64) aconnector->disallow_edp_enter_psr; 3111 return 0; 3112 } 3113 3114 /* set kernel disallow eDP enter psr state 3115 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3116 * 0: allow edp enter psr; 1: disallow 3117 * 3118 * usage: test app read crc from PSR eDP rx. 3119 * 3120 * during kernel boot up, kernel write dpcd 0x170 = 5. 3121 * this notify eDP rx psr enable and let rx check crc. 3122 * rx fw will start checking crc for rx internal logic. 3123 * crc read count within dpcd 0x246 is not updated and 3124 * value is 0. when eDP tx driver wants to read rx crc 3125 * from dpcd 0x246, 0x270, read count 0 lead tx driver 3126 * timeout. 3127 * 3128 * to avoid this, we add this debugfs to let test app to disbable 3129 * rx crc checking for rx internal logic. then test app can read 3130 * non-zero crc read count. 3131 * 3132 * expected app sequence is as below: 3133 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. 3134 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3135 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but 3136 * without dpcd 0x170 = 5. 3137 * 4. read crc from rx dpcd 0x270, 0x246, etc. 3138 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr. 3139 * this will let eDP back to normal with psr setup dpcd 0x170 = 5. 3140 */ 3141 static int disallow_edp_enter_psr_set(void *data, u64 val) 3142 { 3143 struct amdgpu_dm_connector *aconnector = data; 3144 3145 aconnector->disallow_edp_enter_psr = val ? true : false; 3146 return 0; 3147 } 3148 3149 static int dmub_trace_mask_set(void *data, u64 val) 3150 { 3151 struct amdgpu_device *adev = data; 3152 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3153 enum dmub_gpint_command cmd; 3154 u64 mask = 0xffff; 3155 u8 shift = 0; 3156 u32 res; 3157 int i; 3158 3159 if (!srv->fw_version) 3160 return -EINVAL; 3161 3162 for (i = 0; i < 4; i++) { 3163 res = (val & mask) >> shift; 3164 3165 switch (i) { 3166 case 0: 3167 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0; 3168 break; 3169 case 1: 3170 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1; 3171 break; 3172 case 2: 3173 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2; 3174 break; 3175 case 3: 3176 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3; 3177 break; 3178 } 3179 3180 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT)) 3181 return -EIO; 3182 3183 usleep_range(100, 1000); 3184 3185 mask <<= 16; 3186 shift += 16; 3187 } 3188 3189 return 0; 3190 } 3191 3192 static int dmub_trace_mask_show(void *data, u64 *val) 3193 { 3194 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0; 3195 struct amdgpu_device *adev = data; 3196 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3197 u8 shift = 0; 3198 u64 raw = 0; 3199 u64 res = 0; 3200 int i = 0; 3201 3202 if (!srv->fw_version) 3203 return -EINVAL; 3204 3205 while (i < 4) { 3206 uint32_t response; 3207 3208 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 3209 return -EIO; 3210 3211 raw = response; 3212 usleep_range(100, 1000); 3213 3214 cmd++; 3215 res |= (raw << shift); 3216 shift += 16; 3217 i++; 3218 } 3219 3220 *val = res; 3221 3222 return 0; 3223 } 3224 3225 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, 3226 dmub_trace_mask_set, "0x%llx\n"); 3227 3228 /* 3229 * Set dmcub trace event IRQ enable or disable. 3230 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3231 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3232 */ 3233 static int dmcub_trace_event_state_set(void *data, u64 val) 3234 { 3235 struct amdgpu_device *adev = data; 3236 3237 if (val == 1 || val == 0) { 3238 dc_dmub_trace_event_control(adev->dm.dc, val); 3239 adev->dm.dmcub_trace_event_en = (bool)val; 3240 } else 3241 return 0; 3242 3243 return 0; 3244 } 3245 3246 /* 3247 * The interface doesn't need get function, so it will return the 3248 * value of zero 3249 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3250 */ 3251 static int dmcub_trace_event_state_get(void *data, u64 *val) 3252 { 3253 struct amdgpu_device *adev = data; 3254 3255 *val = adev->dm.dmcub_trace_event_en; 3256 return 0; 3257 } 3258 3259 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 3260 dmcub_trace_event_state_set, "%llu\n"); 3261 3262 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n"); 3263 3264 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 3265 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 3266 "%llu\n"); 3267 3268 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 3269 allow_edp_hotplug_detection_get, 3270 allow_edp_hotplug_detection_set, "%llu\n"); 3271 3272 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, 3273 disallow_edp_enter_psr_get, 3274 disallow_edp_enter_psr_set, "%llu\n"); 3275 3276 DEFINE_SHOW_ATTRIBUTE(current_backlight); 3277 DEFINE_SHOW_ATTRIBUTE(target_backlight); 3278 DEFINE_SHOW_ATTRIBUTE(ips_status); 3279 3280 static const struct { 3281 char *name; 3282 const struct file_operations *fops; 3283 } connector_debugfs_entries[] = { 3284 {"force_yuv420_output", &force_yuv420_output_fops}, 3285 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 3286 {"internal_display", &internal_display_fops}, 3287 {"odm_combine_segments", &odm_combine_segments_fops} 3288 }; 3289 3290 /* 3291 * Returns supported customized link rates by this eDP panel. 3292 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3293 */ 3294 static int edp_ilr_show(struct seq_file *m, void *unused) 3295 { 3296 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 3297 struct dc_link *link = aconnector->dc_link; 3298 uint8_t supported_link_rates[16]; 3299 uint32_t link_rate_in_khz; 3300 uint32_t entry = 0; 3301 uint8_t dpcd_rev; 3302 3303 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 3304 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3305 supported_link_rates, sizeof(supported_link_rates)); 3306 3307 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3308 3309 if (dpcd_rev >= DP_DPCD_REV_13 && 3310 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 3311 3312 for (entry = 0; entry < 16; entry += 2) { 3313 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 3314 supported_link_rates[entry]) * 200; 3315 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 3316 } 3317 } else { 3318 seq_puts(m, "ILR is not supported by this eDP panel.\n"); 3319 } 3320 3321 return 0; 3322 } 3323 3324 /* 3325 * Set supported customized link rate to eDP panel. 3326 * 3327 * echo <lane_count> <link_rate option> > ilr_setting 3328 * 3329 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 3330 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3331 * to set 4 lanes and 2.16 GHz 3332 */ 3333 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 3334 size_t size, loff_t *pos) 3335 { 3336 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 3337 struct dc_link *link = connector->dc_link; 3338 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3339 struct dc *dc = (struct dc *)link->dc; 3340 struct dc_link_settings prefer_link_settings; 3341 char *wr_buf = NULL; 3342 const uint32_t wr_buf_size = 40; 3343 /* 0: lane_count; 1: link_rate */ 3344 int max_param_num = 2; 3345 uint8_t param_nums = 0; 3346 long param[2]; 3347 bool valid_input = true; 3348 3349 if (size == 0) 3350 return -EINVAL; 3351 3352 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 3353 if (!wr_buf) 3354 return -ENOMEM; 3355 3356 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 3357 (long *)param, buf, 3358 max_param_num, 3359 ¶m_nums)) { 3360 kfree(wr_buf); 3361 return -EINVAL; 3362 } 3363 3364 if (param_nums <= 0) { 3365 kfree(wr_buf); 3366 return -EINVAL; 3367 } 3368 3369 switch (param[0]) { 3370 case LANE_COUNT_ONE: 3371 case LANE_COUNT_TWO: 3372 case LANE_COUNT_FOUR: 3373 break; 3374 default: 3375 valid_input = false; 3376 break; 3377 } 3378 3379 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 3380 valid_input = false; 3381 3382 if (!valid_input) { 3383 kfree(wr_buf); 3384 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 3385 prefer_link_settings.use_link_rate_set = false; 3386 mutex_lock(&adev->dm.dc_lock); 3387 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 3388 mutex_unlock(&adev->dm.dc_lock); 3389 return size; 3390 } 3391 3392 /* save user force lane_count, link_rate to preferred settings 3393 * spread spectrum will not be changed 3394 */ 3395 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3396 prefer_link_settings.lane_count = param[0]; 3397 prefer_link_settings.use_link_rate_set = true; 3398 prefer_link_settings.link_rate_set = param[1]; 3399 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3400 3401 mutex_lock(&adev->dm.dc_lock); 3402 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3403 NULL, link, false); 3404 mutex_unlock(&adev->dm.dc_lock); 3405 3406 kfree(wr_buf); 3407 return size; 3408 } 3409 3410 static int edp_ilr_open(struct inode *inode, struct file *file) 3411 { 3412 return single_open(file, edp_ilr_show, inode->i_private); 3413 } 3414 3415 static const struct file_operations edp_ilr_debugfs_fops = { 3416 .owner = THIS_MODULE, 3417 .open = edp_ilr_open, 3418 .read = seq_read, 3419 .llseek = seq_lseek, 3420 .release = single_release, 3421 .write = edp_ilr_write 3422 }; 3423 3424 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3425 { 3426 int i; 3427 struct dentry *dir = connector->base.debugfs_entry; 3428 3429 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3430 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3431 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3432 debugfs_create_file(dp_debugfs_entries[i].name, 3433 0644, dir, connector, 3434 dp_debugfs_entries[i].fops); 3435 } 3436 } 3437 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3438 debugfs_create_file("replay_capability", 0444, dir, connector, 3439 &replay_capability_fops); 3440 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops); 3441 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3442 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3443 debugfs_create_file_unsafe("psr_residency", 0444, dir, 3444 connector, &psr_residency_fops); 3445 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3446 ¤t_backlight_fops); 3447 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3448 &target_backlight_fops); 3449 debugfs_create_file("ilr_setting", 0644, dir, connector, 3450 &edp_ilr_debugfs_fops); 3451 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3452 &allow_edp_hotplug_detection_fops); 3453 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, 3454 &disallow_edp_enter_psr_fops); 3455 } 3456 3457 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3458 debugfs_create_file(connector_debugfs_entries[i].name, 3459 0644, dir, connector, 3460 connector_debugfs_entries[i].fops); 3461 } 3462 3463 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3464 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3465 debugfs_create_file(hdmi_debugfs_entries[i].name, 3466 0644, dir, connector, 3467 hdmi_debugfs_entries[i].fops); 3468 } 3469 } 3470 } 3471 3472 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3473 /* 3474 * Set crc window coordinate x start 3475 */ 3476 static int crc_win_x_start_set(void *data, u64 val) 3477 { 3478 struct drm_crtc *crtc = data; 3479 struct drm_device *drm_dev = crtc->dev; 3480 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3481 3482 spin_lock_irq(&drm_dev->event_lock); 3483 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3484 acrtc->dm_irq_params.window_param.update_win = false; 3485 spin_unlock_irq(&drm_dev->event_lock); 3486 3487 return 0; 3488 } 3489 3490 /* 3491 * Get crc window coordinate x start 3492 */ 3493 static int crc_win_x_start_get(void *data, u64 *val) 3494 { 3495 struct drm_crtc *crtc = data; 3496 struct drm_device *drm_dev = crtc->dev; 3497 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3498 3499 spin_lock_irq(&drm_dev->event_lock); 3500 *val = acrtc->dm_irq_params.window_param.x_start; 3501 spin_unlock_irq(&drm_dev->event_lock); 3502 3503 return 0; 3504 } 3505 3506 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3507 crc_win_x_start_set, "%llu\n"); 3508 3509 3510 /* 3511 * Set crc window coordinate y start 3512 */ 3513 static int crc_win_y_start_set(void *data, u64 val) 3514 { 3515 struct drm_crtc *crtc = data; 3516 struct drm_device *drm_dev = crtc->dev; 3517 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3518 3519 spin_lock_irq(&drm_dev->event_lock); 3520 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3521 acrtc->dm_irq_params.window_param.update_win = false; 3522 spin_unlock_irq(&drm_dev->event_lock); 3523 3524 return 0; 3525 } 3526 3527 /* 3528 * Get crc window coordinate y start 3529 */ 3530 static int crc_win_y_start_get(void *data, u64 *val) 3531 { 3532 struct drm_crtc *crtc = data; 3533 struct drm_device *drm_dev = crtc->dev; 3534 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3535 3536 spin_lock_irq(&drm_dev->event_lock); 3537 *val = acrtc->dm_irq_params.window_param.y_start; 3538 spin_unlock_irq(&drm_dev->event_lock); 3539 3540 return 0; 3541 } 3542 3543 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3544 crc_win_y_start_set, "%llu\n"); 3545 3546 /* 3547 * Set crc window coordinate x end 3548 */ 3549 static int crc_win_x_end_set(void *data, u64 val) 3550 { 3551 struct drm_crtc *crtc = data; 3552 struct drm_device *drm_dev = crtc->dev; 3553 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3554 3555 spin_lock_irq(&drm_dev->event_lock); 3556 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3557 acrtc->dm_irq_params.window_param.update_win = false; 3558 spin_unlock_irq(&drm_dev->event_lock); 3559 3560 return 0; 3561 } 3562 3563 /* 3564 * Get crc window coordinate x end 3565 */ 3566 static int crc_win_x_end_get(void *data, u64 *val) 3567 { 3568 struct drm_crtc *crtc = data; 3569 struct drm_device *drm_dev = crtc->dev; 3570 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3571 3572 spin_lock_irq(&drm_dev->event_lock); 3573 *val = acrtc->dm_irq_params.window_param.x_end; 3574 spin_unlock_irq(&drm_dev->event_lock); 3575 3576 return 0; 3577 } 3578 3579 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3580 crc_win_x_end_set, "%llu\n"); 3581 3582 /* 3583 * Set crc window coordinate y end 3584 */ 3585 static int crc_win_y_end_set(void *data, u64 val) 3586 { 3587 struct drm_crtc *crtc = data; 3588 struct drm_device *drm_dev = crtc->dev; 3589 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3590 3591 spin_lock_irq(&drm_dev->event_lock); 3592 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3593 acrtc->dm_irq_params.window_param.update_win = false; 3594 spin_unlock_irq(&drm_dev->event_lock); 3595 3596 return 0; 3597 } 3598 3599 /* 3600 * Get crc window coordinate y end 3601 */ 3602 static int crc_win_y_end_get(void *data, u64 *val) 3603 { 3604 struct drm_crtc *crtc = data; 3605 struct drm_device *drm_dev = crtc->dev; 3606 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3607 3608 spin_lock_irq(&drm_dev->event_lock); 3609 *val = acrtc->dm_irq_params.window_param.y_end; 3610 spin_unlock_irq(&drm_dev->event_lock); 3611 3612 return 0; 3613 } 3614 3615 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3616 crc_win_y_end_set, "%llu\n"); 3617 /* 3618 * Trigger to commit crc window 3619 */ 3620 static int crc_win_update_set(void *data, u64 val) 3621 { 3622 struct drm_crtc *crtc = data; 3623 struct amdgpu_crtc *acrtc; 3624 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3625 3626 if (val) { 3627 acrtc = to_amdgpu_crtc(crtc); 3628 mutex_lock(&adev->dm.dc_lock); 3629 /* PSR may write to OTG CRC window control register, 3630 * so close it before starting secure_display. 3631 */ 3632 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3633 3634 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3635 3636 acrtc->dm_irq_params.window_param.activated = true; 3637 acrtc->dm_irq_params.window_param.update_win = true; 3638 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3639 3640 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3641 mutex_unlock(&adev->dm.dc_lock); 3642 } 3643 3644 return 0; 3645 } 3646 3647 /* 3648 * Get crc window update flag 3649 */ 3650 static int crc_win_update_get(void *data, u64 *val) 3651 { 3652 *val = 0; 3653 return 0; 3654 } 3655 3656 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3657 crc_win_update_set, "%llu\n"); 3658 #endif 3659 void crtc_debugfs_init(struct drm_crtc *crtc) 3660 { 3661 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3662 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3663 3664 if (!dir) 3665 return; 3666 3667 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3668 &crc_win_x_start_fops); 3669 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3670 &crc_win_y_start_fops); 3671 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3672 &crc_win_x_end_fops); 3673 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3674 &crc_win_y_end_fops); 3675 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3676 &crc_win_update_fops); 3677 dput(dir); 3678 #endif 3679 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3680 crtc, &amdgpu_current_bpc_fops); 3681 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 3682 crtc, &amdgpu_current_colorspace_fops); 3683 } 3684 3685 /* 3686 * Writes DTN log state to the user supplied buffer. 3687 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3688 */ 3689 static ssize_t dtn_log_read( 3690 struct file *f, 3691 char __user *buf, 3692 size_t size, 3693 loff_t *pos) 3694 { 3695 struct amdgpu_device *adev = file_inode(f)->i_private; 3696 struct dc *dc = adev->dm.dc; 3697 struct dc_log_buffer_ctx log_ctx = { 0 }; 3698 ssize_t result = 0; 3699 3700 if (!buf || !size) 3701 return -EINVAL; 3702 3703 if (!dc->hwss.log_hw_state) 3704 return 0; 3705 3706 dc->hwss.log_hw_state(dc, &log_ctx); 3707 3708 if (*pos < log_ctx.pos) { 3709 size_t to_copy = log_ctx.pos - *pos; 3710 3711 to_copy = min(to_copy, size); 3712 3713 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3714 *pos += to_copy; 3715 result = to_copy; 3716 } 3717 } 3718 3719 kfree(log_ctx.buf); 3720 3721 return result; 3722 } 3723 3724 /* 3725 * Writes DTN log state to dmesg when triggered via a write. 3726 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3727 */ 3728 static ssize_t dtn_log_write( 3729 struct file *f, 3730 const char __user *buf, 3731 size_t size, 3732 loff_t *pos) 3733 { 3734 struct amdgpu_device *adev = file_inode(f)->i_private; 3735 struct dc *dc = adev->dm.dc; 3736 3737 /* Write triggers log output via dmesg. */ 3738 if (size == 0) 3739 return 0; 3740 3741 if (dc->hwss.log_hw_state) 3742 dc->hwss.log_hw_state(dc, NULL); 3743 3744 return size; 3745 } 3746 3747 static int mst_topo_show(struct seq_file *m, void *unused) 3748 { 3749 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3750 struct drm_device *dev = adev_to_drm(adev); 3751 struct drm_connector *connector; 3752 struct drm_connector_list_iter conn_iter; 3753 struct amdgpu_dm_connector *aconnector; 3754 3755 drm_connector_list_iter_begin(dev, &conn_iter); 3756 drm_for_each_connector_iter(connector, &conn_iter) { 3757 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3758 continue; 3759 3760 aconnector = to_amdgpu_dm_connector(connector); 3761 3762 /* Ensure we're only dumping the topology of a root mst node */ 3763 if (!aconnector->mst_mgr.mst_state) 3764 continue; 3765 3766 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3767 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3768 } 3769 drm_connector_list_iter_end(&conn_iter); 3770 3771 return 0; 3772 } 3773 3774 /* 3775 * Sets trigger hpd for MST topologies. 3776 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3777 * All topologies will be disconnected if val of 0 is set . 3778 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3779 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3780 */ 3781 static int trigger_hpd_mst_set(void *data, u64 val) 3782 { 3783 struct amdgpu_device *adev = data; 3784 struct drm_device *dev = adev_to_drm(adev); 3785 struct drm_connector_list_iter iter; 3786 struct amdgpu_dm_connector *aconnector; 3787 struct drm_connector *connector; 3788 struct dc_link *link = NULL; 3789 int ret; 3790 3791 if (val == 1) { 3792 drm_connector_list_iter_begin(dev, &iter); 3793 drm_for_each_connector_iter(connector, &iter) { 3794 aconnector = to_amdgpu_dm_connector(connector); 3795 if (aconnector->dc_link->type == dc_connection_mst_branch && 3796 aconnector->mst_mgr.aux) { 3797 mutex_lock(&adev->dm.dc_lock); 3798 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3799 mutex_unlock(&adev->dm.dc_lock); 3800 3801 if (!ret) 3802 DRM_ERROR("DM_MST: Failed to detect dc link!"); 3803 3804 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3805 if (ret < 0) 3806 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 3807 } 3808 } 3809 } else if (val == 0) { 3810 drm_connector_list_iter_begin(dev, &iter); 3811 drm_for_each_connector_iter(connector, &iter) { 3812 aconnector = to_amdgpu_dm_connector(connector); 3813 if (!aconnector->dc_link) 3814 continue; 3815 3816 if (!aconnector->mst_root) 3817 continue; 3818 3819 link = aconnector->dc_link; 3820 dc_link_dp_receiver_power_ctrl(link, false); 3821 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3822 link->mst_stream_alloc_table.stream_count = 0; 3823 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3824 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3825 } 3826 } else { 3827 return 0; 3828 } 3829 drm_kms_helper_hotplug_event(dev); 3830 3831 return 0; 3832 } 3833 3834 /* 3835 * The interface doesn't need get function, so it will return the 3836 * value of zero 3837 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3838 */ 3839 static int trigger_hpd_mst_get(void *data, u64 *val) 3840 { 3841 *val = 0; 3842 return 0; 3843 } 3844 3845 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3846 trigger_hpd_mst_set, "%llu\n"); 3847 3848 3849 /* 3850 * Sets the force_timing_sync debug option from the given string. 3851 * All connected displays will be force synchronized immediately. 3852 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3853 */ 3854 static int force_timing_sync_set(void *data, u64 val) 3855 { 3856 struct amdgpu_device *adev = data; 3857 3858 adev->dm.force_timing_sync = (bool)val; 3859 3860 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3861 3862 return 0; 3863 } 3864 3865 /* 3866 * Gets the force_timing_sync debug option value into the given buffer. 3867 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3868 */ 3869 static int force_timing_sync_get(void *data, u64 *val) 3870 { 3871 struct amdgpu_device *adev = data; 3872 3873 *val = adev->dm.force_timing_sync; 3874 3875 return 0; 3876 } 3877 3878 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3879 force_timing_sync_set, "%llu\n"); 3880 3881 3882 /* 3883 * Disables all HPD and HPD RX interrupt handling in the 3884 * driver when set to 1. Default is 0. 3885 */ 3886 static int disable_hpd_set(void *data, u64 val) 3887 { 3888 struct amdgpu_device *adev = data; 3889 3890 adev->dm.disable_hpd_irq = (bool)val; 3891 3892 return 0; 3893 } 3894 3895 3896 /* 3897 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3898 * 0 otherwise. 3899 */ 3900 static int disable_hpd_get(void *data, u64 *val) 3901 { 3902 struct amdgpu_device *adev = data; 3903 3904 *val = adev->dm.disable_hpd_irq; 3905 3906 return 0; 3907 } 3908 3909 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3910 disable_hpd_set, "%llu\n"); 3911 3912 /* 3913 * Prints hardware capabilities. These are used for IGT testing. 3914 */ 3915 static int capabilities_show(struct seq_file *m, void *unused) 3916 { 3917 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3918 struct dc *dc = adev->dm.dc; 3919 bool mall_supported = dc->caps.mall_size_total; 3920 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us; 3921 unsigned int mall_in_use = false; 3922 unsigned int subvp_in_use = false; 3923 3924 struct hubbub *hubbub = dc->res_pool->hubbub; 3925 3926 if (hubbub->funcs->get_mall_en) 3927 hubbub->funcs->get_mall_en(hubbub, &mall_in_use); 3928 3929 if (dc->cap_funcs.get_subvp_en) 3930 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state); 3931 3932 seq_printf(m, "mall supported: %s, enabled: %s\n", 3933 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no"); 3934 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n", 3935 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no"); 3936 3937 return 0; 3938 } 3939 3940 DEFINE_SHOW_ATTRIBUTE(capabilities); 3941 3942 /* 3943 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3944 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3945 */ 3946 static int dp_force_sst_set(void *data, u64 val) 3947 { 3948 struct amdgpu_device *adev = data; 3949 3950 adev->dm.dc->debug.set_mst_en_for_sst = val; 3951 3952 return 0; 3953 } 3954 3955 static int dp_force_sst_get(void *data, u64 *val) 3956 { 3957 struct amdgpu_device *adev = data; 3958 3959 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3960 3961 return 0; 3962 } 3963 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3964 dp_force_sst_set, "%llu\n"); 3965 3966 /* 3967 * Force DP2 sequence without VESA certified cable. 3968 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3969 */ 3970 static int dp_ignore_cable_id_set(void *data, u64 val) 3971 { 3972 struct amdgpu_device *adev = data; 3973 3974 adev->dm.dc->debug.ignore_cable_id = val; 3975 3976 return 0; 3977 } 3978 3979 static int dp_ignore_cable_id_get(void *data, u64 *val) 3980 { 3981 struct amdgpu_device *adev = data; 3982 3983 *val = adev->dm.dc->debug.ignore_cable_id; 3984 3985 return 0; 3986 } 3987 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3988 dp_ignore_cable_id_set, "%llu\n"); 3989 3990 /* 3991 * Sets the DC visual confirm debug option from the given string. 3992 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3993 */ 3994 static int visual_confirm_set(void *data, u64 val) 3995 { 3996 struct amdgpu_device *adev = data; 3997 3998 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3999 4000 return 0; 4001 } 4002 4003 /* 4004 * Reads the DC visual confirm debug option value into the given buffer. 4005 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 4006 */ 4007 static int visual_confirm_get(void *data, u64 *val) 4008 { 4009 struct amdgpu_device *adev = data; 4010 4011 *val = adev->dm.dc->debug.visual_confirm; 4012 4013 return 0; 4014 } 4015 4016 DEFINE_SHOW_ATTRIBUTE(mst_topo); 4017 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 4018 visual_confirm_set, "%llu\n"); 4019 4020 4021 /* 4022 * Sets the DC skip_detection_link_training debug option from the given string. 4023 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 4024 */ 4025 static int skip_detection_link_training_set(void *data, u64 val) 4026 { 4027 struct amdgpu_device *adev = data; 4028 4029 if (val == 0) 4030 adev->dm.dc->debug.skip_detection_link_training = false; 4031 else 4032 adev->dm.dc->debug.skip_detection_link_training = true; 4033 4034 return 0; 4035 } 4036 4037 /* 4038 * Reads the DC skip_detection_link_training debug option value into the given buffer. 4039 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 4040 */ 4041 static int skip_detection_link_training_get(void *data, u64 *val) 4042 { 4043 struct amdgpu_device *adev = data; 4044 4045 *val = adev->dm.dc->debug.skip_detection_link_training; 4046 4047 return 0; 4048 } 4049 4050 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 4051 skip_detection_link_training_get, 4052 skip_detection_link_training_set, "%llu\n"); 4053 4054 /* 4055 * Dumps the DCC_EN bit for each pipe. 4056 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 4057 */ 4058 static ssize_t dcc_en_bits_read( 4059 struct file *f, 4060 char __user *buf, 4061 size_t size, 4062 loff_t *pos) 4063 { 4064 struct amdgpu_device *adev = file_inode(f)->i_private; 4065 struct dc *dc = adev->dm.dc; 4066 char *rd_buf = NULL; 4067 const uint32_t rd_buf_size = 32; 4068 uint32_t result = 0; 4069 int offset = 0; 4070 int num_pipes = dc->res_pool->pipe_count; 4071 int *dcc_en_bits; 4072 int i, r; 4073 4074 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 4075 if (!dcc_en_bits) 4076 return -ENOMEM; 4077 4078 if (!dc->hwss.get_dcc_en_bits) { 4079 kfree(dcc_en_bits); 4080 return 0; 4081 } 4082 4083 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 4084 4085 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 4086 if (!rd_buf) { 4087 kfree(dcc_en_bits); 4088 return -ENOMEM; 4089 } 4090 4091 for (i = 0; i < num_pipes; i++) 4092 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 4093 "%d ", dcc_en_bits[i]); 4094 rd_buf[strlen(rd_buf)] = '\n'; 4095 4096 kfree(dcc_en_bits); 4097 4098 while (size) { 4099 if (*pos >= rd_buf_size) 4100 break; 4101 r = put_user(*(rd_buf + result), buf); 4102 if (r) { 4103 kfree(rd_buf); 4104 return r; /* r = -EFAULT */ 4105 } 4106 buf += 1; 4107 size -= 1; 4108 *pos += 1; 4109 result += 1; 4110 } 4111 4112 kfree(rd_buf); 4113 return result; 4114 } 4115 4116 void dtn_debugfs_init(struct amdgpu_device *adev) 4117 { 4118 static const struct file_operations dtn_log_fops = { 4119 .owner = THIS_MODULE, 4120 .read = dtn_log_read, 4121 .write = dtn_log_write, 4122 .llseek = default_llseek 4123 }; 4124 static const struct file_operations dcc_en_bits_fops = { 4125 .owner = THIS_MODULE, 4126 .read = dcc_en_bits_read, 4127 .llseek = default_llseek 4128 }; 4129 4130 struct drm_minor *minor = adev_to_drm(adev)->primary; 4131 struct dentry *root = minor->debugfs_root; 4132 4133 debugfs_create_file("amdgpu_mst_topology", 0444, root, 4134 adev, &mst_topo_fops); 4135 debugfs_create_file("amdgpu_dm_capabilities", 0444, root, 4136 adev, &capabilities_fops); 4137 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 4138 &dtn_log_fops); 4139 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 4140 &dp_set_mst_en_for_sst_ops); 4141 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 4142 &dp_ignore_cable_id_ops); 4143 4144 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 4145 &visual_confirm_fops); 4146 4147 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 4148 &skip_detection_link_training_fops); 4149 4150 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 4151 adev, &dmub_tracebuffer_fops); 4152 4153 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 4154 adev, &dmub_fw_state_fops); 4155 4156 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 4157 adev, &force_timing_sync_ops); 4158 4159 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root, 4160 adev, &dmub_trace_mask_fops); 4161 4162 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 4163 adev, &dmcub_trace_event_state_fops); 4164 4165 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 4166 adev, &trigger_hpd_mst_ops); 4167 4168 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 4169 &dcc_en_bits_fops); 4170 4171 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 4172 &disable_hpd_ops); 4173 4174 if (adev->dm.dc->caps.ips_support) 4175 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, 4176 &ips_status_fops); 4177 } 4178