1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "dc_link.h" 39 #include "link_hwss.h" 40 #include "dc/dc_dmub_srv.h" 41 42 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 43 #include "amdgpu_dm_psr.h" 44 #endif 45 46 struct dmub_debugfs_trace_header { 47 uint32_t entry_count; 48 uint32_t reserved[3]; 49 }; 50 51 struct dmub_debugfs_trace_entry { 52 uint32_t trace_code; 53 uint32_t tick_count; 54 uint32_t param0; 55 uint32_t param1; 56 }; 57 58 static const char *const mst_progress_status[] = { 59 "probe", 60 "remote_edid", 61 "allocate_new_payload", 62 "clear_allocated_payload", 63 }; 64 65 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 66 * 67 * Function takes in attributes passed to debugfs write entry 68 * and writes into param array. 69 * The user passes max_param_num to identify maximum number of 70 * parameters that could be parsed. 71 * 72 */ 73 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 74 long *param, const char __user *buf, 75 int max_param_num, 76 uint8_t *param_nums) 77 { 78 char *wr_buf_ptr = NULL; 79 uint32_t wr_buf_count = 0; 80 int r; 81 char *sub_str = NULL; 82 const char delimiter[3] = {' ', '\n', '\0'}; 83 uint8_t param_index = 0; 84 85 *param_nums = 0; 86 87 wr_buf_ptr = wr_buf; 88 89 /* r is bytes not be copied */ 90 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 91 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 92 return -EFAULT; 93 } 94 95 /* check number of parameters. isspace could not differ space and \n */ 96 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 97 /* skip space*/ 98 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 99 wr_buf_ptr++; 100 wr_buf_count++; 101 } 102 103 if (wr_buf_count == wr_buf_size) 104 break; 105 106 /* skip non-space*/ 107 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 108 wr_buf_ptr++; 109 wr_buf_count++; 110 } 111 112 (*param_nums)++; 113 114 if (wr_buf_count == wr_buf_size) 115 break; 116 } 117 118 if (*param_nums > max_param_num) 119 *param_nums = max_param_num; 120 121 wr_buf_ptr = wr_buf; /* reset buf pointer */ 122 wr_buf_count = 0; /* number of char already checked */ 123 124 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 125 wr_buf_ptr++; 126 wr_buf_count++; 127 } 128 129 while (param_index < *param_nums) { 130 /* after strsep, wr_buf_ptr will be moved to after space */ 131 sub_str = strsep(&wr_buf_ptr, delimiter); 132 133 r = kstrtol(sub_str, 16, &(param[param_index])); 134 135 if (r) 136 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 137 138 param_index++; 139 } 140 141 return 0; 142 } 143 144 /* function description 145 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 146 * 147 * valid lane count value: 1, 2, 4 148 * valid link rate value: 149 * 06h = 1.62Gbps per lane 150 * 0Ah = 2.7Gbps per lane 151 * 0Ch = 3.24Gbps per lane 152 * 14h = 5.4Gbps per lane 153 * 1Eh = 8.1Gbps per lane 154 * 155 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 156 * 157 * --- to get dp configuration 158 * 159 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 160 * 161 * It will list current, verified, reported, preferred dp configuration. 162 * current -- for current video mode 163 * verified --- maximum configuration which pass link training 164 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 165 * preferred --- user force settings 166 * 167 * --- set (or force) dp configuration 168 * 169 * echo <lane_count> <link_rate> > link_settings 170 * 171 * for example, to force to 2 lane, 2.7GHz, 172 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 173 * 174 * spread_spectrum could not be changed dynamically. 175 * 176 * in case invalid lane count, link rate are force, no hw programming will be 177 * done. please check link settings after force operation to see if HW get 178 * programming. 179 * 180 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 181 * 182 * check current and preferred settings. 183 * 184 */ 185 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 186 size_t size, loff_t *pos) 187 { 188 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 189 struct dc_link *link = connector->dc_link; 190 char *rd_buf = NULL; 191 char *rd_buf_ptr = NULL; 192 const uint32_t rd_buf_size = 100; 193 uint32_t result = 0; 194 uint8_t str_len = 0; 195 int r; 196 197 if (*pos & 3 || size & 3) 198 return -EINVAL; 199 200 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 201 if (!rd_buf) 202 return 0; 203 204 rd_buf_ptr = rd_buf; 205 206 str_len = strlen("Current: %d 0x%x %d "); 207 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 208 link->cur_link_settings.lane_count, 209 link->cur_link_settings.link_rate, 210 link->cur_link_settings.link_spread); 211 rd_buf_ptr += str_len; 212 213 str_len = strlen("Verified: %d 0x%x %d "); 214 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 215 link->verified_link_cap.lane_count, 216 link->verified_link_cap.link_rate, 217 link->verified_link_cap.link_spread); 218 rd_buf_ptr += str_len; 219 220 str_len = strlen("Reported: %d 0x%x %d "); 221 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 222 link->reported_link_cap.lane_count, 223 link->reported_link_cap.link_rate, 224 link->reported_link_cap.link_spread); 225 rd_buf_ptr += str_len; 226 227 str_len = strlen("Preferred: %d 0x%x %d "); 228 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 229 link->preferred_link_setting.lane_count, 230 link->preferred_link_setting.link_rate, 231 link->preferred_link_setting.link_spread); 232 233 while (size) { 234 if (*pos >= rd_buf_size) 235 break; 236 237 r = put_user(*(rd_buf + result), buf); 238 if (r) { 239 kfree(rd_buf); 240 return r; /* r = -EFAULT */ 241 } 242 243 buf += 1; 244 size -= 1; 245 *pos += 1; 246 result += 1; 247 } 248 249 kfree(rd_buf); 250 return result; 251 } 252 253 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 254 size_t size, loff_t *pos) 255 { 256 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 257 struct dc_link *link = connector->dc_link; 258 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 259 struct dc *dc = (struct dc *)link->dc; 260 struct dc_link_settings prefer_link_settings; 261 char *wr_buf = NULL; 262 const uint32_t wr_buf_size = 40; 263 /* 0: lane_count; 1: link_rate */ 264 int max_param_num = 2; 265 uint8_t param_nums = 0; 266 long param[2]; 267 bool valid_input = true; 268 269 if (size == 0) 270 return -EINVAL; 271 272 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 273 if (!wr_buf) 274 return -ENOSPC; 275 276 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 277 (long *)param, buf, 278 max_param_num, 279 ¶m_nums)) { 280 kfree(wr_buf); 281 return -EINVAL; 282 } 283 284 if (param_nums <= 0) { 285 kfree(wr_buf); 286 DRM_DEBUG_DRIVER("user data not be read\n"); 287 return -EINVAL; 288 } 289 290 switch (param[0]) { 291 case LANE_COUNT_ONE: 292 case LANE_COUNT_TWO: 293 case LANE_COUNT_FOUR: 294 break; 295 default: 296 valid_input = false; 297 break; 298 } 299 300 switch (param[1]) { 301 case LINK_RATE_LOW: 302 case LINK_RATE_HIGH: 303 case LINK_RATE_RBR2: 304 case LINK_RATE_HIGH2: 305 case LINK_RATE_HIGH3: 306 case LINK_RATE_UHBR10: 307 case LINK_RATE_UHBR13_5: 308 case LINK_RATE_UHBR20: 309 break; 310 default: 311 valid_input = false; 312 break; 313 } 314 315 if (!valid_input) { 316 kfree(wr_buf); 317 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 318 mutex_lock(&adev->dm.dc_lock); 319 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 320 mutex_unlock(&adev->dm.dc_lock); 321 return size; 322 } 323 324 /* save user force lane_count, link_rate to preferred settings 325 * spread spectrum will not be changed 326 */ 327 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 328 prefer_link_settings.use_link_rate_set = false; 329 prefer_link_settings.lane_count = param[0]; 330 prefer_link_settings.link_rate = param[1]; 331 332 mutex_lock(&adev->dm.dc_lock); 333 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 334 mutex_unlock(&adev->dm.dc_lock); 335 336 kfree(wr_buf); 337 return size; 338 } 339 340 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 341 * post-cursor2 (defined by VESA DP specification) 342 * 343 * valid values 344 * voltage swing: 0,1,2,3 345 * pre-emphasis : 0,1,2,3 346 * post cursor2 : 0,1,2,3 347 * 348 * 349 * how to use this debugfs 350 * 351 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 352 * 353 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 354 * 355 * To figure out which DP-x is the display for DP to be check, 356 * cd DP-x 357 * ls -ll 358 * There should be debugfs file, like link_settings, phy_settings. 359 * cat link_settings 360 * from lane_count, link_rate to figure which DP-x is for display to be worked 361 * on 362 * 363 * To get current DP PHY settings, 364 * cat phy_settings 365 * 366 * To change DP PHY settings, 367 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 368 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 369 * 0, 370 * echo 2 3 0 > phy_settings 371 * 372 * To check if change be applied, get current phy settings by 373 * cat phy_settings 374 * 375 * In case invalid values are set by user, like 376 * echo 1 4 0 > phy_settings 377 * 378 * HW will NOT be programmed by these settings. 379 * cat phy_settings will show the previous valid settings. 380 */ 381 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 382 size_t size, loff_t *pos) 383 { 384 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 385 struct dc_link *link = connector->dc_link; 386 char *rd_buf = NULL; 387 const uint32_t rd_buf_size = 20; 388 uint32_t result = 0; 389 int r; 390 391 if (*pos & 3 || size & 3) 392 return -EINVAL; 393 394 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 395 if (!rd_buf) 396 return -EINVAL; 397 398 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 399 link->cur_lane_setting[0].VOLTAGE_SWING, 400 link->cur_lane_setting[0].PRE_EMPHASIS, 401 link->cur_lane_setting[0].POST_CURSOR2); 402 403 while (size) { 404 if (*pos >= rd_buf_size) 405 break; 406 407 r = put_user((*(rd_buf + result)), buf); 408 if (r) { 409 kfree(rd_buf); 410 return r; /* r = -EFAULT */ 411 } 412 413 buf += 1; 414 size -= 1; 415 *pos += 1; 416 result += 1; 417 } 418 419 kfree(rd_buf); 420 return result; 421 } 422 423 static int dp_lttpr_status_show(struct seq_file *m, void *d) 424 { 425 char *data; 426 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 427 struct dc_link *link = connector->dc_link; 428 uint32_t read_size = 1; 429 uint8_t repeater_count = 0; 430 431 data = kzalloc(read_size, GFP_KERNEL); 432 if (!data) 433 return 0; 434 435 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 436 437 switch ((uint8_t)*data) { 438 case 0x80: 439 repeater_count = 1; 440 break; 441 case 0x40: 442 repeater_count = 2; 443 break; 444 case 0x20: 445 repeater_count = 3; 446 break; 447 case 0x10: 448 repeater_count = 4; 449 break; 450 case 0x8: 451 repeater_count = 5; 452 break; 453 case 0x4: 454 repeater_count = 6; 455 break; 456 case 0x2: 457 repeater_count = 7; 458 break; 459 case 0x1: 460 repeater_count = 8; 461 break; 462 case 0x0: 463 repeater_count = 0; 464 break; 465 default: 466 repeater_count = (uint8_t)*data; 467 break; 468 } 469 470 seq_printf(m, "phy repeater count: %d\n", repeater_count); 471 472 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 473 474 if ((uint8_t)*data == 0x55) 475 seq_printf(m, "phy repeater mode: transparent\n"); 476 else if ((uint8_t)*data == 0xAA) 477 seq_printf(m, "phy repeater mode: non-transparent\n"); 478 else if ((uint8_t)*data == 0x00) 479 seq_printf(m, "phy repeater mode: non lttpr\n"); 480 else 481 seq_printf(m, "phy repeater mode: read error\n"); 482 483 kfree(data); 484 return 0; 485 } 486 487 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 488 size_t size, loff_t *pos) 489 { 490 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 491 struct dc_link *link = connector->dc_link; 492 struct dc *dc = (struct dc *)link->dc; 493 char *wr_buf = NULL; 494 uint32_t wr_buf_size = 40; 495 long param[3]; 496 bool use_prefer_link_setting; 497 struct link_training_settings link_lane_settings; 498 int max_param_num = 3; 499 uint8_t param_nums = 0; 500 int r = 0; 501 502 503 if (size == 0) 504 return -EINVAL; 505 506 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 507 if (!wr_buf) 508 return -ENOSPC; 509 510 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 511 (long *)param, buf, 512 max_param_num, 513 ¶m_nums)) { 514 kfree(wr_buf); 515 return -EINVAL; 516 } 517 518 if (param_nums <= 0) { 519 kfree(wr_buf); 520 DRM_DEBUG_DRIVER("user data not be read\n"); 521 return -EINVAL; 522 } 523 524 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 525 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 526 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 527 kfree(wr_buf); 528 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 529 return size; 530 } 531 532 /* get link settings: lane count, link rate */ 533 use_prefer_link_setting = 534 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 535 (link->test_pattern_enabled)); 536 537 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 538 539 if (use_prefer_link_setting) { 540 link_lane_settings.link_settings.lane_count = 541 link->preferred_link_setting.lane_count; 542 link_lane_settings.link_settings.link_rate = 543 link->preferred_link_setting.link_rate; 544 link_lane_settings.link_settings.link_spread = 545 link->preferred_link_setting.link_spread; 546 } else { 547 link_lane_settings.link_settings.lane_count = 548 link->cur_link_settings.lane_count; 549 link_lane_settings.link_settings.link_rate = 550 link->cur_link_settings.link_rate; 551 link_lane_settings.link_settings.link_spread = 552 link->cur_link_settings.link_spread; 553 } 554 555 /* apply phy settings from user */ 556 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 557 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 558 (enum dc_voltage_swing) (param[0]); 559 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 560 (enum dc_pre_emphasis) (param[1]); 561 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 562 (enum dc_post_cursor2) (param[2]); 563 } 564 565 /* program ASIC registers and DPCD registers */ 566 dc_link_set_drive_settings(dc, &link_lane_settings, link); 567 568 kfree(wr_buf); 569 return size; 570 } 571 572 /* function description 573 * 574 * set PHY layer or Link layer test pattern 575 * PHY test pattern is used for PHY SI check. 576 * Link layer test will not affect PHY SI. 577 * 578 * Reset Test Pattern: 579 * 0 = DP_TEST_PATTERN_VIDEO_MODE 580 * 581 * PHY test pattern supported: 582 * 1 = DP_TEST_PATTERN_D102 583 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 584 * 3 = DP_TEST_PATTERN_PRBS7 585 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 586 * 5 = DP_TEST_PATTERN_CP2520_1 587 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 588 * 7 = DP_TEST_PATTERN_CP2520_3 589 * 590 * DP PHY Link Training Patterns 591 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 592 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 593 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 594 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 595 * 596 * DP Link Layer Test pattern 597 * c = DP_TEST_PATTERN_COLOR_SQUARES 598 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 599 * e = DP_TEST_PATTERN_VERTICAL_BARS 600 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 601 * 10= DP_TEST_PATTERN_COLOR_RAMP 602 * 603 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 604 * 605 * --- set test pattern 606 * echo <test pattern #> > test_pattern 607 * 608 * If test pattern # is not supported, NO HW programming will be done. 609 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 610 * for the user pattern. input 10 bytes data are separated by space 611 * 612 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 613 * 614 * --- reset test pattern 615 * echo 0 > test_pattern 616 * 617 * --- HPD detection is disabled when set PHY test pattern 618 * 619 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 620 * is disable. User could unplug DP display from DP connected and plug scope to 621 * check test pattern PHY SI. 622 * If there is need unplug scope and plug DP display back, do steps below: 623 * echo 0 > phy_test_pattern 624 * unplug scope 625 * plug DP display. 626 * 627 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 628 * driver could detect "unplug scope" and "plug DP display" 629 */ 630 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 631 size_t size, loff_t *pos) 632 { 633 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 634 struct dc_link *link = connector->dc_link; 635 char *wr_buf = NULL; 636 uint32_t wr_buf_size = 100; 637 long param[11] = {0x0}; 638 int max_param_num = 11; 639 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 640 bool disable_hpd = false; 641 bool valid_test_pattern = false; 642 uint8_t param_nums = 0; 643 /* init with default 80bit custom pattern */ 644 uint8_t custom_pattern[10] = { 645 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 646 0x1f, 0x7c, 0xf0, 0xc1, 0x07 647 }; 648 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 649 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 650 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 651 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 652 struct link_training_settings link_training_settings; 653 int i; 654 655 if (size == 0) 656 return -EINVAL; 657 658 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 659 if (!wr_buf) 660 return -ENOSPC; 661 662 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 663 (long *)param, buf, 664 max_param_num, 665 ¶m_nums)) { 666 kfree(wr_buf); 667 return -EINVAL; 668 } 669 670 if (param_nums <= 0) { 671 kfree(wr_buf); 672 DRM_DEBUG_DRIVER("user data not be read\n"); 673 return -EINVAL; 674 } 675 676 677 test_pattern = param[0]; 678 679 switch (test_pattern) { 680 case DP_TEST_PATTERN_VIDEO_MODE: 681 case DP_TEST_PATTERN_COLOR_SQUARES: 682 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 683 case DP_TEST_PATTERN_VERTICAL_BARS: 684 case DP_TEST_PATTERN_HORIZONTAL_BARS: 685 case DP_TEST_PATTERN_COLOR_RAMP: 686 valid_test_pattern = true; 687 break; 688 689 case DP_TEST_PATTERN_D102: 690 case DP_TEST_PATTERN_SYMBOL_ERROR: 691 case DP_TEST_PATTERN_PRBS7: 692 case DP_TEST_PATTERN_80BIT_CUSTOM: 693 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 694 case DP_TEST_PATTERN_TRAINING_PATTERN4: 695 disable_hpd = true; 696 valid_test_pattern = true; 697 break; 698 699 default: 700 valid_test_pattern = false; 701 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 702 break; 703 } 704 705 if (!valid_test_pattern) { 706 kfree(wr_buf); 707 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 708 return size; 709 } 710 711 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 712 for (i = 0; i < 10; i++) { 713 if ((uint8_t) param[i + 1] != 0x0) 714 break; 715 } 716 717 if (i < 10) { 718 /* not use default value */ 719 for (i = 0; i < 10; i++) 720 custom_pattern[i] = (uint8_t) param[i + 1]; 721 } 722 } 723 724 /* Usage: set DP physical test pattern using debugfs with normal DP 725 * panel. Then plug out DP panel and connect a scope to measure 726 * For normal video mode and test pattern generated from CRCT, 727 * they are visibile to user. So do not disable HPD. 728 * Video Mode is also set to clear the test pattern, so enable HPD 729 * because it might have been disabled after a test pattern was set. 730 * AUX depends on HPD * sequence dependent, do not move! 731 */ 732 if (!disable_hpd) 733 dc_link_enable_hpd(link); 734 735 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 736 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 737 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 738 739 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 740 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 741 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 742 743 link_training_settings.link_settings = cur_link_settings; 744 745 746 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 747 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 748 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 749 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 750 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 751 link_training_settings.link_settings = prefer_link_settings; 752 } 753 754 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 755 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 756 757 dc_link_set_test_pattern( 758 link, 759 test_pattern, 760 DP_TEST_PATTERN_COLOR_SPACE_RGB, 761 &link_training_settings, 762 custom_pattern, 763 10); 764 765 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 766 * Then plug out DP panel and connect a scope to measure DP PHY signal. 767 * Need disable interrupt to avoid SW driver disable DP output. This is 768 * done after the test pattern is set. 769 */ 770 if (valid_test_pattern && disable_hpd) 771 dc_link_disable_hpd(link); 772 773 kfree(wr_buf); 774 775 return size; 776 } 777 778 /* 779 * Returns the DMCUB tracebuffer contents. 780 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 781 */ 782 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 783 { 784 struct amdgpu_device *adev = m->private; 785 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 786 struct dmub_debugfs_trace_entry *entries; 787 uint8_t *tbuf_base; 788 uint32_t tbuf_size, max_entries, num_entries, i; 789 790 if (!fb_info) 791 return 0; 792 793 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 794 if (!tbuf_base) 795 return 0; 796 797 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 798 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 799 sizeof(struct dmub_debugfs_trace_entry); 800 801 num_entries = 802 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 803 804 num_entries = min(num_entries, max_entries); 805 806 entries = (struct dmub_debugfs_trace_entry 807 *)(tbuf_base + 808 sizeof(struct dmub_debugfs_trace_header)); 809 810 for (i = 0; i < num_entries; ++i) { 811 struct dmub_debugfs_trace_entry *entry = &entries[i]; 812 813 seq_printf(m, 814 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 815 entry->trace_code, entry->tick_count, entry->param0, 816 entry->param1); 817 } 818 819 return 0; 820 } 821 822 /* 823 * Returns the DMCUB firmware state contents. 824 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 825 */ 826 static int dmub_fw_state_show(struct seq_file *m, void *data) 827 { 828 struct amdgpu_device *adev = m->private; 829 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 830 uint8_t *state_base; 831 uint32_t state_size; 832 833 if (!fb_info) 834 return 0; 835 836 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 837 if (!state_base) 838 return 0; 839 840 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 841 842 return seq_write(m, state_base, state_size); 843 } 844 845 /* psr_capability_show() - show eDP panel PSR capability 846 * 847 * The read function: sink_psr_capability_show 848 * Shows if sink has PSR capability or not. 849 * If yes - the PSR version is appended 850 * 851 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 852 * 853 * Expected output: 854 * "Sink support: no\n" - if panel doesn't support PSR 855 * "Sink support: yes [0x01]\n" - if panel supports PSR1 856 * "Driver support: no\n" - if driver doesn't support PSR 857 * "Driver support: yes [0x01]\n" - if driver supports PSR1 858 */ 859 static int psr_capability_show(struct seq_file *m, void *data) 860 { 861 struct drm_connector *connector = m->private; 862 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 863 struct dc_link *link = aconnector->dc_link; 864 865 if (!link) 866 return -ENODEV; 867 868 if (link->type == dc_connection_none) 869 return -ENODEV; 870 871 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 872 return -ENODEV; 873 874 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 875 if (link->dpcd_caps.psr_info.psr_version) 876 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 877 seq_puts(m, "\n"); 878 879 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 880 if (link->psr_settings.psr_version) 881 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 882 seq_puts(m, "\n"); 883 884 return 0; 885 } 886 887 /* 888 * Returns the current bpc for the crtc. 889 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 890 */ 891 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 892 { 893 struct drm_crtc *crtc = m->private; 894 struct drm_device *dev = crtc->dev; 895 struct dm_crtc_state *dm_crtc_state = NULL; 896 int res = -ENODEV; 897 unsigned int bpc; 898 899 mutex_lock(&dev->mode_config.mutex); 900 drm_modeset_lock(&crtc->mutex, NULL); 901 if (crtc->state == NULL) 902 goto unlock; 903 904 dm_crtc_state = to_dm_crtc_state(crtc->state); 905 if (dm_crtc_state->stream == NULL) 906 goto unlock; 907 908 switch (dm_crtc_state->stream->timing.display_color_depth) { 909 case COLOR_DEPTH_666: 910 bpc = 6; 911 break; 912 case COLOR_DEPTH_888: 913 bpc = 8; 914 break; 915 case COLOR_DEPTH_101010: 916 bpc = 10; 917 break; 918 case COLOR_DEPTH_121212: 919 bpc = 12; 920 break; 921 case COLOR_DEPTH_161616: 922 bpc = 16; 923 break; 924 default: 925 goto unlock; 926 } 927 928 seq_printf(m, "Current: %u\n", bpc); 929 res = 0; 930 931 unlock: 932 drm_modeset_unlock(&crtc->mutex); 933 mutex_unlock(&dev->mode_config.mutex); 934 935 return res; 936 } 937 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 938 939 /* 940 * Example usage: 941 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 942 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 943 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 944 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 945 */ 946 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 947 size_t size, loff_t *pos) 948 { 949 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 950 char *wr_buf = NULL; 951 uint32_t wr_buf_size = 42; 952 int max_param_num = 1; 953 long param; 954 uint8_t param_nums = 0; 955 956 if (size == 0) 957 return -EINVAL; 958 959 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 960 961 if (!wr_buf) { 962 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 963 return -ENOSPC; 964 } 965 966 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 967 ¶m, buf, 968 max_param_num, 969 ¶m_nums)) { 970 kfree(wr_buf); 971 return -EINVAL; 972 } 973 974 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 975 976 kfree(wr_buf); 977 return 0; 978 } 979 980 #ifdef CONFIG_DRM_AMD_DC_HDCP 981 /* 982 * Returns the HDCP capability of the Display (1.4 for now). 983 * 984 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 985 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 986 * 987 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 988 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 989 */ 990 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 991 { 992 struct drm_connector *connector = m->private; 993 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 994 bool hdcp_cap, hdcp2_cap; 995 996 if (connector->status != connector_status_connected) 997 return -ENODEV; 998 999 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1000 1001 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1002 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1003 1004 1005 if (hdcp_cap) 1006 seq_printf(m, "%s ", "HDCP1.4"); 1007 if (hdcp2_cap) 1008 seq_printf(m, "%s ", "HDCP2.2"); 1009 1010 if (!hdcp_cap && !hdcp2_cap) 1011 seq_printf(m, "%s ", "None"); 1012 1013 seq_puts(m, "\n"); 1014 1015 return 0; 1016 } 1017 #endif 1018 1019 /* 1020 * Returns whether the connected display is internal and not hotpluggable. 1021 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1022 */ 1023 static int internal_display_show(struct seq_file *m, void *data) 1024 { 1025 struct drm_connector *connector = m->private; 1026 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1027 struct dc_link *link = aconnector->dc_link; 1028 1029 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1030 1031 return 0; 1032 } 1033 1034 /* function description 1035 * 1036 * generic SDP message access for testing 1037 * 1038 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1039 * 1040 * SDP header 1041 * Hb0 : Secondary-Data Packet ID 1042 * Hb1 : Secondary-Data Packet type 1043 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1044 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1045 * 1046 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1047 */ 1048 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1049 size_t size, loff_t *pos) 1050 { 1051 int r; 1052 uint8_t data[36]; 1053 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1054 struct dm_crtc_state *acrtc_state; 1055 uint32_t write_size = 36; 1056 1057 if (connector->base.status != connector_status_connected) 1058 return -ENODEV; 1059 1060 if (size == 0) 1061 return 0; 1062 1063 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1064 1065 r = copy_from_user(data, buf, write_size); 1066 1067 write_size -= r; 1068 1069 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1070 1071 return write_size; 1072 } 1073 1074 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1075 size_t size, loff_t *pos) 1076 { 1077 int r; 1078 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1079 1080 if (size < sizeof(connector->debugfs_dpcd_address)) 1081 return -EINVAL; 1082 1083 r = copy_from_user(&connector->debugfs_dpcd_address, 1084 buf, sizeof(connector->debugfs_dpcd_address)); 1085 1086 return size - r; 1087 } 1088 1089 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1090 size_t size, loff_t *pos) 1091 { 1092 int r; 1093 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1094 1095 if (size < sizeof(connector->debugfs_dpcd_size)) 1096 return -EINVAL; 1097 1098 r = copy_from_user(&connector->debugfs_dpcd_size, 1099 buf, sizeof(connector->debugfs_dpcd_size)); 1100 1101 if (connector->debugfs_dpcd_size > 256) 1102 connector->debugfs_dpcd_size = 0; 1103 1104 return size - r; 1105 } 1106 1107 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1108 size_t size, loff_t *pos) 1109 { 1110 int r; 1111 char *data; 1112 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1113 struct dc_link *link = connector->dc_link; 1114 uint32_t write_size = connector->debugfs_dpcd_size; 1115 1116 if (!write_size || size < write_size) 1117 return -EINVAL; 1118 1119 data = kzalloc(write_size, GFP_KERNEL); 1120 if (!data) 1121 return 0; 1122 1123 r = copy_from_user(data, buf, write_size); 1124 1125 dm_helpers_dp_write_dpcd(link->ctx, link, 1126 connector->debugfs_dpcd_address, data, write_size - r); 1127 kfree(data); 1128 return write_size - r; 1129 } 1130 1131 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1132 size_t size, loff_t *pos) 1133 { 1134 int r; 1135 char *data; 1136 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1137 struct dc_link *link = connector->dc_link; 1138 uint32_t read_size = connector->debugfs_dpcd_size; 1139 1140 if (!read_size || size < read_size) 1141 return 0; 1142 1143 data = kzalloc(read_size, GFP_KERNEL); 1144 if (!data) 1145 return 0; 1146 1147 dm_helpers_dp_read_dpcd(link->ctx, link, 1148 connector->debugfs_dpcd_address, data, read_size); 1149 1150 r = copy_to_user(buf, data, read_size); 1151 1152 kfree(data); 1153 return read_size - r; 1154 } 1155 1156 /* function: Read link's DSC & FEC capabilities 1157 * 1158 * 1159 * Access it with the following command (you need to specify 1160 * connector like DP-1): 1161 * 1162 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1163 * 1164 */ 1165 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1166 { 1167 struct drm_connector *connector = m->private; 1168 struct drm_modeset_acquire_ctx ctx; 1169 struct drm_device *dev = connector->dev; 1170 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1171 int ret = 0; 1172 bool try_again = false; 1173 bool is_fec_supported = false; 1174 bool is_dsc_supported = false; 1175 struct dpcd_caps dpcd_caps; 1176 1177 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1178 do { 1179 try_again = false; 1180 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1181 if (ret) { 1182 if (ret == -EDEADLK) { 1183 ret = drm_modeset_backoff(&ctx); 1184 if (!ret) { 1185 try_again = true; 1186 continue; 1187 } 1188 } 1189 break; 1190 } 1191 if (connector->status != connector_status_connected) { 1192 ret = -ENODEV; 1193 break; 1194 } 1195 dpcd_caps = aconnector->dc_link->dpcd_caps; 1196 if (aconnector->port) { 1197 /* aconnector sets dsc_aux during get_modes call 1198 * if MST connector has it means it can either 1199 * enable DSC on the sink device or on MST branch 1200 * its connected to. 1201 */ 1202 if (aconnector->dsc_aux) { 1203 is_fec_supported = true; 1204 is_dsc_supported = true; 1205 } 1206 } else { 1207 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1208 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1209 } 1210 } while (try_again); 1211 1212 drm_modeset_drop_locks(&ctx); 1213 drm_modeset_acquire_fini(&ctx); 1214 1215 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1216 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1217 1218 return ret; 1219 } 1220 1221 /* function: Trigger virtual HPD redetection on connector 1222 * 1223 * This function will perform link rediscovery, link disable 1224 * and enable, and dm connector state update. 1225 * 1226 * Retrigger HPD on an existing connector by echoing 1 into 1227 * its respectful "trigger_hotplug" debugfs entry: 1228 * 1229 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1230 * 1231 * This function can perform HPD unplug: 1232 * 1233 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1234 * 1235 */ 1236 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1237 size_t size, loff_t *pos) 1238 { 1239 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1240 struct drm_connector *connector = &aconnector->base; 1241 struct dc_link *link = NULL; 1242 struct drm_device *dev = connector->dev; 1243 struct amdgpu_device *adev = drm_to_adev(dev); 1244 enum dc_connection_type new_connection_type = dc_connection_none; 1245 char *wr_buf = NULL; 1246 uint32_t wr_buf_size = 42; 1247 int max_param_num = 1; 1248 long param[1] = {0}; 1249 uint8_t param_nums = 0; 1250 bool ret = false; 1251 1252 if (!aconnector || !aconnector->dc_link) 1253 return -EINVAL; 1254 1255 if (size == 0) 1256 return -EINVAL; 1257 1258 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1259 1260 if (!wr_buf) { 1261 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1262 return -ENOSPC; 1263 } 1264 1265 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1266 (long *)param, buf, 1267 max_param_num, 1268 ¶m_nums)) { 1269 kfree(wr_buf); 1270 return -EINVAL; 1271 } 1272 1273 kfree(wr_buf); 1274 1275 if (param_nums <= 0) { 1276 DRM_DEBUG_DRIVER("user data not be read\n"); 1277 return -EINVAL; 1278 } 1279 1280 mutex_lock(&aconnector->hpd_lock); 1281 1282 /* Don't support for mst end device*/ 1283 if (aconnector->mst_port) { 1284 mutex_unlock(&aconnector->hpd_lock); 1285 return -EINVAL; 1286 } 1287 1288 if (param[0] == 1) { 1289 1290 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1291 new_connection_type != dc_connection_none) 1292 goto unlock; 1293 1294 mutex_lock(&adev->dm.dc_lock); 1295 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1296 mutex_unlock(&adev->dm.dc_lock); 1297 1298 if (!ret) 1299 goto unlock; 1300 1301 amdgpu_dm_update_connector_after_detect(aconnector); 1302 1303 drm_modeset_lock_all(dev); 1304 dm_restore_drm_connector_state(dev, connector); 1305 drm_modeset_unlock_all(dev); 1306 1307 drm_kms_helper_connector_hotplug_event(connector); 1308 } else if (param[0] == 0) { 1309 if (!aconnector->dc_link) 1310 goto unlock; 1311 1312 link = aconnector->dc_link; 1313 1314 if (link->local_sink) { 1315 dc_sink_release(link->local_sink); 1316 link->local_sink = NULL; 1317 } 1318 1319 link->dpcd_sink_count = 0; 1320 link->type = dc_connection_none; 1321 link->dongle_max_pix_clk = 0; 1322 1323 amdgpu_dm_update_connector_after_detect(aconnector); 1324 1325 /* If the aconnector is the root node in mst topology */ 1326 if (aconnector->mst_mgr.mst_state == true) 1327 reset_cur_dp_mst_topology(link); 1328 1329 drm_modeset_lock_all(dev); 1330 dm_restore_drm_connector_state(dev, connector); 1331 drm_modeset_unlock_all(dev); 1332 1333 drm_kms_helper_connector_hotplug_event(connector); 1334 } 1335 1336 unlock: 1337 mutex_unlock(&aconnector->hpd_lock); 1338 1339 return size; 1340 } 1341 1342 /* function: read DSC status on the connector 1343 * 1344 * The read function: dp_dsc_clock_en_read 1345 * returns current status of DSC clock on the connector. 1346 * The return is a boolean flag: 1 or 0. 1347 * 1348 * Access it with the following command (you need to specify 1349 * connector like DP-1): 1350 * 1351 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1352 * 1353 * Expected output: 1354 * 1 - means that DSC is currently enabled 1355 * 0 - means that DSC is disabled 1356 */ 1357 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1358 size_t size, loff_t *pos) 1359 { 1360 char *rd_buf = NULL; 1361 char *rd_buf_ptr = NULL; 1362 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1363 struct display_stream_compressor *dsc; 1364 struct dcn_dsc_state dsc_state = {0}; 1365 const uint32_t rd_buf_size = 10; 1366 struct pipe_ctx *pipe_ctx; 1367 ssize_t result = 0; 1368 int i, r, str_len = 30; 1369 1370 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1371 1372 if (!rd_buf) 1373 return -ENOMEM; 1374 1375 rd_buf_ptr = rd_buf; 1376 1377 for (i = 0; i < MAX_PIPES; i++) { 1378 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1379 if (pipe_ctx->stream && 1380 pipe_ctx->stream->link == aconnector->dc_link) 1381 break; 1382 } 1383 1384 dsc = pipe_ctx->stream_res.dsc; 1385 if (dsc) 1386 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1387 1388 snprintf(rd_buf_ptr, str_len, 1389 "%d\n", 1390 dsc_state.dsc_clock_en); 1391 rd_buf_ptr += str_len; 1392 1393 while (size) { 1394 if (*pos >= rd_buf_size) 1395 break; 1396 1397 r = put_user(*(rd_buf + result), buf); 1398 if (r) { 1399 kfree(rd_buf); 1400 return r; /* r = -EFAULT */ 1401 } 1402 1403 buf += 1; 1404 size -= 1; 1405 *pos += 1; 1406 result += 1; 1407 } 1408 1409 kfree(rd_buf); 1410 return result; 1411 } 1412 1413 /* function: write force DSC on the connector 1414 * 1415 * The write function: dp_dsc_clock_en_write 1416 * enables to force DSC on the connector. 1417 * User can write to either force enable or force disable DSC 1418 * on the next modeset or set it to driver default 1419 * 1420 * Accepted inputs: 1421 * 0 - default DSC enablement policy 1422 * 1 - force enable DSC on the connector 1423 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1424 * 1425 * Writing DSC settings is done with the following command: 1426 * - To force enable DSC (you need to specify 1427 * connector like DP-1): 1428 * 1429 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1430 * 1431 * - To return to default state set the flag to zero and 1432 * let driver deal with DSC automatically 1433 * (you need to specify connector like DP-1): 1434 * 1435 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1436 * 1437 */ 1438 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1439 size_t size, loff_t *pos) 1440 { 1441 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1442 struct drm_connector *connector = &aconnector->base; 1443 struct drm_device *dev = connector->dev; 1444 struct drm_crtc *crtc = NULL; 1445 struct dm_crtc_state *dm_crtc_state = NULL; 1446 struct pipe_ctx *pipe_ctx; 1447 int i; 1448 char *wr_buf = NULL; 1449 uint32_t wr_buf_size = 42; 1450 int max_param_num = 1; 1451 long param[1] = {0}; 1452 uint8_t param_nums = 0; 1453 1454 if (size == 0) 1455 return -EINVAL; 1456 1457 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1458 1459 if (!wr_buf) { 1460 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1461 return -ENOSPC; 1462 } 1463 1464 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1465 (long *)param, buf, 1466 max_param_num, 1467 ¶m_nums)) { 1468 kfree(wr_buf); 1469 return -EINVAL; 1470 } 1471 1472 if (param_nums <= 0) { 1473 DRM_DEBUG_DRIVER("user data not be read\n"); 1474 kfree(wr_buf); 1475 return -EINVAL; 1476 } 1477 1478 for (i = 0; i < MAX_PIPES; i++) { 1479 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1480 if (pipe_ctx->stream && 1481 pipe_ctx->stream->link == aconnector->dc_link) 1482 break; 1483 } 1484 1485 if (!pipe_ctx->stream) 1486 goto done; 1487 1488 // Get CRTC state 1489 mutex_lock(&dev->mode_config.mutex); 1490 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1491 1492 if (connector->state == NULL) 1493 goto unlock; 1494 1495 crtc = connector->state->crtc; 1496 if (crtc == NULL) 1497 goto unlock; 1498 1499 drm_modeset_lock(&crtc->mutex, NULL); 1500 if (crtc->state == NULL) 1501 goto unlock; 1502 1503 dm_crtc_state = to_dm_crtc_state(crtc->state); 1504 if (dm_crtc_state->stream == NULL) 1505 goto unlock; 1506 1507 if (param[0] == 1) 1508 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1509 else if (param[0] == 2) 1510 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1511 else 1512 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1513 1514 dm_crtc_state->dsc_force_changed = true; 1515 1516 unlock: 1517 if (crtc) 1518 drm_modeset_unlock(&crtc->mutex); 1519 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1520 mutex_unlock(&dev->mode_config.mutex); 1521 1522 done: 1523 kfree(wr_buf); 1524 return size; 1525 } 1526 1527 /* function: read DSC slice width parameter on the connector 1528 * 1529 * The read function: dp_dsc_slice_width_read 1530 * returns dsc slice width used in the current configuration 1531 * The return is an integer: 0 or other positive number 1532 * 1533 * Access the status with the following command: 1534 * 1535 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1536 * 1537 * 0 - means that DSC is disabled 1538 * 1539 * Any other number more than zero represents the 1540 * slice width currently used by DSC in pixels 1541 * 1542 */ 1543 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1544 size_t size, loff_t *pos) 1545 { 1546 char *rd_buf = NULL; 1547 char *rd_buf_ptr = NULL; 1548 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1549 struct display_stream_compressor *dsc; 1550 struct dcn_dsc_state dsc_state = {0}; 1551 const uint32_t rd_buf_size = 100; 1552 struct pipe_ctx *pipe_ctx; 1553 ssize_t result = 0; 1554 int i, r, str_len = 30; 1555 1556 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1557 1558 if (!rd_buf) 1559 return -ENOMEM; 1560 1561 rd_buf_ptr = rd_buf; 1562 1563 for (i = 0; i < MAX_PIPES; i++) { 1564 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1565 if (pipe_ctx->stream && 1566 pipe_ctx->stream->link == aconnector->dc_link) 1567 break; 1568 } 1569 1570 dsc = pipe_ctx->stream_res.dsc; 1571 if (dsc) 1572 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1573 1574 snprintf(rd_buf_ptr, str_len, 1575 "%d\n", 1576 dsc_state.dsc_slice_width); 1577 rd_buf_ptr += str_len; 1578 1579 while (size) { 1580 if (*pos >= rd_buf_size) 1581 break; 1582 1583 r = put_user(*(rd_buf + result), buf); 1584 if (r) { 1585 kfree(rd_buf); 1586 return r; /* r = -EFAULT */ 1587 } 1588 1589 buf += 1; 1590 size -= 1; 1591 *pos += 1; 1592 result += 1; 1593 } 1594 1595 kfree(rd_buf); 1596 return result; 1597 } 1598 1599 /* function: write DSC slice width parameter 1600 * 1601 * The write function: dp_dsc_slice_width_write 1602 * overwrites automatically generated DSC configuration 1603 * of slice width. 1604 * 1605 * The user has to write the slice width divisible by the 1606 * picture width. 1607 * 1608 * Also the user has to write width in hexidecimal 1609 * rather than in decimal. 1610 * 1611 * Writing DSC settings is done with the following command: 1612 * - To force overwrite slice width: (example sets to 1920 pixels) 1613 * 1614 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1615 * 1616 * - To stop overwriting and let driver find the optimal size, 1617 * set the width to zero: 1618 * 1619 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1620 * 1621 */ 1622 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1623 size_t size, loff_t *pos) 1624 { 1625 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1626 struct pipe_ctx *pipe_ctx; 1627 struct drm_connector *connector = &aconnector->base; 1628 struct drm_device *dev = connector->dev; 1629 struct drm_crtc *crtc = NULL; 1630 struct dm_crtc_state *dm_crtc_state = NULL; 1631 int i; 1632 char *wr_buf = NULL; 1633 uint32_t wr_buf_size = 42; 1634 int max_param_num = 1; 1635 long param[1] = {0}; 1636 uint8_t param_nums = 0; 1637 1638 if (size == 0) 1639 return -EINVAL; 1640 1641 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1642 1643 if (!wr_buf) { 1644 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1645 return -ENOSPC; 1646 } 1647 1648 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1649 (long *)param, buf, 1650 max_param_num, 1651 ¶m_nums)) { 1652 kfree(wr_buf); 1653 return -EINVAL; 1654 } 1655 1656 if (param_nums <= 0) { 1657 DRM_DEBUG_DRIVER("user data not be read\n"); 1658 kfree(wr_buf); 1659 return -EINVAL; 1660 } 1661 1662 for (i = 0; i < MAX_PIPES; i++) { 1663 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1664 if (pipe_ctx->stream && 1665 pipe_ctx->stream->link == aconnector->dc_link) 1666 break; 1667 } 1668 1669 if (!pipe_ctx->stream) 1670 goto done; 1671 1672 // Safely get CRTC state 1673 mutex_lock(&dev->mode_config.mutex); 1674 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1675 1676 if (connector->state == NULL) 1677 goto unlock; 1678 1679 crtc = connector->state->crtc; 1680 if (crtc == NULL) 1681 goto unlock; 1682 1683 drm_modeset_lock(&crtc->mutex, NULL); 1684 if (crtc->state == NULL) 1685 goto unlock; 1686 1687 dm_crtc_state = to_dm_crtc_state(crtc->state); 1688 if (dm_crtc_state->stream == NULL) 1689 goto unlock; 1690 1691 if (param[0] > 0) 1692 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1693 pipe_ctx->stream->timing.h_addressable, 1694 param[0]); 1695 else 1696 aconnector->dsc_settings.dsc_num_slices_h = 0; 1697 1698 dm_crtc_state->dsc_force_changed = true; 1699 1700 unlock: 1701 if (crtc) 1702 drm_modeset_unlock(&crtc->mutex); 1703 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1704 mutex_unlock(&dev->mode_config.mutex); 1705 1706 done: 1707 kfree(wr_buf); 1708 return size; 1709 } 1710 1711 /* function: read DSC slice height parameter on the connector 1712 * 1713 * The read function: dp_dsc_slice_height_read 1714 * returns dsc slice height used in the current configuration 1715 * The return is an integer: 0 or other positive number 1716 * 1717 * Access the status with the following command: 1718 * 1719 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1720 * 1721 * 0 - means that DSC is disabled 1722 * 1723 * Any other number more than zero represents the 1724 * slice height currently used by DSC in pixels 1725 * 1726 */ 1727 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1728 size_t size, loff_t *pos) 1729 { 1730 char *rd_buf = NULL; 1731 char *rd_buf_ptr = NULL; 1732 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1733 struct display_stream_compressor *dsc; 1734 struct dcn_dsc_state dsc_state = {0}; 1735 const uint32_t rd_buf_size = 100; 1736 struct pipe_ctx *pipe_ctx; 1737 ssize_t result = 0; 1738 int i, r, str_len = 30; 1739 1740 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1741 1742 if (!rd_buf) 1743 return -ENOMEM; 1744 1745 rd_buf_ptr = rd_buf; 1746 1747 for (i = 0; i < MAX_PIPES; i++) { 1748 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1749 if (pipe_ctx->stream && 1750 pipe_ctx->stream->link == aconnector->dc_link) 1751 break; 1752 } 1753 1754 dsc = pipe_ctx->stream_res.dsc; 1755 if (dsc) 1756 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1757 1758 snprintf(rd_buf_ptr, str_len, 1759 "%d\n", 1760 dsc_state.dsc_slice_height); 1761 rd_buf_ptr += str_len; 1762 1763 while (size) { 1764 if (*pos >= rd_buf_size) 1765 break; 1766 1767 r = put_user(*(rd_buf + result), buf); 1768 if (r) { 1769 kfree(rd_buf); 1770 return r; /* r = -EFAULT */ 1771 } 1772 1773 buf += 1; 1774 size -= 1; 1775 *pos += 1; 1776 result += 1; 1777 } 1778 1779 kfree(rd_buf); 1780 return result; 1781 } 1782 1783 /* function: write DSC slice height parameter 1784 * 1785 * The write function: dp_dsc_slice_height_write 1786 * overwrites automatically generated DSC configuration 1787 * of slice height. 1788 * 1789 * The user has to write the slice height divisible by the 1790 * picture height. 1791 * 1792 * Also the user has to write height in hexidecimal 1793 * rather than in decimal. 1794 * 1795 * Writing DSC settings is done with the following command: 1796 * - To force overwrite slice height (example sets to 128 pixels): 1797 * 1798 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1799 * 1800 * - To stop overwriting and let driver find the optimal size, 1801 * set the height to zero: 1802 * 1803 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1804 * 1805 */ 1806 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1807 size_t size, loff_t *pos) 1808 { 1809 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1810 struct drm_connector *connector = &aconnector->base; 1811 struct drm_device *dev = connector->dev; 1812 struct drm_crtc *crtc = NULL; 1813 struct dm_crtc_state *dm_crtc_state = NULL; 1814 struct pipe_ctx *pipe_ctx; 1815 int i; 1816 char *wr_buf = NULL; 1817 uint32_t wr_buf_size = 42; 1818 int max_param_num = 1; 1819 uint8_t param_nums = 0; 1820 long param[1] = {0}; 1821 1822 if (size == 0) 1823 return -EINVAL; 1824 1825 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1826 1827 if (!wr_buf) { 1828 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1829 return -ENOSPC; 1830 } 1831 1832 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1833 (long *)param, buf, 1834 max_param_num, 1835 ¶m_nums)) { 1836 kfree(wr_buf); 1837 return -EINVAL; 1838 } 1839 1840 if (param_nums <= 0) { 1841 DRM_DEBUG_DRIVER("user data not be read\n"); 1842 kfree(wr_buf); 1843 return -EINVAL; 1844 } 1845 1846 for (i = 0; i < MAX_PIPES; i++) { 1847 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1848 if (pipe_ctx->stream && 1849 pipe_ctx->stream->link == aconnector->dc_link) 1850 break; 1851 } 1852 1853 if (!pipe_ctx->stream) 1854 goto done; 1855 1856 // Get CRTC state 1857 mutex_lock(&dev->mode_config.mutex); 1858 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1859 1860 if (connector->state == NULL) 1861 goto unlock; 1862 1863 crtc = connector->state->crtc; 1864 if (crtc == NULL) 1865 goto unlock; 1866 1867 drm_modeset_lock(&crtc->mutex, NULL); 1868 if (crtc->state == NULL) 1869 goto unlock; 1870 1871 dm_crtc_state = to_dm_crtc_state(crtc->state); 1872 if (dm_crtc_state->stream == NULL) 1873 goto unlock; 1874 1875 if (param[0] > 0) 1876 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1877 pipe_ctx->stream->timing.v_addressable, 1878 param[0]); 1879 else 1880 aconnector->dsc_settings.dsc_num_slices_v = 0; 1881 1882 dm_crtc_state->dsc_force_changed = true; 1883 1884 unlock: 1885 if (crtc) 1886 drm_modeset_unlock(&crtc->mutex); 1887 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1888 mutex_unlock(&dev->mode_config.mutex); 1889 1890 done: 1891 kfree(wr_buf); 1892 return size; 1893 } 1894 1895 /* function: read DSC target rate on the connector in bits per pixel 1896 * 1897 * The read function: dp_dsc_bits_per_pixel_read 1898 * returns target rate of compression in bits per pixel 1899 * The return is an integer: 0 or other positive integer 1900 * 1901 * Access it with the following command: 1902 * 1903 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1904 * 1905 * 0 - means that DSC is disabled 1906 */ 1907 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1908 size_t size, loff_t *pos) 1909 { 1910 char *rd_buf = NULL; 1911 char *rd_buf_ptr = NULL; 1912 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1913 struct display_stream_compressor *dsc; 1914 struct dcn_dsc_state dsc_state = {0}; 1915 const uint32_t rd_buf_size = 100; 1916 struct pipe_ctx *pipe_ctx; 1917 ssize_t result = 0; 1918 int i, r, str_len = 30; 1919 1920 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1921 1922 if (!rd_buf) 1923 return -ENOMEM; 1924 1925 rd_buf_ptr = rd_buf; 1926 1927 for (i = 0; i < MAX_PIPES; i++) { 1928 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1929 if (pipe_ctx->stream && 1930 pipe_ctx->stream->link == aconnector->dc_link) 1931 break; 1932 } 1933 1934 dsc = pipe_ctx->stream_res.dsc; 1935 if (dsc) 1936 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1937 1938 snprintf(rd_buf_ptr, str_len, 1939 "%d\n", 1940 dsc_state.dsc_bits_per_pixel); 1941 rd_buf_ptr += str_len; 1942 1943 while (size) { 1944 if (*pos >= rd_buf_size) 1945 break; 1946 1947 r = put_user(*(rd_buf + result), buf); 1948 if (r) { 1949 kfree(rd_buf); 1950 return r; /* r = -EFAULT */ 1951 } 1952 1953 buf += 1; 1954 size -= 1; 1955 *pos += 1; 1956 result += 1; 1957 } 1958 1959 kfree(rd_buf); 1960 return result; 1961 } 1962 1963 /* function: write DSC target rate in bits per pixel 1964 * 1965 * The write function: dp_dsc_bits_per_pixel_write 1966 * overwrites automatically generated DSC configuration 1967 * of DSC target bit rate. 1968 * 1969 * Also the user has to write bpp in hexidecimal 1970 * rather than in decimal. 1971 * 1972 * Writing DSC settings is done with the following command: 1973 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1974 * 1975 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1976 * 1977 * - To stop overwriting and let driver find the optimal rate, 1978 * set the rate to zero: 1979 * 1980 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1981 * 1982 */ 1983 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1984 size_t size, loff_t *pos) 1985 { 1986 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1987 struct drm_connector *connector = &aconnector->base; 1988 struct drm_device *dev = connector->dev; 1989 struct drm_crtc *crtc = NULL; 1990 struct dm_crtc_state *dm_crtc_state = NULL; 1991 struct pipe_ctx *pipe_ctx; 1992 int i; 1993 char *wr_buf = NULL; 1994 uint32_t wr_buf_size = 42; 1995 int max_param_num = 1; 1996 uint8_t param_nums = 0; 1997 long param[1] = {0}; 1998 1999 if (size == 0) 2000 return -EINVAL; 2001 2002 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2003 2004 if (!wr_buf) { 2005 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2006 return -ENOSPC; 2007 } 2008 2009 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2010 (long *)param, buf, 2011 max_param_num, 2012 ¶m_nums)) { 2013 kfree(wr_buf); 2014 return -EINVAL; 2015 } 2016 2017 if (param_nums <= 0) { 2018 DRM_DEBUG_DRIVER("user data not be read\n"); 2019 kfree(wr_buf); 2020 return -EINVAL; 2021 } 2022 2023 for (i = 0; i < MAX_PIPES; i++) { 2024 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2025 if (pipe_ctx->stream && 2026 pipe_ctx->stream->link == aconnector->dc_link) 2027 break; 2028 } 2029 2030 if (!pipe_ctx->stream) 2031 goto done; 2032 2033 // Get CRTC state 2034 mutex_lock(&dev->mode_config.mutex); 2035 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2036 2037 if (connector->state == NULL) 2038 goto unlock; 2039 2040 crtc = connector->state->crtc; 2041 if (crtc == NULL) 2042 goto unlock; 2043 2044 drm_modeset_lock(&crtc->mutex, NULL); 2045 if (crtc->state == NULL) 2046 goto unlock; 2047 2048 dm_crtc_state = to_dm_crtc_state(crtc->state); 2049 if (dm_crtc_state->stream == NULL) 2050 goto unlock; 2051 2052 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2053 2054 dm_crtc_state->dsc_force_changed = true; 2055 2056 unlock: 2057 if (crtc) 2058 drm_modeset_unlock(&crtc->mutex); 2059 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2060 mutex_unlock(&dev->mode_config.mutex); 2061 2062 done: 2063 kfree(wr_buf); 2064 return size; 2065 } 2066 2067 /* function: read DSC picture width parameter on the connector 2068 * 2069 * The read function: dp_dsc_pic_width_read 2070 * returns dsc picture width used in the current configuration 2071 * It is the same as h_addressable of the current 2072 * display's timing 2073 * The return is an integer: 0 or other positive integer 2074 * If 0 then DSC is disabled. 2075 * 2076 * Access it with the following command: 2077 * 2078 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2079 * 2080 * 0 - means that DSC is disabled 2081 */ 2082 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2083 size_t size, loff_t *pos) 2084 { 2085 char *rd_buf = NULL; 2086 char *rd_buf_ptr = NULL; 2087 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2088 struct display_stream_compressor *dsc; 2089 struct dcn_dsc_state dsc_state = {0}; 2090 const uint32_t rd_buf_size = 100; 2091 struct pipe_ctx *pipe_ctx; 2092 ssize_t result = 0; 2093 int i, r, str_len = 30; 2094 2095 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2096 2097 if (!rd_buf) 2098 return -ENOMEM; 2099 2100 rd_buf_ptr = rd_buf; 2101 2102 for (i = 0; i < MAX_PIPES; i++) { 2103 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2104 if (pipe_ctx->stream && 2105 pipe_ctx->stream->link == aconnector->dc_link) 2106 break; 2107 } 2108 2109 dsc = pipe_ctx->stream_res.dsc; 2110 if (dsc) 2111 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2112 2113 snprintf(rd_buf_ptr, str_len, 2114 "%d\n", 2115 dsc_state.dsc_pic_width); 2116 rd_buf_ptr += str_len; 2117 2118 while (size) { 2119 if (*pos >= rd_buf_size) 2120 break; 2121 2122 r = put_user(*(rd_buf + result), buf); 2123 if (r) { 2124 kfree(rd_buf); 2125 return r; /* r = -EFAULT */ 2126 } 2127 2128 buf += 1; 2129 size -= 1; 2130 *pos += 1; 2131 result += 1; 2132 } 2133 2134 kfree(rd_buf); 2135 return result; 2136 } 2137 2138 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2139 size_t size, loff_t *pos) 2140 { 2141 char *rd_buf = NULL; 2142 char *rd_buf_ptr = NULL; 2143 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2144 struct display_stream_compressor *dsc; 2145 struct dcn_dsc_state dsc_state = {0}; 2146 const uint32_t rd_buf_size = 100; 2147 struct pipe_ctx *pipe_ctx; 2148 ssize_t result = 0; 2149 int i, r, str_len = 30; 2150 2151 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2152 2153 if (!rd_buf) 2154 return -ENOMEM; 2155 2156 rd_buf_ptr = rd_buf; 2157 2158 for (i = 0; i < MAX_PIPES; i++) { 2159 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2160 if (pipe_ctx->stream && 2161 pipe_ctx->stream->link == aconnector->dc_link) 2162 break; 2163 } 2164 2165 dsc = pipe_ctx->stream_res.dsc; 2166 if (dsc) 2167 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2168 2169 snprintf(rd_buf_ptr, str_len, 2170 "%d\n", 2171 dsc_state.dsc_pic_height); 2172 rd_buf_ptr += str_len; 2173 2174 while (size) { 2175 if (*pos >= rd_buf_size) 2176 break; 2177 2178 r = put_user(*(rd_buf + result), buf); 2179 if (r) { 2180 kfree(rd_buf); 2181 return r; /* r = -EFAULT */ 2182 } 2183 2184 buf += 1; 2185 size -= 1; 2186 *pos += 1; 2187 result += 1; 2188 } 2189 2190 kfree(rd_buf); 2191 return result; 2192 } 2193 2194 /* function: read DSC chunk size parameter on the connector 2195 * 2196 * The read function: dp_dsc_chunk_size_read 2197 * returns dsc chunk size set in the current configuration 2198 * The value is calculated automatically by DSC code 2199 * and depends on slice parameters and bpp target rate 2200 * The return is an integer: 0 or other positive integer 2201 * If 0 then DSC is disabled. 2202 * 2203 * Access it with the following command: 2204 * 2205 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2206 * 2207 * 0 - means that DSC is disabled 2208 */ 2209 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2210 size_t size, loff_t *pos) 2211 { 2212 char *rd_buf = NULL; 2213 char *rd_buf_ptr = NULL; 2214 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2215 struct display_stream_compressor *dsc; 2216 struct dcn_dsc_state dsc_state = {0}; 2217 const uint32_t rd_buf_size = 100; 2218 struct pipe_ctx *pipe_ctx; 2219 ssize_t result = 0; 2220 int i, r, str_len = 30; 2221 2222 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2223 2224 if (!rd_buf) 2225 return -ENOMEM; 2226 2227 rd_buf_ptr = rd_buf; 2228 2229 for (i = 0; i < MAX_PIPES; i++) { 2230 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2231 if (pipe_ctx->stream && 2232 pipe_ctx->stream->link == aconnector->dc_link) 2233 break; 2234 } 2235 2236 dsc = pipe_ctx->stream_res.dsc; 2237 if (dsc) 2238 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2239 2240 snprintf(rd_buf_ptr, str_len, 2241 "%d\n", 2242 dsc_state.dsc_chunk_size); 2243 rd_buf_ptr += str_len; 2244 2245 while (size) { 2246 if (*pos >= rd_buf_size) 2247 break; 2248 2249 r = put_user(*(rd_buf + result), buf); 2250 if (r) { 2251 kfree(rd_buf); 2252 return r; /* r = -EFAULT */ 2253 } 2254 2255 buf += 1; 2256 size -= 1; 2257 *pos += 1; 2258 result += 1; 2259 } 2260 2261 kfree(rd_buf); 2262 return result; 2263 } 2264 2265 /* function: read DSC slice bpg offset on the connector 2266 * 2267 * The read function: dp_dsc_slice_bpg_offset_read 2268 * returns dsc bpg slice offset set in the current configuration 2269 * The value is calculated automatically by DSC code 2270 * and depends on slice parameters and bpp target rate 2271 * The return is an integer: 0 or other positive integer 2272 * If 0 then DSC is disabled. 2273 * 2274 * Access it with the following command: 2275 * 2276 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2277 * 2278 * 0 - means that DSC is disabled 2279 */ 2280 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2281 size_t size, loff_t *pos) 2282 { 2283 char *rd_buf = NULL; 2284 char *rd_buf_ptr = NULL; 2285 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2286 struct display_stream_compressor *dsc; 2287 struct dcn_dsc_state dsc_state = {0}; 2288 const uint32_t rd_buf_size = 100; 2289 struct pipe_ctx *pipe_ctx; 2290 ssize_t result = 0; 2291 int i, r, str_len = 30; 2292 2293 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2294 2295 if (!rd_buf) 2296 return -ENOMEM; 2297 2298 rd_buf_ptr = rd_buf; 2299 2300 for (i = 0; i < MAX_PIPES; i++) { 2301 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2302 if (pipe_ctx->stream && 2303 pipe_ctx->stream->link == aconnector->dc_link) 2304 break; 2305 } 2306 2307 dsc = pipe_ctx->stream_res.dsc; 2308 if (dsc) 2309 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2310 2311 snprintf(rd_buf_ptr, str_len, 2312 "%d\n", 2313 dsc_state.dsc_slice_bpg_offset); 2314 rd_buf_ptr += str_len; 2315 2316 while (size) { 2317 if (*pos >= rd_buf_size) 2318 break; 2319 2320 r = put_user(*(rd_buf + result), buf); 2321 if (r) { 2322 kfree(rd_buf); 2323 return r; /* r = -EFAULT */ 2324 } 2325 2326 buf += 1; 2327 size -= 1; 2328 *pos += 1; 2329 result += 1; 2330 } 2331 2332 kfree(rd_buf); 2333 return result; 2334 } 2335 2336 2337 /* 2338 * function description: Read max_requested_bpc property from the connector 2339 * 2340 * Access it with the following command: 2341 * 2342 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2343 * 2344 */ 2345 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2346 size_t size, loff_t *pos) 2347 { 2348 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2349 struct drm_connector *connector = &aconnector->base; 2350 struct drm_device *dev = connector->dev; 2351 struct dm_connector_state *state; 2352 ssize_t result = 0; 2353 char *rd_buf = NULL; 2354 char *rd_buf_ptr = NULL; 2355 const uint32_t rd_buf_size = 10; 2356 int r; 2357 2358 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2359 2360 if (!rd_buf) 2361 return -ENOMEM; 2362 2363 mutex_lock(&dev->mode_config.mutex); 2364 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2365 2366 if (connector->state == NULL) 2367 goto unlock; 2368 2369 state = to_dm_connector_state(connector->state); 2370 2371 rd_buf_ptr = rd_buf; 2372 snprintf(rd_buf_ptr, rd_buf_size, 2373 "%u\n", 2374 state->base.max_requested_bpc); 2375 2376 while (size) { 2377 if (*pos >= rd_buf_size) 2378 break; 2379 2380 r = put_user(*(rd_buf + result), buf); 2381 if (r) { 2382 result = r; /* r = -EFAULT */ 2383 goto unlock; 2384 } 2385 buf += 1; 2386 size -= 1; 2387 *pos += 1; 2388 result += 1; 2389 } 2390 unlock: 2391 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2392 mutex_unlock(&dev->mode_config.mutex); 2393 kfree(rd_buf); 2394 return result; 2395 } 2396 2397 2398 /* 2399 * function description: Set max_requested_bpc property on the connector 2400 * 2401 * This function will not force the input BPC on connector, it will only 2402 * change the max value. This is equivalent to setting max_bpc through 2403 * xrandr. 2404 * 2405 * The BPC value written must be >= 6 and <= 16. Values outside of this 2406 * range will result in errors. 2407 * 2408 * BPC values: 2409 * 0x6 - 6 BPC 2410 * 0x8 - 8 BPC 2411 * 0xa - 10 BPC 2412 * 0xc - 12 BPC 2413 * 0x10 - 16 BPC 2414 * 2415 * Write the max_bpc in the following way: 2416 * 2417 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2418 * 2419 */ 2420 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2421 size_t size, loff_t *pos) 2422 { 2423 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2424 struct drm_connector *connector = &aconnector->base; 2425 struct dm_connector_state *state; 2426 struct drm_device *dev = connector->dev; 2427 char *wr_buf = NULL; 2428 uint32_t wr_buf_size = 42; 2429 int max_param_num = 1; 2430 long param[1] = {0}; 2431 uint8_t param_nums = 0; 2432 2433 if (size == 0) 2434 return -EINVAL; 2435 2436 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2437 2438 if (!wr_buf) { 2439 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2440 return -ENOSPC; 2441 } 2442 2443 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2444 (long *)param, buf, 2445 max_param_num, 2446 ¶m_nums)) { 2447 kfree(wr_buf); 2448 return -EINVAL; 2449 } 2450 2451 if (param_nums <= 0) { 2452 DRM_DEBUG_DRIVER("user data not be read\n"); 2453 kfree(wr_buf); 2454 return -EINVAL; 2455 } 2456 2457 if (param[0] < 6 || param[0] > 16) { 2458 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2459 kfree(wr_buf); 2460 return -EINVAL; 2461 } 2462 2463 mutex_lock(&dev->mode_config.mutex); 2464 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2465 2466 if (connector->state == NULL) 2467 goto unlock; 2468 2469 state = to_dm_connector_state(connector->state); 2470 state->base.max_requested_bpc = param[0]; 2471 unlock: 2472 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2473 mutex_unlock(&dev->mode_config.mutex); 2474 2475 kfree(wr_buf); 2476 return size; 2477 } 2478 2479 /* 2480 * Backlight at this moment. Read only. 2481 * As written to display, taking ABM and backlight lut into account. 2482 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2483 * 2484 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2485 */ 2486 static int current_backlight_show(struct seq_file *m, void *unused) 2487 { 2488 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2489 struct dc_link *link = aconnector->dc_link; 2490 unsigned int backlight; 2491 2492 backlight = dc_link_get_backlight_level(link); 2493 seq_printf(m, "0x%x\n", backlight); 2494 2495 return 0; 2496 } 2497 2498 /* 2499 * Backlight value that is being approached. Read only. 2500 * As written to display, taking ABM and backlight lut into account. 2501 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2502 * 2503 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2504 */ 2505 static int target_backlight_show(struct seq_file *m, void *unused) 2506 { 2507 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2508 struct dc_link *link = aconnector->dc_link; 2509 unsigned int backlight; 2510 2511 backlight = dc_link_get_target_backlight_pwm(link); 2512 seq_printf(m, "0x%x\n", backlight); 2513 2514 return 0; 2515 } 2516 2517 /* 2518 * function description: Determine if the connector is mst connector 2519 * 2520 * This function helps to determine whether a connector is a mst connector. 2521 * - "root" stands for the root connector of the topology 2522 * - "branch" stands for branch device of the topology 2523 * - "end" stands for leaf node connector of the topology 2524 * - "no" stands for the connector is not a device of a mst topology 2525 * Access it with the following command: 2526 * 2527 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2528 * 2529 */ 2530 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2531 { 2532 struct drm_connector *connector = m->private; 2533 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2534 struct drm_dp_mst_topology_mgr *mgr = NULL; 2535 struct drm_dp_mst_port *port = NULL; 2536 char *role = NULL; 2537 2538 mutex_lock(&aconnector->hpd_lock); 2539 2540 if (aconnector->mst_mgr.mst_state) { 2541 role = "root"; 2542 } else if (aconnector->mst_port && 2543 aconnector->mst_port->mst_mgr.mst_state) { 2544 2545 role = "end"; 2546 2547 mgr = &aconnector->mst_port->mst_mgr; 2548 port = aconnector->port; 2549 2550 drm_modeset_lock(&mgr->base.lock, NULL); 2551 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2552 port->mcs) 2553 role = "branch"; 2554 drm_modeset_unlock(&mgr->base.lock); 2555 2556 } else { 2557 role = "no"; 2558 } 2559 2560 seq_printf(m, "%s\n", role); 2561 2562 mutex_unlock(&aconnector->hpd_lock); 2563 2564 return 0; 2565 } 2566 2567 /* 2568 * function description: Read out the mst progress status 2569 * 2570 * This function helps to determine the mst progress status of 2571 * a mst connector. 2572 * 2573 * Access it with the following command: 2574 * 2575 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2576 * 2577 */ 2578 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2579 { 2580 struct drm_connector *connector = m->private; 2581 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2582 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2583 int i; 2584 2585 mutex_lock(&aconnector->hpd_lock); 2586 mutex_lock(&adev->dm.dc_lock); 2587 2588 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2589 seq_puts(m, "disabled\n"); 2590 } else { 2591 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2592 seq_printf(m, "%s:%s\n", 2593 mst_progress_status[i], 2594 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2595 } 2596 2597 mutex_unlock(&adev->dm.dc_lock); 2598 mutex_unlock(&aconnector->hpd_lock); 2599 2600 return 0; 2601 } 2602 2603 /* 2604 * Reports whether the connected display is a USB4 DPIA tunneled display 2605 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2606 */ 2607 static int is_dpia_link_show(struct seq_file *m, void *data) 2608 { 2609 struct drm_connector *connector = m->private; 2610 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2611 struct dc_link *link = aconnector->dc_link; 2612 2613 if (connector->status != connector_status_connected) 2614 return -ENODEV; 2615 2616 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2617 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2618 2619 return 0; 2620 } 2621 2622 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2623 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2624 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2625 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2626 #ifdef CONFIG_DRM_AMD_DC_HDCP 2627 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2628 #endif 2629 DEFINE_SHOW_ATTRIBUTE(internal_display); 2630 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2631 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2632 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2633 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2634 2635 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2636 .owner = THIS_MODULE, 2637 .read = dp_dsc_clock_en_read, 2638 .write = dp_dsc_clock_en_write, 2639 .llseek = default_llseek 2640 }; 2641 2642 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2643 .owner = THIS_MODULE, 2644 .read = dp_dsc_slice_width_read, 2645 .write = dp_dsc_slice_width_write, 2646 .llseek = default_llseek 2647 }; 2648 2649 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2650 .owner = THIS_MODULE, 2651 .read = dp_dsc_slice_height_read, 2652 .write = dp_dsc_slice_height_write, 2653 .llseek = default_llseek 2654 }; 2655 2656 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2657 .owner = THIS_MODULE, 2658 .read = dp_dsc_bits_per_pixel_read, 2659 .write = dp_dsc_bits_per_pixel_write, 2660 .llseek = default_llseek 2661 }; 2662 2663 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2664 .owner = THIS_MODULE, 2665 .read = dp_dsc_pic_width_read, 2666 .llseek = default_llseek 2667 }; 2668 2669 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2670 .owner = THIS_MODULE, 2671 .read = dp_dsc_pic_height_read, 2672 .llseek = default_llseek 2673 }; 2674 2675 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2676 .owner = THIS_MODULE, 2677 .read = dp_dsc_chunk_size_read, 2678 .llseek = default_llseek 2679 }; 2680 2681 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2682 .owner = THIS_MODULE, 2683 .read = dp_dsc_slice_bpg_offset_read, 2684 .llseek = default_llseek 2685 }; 2686 2687 static const struct file_operations trigger_hotplug_debugfs_fops = { 2688 .owner = THIS_MODULE, 2689 .write = trigger_hotplug, 2690 .llseek = default_llseek 2691 }; 2692 2693 static const struct file_operations dp_link_settings_debugfs_fops = { 2694 .owner = THIS_MODULE, 2695 .read = dp_link_settings_read, 2696 .write = dp_link_settings_write, 2697 .llseek = default_llseek 2698 }; 2699 2700 static const struct file_operations dp_phy_settings_debugfs_fop = { 2701 .owner = THIS_MODULE, 2702 .read = dp_phy_settings_read, 2703 .write = dp_phy_settings_write, 2704 .llseek = default_llseek 2705 }; 2706 2707 static const struct file_operations dp_phy_test_pattern_fops = { 2708 .owner = THIS_MODULE, 2709 .write = dp_phy_test_pattern_debugfs_write, 2710 .llseek = default_llseek 2711 }; 2712 2713 static const struct file_operations sdp_message_fops = { 2714 .owner = THIS_MODULE, 2715 .write = dp_sdp_message_debugfs_write, 2716 .llseek = default_llseek 2717 }; 2718 2719 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2720 .owner = THIS_MODULE, 2721 .write = dp_dpcd_address_write, 2722 .llseek = default_llseek 2723 }; 2724 2725 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2726 .owner = THIS_MODULE, 2727 .write = dp_dpcd_size_write, 2728 .llseek = default_llseek 2729 }; 2730 2731 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2732 .owner = THIS_MODULE, 2733 .read = dp_dpcd_data_read, 2734 .write = dp_dpcd_data_write, 2735 .llseek = default_llseek 2736 }; 2737 2738 static const struct file_operations dp_max_bpc_debugfs_fops = { 2739 .owner = THIS_MODULE, 2740 .read = dp_max_bpc_read, 2741 .write = dp_max_bpc_write, 2742 .llseek = default_llseek 2743 }; 2744 2745 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2746 .owner = THIS_MODULE, 2747 .write = dp_dsc_passthrough_set, 2748 .llseek = default_llseek 2749 }; 2750 2751 static const struct { 2752 char *name; 2753 const struct file_operations *fops; 2754 } dp_debugfs_entries[] = { 2755 {"link_settings", &dp_link_settings_debugfs_fops}, 2756 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2757 {"lttpr_status", &dp_lttpr_status_fops}, 2758 {"test_pattern", &dp_phy_test_pattern_fops}, 2759 #ifdef CONFIG_DRM_AMD_DC_HDCP 2760 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2761 #endif 2762 {"sdp_message", &sdp_message_fops}, 2763 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2764 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2765 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2766 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2767 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2768 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2769 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2770 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2771 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2772 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2773 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2774 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2775 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2776 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2777 {"is_mst_connector", &dp_is_mst_connector_fops}, 2778 {"mst_progress_status", &dp_mst_progress_status_fops}, 2779 {"is_dpia_link", &is_dpia_link_fops} 2780 }; 2781 2782 #ifdef CONFIG_DRM_AMD_DC_HDCP 2783 static const struct { 2784 char *name; 2785 const struct file_operations *fops; 2786 } hdmi_debugfs_entries[] = { 2787 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2788 }; 2789 #endif 2790 /* 2791 * Force YUV420 output if available from the given mode 2792 */ 2793 static int force_yuv420_output_set(void *data, u64 val) 2794 { 2795 struct amdgpu_dm_connector *connector = data; 2796 2797 connector->force_yuv420_output = (bool)val; 2798 2799 return 0; 2800 } 2801 2802 /* 2803 * Check if YUV420 is forced when available from the given mode 2804 */ 2805 static int force_yuv420_output_get(void *data, u64 *val) 2806 { 2807 struct amdgpu_dm_connector *connector = data; 2808 2809 *val = connector->force_yuv420_output; 2810 2811 return 0; 2812 } 2813 2814 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2815 force_yuv420_output_set, "%llu\n"); 2816 2817 /* 2818 * Read PSR state 2819 */ 2820 static int psr_get(void *data, u64 *val) 2821 { 2822 struct amdgpu_dm_connector *connector = data; 2823 struct dc_link *link = connector->dc_link; 2824 enum dc_psr_state state = PSR_STATE0; 2825 2826 dc_link_get_psr_state(link, &state); 2827 2828 *val = state; 2829 2830 return 0; 2831 } 2832 2833 /* 2834 * Set dmcub trace event IRQ enable or disable. 2835 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2836 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2837 */ 2838 static int dmcub_trace_event_state_set(void *data, u64 val) 2839 { 2840 struct amdgpu_device *adev = data; 2841 2842 if (val == 1 || val == 0) { 2843 dc_dmub_trace_event_control(adev->dm.dc, val); 2844 adev->dm.dmcub_trace_event_en = (bool)val; 2845 } else 2846 return 0; 2847 2848 return 0; 2849 } 2850 2851 /* 2852 * The interface doesn't need get function, so it will return the 2853 * value of zero 2854 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2855 */ 2856 static int dmcub_trace_event_state_get(void *data, u64 *val) 2857 { 2858 struct amdgpu_device *adev = data; 2859 2860 *val = adev->dm.dmcub_trace_event_en; 2861 return 0; 2862 } 2863 2864 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2865 dmcub_trace_event_state_set, "%llu\n"); 2866 2867 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2868 2869 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2870 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2871 2872 static const struct { 2873 char *name; 2874 const struct file_operations *fops; 2875 } connector_debugfs_entries[] = { 2876 {"force_yuv420_output", &force_yuv420_output_fops}, 2877 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2878 {"internal_display", &internal_display_fops} 2879 }; 2880 2881 /* 2882 * Returns supported customized link rates by this eDP panel. 2883 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2884 */ 2885 static int edp_ilr_show(struct seq_file *m, void *unused) 2886 { 2887 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2888 struct dc_link *link = aconnector->dc_link; 2889 uint8_t supported_link_rates[16]; 2890 uint32_t link_rate_in_khz; 2891 uint32_t entry = 0; 2892 uint8_t dpcd_rev; 2893 2894 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2895 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2896 supported_link_rates, sizeof(supported_link_rates)); 2897 2898 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2899 2900 if (dpcd_rev >= DP_DPCD_REV_13 && 2901 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2902 2903 for (entry = 0; entry < 16; entry += 2) { 2904 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2905 supported_link_rates[entry]) * 200; 2906 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2907 } 2908 } else { 2909 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2910 } 2911 2912 return 0; 2913 } 2914 2915 /* 2916 * Set supported customized link rate to eDP panel. 2917 * 2918 * echo <lane_count> <link_rate option> > ilr_setting 2919 * 2920 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2921 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2922 * to set 4 lanes and 2.16 GHz 2923 */ 2924 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2925 size_t size, loff_t *pos) 2926 { 2927 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2928 struct dc_link *link = connector->dc_link; 2929 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2930 struct dc *dc = (struct dc *)link->dc; 2931 struct dc_link_settings prefer_link_settings; 2932 char *wr_buf = NULL; 2933 const uint32_t wr_buf_size = 40; 2934 /* 0: lane_count; 1: link_rate */ 2935 int max_param_num = 2; 2936 uint8_t param_nums = 0; 2937 long param[2]; 2938 bool valid_input = true; 2939 2940 if (size == 0) 2941 return -EINVAL; 2942 2943 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2944 if (!wr_buf) 2945 return -ENOMEM; 2946 2947 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2948 (long *)param, buf, 2949 max_param_num, 2950 ¶m_nums)) { 2951 kfree(wr_buf); 2952 return -EINVAL; 2953 } 2954 2955 if (param_nums <= 0) { 2956 kfree(wr_buf); 2957 return -EINVAL; 2958 } 2959 2960 switch (param[0]) { 2961 case LANE_COUNT_ONE: 2962 case LANE_COUNT_TWO: 2963 case LANE_COUNT_FOUR: 2964 break; 2965 default: 2966 valid_input = false; 2967 break; 2968 } 2969 2970 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2971 valid_input = false; 2972 2973 if (!valid_input) { 2974 kfree(wr_buf); 2975 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2976 prefer_link_settings.use_link_rate_set = false; 2977 mutex_lock(&adev->dm.dc_lock); 2978 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2979 mutex_unlock(&adev->dm.dc_lock); 2980 return size; 2981 } 2982 2983 /* save user force lane_count, link_rate to preferred settings 2984 * spread spectrum will not be changed 2985 */ 2986 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2987 prefer_link_settings.lane_count = param[0]; 2988 prefer_link_settings.use_link_rate_set = true; 2989 prefer_link_settings.link_rate_set = param[1]; 2990 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2991 2992 mutex_lock(&adev->dm.dc_lock); 2993 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2994 NULL, link, false); 2995 mutex_unlock(&adev->dm.dc_lock); 2996 2997 kfree(wr_buf); 2998 return size; 2999 } 3000 3001 static int edp_ilr_open(struct inode *inode, struct file *file) 3002 { 3003 return single_open(file, edp_ilr_show, inode->i_private); 3004 } 3005 3006 static const struct file_operations edp_ilr_debugfs_fops = { 3007 .owner = THIS_MODULE, 3008 .open = edp_ilr_open, 3009 .read = seq_read, 3010 .llseek = seq_lseek, 3011 .release = single_release, 3012 .write = edp_ilr_write 3013 }; 3014 3015 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3016 { 3017 int i; 3018 struct dentry *dir = connector->base.debugfs_entry; 3019 3020 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3021 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3022 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3023 debugfs_create_file(dp_debugfs_entries[i].name, 3024 0644, dir, connector, 3025 dp_debugfs_entries[i].fops); 3026 } 3027 } 3028 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3029 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3030 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3031 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3032 ¤t_backlight_fops); 3033 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3034 &target_backlight_fops); 3035 debugfs_create_file("ilr_setting", 0644, dir, connector, 3036 &edp_ilr_debugfs_fops); 3037 } 3038 3039 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3040 debugfs_create_file(connector_debugfs_entries[i].name, 3041 0644, dir, connector, 3042 connector_debugfs_entries[i].fops); 3043 } 3044 3045 connector->debugfs_dpcd_address = 0; 3046 connector->debugfs_dpcd_size = 0; 3047 3048 #ifdef CONFIG_DRM_AMD_DC_HDCP 3049 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3050 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3051 debugfs_create_file(hdmi_debugfs_entries[i].name, 3052 0644, dir, connector, 3053 hdmi_debugfs_entries[i].fops); 3054 } 3055 } 3056 #endif 3057 } 3058 3059 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3060 /* 3061 * Set crc window coordinate x start 3062 */ 3063 static int crc_win_x_start_set(void *data, u64 val) 3064 { 3065 struct drm_crtc *crtc = data; 3066 struct drm_device *drm_dev = crtc->dev; 3067 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3068 3069 spin_lock_irq(&drm_dev->event_lock); 3070 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3071 acrtc->dm_irq_params.window_param.update_win = false; 3072 spin_unlock_irq(&drm_dev->event_lock); 3073 3074 return 0; 3075 } 3076 3077 /* 3078 * Get crc window coordinate x start 3079 */ 3080 static int crc_win_x_start_get(void *data, u64 *val) 3081 { 3082 struct drm_crtc *crtc = data; 3083 struct drm_device *drm_dev = crtc->dev; 3084 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3085 3086 spin_lock_irq(&drm_dev->event_lock); 3087 *val = acrtc->dm_irq_params.window_param.x_start; 3088 spin_unlock_irq(&drm_dev->event_lock); 3089 3090 return 0; 3091 } 3092 3093 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3094 crc_win_x_start_set, "%llu\n"); 3095 3096 3097 /* 3098 * Set crc window coordinate y start 3099 */ 3100 static int crc_win_y_start_set(void *data, u64 val) 3101 { 3102 struct drm_crtc *crtc = data; 3103 struct drm_device *drm_dev = crtc->dev; 3104 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3105 3106 spin_lock_irq(&drm_dev->event_lock); 3107 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3108 acrtc->dm_irq_params.window_param.update_win = false; 3109 spin_unlock_irq(&drm_dev->event_lock); 3110 3111 return 0; 3112 } 3113 3114 /* 3115 * Get crc window coordinate y start 3116 */ 3117 static int crc_win_y_start_get(void *data, u64 *val) 3118 { 3119 struct drm_crtc *crtc = data; 3120 struct drm_device *drm_dev = crtc->dev; 3121 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3122 3123 spin_lock_irq(&drm_dev->event_lock); 3124 *val = acrtc->dm_irq_params.window_param.y_start; 3125 spin_unlock_irq(&drm_dev->event_lock); 3126 3127 return 0; 3128 } 3129 3130 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3131 crc_win_y_start_set, "%llu\n"); 3132 3133 /* 3134 * Set crc window coordinate x end 3135 */ 3136 static int crc_win_x_end_set(void *data, u64 val) 3137 { 3138 struct drm_crtc *crtc = data; 3139 struct drm_device *drm_dev = crtc->dev; 3140 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3141 3142 spin_lock_irq(&drm_dev->event_lock); 3143 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3144 acrtc->dm_irq_params.window_param.update_win = false; 3145 spin_unlock_irq(&drm_dev->event_lock); 3146 3147 return 0; 3148 } 3149 3150 /* 3151 * Get crc window coordinate x end 3152 */ 3153 static int crc_win_x_end_get(void *data, u64 *val) 3154 { 3155 struct drm_crtc *crtc = data; 3156 struct drm_device *drm_dev = crtc->dev; 3157 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3158 3159 spin_lock_irq(&drm_dev->event_lock); 3160 *val = acrtc->dm_irq_params.window_param.x_end; 3161 spin_unlock_irq(&drm_dev->event_lock); 3162 3163 return 0; 3164 } 3165 3166 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3167 crc_win_x_end_set, "%llu\n"); 3168 3169 /* 3170 * Set crc window coordinate y end 3171 */ 3172 static int crc_win_y_end_set(void *data, u64 val) 3173 { 3174 struct drm_crtc *crtc = data; 3175 struct drm_device *drm_dev = crtc->dev; 3176 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3177 3178 spin_lock_irq(&drm_dev->event_lock); 3179 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3180 acrtc->dm_irq_params.window_param.update_win = false; 3181 spin_unlock_irq(&drm_dev->event_lock); 3182 3183 return 0; 3184 } 3185 3186 /* 3187 * Get crc window coordinate y end 3188 */ 3189 static int crc_win_y_end_get(void *data, u64 *val) 3190 { 3191 struct drm_crtc *crtc = data; 3192 struct drm_device *drm_dev = crtc->dev; 3193 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3194 3195 spin_lock_irq(&drm_dev->event_lock); 3196 *val = acrtc->dm_irq_params.window_param.y_end; 3197 spin_unlock_irq(&drm_dev->event_lock); 3198 3199 return 0; 3200 } 3201 3202 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3203 crc_win_y_end_set, "%llu\n"); 3204 /* 3205 * Trigger to commit crc window 3206 */ 3207 static int crc_win_update_set(void *data, u64 val) 3208 { 3209 struct drm_crtc *crtc = data; 3210 struct amdgpu_crtc *acrtc; 3211 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3212 3213 if (val) { 3214 acrtc = to_amdgpu_crtc(crtc); 3215 mutex_lock(&adev->dm.dc_lock); 3216 /* PSR may write to OTG CRC window control register, 3217 * so close it before starting secure_display. 3218 */ 3219 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3220 3221 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3222 3223 acrtc->dm_irq_params.window_param.activated = true; 3224 acrtc->dm_irq_params.window_param.update_win = true; 3225 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3226 3227 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3228 mutex_unlock(&adev->dm.dc_lock); 3229 } 3230 3231 return 0; 3232 } 3233 3234 /* 3235 * Get crc window update flag 3236 */ 3237 static int crc_win_update_get(void *data, u64 *val) 3238 { 3239 *val = 0; 3240 return 0; 3241 } 3242 3243 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3244 crc_win_update_set, "%llu\n"); 3245 #endif 3246 void crtc_debugfs_init(struct drm_crtc *crtc) 3247 { 3248 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3249 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3250 3251 if (!dir) 3252 return; 3253 3254 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3255 &crc_win_x_start_fops); 3256 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3257 &crc_win_y_start_fops); 3258 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3259 &crc_win_x_end_fops); 3260 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3261 &crc_win_y_end_fops); 3262 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3263 &crc_win_update_fops); 3264 dput(dir); 3265 #endif 3266 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3267 crtc, &amdgpu_current_bpc_fops); 3268 } 3269 3270 /* 3271 * Writes DTN log state to the user supplied buffer. 3272 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3273 */ 3274 static ssize_t dtn_log_read( 3275 struct file *f, 3276 char __user *buf, 3277 size_t size, 3278 loff_t *pos) 3279 { 3280 struct amdgpu_device *adev = file_inode(f)->i_private; 3281 struct dc *dc = adev->dm.dc; 3282 struct dc_log_buffer_ctx log_ctx = { 0 }; 3283 ssize_t result = 0; 3284 3285 if (!buf || !size) 3286 return -EINVAL; 3287 3288 if (!dc->hwss.log_hw_state) 3289 return 0; 3290 3291 dc->hwss.log_hw_state(dc, &log_ctx); 3292 3293 if (*pos < log_ctx.pos) { 3294 size_t to_copy = log_ctx.pos - *pos; 3295 3296 to_copy = min(to_copy, size); 3297 3298 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3299 *pos += to_copy; 3300 result = to_copy; 3301 } 3302 } 3303 3304 kfree(log_ctx.buf); 3305 3306 return result; 3307 } 3308 3309 /* 3310 * Writes DTN log state to dmesg when triggered via a write. 3311 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3312 */ 3313 static ssize_t dtn_log_write( 3314 struct file *f, 3315 const char __user *buf, 3316 size_t size, 3317 loff_t *pos) 3318 { 3319 struct amdgpu_device *adev = file_inode(f)->i_private; 3320 struct dc *dc = adev->dm.dc; 3321 3322 /* Write triggers log output via dmesg. */ 3323 if (size == 0) 3324 return 0; 3325 3326 if (dc->hwss.log_hw_state) 3327 dc->hwss.log_hw_state(dc, NULL); 3328 3329 return size; 3330 } 3331 3332 static int mst_topo_show(struct seq_file *m, void *unused) 3333 { 3334 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3335 struct drm_device *dev = adev_to_drm(adev); 3336 struct drm_connector *connector; 3337 struct drm_connector_list_iter conn_iter; 3338 struct amdgpu_dm_connector *aconnector; 3339 3340 drm_connector_list_iter_begin(dev, &conn_iter); 3341 drm_for_each_connector_iter(connector, &conn_iter) { 3342 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3343 continue; 3344 3345 aconnector = to_amdgpu_dm_connector(connector); 3346 3347 /* Ensure we're only dumping the topology of a root mst node */ 3348 if (!aconnector->mst_mgr.mst_state) 3349 continue; 3350 3351 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3352 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3353 } 3354 drm_connector_list_iter_end(&conn_iter); 3355 3356 return 0; 3357 } 3358 3359 /* 3360 * Sets trigger hpd for MST topologies. 3361 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3362 * All topologies will be disconnected if val of 0 is set . 3363 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3364 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3365 */ 3366 static int trigger_hpd_mst_set(void *data, u64 val) 3367 { 3368 struct amdgpu_device *adev = data; 3369 struct drm_device *dev = adev_to_drm(adev); 3370 struct drm_connector_list_iter iter; 3371 struct amdgpu_dm_connector *aconnector; 3372 struct drm_connector *connector; 3373 struct dc_link *link = NULL; 3374 3375 if (val == 1) { 3376 drm_connector_list_iter_begin(dev, &iter); 3377 drm_for_each_connector_iter(connector, &iter) { 3378 aconnector = to_amdgpu_dm_connector(connector); 3379 if (aconnector->dc_link->type == dc_connection_mst_branch && 3380 aconnector->mst_mgr.aux) { 3381 mutex_lock(&adev->dm.dc_lock); 3382 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3383 mutex_unlock(&adev->dm.dc_lock); 3384 3385 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3386 } 3387 } 3388 } else if (val == 0) { 3389 drm_connector_list_iter_begin(dev, &iter); 3390 drm_for_each_connector_iter(connector, &iter) { 3391 aconnector = to_amdgpu_dm_connector(connector); 3392 if (!aconnector->dc_link) 3393 continue; 3394 3395 if (!aconnector->mst_port) 3396 continue; 3397 3398 link = aconnector->dc_link; 3399 dc_link_dp_receiver_power_ctrl(link, false); 3400 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3401 link->mst_stream_alloc_table.stream_count = 0; 3402 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3403 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3404 } 3405 } else { 3406 return 0; 3407 } 3408 drm_kms_helper_hotplug_event(dev); 3409 3410 return 0; 3411 } 3412 3413 /* 3414 * The interface doesn't need get function, so it will return the 3415 * value of zero 3416 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3417 */ 3418 static int trigger_hpd_mst_get(void *data, u64 *val) 3419 { 3420 *val = 0; 3421 return 0; 3422 } 3423 3424 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3425 trigger_hpd_mst_set, "%llu\n"); 3426 3427 3428 /* 3429 * Sets the force_timing_sync debug option from the given string. 3430 * All connected displays will be force synchronized immediately. 3431 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3432 */ 3433 static int force_timing_sync_set(void *data, u64 val) 3434 { 3435 struct amdgpu_device *adev = data; 3436 3437 adev->dm.force_timing_sync = (bool)val; 3438 3439 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3440 3441 return 0; 3442 } 3443 3444 /* 3445 * Gets the force_timing_sync debug option value into the given buffer. 3446 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3447 */ 3448 static int force_timing_sync_get(void *data, u64 *val) 3449 { 3450 struct amdgpu_device *adev = data; 3451 3452 *val = adev->dm.force_timing_sync; 3453 3454 return 0; 3455 } 3456 3457 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3458 force_timing_sync_set, "%llu\n"); 3459 3460 3461 /* 3462 * Disables all HPD and HPD RX interrupt handling in the 3463 * driver when set to 1. Default is 0. 3464 */ 3465 static int disable_hpd_set(void *data, u64 val) 3466 { 3467 struct amdgpu_device *adev = data; 3468 3469 adev->dm.disable_hpd_irq = (bool)val; 3470 3471 return 0; 3472 } 3473 3474 3475 /* 3476 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3477 * 0 otherwise. 3478 */ 3479 static int disable_hpd_get(void *data, u64 *val) 3480 { 3481 struct amdgpu_device *adev = data; 3482 3483 *val = adev->dm.disable_hpd_irq; 3484 3485 return 0; 3486 } 3487 3488 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3489 disable_hpd_set, "%llu\n"); 3490 3491 /* 3492 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3493 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3494 */ 3495 static int dp_force_sst_set(void *data, u64 val) 3496 { 3497 struct amdgpu_device *adev = data; 3498 3499 adev->dm.dc->debug.set_mst_en_for_sst = val; 3500 3501 return 0; 3502 } 3503 3504 static int dp_force_sst_get(void *data, u64 *val) 3505 { 3506 struct amdgpu_device *adev = data; 3507 3508 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3509 3510 return 0; 3511 } 3512 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3513 dp_force_sst_set, "%llu\n"); 3514 3515 /* 3516 * Force DP2 sequence without VESA certified cable. 3517 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3518 */ 3519 static int dp_ignore_cable_id_set(void *data, u64 val) 3520 { 3521 struct amdgpu_device *adev = data; 3522 3523 adev->dm.dc->debug.ignore_cable_id = val; 3524 3525 return 0; 3526 } 3527 3528 static int dp_ignore_cable_id_get(void *data, u64 *val) 3529 { 3530 struct amdgpu_device *adev = data; 3531 3532 *val = adev->dm.dc->debug.ignore_cable_id; 3533 3534 return 0; 3535 } 3536 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3537 dp_ignore_cable_id_set, "%llu\n"); 3538 3539 /* 3540 * Sets the DC visual confirm debug option from the given string. 3541 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3542 */ 3543 static int visual_confirm_set(void *data, u64 val) 3544 { 3545 struct amdgpu_device *adev = data; 3546 3547 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3548 3549 return 0; 3550 } 3551 3552 /* 3553 * Reads the DC visual confirm debug option value into the given buffer. 3554 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3555 */ 3556 static int visual_confirm_get(void *data, u64 *val) 3557 { 3558 struct amdgpu_device *adev = data; 3559 3560 *val = adev->dm.dc->debug.visual_confirm; 3561 3562 return 0; 3563 } 3564 3565 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3566 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3567 visual_confirm_set, "%llu\n"); 3568 3569 3570 /* 3571 * Sets the DC skip_detection_link_training debug option from the given string. 3572 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3573 */ 3574 static int skip_detection_link_training_set(void *data, u64 val) 3575 { 3576 struct amdgpu_device *adev = data; 3577 3578 if (val == 0) 3579 adev->dm.dc->debug.skip_detection_link_training = false; 3580 else 3581 adev->dm.dc->debug.skip_detection_link_training = true; 3582 3583 return 0; 3584 } 3585 3586 /* 3587 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3588 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3589 */ 3590 static int skip_detection_link_training_get(void *data, u64 *val) 3591 { 3592 struct amdgpu_device *adev = data; 3593 3594 *val = adev->dm.dc->debug.skip_detection_link_training; 3595 3596 return 0; 3597 } 3598 3599 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3600 skip_detection_link_training_get, 3601 skip_detection_link_training_set, "%llu\n"); 3602 3603 /* 3604 * Dumps the DCC_EN bit for each pipe. 3605 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3606 */ 3607 static ssize_t dcc_en_bits_read( 3608 struct file *f, 3609 char __user *buf, 3610 size_t size, 3611 loff_t *pos) 3612 { 3613 struct amdgpu_device *adev = file_inode(f)->i_private; 3614 struct dc *dc = adev->dm.dc; 3615 char *rd_buf = NULL; 3616 const uint32_t rd_buf_size = 32; 3617 uint32_t result = 0; 3618 int offset = 0; 3619 int num_pipes = dc->res_pool->pipe_count; 3620 int *dcc_en_bits; 3621 int i, r; 3622 3623 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3624 if (!dcc_en_bits) 3625 return -ENOMEM; 3626 3627 if (!dc->hwss.get_dcc_en_bits) { 3628 kfree(dcc_en_bits); 3629 return 0; 3630 } 3631 3632 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3633 3634 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3635 if (!rd_buf) { 3636 kfree(dcc_en_bits); 3637 return -ENOMEM; 3638 } 3639 3640 for (i = 0; i < num_pipes; i++) 3641 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3642 "%d ", dcc_en_bits[i]); 3643 rd_buf[strlen(rd_buf)] = '\n'; 3644 3645 kfree(dcc_en_bits); 3646 3647 while (size) { 3648 if (*pos >= rd_buf_size) 3649 break; 3650 r = put_user(*(rd_buf + result), buf); 3651 if (r) { 3652 kfree(rd_buf); 3653 return r; /* r = -EFAULT */ 3654 } 3655 buf += 1; 3656 size -= 1; 3657 *pos += 1; 3658 result += 1; 3659 } 3660 3661 kfree(rd_buf); 3662 return result; 3663 } 3664 3665 void dtn_debugfs_init(struct amdgpu_device *adev) 3666 { 3667 static const struct file_operations dtn_log_fops = { 3668 .owner = THIS_MODULE, 3669 .read = dtn_log_read, 3670 .write = dtn_log_write, 3671 .llseek = default_llseek 3672 }; 3673 static const struct file_operations dcc_en_bits_fops = { 3674 .owner = THIS_MODULE, 3675 .read = dcc_en_bits_read, 3676 .llseek = default_llseek 3677 }; 3678 3679 struct drm_minor *minor = adev_to_drm(adev)->primary; 3680 struct dentry *root = minor->debugfs_root; 3681 3682 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3683 adev, &mst_topo_fops); 3684 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3685 &dtn_log_fops); 3686 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3687 &dp_set_mst_en_for_sst_ops); 3688 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3689 &dp_ignore_cable_id_ops); 3690 3691 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3692 &visual_confirm_fops); 3693 3694 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3695 &skip_detection_link_training_fops); 3696 3697 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3698 adev, &dmub_tracebuffer_fops); 3699 3700 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3701 adev, &dmub_fw_state_fops); 3702 3703 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3704 adev, &force_timing_sync_ops); 3705 3706 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3707 adev, &dmcub_trace_event_state_fops); 3708 3709 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3710 adev, &trigger_hpd_mst_ops); 3711 3712 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3713 &dcc_en_bits_fops); 3714 3715 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3716 &disable_hpd_ops); 3717 3718 } 3719