1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "amdgpu_dm_replay.h" 34 #include "dm_helpers.h" 35 #include "dmub/dmub_srv.h" 36 #include "resource.h" 37 #include "dsc.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 #include "link/protocols/link_dp_capability.h" 41 #include "inc/hw/dchubbub.h" 42 43 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 44 #include "amdgpu_dm_psr.h" 45 #endif 46 47 struct dmub_debugfs_trace_header { 48 uint32_t entry_count; 49 uint32_t reserved[3]; 50 }; 51 52 struct dmub_debugfs_trace_entry { 53 uint32_t trace_code; 54 uint32_t tick_count; 55 uint32_t param0; 56 uint32_t param1; 57 }; 58 59 static const char *const mst_progress_status[] = { 60 "probe", 61 "remote_edid", 62 "allocate_new_payload", 63 "clear_allocated_payload", 64 }; 65 66 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 67 * 68 * Function takes in attributes passed to debugfs write entry 69 * and writes into param array. 70 * The user passes max_param_num to identify maximum number of 71 * parameters that could be parsed. 72 * 73 */ 74 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 75 long *param, const char __user *buf, 76 int max_param_num, 77 uint8_t *param_nums) 78 { 79 char *wr_buf_ptr = NULL; 80 uint32_t wr_buf_count = 0; 81 int r; 82 char *sub_str = NULL; 83 const char delimiter[3] = {' ', '\n', '\0'}; 84 uint8_t param_index = 0; 85 86 *param_nums = 0; 87 88 wr_buf_ptr = wr_buf; 89 90 /* r is bytes not be copied */ 91 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 92 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 93 return -EFAULT; 94 } 95 96 /* check number of parameters. isspace could not differ space and \n */ 97 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 98 /* skip space*/ 99 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 100 wr_buf_ptr++; 101 wr_buf_count++; 102 } 103 104 if (wr_buf_count == wr_buf_size) 105 break; 106 107 /* skip non-space*/ 108 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 109 wr_buf_ptr++; 110 wr_buf_count++; 111 } 112 113 (*param_nums)++; 114 115 if (wr_buf_count == wr_buf_size) 116 break; 117 } 118 119 if (*param_nums > max_param_num) 120 *param_nums = max_param_num; 121 122 wr_buf_ptr = wr_buf; /* reset buf pointer */ 123 wr_buf_count = 0; /* number of char already checked */ 124 125 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 126 wr_buf_ptr++; 127 wr_buf_count++; 128 } 129 130 while (param_index < *param_nums) { 131 /* after strsep, wr_buf_ptr will be moved to after space */ 132 sub_str = strsep(&wr_buf_ptr, delimiter); 133 134 r = kstrtol(sub_str, 16, &(param[param_index])); 135 136 if (r) 137 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 138 139 param_index++; 140 } 141 142 return 0; 143 } 144 145 /* function description 146 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 147 * 148 * valid lane count value: 1, 2, 4 149 * valid link rate value: 150 * 06h = 1.62Gbps per lane 151 * 0Ah = 2.7Gbps per lane 152 * 0Ch = 3.24Gbps per lane 153 * 14h = 5.4Gbps per lane 154 * 1Eh = 8.1Gbps per lane 155 * 156 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 157 * 158 * --- to get dp configuration 159 * 160 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * It will list current, verified, reported, preferred dp configuration. 163 * current -- for current video mode 164 * verified --- maximum configuration which pass link training 165 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 166 * preferred --- user force settings 167 * 168 * --- set (or force) dp configuration 169 * 170 * echo <lane_count> <link_rate> > link_settings 171 * 172 * for example, to force to 2 lane, 2.7GHz, 173 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 174 * 175 * spread_spectrum could not be changed dynamically. 176 * 177 * in case invalid lane count, link rate are force, no hw programming will be 178 * done. please check link settings after force operation to see if HW get 179 * programming. 180 * 181 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 182 * 183 * check current and preferred settings. 184 * 185 */ 186 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 187 size_t size, loff_t *pos) 188 { 189 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 190 struct dc_link *link = connector->dc_link; 191 char *rd_buf = NULL; 192 char *rd_buf_ptr = NULL; 193 const uint32_t rd_buf_size = 100; 194 uint32_t result = 0; 195 uint8_t str_len = 0; 196 int r; 197 198 if (*pos & 3 || size & 3) 199 return -EINVAL; 200 201 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 202 if (!rd_buf) 203 return 0; 204 205 rd_buf_ptr = rd_buf; 206 207 str_len = strlen("Current: %d 0x%x %d "); 208 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 209 link->cur_link_settings.lane_count, 210 link->cur_link_settings.link_rate, 211 link->cur_link_settings.link_spread); 212 rd_buf_ptr += str_len; 213 214 str_len = strlen("Verified: %d 0x%x %d "); 215 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 216 link->verified_link_cap.lane_count, 217 link->verified_link_cap.link_rate, 218 link->verified_link_cap.link_spread); 219 rd_buf_ptr += str_len; 220 221 str_len = strlen("Reported: %d 0x%x %d "); 222 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 223 link->reported_link_cap.lane_count, 224 link->reported_link_cap.link_rate, 225 link->reported_link_cap.link_spread); 226 rd_buf_ptr += str_len; 227 228 str_len = strlen("Preferred: %d 0x%x %d "); 229 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 230 link->preferred_link_setting.lane_count, 231 link->preferred_link_setting.link_rate, 232 link->preferred_link_setting.link_spread); 233 234 while (size) { 235 if (*pos >= rd_buf_size) 236 break; 237 238 r = put_user(*(rd_buf + result), buf); 239 if (r) { 240 kfree(rd_buf); 241 return r; /* r = -EFAULT */ 242 } 243 244 buf += 1; 245 size -= 1; 246 *pos += 1; 247 result += 1; 248 } 249 250 kfree(rd_buf); 251 return result; 252 } 253 254 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 255 size_t size, loff_t *pos) 256 { 257 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 258 struct dc_link *link = connector->dc_link; 259 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 260 struct dc *dc = (struct dc *)link->dc; 261 struct dc_link_settings prefer_link_settings = {0}; 262 char *wr_buf = NULL; 263 const uint32_t wr_buf_size = 40; 264 /* 0: lane_count; 1: link_rate */ 265 int max_param_num = 2; 266 uint8_t param_nums = 0; 267 long param[2]; 268 bool valid_input = true; 269 270 if (size == 0) 271 return -EINVAL; 272 273 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 274 if (!wr_buf) 275 return -ENOSPC; 276 277 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 278 (long *)param, buf, 279 max_param_num, 280 ¶m_nums)) { 281 kfree(wr_buf); 282 return -EINVAL; 283 } 284 285 if (param_nums <= 0) { 286 kfree(wr_buf); 287 DRM_DEBUG_DRIVER("user data not be read\n"); 288 return -EINVAL; 289 } 290 291 switch (param[0]) { 292 case LANE_COUNT_ONE: 293 case LANE_COUNT_TWO: 294 case LANE_COUNT_FOUR: 295 break; 296 default: 297 valid_input = false; 298 break; 299 } 300 301 switch (param[1]) { 302 case LINK_RATE_LOW: 303 case LINK_RATE_HIGH: 304 case LINK_RATE_RBR2: 305 case LINK_RATE_HIGH2: 306 case LINK_RATE_HIGH3: 307 case LINK_RATE_UHBR10: 308 case LINK_RATE_UHBR13_5: 309 case LINK_RATE_UHBR20: 310 break; 311 default: 312 valid_input = false; 313 break; 314 } 315 316 if (!valid_input) { 317 kfree(wr_buf); 318 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 319 mutex_lock(&adev->dm.dc_lock); 320 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 321 mutex_unlock(&adev->dm.dc_lock); 322 return size; 323 } 324 325 /* save user force lane_count, link_rate to preferred settings 326 * spread spectrum will not be changed 327 */ 328 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 329 prefer_link_settings.use_link_rate_set = false; 330 prefer_link_settings.lane_count = param[0]; 331 prefer_link_settings.link_rate = param[1]; 332 333 mutex_lock(&adev->dm.dc_lock); 334 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 335 mutex_unlock(&adev->dm.dc_lock); 336 337 kfree(wr_buf); 338 return size; 339 } 340 341 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) 342 { 343 bool is_end_device = false; 344 struct drm_dp_mst_topology_mgr *mgr = NULL; 345 struct drm_dp_mst_port *port = NULL; 346 347 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) { 348 mgr = &aconnector->mst_root->mst_mgr; 349 port = aconnector->mst_output_port; 350 351 drm_modeset_lock(&mgr->base.lock, NULL); 352 if (port->pdt == DP_PEER_DEVICE_SST_SINK || 353 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) 354 is_end_device = true; 355 drm_modeset_unlock(&mgr->base.lock); 356 } 357 358 return is_end_device; 359 } 360 361 /* Change MST link setting 362 * 363 * valid lane count value: 1, 2, 4 364 * valid link rate value: 365 * 06h = 1.62Gbps per lane 366 * 0Ah = 2.7Gbps per lane 367 * 0Ch = 3.24Gbps per lane 368 * 14h = 5.4Gbps per lane 369 * 1Eh = 8.1Gbps per lane 370 * 3E8h = 10.0Gbps per lane 371 * 546h = 13.5Gbps per lane 372 * 7D0h = 20.0Gbps per lane 373 * 374 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings 375 * 376 * for example, to force to 2 lane, 10.0GHz, 377 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings 378 * 379 * Valid input will trigger hotplug event to get new link setting applied 380 * Invalid input will trigger training setting reset 381 * 382 * The usage can be referred to link_settings entry 383 * 384 */ 385 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, 386 size_t size, loff_t *pos) 387 { 388 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 389 struct dc_link *link = aconnector->dc_link; 390 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 391 struct dc *dc = (struct dc *)link->dc; 392 struct dc_link_settings prefer_link_settings = {0}; 393 char *wr_buf = NULL; 394 const uint32_t wr_buf_size = 40; 395 /* 0: lane_count; 1: link_rate */ 396 int max_param_num = 2; 397 uint8_t param_nums = 0; 398 long param[2]; 399 bool valid_input = true; 400 401 if (!dp_mst_is_end_device(aconnector)) 402 return -EINVAL; 403 404 if (size == 0) 405 return -EINVAL; 406 407 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 408 if (!wr_buf) 409 return -ENOSPC; 410 411 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 412 (long *)param, buf, 413 max_param_num, 414 ¶m_nums)) { 415 kfree(wr_buf); 416 return -EINVAL; 417 } 418 419 if (param_nums <= 0) { 420 kfree(wr_buf); 421 DRM_DEBUG_DRIVER("user data not be read\n"); 422 return -EINVAL; 423 } 424 425 switch (param[0]) { 426 case LANE_COUNT_ONE: 427 case LANE_COUNT_TWO: 428 case LANE_COUNT_FOUR: 429 break; 430 default: 431 valid_input = false; 432 break; 433 } 434 435 switch (param[1]) { 436 case LINK_RATE_LOW: 437 case LINK_RATE_HIGH: 438 case LINK_RATE_RBR2: 439 case LINK_RATE_HIGH2: 440 case LINK_RATE_HIGH3: 441 case LINK_RATE_UHBR10: 442 case LINK_RATE_UHBR13_5: 443 case LINK_RATE_UHBR20: 444 break; 445 default: 446 valid_input = false; 447 break; 448 } 449 450 if (!valid_input) { 451 kfree(wr_buf); 452 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 453 mutex_lock(&adev->dm.dc_lock); 454 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 455 mutex_unlock(&adev->dm.dc_lock); 456 return -EINVAL; 457 } 458 459 /* save user force lane_count, link_rate to preferred settings 460 * spread spectrum will not be changed 461 */ 462 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 463 prefer_link_settings.use_link_rate_set = false; 464 prefer_link_settings.lane_count = param[0]; 465 prefer_link_settings.link_rate = param[1]; 466 467 /* skip immediate retrain, and train to new link setting after hotplug event triggered */ 468 mutex_lock(&adev->dm.dc_lock); 469 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 470 mutex_unlock(&adev->dm.dc_lock); 471 472 mutex_lock(&aconnector->base.dev->mode_config.mutex); 473 aconnector->base.force = DRM_FORCE_OFF; 474 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 475 drm_kms_helper_hotplug_event(aconnector->base.dev); 476 477 msleep(100); 478 479 mutex_lock(&aconnector->base.dev->mode_config.mutex); 480 aconnector->base.force = DRM_FORCE_UNSPECIFIED; 481 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 482 drm_kms_helper_hotplug_event(aconnector->base.dev); 483 484 kfree(wr_buf); 485 return size; 486 } 487 488 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 489 * post-cursor2 (defined by VESA DP specification) 490 * 491 * valid values 492 * voltage swing: 0,1,2,3 493 * pre-emphasis : 0,1,2,3 494 * post cursor2 : 0,1,2,3 495 * 496 * 497 * how to use this debugfs 498 * 499 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 500 * 501 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 502 * 503 * To figure out which DP-x is the display for DP to be check, 504 * cd DP-x 505 * ls -ll 506 * There should be debugfs file, like link_settings, phy_settings. 507 * cat link_settings 508 * from lane_count, link_rate to figure which DP-x is for display to be worked 509 * on 510 * 511 * To get current DP PHY settings, 512 * cat phy_settings 513 * 514 * To change DP PHY settings, 515 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 516 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 517 * 0, 518 * echo 2 3 0 > phy_settings 519 * 520 * To check if change be applied, get current phy settings by 521 * cat phy_settings 522 * 523 * In case invalid values are set by user, like 524 * echo 1 4 0 > phy_settings 525 * 526 * HW will NOT be programmed by these settings. 527 * cat phy_settings will show the previous valid settings. 528 */ 529 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 530 size_t size, loff_t *pos) 531 { 532 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 533 struct dc_link *link = connector->dc_link; 534 char *rd_buf = NULL; 535 const uint32_t rd_buf_size = 20; 536 uint32_t result = 0; 537 int r; 538 539 if (*pos & 3 || size & 3) 540 return -EINVAL; 541 542 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 543 if (!rd_buf) 544 return -EINVAL; 545 546 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 547 link->cur_lane_setting[0].VOLTAGE_SWING, 548 link->cur_lane_setting[0].PRE_EMPHASIS, 549 link->cur_lane_setting[0].POST_CURSOR2); 550 551 while (size) { 552 if (*pos >= rd_buf_size) 553 break; 554 555 r = put_user((*(rd_buf + result)), buf); 556 if (r) { 557 kfree(rd_buf); 558 return r; /* r = -EFAULT */ 559 } 560 561 buf += 1; 562 size -= 1; 563 *pos += 1; 564 result += 1; 565 } 566 567 kfree(rd_buf); 568 return result; 569 } 570 571 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 572 { 573 struct drm_connector *connector = m->private; 574 struct amdgpu_dm_connector *aconnector = 575 to_amdgpu_dm_connector(connector); 576 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 577 578 if (connector->status != connector_status_connected) 579 return -ENODEV; 580 581 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 582 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 583 caps.phy_repeater_cnt); 584 585 seq_puts(m, "phy repeater mode: "); 586 587 switch (caps.mode) { 588 case DP_PHY_REPEATER_MODE_TRANSPARENT: 589 seq_puts(m, "transparent"); 590 break; 591 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 592 seq_puts(m, "non-transparent"); 593 break; 594 case 0x00: 595 seq_puts(m, "non lttpr"); 596 break; 597 default: 598 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 599 break; 600 } 601 602 seq_puts(m, "\n"); 603 return 0; 604 } 605 606 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 607 size_t size, loff_t *pos) 608 { 609 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 610 struct dc_link *link = connector->dc_link; 611 struct dc *dc = (struct dc *)link->dc; 612 char *wr_buf = NULL; 613 uint32_t wr_buf_size = 40; 614 long param[3]; 615 bool use_prefer_link_setting; 616 struct link_training_settings link_lane_settings = {0}; 617 int max_param_num = 3; 618 uint8_t param_nums = 0; 619 int r = 0; 620 621 622 if (size == 0) 623 return -EINVAL; 624 625 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 626 if (!wr_buf) 627 return -ENOSPC; 628 629 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 630 (long *)param, buf, 631 max_param_num, 632 ¶m_nums)) { 633 kfree(wr_buf); 634 return -EINVAL; 635 } 636 637 if (param_nums <= 0) { 638 kfree(wr_buf); 639 DRM_DEBUG_DRIVER("user data not be read\n"); 640 return -EINVAL; 641 } 642 643 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 644 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 645 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 646 kfree(wr_buf); 647 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 648 return size; 649 } 650 651 /* get link settings: lane count, link rate */ 652 use_prefer_link_setting = 653 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 654 (link->test_pattern_enabled)); 655 656 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 657 658 if (use_prefer_link_setting) { 659 link_lane_settings.link_settings.lane_count = 660 link->preferred_link_setting.lane_count; 661 link_lane_settings.link_settings.link_rate = 662 link->preferred_link_setting.link_rate; 663 link_lane_settings.link_settings.link_spread = 664 link->preferred_link_setting.link_spread; 665 } else { 666 link_lane_settings.link_settings.lane_count = 667 link->cur_link_settings.lane_count; 668 link_lane_settings.link_settings.link_rate = 669 link->cur_link_settings.link_rate; 670 link_lane_settings.link_settings.link_spread = 671 link->cur_link_settings.link_spread; 672 } 673 674 /* apply phy settings from user */ 675 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 676 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 677 (enum dc_voltage_swing) (param[0]); 678 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 679 (enum dc_pre_emphasis) (param[1]); 680 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 681 (enum dc_post_cursor2) (param[2]); 682 } 683 684 /* program ASIC registers and DPCD registers */ 685 dc_link_set_drive_settings(dc, &link_lane_settings, link); 686 687 kfree(wr_buf); 688 return size; 689 } 690 691 /* function description 692 * 693 * set PHY layer or Link layer test pattern 694 * PHY test pattern is used for PHY SI check. 695 * Link layer test will not affect PHY SI. 696 * 697 * Reset Test Pattern: 698 * 0 = DP_TEST_PATTERN_VIDEO_MODE 699 * 700 * PHY test pattern supported: 701 * 1 = DP_TEST_PATTERN_D102 702 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 703 * 3 = DP_TEST_PATTERN_PRBS7 704 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 705 * 5 = DP_TEST_PATTERN_CP2520_1 706 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 707 * 7 = DP_TEST_PATTERN_CP2520_3 708 * 709 * DP PHY Link Training Patterns 710 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 711 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 712 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 713 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 714 * 715 * DP Link Layer Test pattern 716 * c = DP_TEST_PATTERN_COLOR_SQUARES 717 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 718 * e = DP_TEST_PATTERN_VERTICAL_BARS 719 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 720 * 10= DP_TEST_PATTERN_COLOR_RAMP 721 * 722 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 723 * 724 * --- set test pattern 725 * echo <test pattern #> > test_pattern 726 * 727 * If test pattern # is not supported, NO HW programming will be done. 728 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 729 * for the user pattern. input 10 bytes data are separated by space 730 * 731 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 732 * 733 * --- reset test pattern 734 * echo 0 > test_pattern 735 * 736 * --- HPD detection is disabled when set PHY test pattern 737 * 738 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 739 * is disable. User could unplug DP display from DP connected and plug scope to 740 * check test pattern PHY SI. 741 * If there is need unplug scope and plug DP display back, do steps below: 742 * echo 0 > phy_test_pattern 743 * unplug scope 744 * plug DP display. 745 * 746 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 747 * driver could detect "unplug scope" and "plug DP display" 748 */ 749 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 750 size_t size, loff_t *pos) 751 { 752 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 753 struct dc_link *link = connector->dc_link; 754 char *wr_buf = NULL; 755 uint32_t wr_buf_size = 100; 756 long param[11] = {0x0}; 757 int max_param_num = 11; 758 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 759 bool disable_hpd = false; 760 bool valid_test_pattern = false; 761 uint8_t param_nums = 0; 762 /* init with default 80bit custom pattern */ 763 uint8_t custom_pattern[10] = { 764 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 765 0x1f, 0x7c, 0xf0, 0xc1, 0x07 766 }; 767 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 768 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 769 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 770 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 771 struct link_training_settings link_training_settings = {0}; 772 int i; 773 774 if (size == 0) 775 return -EINVAL; 776 777 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 778 if (!wr_buf) 779 return -ENOSPC; 780 781 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 782 (long *)param, buf, 783 max_param_num, 784 ¶m_nums)) { 785 kfree(wr_buf); 786 return -EINVAL; 787 } 788 789 if (param_nums <= 0) { 790 kfree(wr_buf); 791 DRM_DEBUG_DRIVER("user data not be read\n"); 792 return -EINVAL; 793 } 794 795 796 test_pattern = param[0]; 797 798 switch (test_pattern) { 799 case DP_TEST_PATTERN_VIDEO_MODE: 800 case DP_TEST_PATTERN_COLOR_SQUARES: 801 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 802 case DP_TEST_PATTERN_VERTICAL_BARS: 803 case DP_TEST_PATTERN_HORIZONTAL_BARS: 804 case DP_TEST_PATTERN_COLOR_RAMP: 805 valid_test_pattern = true; 806 break; 807 808 case DP_TEST_PATTERN_D102: 809 case DP_TEST_PATTERN_SYMBOL_ERROR: 810 case DP_TEST_PATTERN_PRBS7: 811 case DP_TEST_PATTERN_80BIT_CUSTOM: 812 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 813 case DP_TEST_PATTERN_TRAINING_PATTERN4: 814 disable_hpd = true; 815 valid_test_pattern = true; 816 break; 817 818 default: 819 valid_test_pattern = false; 820 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 821 break; 822 } 823 824 if (!valid_test_pattern) { 825 kfree(wr_buf); 826 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 827 return size; 828 } 829 830 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 831 for (i = 0; i < 10; i++) { 832 if ((uint8_t) param[i + 1] != 0x0) 833 break; 834 } 835 836 if (i < 10) { 837 /* not use default value */ 838 for (i = 0; i < 10; i++) 839 custom_pattern[i] = (uint8_t) param[i + 1]; 840 } 841 } 842 843 /* Usage: set DP physical test pattern using debugfs with normal DP 844 * panel. Then plug out DP panel and connect a scope to measure 845 * For normal video mode and test pattern generated from CRCT, 846 * they are visibile to user. So do not disable HPD. 847 * Video Mode is also set to clear the test pattern, so enable HPD 848 * because it might have been disabled after a test pattern was set. 849 * AUX depends on HPD * sequence dependent, do not move! 850 */ 851 if (!disable_hpd) 852 dc_link_enable_hpd(link); 853 854 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 855 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 856 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 857 858 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 859 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 860 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 861 862 link_training_settings.link_settings = cur_link_settings; 863 864 865 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 866 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 867 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 868 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 869 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 870 link_training_settings.link_settings = prefer_link_settings; 871 } 872 873 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 874 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 875 876 dc_link_dp_set_test_pattern( 877 link, 878 test_pattern, 879 DP_TEST_PATTERN_COLOR_SPACE_RGB, 880 &link_training_settings, 881 custom_pattern, 882 10); 883 884 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 885 * Then plug out DP panel and connect a scope to measure DP PHY signal. 886 * Need disable interrupt to avoid SW driver disable DP output. This is 887 * done after the test pattern is set. 888 */ 889 if (valid_test_pattern && disable_hpd) 890 dc_link_disable_hpd(link); 891 892 kfree(wr_buf); 893 894 return size; 895 } 896 897 /* 898 * Returns the DMCUB tracebuffer contents. 899 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 900 */ 901 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 902 { 903 struct amdgpu_device *adev = m->private; 904 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 905 struct dmub_fw_meta_info *fw_meta_info = &adev->dm.dmub_srv->meta_info; 906 struct dmub_debugfs_trace_entry *entries; 907 uint8_t *tbuf_base; 908 uint32_t tbuf_size, max_entries, num_entries, first_entry, i; 909 910 if (!fb_info) 911 return 0; 912 913 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 914 if (!tbuf_base) 915 return 0; 916 917 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size : 918 DMUB_TRACE_BUFFER_SIZE; 919 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 920 sizeof(struct dmub_debugfs_trace_entry); 921 922 num_entries = 923 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 924 925 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that 926 * entries are being overwritten. 927 */ 928 if (num_entries > max_entries) 929 seq_printf(m, "...\n"); 930 931 first_entry = num_entries % max_entries; 932 num_entries = min(num_entries, max_entries); 933 934 entries = (struct dmub_debugfs_trace_entry 935 *)(tbuf_base + 936 sizeof(struct dmub_debugfs_trace_header)); 937 938 /* To print entries chronologically, start from the first entry till the 939 * top of buffer, then from base of buffer to first entry. 940 */ 941 for (i = first_entry; i < num_entries; ++i) { 942 struct dmub_debugfs_trace_entry *entry = &entries[i]; 943 944 seq_printf(m, 945 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 946 entry->trace_code, entry->tick_count, entry->param0, 947 entry->param1); 948 } 949 for (i = 0; i < first_entry; ++i) { 950 struct dmub_debugfs_trace_entry *entry = &entries[i]; 951 952 seq_printf(m, 953 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 954 entry->trace_code, entry->tick_count, entry->param0, 955 entry->param1); 956 } 957 958 return 0; 959 } 960 961 /* 962 * Returns the DMCUB firmware state contents. 963 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 964 */ 965 static int dmub_fw_state_show(struct seq_file *m, void *data) 966 { 967 struct amdgpu_device *adev = m->private; 968 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 969 uint8_t *state_base; 970 uint32_t state_size; 971 972 if (!fb_info) 973 return 0; 974 975 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 976 if (!state_base) 977 return 0; 978 979 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 980 981 return seq_write(m, state_base, state_size); 982 } 983 984 /* replay_capability_show() - show eDP panel replay capability 985 * 986 * The read function: replay_capability_show 987 * Shows if sink and driver has Replay capability or not. 988 * 989 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability 990 * 991 * Expected output: 992 * "Sink support: no\n" - if panel doesn't support Replay 993 * "Sink support: yes\n" - if panel supports Replay 994 * "Driver support: no\n" - if driver doesn't support Replay 995 * "Driver support: yes\n" - if driver supports Replay 996 */ 997 static int replay_capability_show(struct seq_file *m, void *data) 998 { 999 struct drm_connector *connector = m->private; 1000 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1001 struct dc_link *link = aconnector->dc_link; 1002 bool sink_support_replay = false; 1003 bool driver_support_replay = false; 1004 1005 if (!link) 1006 return -ENODEV; 1007 1008 if (link->type == dc_connection_none) 1009 return -ENODEV; 1010 1011 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1012 return -ENODEV; 1013 1014 /* If Replay is already set to support, skip the checks */ 1015 if (link->replay_settings.config.replay_supported) { 1016 sink_support_replay = true; 1017 driver_support_replay = true; 1018 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 1019 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1020 } else { 1021 struct dc *dc = link->ctx->dc; 1022 1023 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1024 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub) 1025 driver_support_replay = 1026 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported; 1027 } 1028 1029 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay)); 1030 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay)); 1031 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported)); 1032 1033 return 0; 1034 } 1035 1036 /* psr_capability_show() - show eDP panel PSR capability 1037 * 1038 * The read function: sink_psr_capability_show 1039 * Shows if sink has PSR capability or not. 1040 * If yes - the PSR version is appended 1041 * 1042 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 1043 * 1044 * Expected output: 1045 * "Sink support: no\n" - if panel doesn't support PSR 1046 * "Sink support: yes [0x01]\n" - if panel supports PSR1 1047 * "Driver support: no\n" - if driver doesn't support PSR 1048 * "Driver support: yes [0x01]\n" - if driver supports PSR1 1049 */ 1050 static int psr_capability_show(struct seq_file *m, void *data) 1051 { 1052 struct drm_connector *connector = m->private; 1053 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1054 struct dc_link *link = aconnector->dc_link; 1055 1056 if (!link) 1057 return -ENODEV; 1058 1059 if (link->type == dc_connection_none) 1060 return -ENODEV; 1061 1062 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1063 return -ENODEV; 1064 1065 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 1066 if (link->dpcd_caps.psr_info.psr_version) 1067 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 1068 seq_puts(m, "\n"); 1069 1070 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 1071 if (link->psr_settings.psr_version) 1072 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 1073 seq_puts(m, "\n"); 1074 1075 return 0; 1076 } 1077 1078 /* 1079 * Returns the current bpc for the crtc. 1080 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 1081 */ 1082 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 1083 { 1084 struct drm_crtc *crtc = m->private; 1085 struct drm_device *dev = crtc->dev; 1086 struct dm_crtc_state *dm_crtc_state = NULL; 1087 int res = -ENODEV; 1088 unsigned int bpc; 1089 1090 mutex_lock(&dev->mode_config.mutex); 1091 drm_modeset_lock(&crtc->mutex, NULL); 1092 if (crtc->state == NULL) 1093 goto unlock; 1094 1095 dm_crtc_state = to_dm_crtc_state(crtc->state); 1096 if (dm_crtc_state->stream == NULL) 1097 goto unlock; 1098 1099 switch (dm_crtc_state->stream->timing.display_color_depth) { 1100 case COLOR_DEPTH_666: 1101 bpc = 6; 1102 break; 1103 case COLOR_DEPTH_888: 1104 bpc = 8; 1105 break; 1106 case COLOR_DEPTH_101010: 1107 bpc = 10; 1108 break; 1109 case COLOR_DEPTH_121212: 1110 bpc = 12; 1111 break; 1112 case COLOR_DEPTH_161616: 1113 bpc = 16; 1114 break; 1115 default: 1116 goto unlock; 1117 } 1118 1119 seq_printf(m, "Current: %u\n", bpc); 1120 res = 0; 1121 1122 unlock: 1123 drm_modeset_unlock(&crtc->mutex); 1124 mutex_unlock(&dev->mode_config.mutex); 1125 1126 return res; 1127 } 1128 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 1129 1130 /* 1131 * Returns the current colorspace for the crtc. 1132 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 1133 */ 1134 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 1135 { 1136 struct drm_crtc *crtc = m->private; 1137 struct drm_device *dev = crtc->dev; 1138 struct dm_crtc_state *dm_crtc_state = NULL; 1139 int res = -ENODEV; 1140 1141 mutex_lock(&dev->mode_config.mutex); 1142 drm_modeset_lock(&crtc->mutex, NULL); 1143 if (crtc->state == NULL) 1144 goto unlock; 1145 1146 dm_crtc_state = to_dm_crtc_state(crtc->state); 1147 if (dm_crtc_state->stream == NULL) 1148 goto unlock; 1149 1150 switch (dm_crtc_state->stream->output_color_space) { 1151 case COLOR_SPACE_SRGB: 1152 seq_puts(m, "sRGB"); 1153 break; 1154 case COLOR_SPACE_YCBCR601: 1155 case COLOR_SPACE_YCBCR601_LIMITED: 1156 seq_puts(m, "BT601_YCC"); 1157 break; 1158 case COLOR_SPACE_YCBCR709: 1159 case COLOR_SPACE_YCBCR709_LIMITED: 1160 seq_puts(m, "BT709_YCC"); 1161 break; 1162 case COLOR_SPACE_ADOBERGB: 1163 seq_puts(m, "opRGB"); 1164 break; 1165 case COLOR_SPACE_2020_RGB_FULLRANGE: 1166 seq_puts(m, "BT2020_RGB"); 1167 break; 1168 case COLOR_SPACE_2020_YCBCR: 1169 seq_puts(m, "BT2020_YCC"); 1170 break; 1171 default: 1172 goto unlock; 1173 } 1174 res = 0; 1175 1176 unlock: 1177 drm_modeset_unlock(&crtc->mutex); 1178 mutex_unlock(&dev->mode_config.mutex); 1179 1180 return res; 1181 } 1182 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 1183 1184 1185 /* 1186 * Example usage: 1187 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 1188 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1189 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 1190 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1191 */ 1192 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 1193 size_t size, loff_t *pos) 1194 { 1195 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1196 char *wr_buf = NULL; 1197 uint32_t wr_buf_size = 42; 1198 int max_param_num = 1; 1199 long param; 1200 uint8_t param_nums = 0; 1201 1202 if (size == 0) 1203 return -EINVAL; 1204 1205 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1206 1207 if (!wr_buf) { 1208 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1209 return -ENOSPC; 1210 } 1211 1212 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1213 ¶m, buf, 1214 max_param_num, 1215 ¶m_nums)) { 1216 kfree(wr_buf); 1217 return -EINVAL; 1218 } 1219 1220 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1221 1222 kfree(wr_buf); 1223 return 0; 1224 } 1225 1226 /* 1227 * Returns the HDCP capability of the Display (1.4 for now). 1228 * 1229 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1230 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1231 * 1232 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1233 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1234 */ 1235 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1236 { 1237 struct drm_connector *connector = m->private; 1238 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1239 bool hdcp_cap, hdcp2_cap; 1240 1241 if (connector->status != connector_status_connected) 1242 return -ENODEV; 1243 1244 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1245 1246 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1247 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1248 1249 1250 if (hdcp_cap) 1251 seq_printf(m, "%s ", "HDCP1.4"); 1252 if (hdcp2_cap) 1253 seq_printf(m, "%s ", "HDCP2.2"); 1254 1255 if (!hdcp_cap && !hdcp2_cap) 1256 seq_printf(m, "%s ", "None"); 1257 1258 seq_puts(m, "\n"); 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * Returns whether the connected display is internal and not hotpluggable. 1265 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1266 */ 1267 static int internal_display_show(struct seq_file *m, void *data) 1268 { 1269 struct drm_connector *connector = m->private; 1270 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1271 struct dc_link *link = aconnector->dc_link; 1272 1273 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1274 1275 return 0; 1276 } 1277 1278 /* 1279 * Returns the number of segments used if ODM Combine mode is enabled. 1280 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments 1281 */ 1282 static int odm_combine_segments_show(struct seq_file *m, void *unused) 1283 { 1284 struct drm_connector *connector = m->private; 1285 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1286 struct dc_link *link = aconnector->dc_link; 1287 struct pipe_ctx *pipe_ctx = NULL; 1288 int i, segments = -EOPNOTSUPP; 1289 1290 for (i = 0; i < MAX_PIPES; i++) { 1291 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 1292 if (pipe_ctx->stream && 1293 pipe_ctx->stream->link == link) 1294 break; 1295 } 1296 1297 if (connector->status != connector_status_connected) 1298 return -ENODEV; 1299 1300 if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1301 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1302 1303 seq_printf(m, "%d\n", segments); 1304 return 0; 1305 } 1306 1307 /* function description 1308 * 1309 * generic SDP message access for testing 1310 * 1311 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1312 * 1313 * SDP header 1314 * Hb0 : Secondary-Data Packet ID 1315 * Hb1 : Secondary-Data Packet type 1316 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1317 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1318 * 1319 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1320 */ 1321 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1322 size_t size, loff_t *pos) 1323 { 1324 int r; 1325 uint8_t data[36] = {0}; 1326 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1327 struct dm_crtc_state *acrtc_state; 1328 uint32_t write_size = 36; 1329 1330 if (connector->base.status != connector_status_connected) 1331 return -ENODEV; 1332 1333 if (size == 0) 1334 return 0; 1335 1336 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1337 1338 r = copy_from_user(data, buf, write_size); 1339 1340 write_size -= r; 1341 1342 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1343 1344 return write_size; 1345 } 1346 1347 /* function: Read link's DSC & FEC capabilities 1348 * 1349 * 1350 * Access it with the following command (you need to specify 1351 * connector like DP-1): 1352 * 1353 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1354 * 1355 */ 1356 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1357 { 1358 struct drm_connector *connector = m->private; 1359 struct drm_modeset_acquire_ctx ctx; 1360 struct drm_device *dev = connector->dev; 1361 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1362 int ret = 0; 1363 bool try_again = false; 1364 bool is_fec_supported = false; 1365 bool is_dsc_supported = false; 1366 struct dpcd_caps dpcd_caps; 1367 1368 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1369 do { 1370 try_again = false; 1371 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1372 if (ret) { 1373 if (ret == -EDEADLK) { 1374 ret = drm_modeset_backoff(&ctx); 1375 if (!ret) { 1376 try_again = true; 1377 continue; 1378 } 1379 } 1380 break; 1381 } 1382 if (connector->status != connector_status_connected) { 1383 ret = -ENODEV; 1384 break; 1385 } 1386 dpcd_caps = aconnector->dc_link->dpcd_caps; 1387 if (aconnector->mst_output_port) { 1388 /* aconnector sets dsc_aux during get_modes call 1389 * if MST connector has it means it can either 1390 * enable DSC on the sink device or on MST branch 1391 * its connected to. 1392 */ 1393 if (aconnector->dsc_aux) { 1394 is_fec_supported = true; 1395 is_dsc_supported = true; 1396 } 1397 } else { 1398 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1399 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1400 } 1401 } while (try_again); 1402 1403 drm_modeset_drop_locks(&ctx); 1404 drm_modeset_acquire_fini(&ctx); 1405 1406 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1407 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1408 1409 return ret; 1410 } 1411 1412 /* function: Trigger virtual HPD redetection on connector 1413 * 1414 * This function will perform link rediscovery, link disable 1415 * and enable, and dm connector state update. 1416 * 1417 * Retrigger HPD on an existing connector by echoing 1 into 1418 * its respectful "trigger_hotplug" debugfs entry: 1419 * 1420 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1421 * 1422 * This function can perform HPD unplug: 1423 * 1424 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1425 * 1426 */ 1427 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1428 size_t size, loff_t *pos) 1429 { 1430 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1431 struct drm_connector *connector = &aconnector->base; 1432 struct dc_link *link = NULL; 1433 struct drm_device *dev = connector->dev; 1434 struct amdgpu_device *adev = drm_to_adev(dev); 1435 enum dc_connection_type new_connection_type = dc_connection_none; 1436 char *wr_buf = NULL; 1437 uint32_t wr_buf_size = 42; 1438 int max_param_num = 1; 1439 long param[1] = {0}; 1440 uint8_t param_nums = 0; 1441 bool ret = false; 1442 1443 if (!aconnector->dc_link) 1444 return -EINVAL; 1445 1446 if (size == 0) 1447 return -EINVAL; 1448 1449 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1450 1451 if (!wr_buf) { 1452 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1453 return -ENOSPC; 1454 } 1455 1456 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1457 (long *)param, buf, 1458 max_param_num, 1459 ¶m_nums)) { 1460 kfree(wr_buf); 1461 return -EINVAL; 1462 } 1463 1464 kfree(wr_buf); 1465 1466 if (param_nums <= 0) { 1467 DRM_DEBUG_DRIVER("user data not be read\n"); 1468 return -EINVAL; 1469 } 1470 1471 mutex_lock(&aconnector->hpd_lock); 1472 1473 /* Don't support for mst end device*/ 1474 if (aconnector->mst_root) { 1475 mutex_unlock(&aconnector->hpd_lock); 1476 return -EINVAL; 1477 } 1478 1479 if (param[0] == 1) { 1480 1481 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1482 new_connection_type != dc_connection_none) 1483 goto unlock; 1484 1485 mutex_lock(&adev->dm.dc_lock); 1486 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1487 mutex_unlock(&adev->dm.dc_lock); 1488 1489 if (!ret) 1490 goto unlock; 1491 1492 amdgpu_dm_update_connector_after_detect(aconnector); 1493 1494 drm_modeset_lock_all(dev); 1495 dm_restore_drm_connector_state(dev, connector); 1496 drm_modeset_unlock_all(dev); 1497 1498 drm_kms_helper_connector_hotplug_event(connector); 1499 } else if (param[0] == 0) { 1500 if (!aconnector->dc_link) 1501 goto unlock; 1502 1503 link = aconnector->dc_link; 1504 1505 if (link->local_sink) { 1506 dc_sink_release(link->local_sink); 1507 link->local_sink = NULL; 1508 } 1509 1510 link->dpcd_sink_count = 0; 1511 link->type = dc_connection_none; 1512 link->dongle_max_pix_clk = 0; 1513 1514 amdgpu_dm_update_connector_after_detect(aconnector); 1515 1516 /* If the aconnector is the root node in mst topology */ 1517 if (aconnector->mst_mgr.mst_state == true) 1518 dc_link_reset_cur_dp_mst_topology(link); 1519 1520 drm_modeset_lock_all(dev); 1521 dm_restore_drm_connector_state(dev, connector); 1522 drm_modeset_unlock_all(dev); 1523 1524 drm_kms_helper_connector_hotplug_event(connector); 1525 } 1526 1527 unlock: 1528 mutex_unlock(&aconnector->hpd_lock); 1529 1530 return size; 1531 } 1532 1533 /* function: read DSC status on the connector 1534 * 1535 * The read function: dp_dsc_clock_en_read 1536 * returns current status of DSC clock on the connector. 1537 * The return is a boolean flag: 1 or 0. 1538 * 1539 * Access it with the following command (you need to specify 1540 * connector like DP-1): 1541 * 1542 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1543 * 1544 * Expected output: 1545 * 1 - means that DSC is currently enabled 1546 * 0 - means that DSC is disabled 1547 */ 1548 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1549 size_t size, loff_t *pos) 1550 { 1551 char *rd_buf = NULL; 1552 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1553 struct display_stream_compressor *dsc; 1554 struct dcn_dsc_state dsc_state = {0}; 1555 const uint32_t rd_buf_size = 10; 1556 struct pipe_ctx *pipe_ctx; 1557 ssize_t result = 0; 1558 int i, r, str_len = 10; 1559 1560 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1561 1562 if (!rd_buf) 1563 return -ENOMEM; 1564 1565 for (i = 0; i < MAX_PIPES; i++) { 1566 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1567 if (pipe_ctx->stream && 1568 pipe_ctx->stream->link == aconnector->dc_link && 1569 pipe_ctx->stream->sink && 1570 pipe_ctx->stream->sink == aconnector->dc_sink) 1571 break; 1572 } 1573 1574 dsc = pipe_ctx->stream_res.dsc; 1575 if (dsc) 1576 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1577 1578 snprintf(rd_buf, str_len, 1579 "%d\n", 1580 dsc_state.dsc_clock_en); 1581 1582 while (size) { 1583 if (*pos >= rd_buf_size) 1584 break; 1585 1586 r = put_user(*(rd_buf + result), buf); 1587 if (r) { 1588 kfree(rd_buf); 1589 return r; /* r = -EFAULT */ 1590 } 1591 1592 buf += 1; 1593 size -= 1; 1594 *pos += 1; 1595 result += 1; 1596 } 1597 1598 kfree(rd_buf); 1599 return result; 1600 } 1601 1602 /* function: write force DSC on the connector 1603 * 1604 * The write function: dp_dsc_clock_en_write 1605 * enables to force DSC on the connector. 1606 * User can write to either force enable or force disable DSC 1607 * on the next modeset or set it to driver default 1608 * 1609 * Accepted inputs: 1610 * 0 - default DSC enablement policy 1611 * 1 - force enable DSC on the connector 1612 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1613 * 1614 * Writing DSC settings is done with the following command: 1615 * - To force enable DSC (you need to specify 1616 * connector like DP-1): 1617 * 1618 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1619 * 1620 * - To return to default state set the flag to zero and 1621 * let driver deal with DSC automatically 1622 * (you need to specify connector like DP-1): 1623 * 1624 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1625 * 1626 */ 1627 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1628 size_t size, loff_t *pos) 1629 { 1630 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1631 struct drm_connector *connector = &aconnector->base; 1632 struct drm_device *dev = connector->dev; 1633 struct drm_crtc *crtc = NULL; 1634 struct dm_crtc_state *dm_crtc_state = NULL; 1635 struct pipe_ctx *pipe_ctx; 1636 int i; 1637 char *wr_buf = NULL; 1638 uint32_t wr_buf_size = 42; 1639 int max_param_num = 1; 1640 long param[1] = {0}; 1641 uint8_t param_nums = 0; 1642 1643 if (size == 0) 1644 return -EINVAL; 1645 1646 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1647 1648 if (!wr_buf) { 1649 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1650 return -ENOSPC; 1651 } 1652 1653 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1654 (long *)param, buf, 1655 max_param_num, 1656 ¶m_nums)) { 1657 kfree(wr_buf); 1658 return -EINVAL; 1659 } 1660 1661 if (param_nums <= 0) { 1662 DRM_DEBUG_DRIVER("user data not be read\n"); 1663 kfree(wr_buf); 1664 return -EINVAL; 1665 } 1666 1667 for (i = 0; i < MAX_PIPES; i++) { 1668 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1669 if (pipe_ctx->stream && 1670 pipe_ctx->stream->link == aconnector->dc_link && 1671 pipe_ctx->stream->sink && 1672 pipe_ctx->stream->sink == aconnector->dc_sink) 1673 break; 1674 } 1675 1676 if (!pipe_ctx->stream) 1677 goto done; 1678 1679 // Get CRTC state 1680 mutex_lock(&dev->mode_config.mutex); 1681 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1682 1683 if (connector->state == NULL) 1684 goto unlock; 1685 1686 crtc = connector->state->crtc; 1687 if (crtc == NULL) 1688 goto unlock; 1689 1690 drm_modeset_lock(&crtc->mutex, NULL); 1691 if (crtc->state == NULL) 1692 goto unlock; 1693 1694 dm_crtc_state = to_dm_crtc_state(crtc->state); 1695 if (dm_crtc_state->stream == NULL) 1696 goto unlock; 1697 1698 if (param[0] == 1) 1699 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1700 else if (param[0] == 2) 1701 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1702 else 1703 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1704 1705 dm_crtc_state->dsc_force_changed = true; 1706 1707 unlock: 1708 if (crtc) 1709 drm_modeset_unlock(&crtc->mutex); 1710 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1711 mutex_unlock(&dev->mode_config.mutex); 1712 1713 done: 1714 kfree(wr_buf); 1715 return size; 1716 } 1717 1718 /* function: read DSC slice width parameter on the connector 1719 * 1720 * The read function: dp_dsc_slice_width_read 1721 * returns dsc slice width used in the current configuration 1722 * The return is an integer: 0 or other positive number 1723 * 1724 * Access the status with the following command: 1725 * 1726 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1727 * 1728 * 0 - means that DSC is disabled 1729 * 1730 * Any other number more than zero represents the 1731 * slice width currently used by DSC in pixels 1732 * 1733 */ 1734 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1735 size_t size, loff_t *pos) 1736 { 1737 char *rd_buf = NULL; 1738 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1739 struct display_stream_compressor *dsc; 1740 struct dcn_dsc_state dsc_state = {0}; 1741 const uint32_t rd_buf_size = 100; 1742 struct pipe_ctx *pipe_ctx; 1743 ssize_t result = 0; 1744 int i, r, str_len = 30; 1745 1746 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1747 1748 if (!rd_buf) 1749 return -ENOMEM; 1750 1751 for (i = 0; i < MAX_PIPES; i++) { 1752 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1753 if (pipe_ctx->stream && 1754 pipe_ctx->stream->link == aconnector->dc_link && 1755 pipe_ctx->stream->sink && 1756 pipe_ctx->stream->sink == aconnector->dc_sink) 1757 break; 1758 } 1759 1760 dsc = pipe_ctx->stream_res.dsc; 1761 if (dsc) 1762 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1763 1764 snprintf(rd_buf, str_len, 1765 "%d\n", 1766 dsc_state.dsc_slice_width); 1767 1768 while (size) { 1769 if (*pos >= rd_buf_size) 1770 break; 1771 1772 r = put_user(*(rd_buf + result), buf); 1773 if (r) { 1774 kfree(rd_buf); 1775 return r; /* r = -EFAULT */ 1776 } 1777 1778 buf += 1; 1779 size -= 1; 1780 *pos += 1; 1781 result += 1; 1782 } 1783 1784 kfree(rd_buf); 1785 return result; 1786 } 1787 1788 /* function: write DSC slice width parameter 1789 * 1790 * The write function: dp_dsc_slice_width_write 1791 * overwrites automatically generated DSC configuration 1792 * of slice width. 1793 * 1794 * The user has to write the slice width divisible by the 1795 * picture width. 1796 * 1797 * Also the user has to write width in hexidecimal 1798 * rather than in decimal. 1799 * 1800 * Writing DSC settings is done with the following command: 1801 * - To force overwrite slice width: (example sets to 1920 pixels) 1802 * 1803 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1804 * 1805 * - To stop overwriting and let driver find the optimal size, 1806 * set the width to zero: 1807 * 1808 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1809 * 1810 */ 1811 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1812 size_t size, loff_t *pos) 1813 { 1814 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1815 struct pipe_ctx *pipe_ctx; 1816 struct drm_connector *connector = &aconnector->base; 1817 struct drm_device *dev = connector->dev; 1818 struct drm_crtc *crtc = NULL; 1819 struct dm_crtc_state *dm_crtc_state = NULL; 1820 int i; 1821 char *wr_buf = NULL; 1822 uint32_t wr_buf_size = 42; 1823 int max_param_num = 1; 1824 long param[1] = {0}; 1825 uint8_t param_nums = 0; 1826 1827 if (size == 0) 1828 return -EINVAL; 1829 1830 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1831 1832 if (!wr_buf) { 1833 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1834 return -ENOSPC; 1835 } 1836 1837 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1838 (long *)param, buf, 1839 max_param_num, 1840 ¶m_nums)) { 1841 kfree(wr_buf); 1842 return -EINVAL; 1843 } 1844 1845 if (param_nums <= 0) { 1846 DRM_DEBUG_DRIVER("user data not be read\n"); 1847 kfree(wr_buf); 1848 return -EINVAL; 1849 } 1850 1851 for (i = 0; i < MAX_PIPES; i++) { 1852 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1853 if (pipe_ctx->stream && 1854 pipe_ctx->stream->link == aconnector->dc_link && 1855 pipe_ctx->stream->sink && 1856 pipe_ctx->stream->sink == aconnector->dc_sink) 1857 break; 1858 } 1859 1860 if (!pipe_ctx->stream) 1861 goto done; 1862 1863 // Safely get CRTC state 1864 mutex_lock(&dev->mode_config.mutex); 1865 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1866 1867 if (connector->state == NULL) 1868 goto unlock; 1869 1870 crtc = connector->state->crtc; 1871 if (crtc == NULL) 1872 goto unlock; 1873 1874 drm_modeset_lock(&crtc->mutex, NULL); 1875 if (crtc->state == NULL) 1876 goto unlock; 1877 1878 dm_crtc_state = to_dm_crtc_state(crtc->state); 1879 if (dm_crtc_state->stream == NULL) 1880 goto unlock; 1881 1882 if (param[0] > 0) 1883 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1884 pipe_ctx->stream->timing.h_addressable, 1885 param[0]); 1886 else 1887 aconnector->dsc_settings.dsc_num_slices_h = 0; 1888 1889 dm_crtc_state->dsc_force_changed = true; 1890 1891 unlock: 1892 if (crtc) 1893 drm_modeset_unlock(&crtc->mutex); 1894 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1895 mutex_unlock(&dev->mode_config.mutex); 1896 1897 done: 1898 kfree(wr_buf); 1899 return size; 1900 } 1901 1902 /* function: read DSC slice height parameter on the connector 1903 * 1904 * The read function: dp_dsc_slice_height_read 1905 * returns dsc slice height used in the current configuration 1906 * The return is an integer: 0 or other positive number 1907 * 1908 * Access the status with the following command: 1909 * 1910 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1911 * 1912 * 0 - means that DSC is disabled 1913 * 1914 * Any other number more than zero represents the 1915 * slice height currently used by DSC in pixels 1916 * 1917 */ 1918 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1919 size_t size, loff_t *pos) 1920 { 1921 char *rd_buf = NULL; 1922 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1923 struct display_stream_compressor *dsc; 1924 struct dcn_dsc_state dsc_state = {0}; 1925 const uint32_t rd_buf_size = 100; 1926 struct pipe_ctx *pipe_ctx; 1927 ssize_t result = 0; 1928 int i, r, str_len = 30; 1929 1930 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1931 1932 if (!rd_buf) 1933 return -ENOMEM; 1934 1935 for (i = 0; i < MAX_PIPES; i++) { 1936 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1937 if (pipe_ctx->stream && 1938 pipe_ctx->stream->link == aconnector->dc_link && 1939 pipe_ctx->stream->sink && 1940 pipe_ctx->stream->sink == aconnector->dc_sink) 1941 break; 1942 } 1943 1944 dsc = pipe_ctx->stream_res.dsc; 1945 if (dsc) 1946 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1947 1948 snprintf(rd_buf, str_len, 1949 "%d\n", 1950 dsc_state.dsc_slice_height); 1951 1952 while (size) { 1953 if (*pos >= rd_buf_size) 1954 break; 1955 1956 r = put_user(*(rd_buf + result), buf); 1957 if (r) { 1958 kfree(rd_buf); 1959 return r; /* r = -EFAULT */ 1960 } 1961 1962 buf += 1; 1963 size -= 1; 1964 *pos += 1; 1965 result += 1; 1966 } 1967 1968 kfree(rd_buf); 1969 return result; 1970 } 1971 1972 /* function: write DSC slice height parameter 1973 * 1974 * The write function: dp_dsc_slice_height_write 1975 * overwrites automatically generated DSC configuration 1976 * of slice height. 1977 * 1978 * The user has to write the slice height divisible by the 1979 * picture height. 1980 * 1981 * Also the user has to write height in hexidecimal 1982 * rather than in decimal. 1983 * 1984 * Writing DSC settings is done with the following command: 1985 * - To force overwrite slice height (example sets to 128 pixels): 1986 * 1987 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1988 * 1989 * - To stop overwriting and let driver find the optimal size, 1990 * set the height to zero: 1991 * 1992 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1993 * 1994 */ 1995 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1996 size_t size, loff_t *pos) 1997 { 1998 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1999 struct drm_connector *connector = &aconnector->base; 2000 struct drm_device *dev = connector->dev; 2001 struct drm_crtc *crtc = NULL; 2002 struct dm_crtc_state *dm_crtc_state = NULL; 2003 struct pipe_ctx *pipe_ctx; 2004 int i; 2005 char *wr_buf = NULL; 2006 uint32_t wr_buf_size = 42; 2007 int max_param_num = 1; 2008 uint8_t param_nums = 0; 2009 long param[1] = {0}; 2010 2011 if (size == 0) 2012 return -EINVAL; 2013 2014 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2015 2016 if (!wr_buf) { 2017 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2018 return -ENOSPC; 2019 } 2020 2021 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2022 (long *)param, buf, 2023 max_param_num, 2024 ¶m_nums)) { 2025 kfree(wr_buf); 2026 return -EINVAL; 2027 } 2028 2029 if (param_nums <= 0) { 2030 DRM_DEBUG_DRIVER("user data not be read\n"); 2031 kfree(wr_buf); 2032 return -EINVAL; 2033 } 2034 2035 for (i = 0; i < MAX_PIPES; i++) { 2036 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2037 if (pipe_ctx->stream && 2038 pipe_ctx->stream->link == aconnector->dc_link && 2039 pipe_ctx->stream->sink && 2040 pipe_ctx->stream->sink == aconnector->dc_sink) 2041 break; 2042 } 2043 2044 if (!pipe_ctx->stream) 2045 goto done; 2046 2047 // Get CRTC state 2048 mutex_lock(&dev->mode_config.mutex); 2049 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2050 2051 if (connector->state == NULL) 2052 goto unlock; 2053 2054 crtc = connector->state->crtc; 2055 if (crtc == NULL) 2056 goto unlock; 2057 2058 drm_modeset_lock(&crtc->mutex, NULL); 2059 if (crtc->state == NULL) 2060 goto unlock; 2061 2062 dm_crtc_state = to_dm_crtc_state(crtc->state); 2063 if (dm_crtc_state->stream == NULL) 2064 goto unlock; 2065 2066 if (param[0] > 0) 2067 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 2068 pipe_ctx->stream->timing.v_addressable, 2069 param[0]); 2070 else 2071 aconnector->dsc_settings.dsc_num_slices_v = 0; 2072 2073 dm_crtc_state->dsc_force_changed = true; 2074 2075 unlock: 2076 if (crtc) 2077 drm_modeset_unlock(&crtc->mutex); 2078 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2079 mutex_unlock(&dev->mode_config.mutex); 2080 2081 done: 2082 kfree(wr_buf); 2083 return size; 2084 } 2085 2086 /* function: read DSC target rate on the connector in bits per pixel 2087 * 2088 * The read function: dp_dsc_bits_per_pixel_read 2089 * returns target rate of compression in bits per pixel 2090 * The return is an integer: 0 or other positive integer 2091 * 2092 * Access it with the following command: 2093 * 2094 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2095 * 2096 * 0 - means that DSC is disabled 2097 */ 2098 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 2099 size_t size, loff_t *pos) 2100 { 2101 char *rd_buf = NULL; 2102 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2103 struct display_stream_compressor *dsc; 2104 struct dcn_dsc_state dsc_state = {0}; 2105 const uint32_t rd_buf_size = 100; 2106 struct pipe_ctx *pipe_ctx; 2107 ssize_t result = 0; 2108 int i, r, str_len = 30; 2109 2110 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2111 2112 if (!rd_buf) 2113 return -ENOMEM; 2114 2115 for (i = 0; i < MAX_PIPES; i++) { 2116 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2117 if (pipe_ctx->stream && 2118 pipe_ctx->stream->link == aconnector->dc_link && 2119 pipe_ctx->stream->sink && 2120 pipe_ctx->stream->sink == aconnector->dc_sink) 2121 break; 2122 } 2123 2124 dsc = pipe_ctx->stream_res.dsc; 2125 if (dsc) 2126 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2127 2128 snprintf(rd_buf, str_len, 2129 "%d\n", 2130 dsc_state.dsc_bits_per_pixel); 2131 2132 while (size) { 2133 if (*pos >= rd_buf_size) 2134 break; 2135 2136 r = put_user(*(rd_buf + result), buf); 2137 if (r) { 2138 kfree(rd_buf); 2139 return r; /* r = -EFAULT */ 2140 } 2141 2142 buf += 1; 2143 size -= 1; 2144 *pos += 1; 2145 result += 1; 2146 } 2147 2148 kfree(rd_buf); 2149 return result; 2150 } 2151 2152 /* function: write DSC target rate in bits per pixel 2153 * 2154 * The write function: dp_dsc_bits_per_pixel_write 2155 * overwrites automatically generated DSC configuration 2156 * of DSC target bit rate. 2157 * 2158 * Also the user has to write bpp in hexidecimal 2159 * rather than in decimal. 2160 * 2161 * Writing DSC settings is done with the following command: 2162 * - To force overwrite rate (example sets to 256 bpp x 1/16): 2163 * 2164 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2165 * 2166 * - To stop overwriting and let driver find the optimal rate, 2167 * set the rate to zero: 2168 * 2169 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2170 * 2171 */ 2172 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2173 size_t size, loff_t *pos) 2174 { 2175 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2176 struct drm_connector *connector = &aconnector->base; 2177 struct drm_device *dev = connector->dev; 2178 struct drm_crtc *crtc = NULL; 2179 struct dm_crtc_state *dm_crtc_state = NULL; 2180 struct pipe_ctx *pipe_ctx; 2181 int i; 2182 char *wr_buf = NULL; 2183 uint32_t wr_buf_size = 42; 2184 int max_param_num = 1; 2185 uint8_t param_nums = 0; 2186 long param[1] = {0}; 2187 2188 if (size == 0) 2189 return -EINVAL; 2190 2191 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2192 2193 if (!wr_buf) { 2194 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2195 return -ENOSPC; 2196 } 2197 2198 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2199 (long *)param, buf, 2200 max_param_num, 2201 ¶m_nums)) { 2202 kfree(wr_buf); 2203 return -EINVAL; 2204 } 2205 2206 if (param_nums <= 0) { 2207 DRM_DEBUG_DRIVER("user data not be read\n"); 2208 kfree(wr_buf); 2209 return -EINVAL; 2210 } 2211 2212 for (i = 0; i < MAX_PIPES; i++) { 2213 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2214 if (pipe_ctx->stream && 2215 pipe_ctx->stream->link == aconnector->dc_link && 2216 pipe_ctx->stream->sink && 2217 pipe_ctx->stream->sink == aconnector->dc_sink) 2218 break; 2219 } 2220 2221 if (!pipe_ctx->stream) 2222 goto done; 2223 2224 // Get CRTC state 2225 mutex_lock(&dev->mode_config.mutex); 2226 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2227 2228 if (connector->state == NULL) 2229 goto unlock; 2230 2231 crtc = connector->state->crtc; 2232 if (crtc == NULL) 2233 goto unlock; 2234 2235 drm_modeset_lock(&crtc->mutex, NULL); 2236 if (crtc->state == NULL) 2237 goto unlock; 2238 2239 dm_crtc_state = to_dm_crtc_state(crtc->state); 2240 if (dm_crtc_state->stream == NULL) 2241 goto unlock; 2242 2243 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2244 2245 dm_crtc_state->dsc_force_changed = true; 2246 2247 unlock: 2248 if (crtc) 2249 drm_modeset_unlock(&crtc->mutex); 2250 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2251 mutex_unlock(&dev->mode_config.mutex); 2252 2253 done: 2254 kfree(wr_buf); 2255 return size; 2256 } 2257 2258 /* function: read DSC picture width parameter on the connector 2259 * 2260 * The read function: dp_dsc_pic_width_read 2261 * returns dsc picture width used in the current configuration 2262 * It is the same as h_addressable of the current 2263 * display's timing 2264 * The return is an integer: 0 or other positive integer 2265 * If 0 then DSC is disabled. 2266 * 2267 * Access it with the following command: 2268 * 2269 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2270 * 2271 * 0 - means that DSC is disabled 2272 */ 2273 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2274 size_t size, loff_t *pos) 2275 { 2276 char *rd_buf = NULL; 2277 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2278 struct display_stream_compressor *dsc; 2279 struct dcn_dsc_state dsc_state = {0}; 2280 const uint32_t rd_buf_size = 100; 2281 struct pipe_ctx *pipe_ctx; 2282 ssize_t result = 0; 2283 int i, r, str_len = 30; 2284 2285 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2286 2287 if (!rd_buf) 2288 return -ENOMEM; 2289 2290 for (i = 0; i < MAX_PIPES; i++) { 2291 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2292 if (pipe_ctx->stream && 2293 pipe_ctx->stream->link == aconnector->dc_link && 2294 pipe_ctx->stream->sink && 2295 pipe_ctx->stream->sink == aconnector->dc_sink) 2296 break; 2297 } 2298 2299 dsc = pipe_ctx->stream_res.dsc; 2300 if (dsc) 2301 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2302 2303 snprintf(rd_buf, str_len, 2304 "%d\n", 2305 dsc_state.dsc_pic_width); 2306 2307 while (size) { 2308 if (*pos >= rd_buf_size) 2309 break; 2310 2311 r = put_user(*(rd_buf + result), buf); 2312 if (r) { 2313 kfree(rd_buf); 2314 return r; /* r = -EFAULT */ 2315 } 2316 2317 buf += 1; 2318 size -= 1; 2319 *pos += 1; 2320 result += 1; 2321 } 2322 2323 kfree(rd_buf); 2324 return result; 2325 } 2326 2327 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2328 size_t size, loff_t *pos) 2329 { 2330 char *rd_buf = NULL; 2331 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2332 struct display_stream_compressor *dsc; 2333 struct dcn_dsc_state dsc_state = {0}; 2334 const uint32_t rd_buf_size = 100; 2335 struct pipe_ctx *pipe_ctx; 2336 ssize_t result = 0; 2337 int i, r, str_len = 30; 2338 2339 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2340 2341 if (!rd_buf) 2342 return -ENOMEM; 2343 2344 for (i = 0; i < MAX_PIPES; i++) { 2345 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2346 if (pipe_ctx->stream && 2347 pipe_ctx->stream->link == aconnector->dc_link && 2348 pipe_ctx->stream->sink && 2349 pipe_ctx->stream->sink == aconnector->dc_sink) 2350 break; 2351 } 2352 2353 dsc = pipe_ctx->stream_res.dsc; 2354 if (dsc) 2355 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2356 2357 snprintf(rd_buf, str_len, 2358 "%d\n", 2359 dsc_state.dsc_pic_height); 2360 2361 while (size) { 2362 if (*pos >= rd_buf_size) 2363 break; 2364 2365 r = put_user(*(rd_buf + result), buf); 2366 if (r) { 2367 kfree(rd_buf); 2368 return r; /* r = -EFAULT */ 2369 } 2370 2371 buf += 1; 2372 size -= 1; 2373 *pos += 1; 2374 result += 1; 2375 } 2376 2377 kfree(rd_buf); 2378 return result; 2379 } 2380 2381 /* function: read DSC chunk size parameter on the connector 2382 * 2383 * The read function: dp_dsc_chunk_size_read 2384 * returns dsc chunk size set in the current configuration 2385 * The value is calculated automatically by DSC code 2386 * and depends on slice parameters and bpp target rate 2387 * The return is an integer: 0 or other positive integer 2388 * If 0 then DSC is disabled. 2389 * 2390 * Access it with the following command: 2391 * 2392 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2393 * 2394 * 0 - means that DSC is disabled 2395 */ 2396 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2397 size_t size, loff_t *pos) 2398 { 2399 char *rd_buf = NULL; 2400 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2401 struct display_stream_compressor *dsc; 2402 struct dcn_dsc_state dsc_state = {0}; 2403 const uint32_t rd_buf_size = 100; 2404 struct pipe_ctx *pipe_ctx; 2405 ssize_t result = 0; 2406 int i, r, str_len = 30; 2407 2408 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2409 2410 if (!rd_buf) 2411 return -ENOMEM; 2412 2413 for (i = 0; i < MAX_PIPES; i++) { 2414 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2415 if (pipe_ctx->stream && 2416 pipe_ctx->stream->link == aconnector->dc_link && 2417 pipe_ctx->stream->sink && 2418 pipe_ctx->stream->sink == aconnector->dc_sink) 2419 break; 2420 } 2421 2422 dsc = pipe_ctx->stream_res.dsc; 2423 if (dsc) 2424 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2425 2426 snprintf(rd_buf, str_len, 2427 "%d\n", 2428 dsc_state.dsc_chunk_size); 2429 2430 while (size) { 2431 if (*pos >= rd_buf_size) 2432 break; 2433 2434 r = put_user(*(rd_buf + result), buf); 2435 if (r) { 2436 kfree(rd_buf); 2437 return r; /* r = -EFAULT */ 2438 } 2439 2440 buf += 1; 2441 size -= 1; 2442 *pos += 1; 2443 result += 1; 2444 } 2445 2446 kfree(rd_buf); 2447 return result; 2448 } 2449 2450 /* function: read DSC slice bpg offset on the connector 2451 * 2452 * The read function: dp_dsc_slice_bpg_offset_read 2453 * returns dsc bpg slice offset set in the current configuration 2454 * The value is calculated automatically by DSC code 2455 * and depends on slice parameters and bpp target rate 2456 * The return is an integer: 0 or other positive integer 2457 * If 0 then DSC is disabled. 2458 * 2459 * Access it with the following command: 2460 * 2461 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2462 * 2463 * 0 - means that DSC is disabled 2464 */ 2465 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2466 size_t size, loff_t *pos) 2467 { 2468 char *rd_buf = NULL; 2469 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2470 struct display_stream_compressor *dsc; 2471 struct dcn_dsc_state dsc_state = {0}; 2472 const uint32_t rd_buf_size = 100; 2473 struct pipe_ctx *pipe_ctx; 2474 ssize_t result = 0; 2475 int i, r, str_len = 30; 2476 2477 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2478 2479 if (!rd_buf) 2480 return -ENOMEM; 2481 2482 for (i = 0; i < MAX_PIPES; i++) { 2483 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2484 if (pipe_ctx->stream && 2485 pipe_ctx->stream->link == aconnector->dc_link && 2486 pipe_ctx->stream->sink && 2487 pipe_ctx->stream->sink == aconnector->dc_sink) 2488 break; 2489 } 2490 2491 dsc = pipe_ctx->stream_res.dsc; 2492 if (dsc) 2493 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2494 2495 snprintf(rd_buf, str_len, 2496 "%d\n", 2497 dsc_state.dsc_slice_bpg_offset); 2498 2499 while (size) { 2500 if (*pos >= rd_buf_size) 2501 break; 2502 2503 r = put_user(*(rd_buf + result), buf); 2504 if (r) { 2505 kfree(rd_buf); 2506 return r; /* r = -EFAULT */ 2507 } 2508 2509 buf += 1; 2510 size -= 1; 2511 *pos += 1; 2512 result += 1; 2513 } 2514 2515 kfree(rd_buf); 2516 return result; 2517 } 2518 2519 2520 /* 2521 * function description: Read max_requested_bpc property from the connector 2522 * 2523 * Access it with the following command: 2524 * 2525 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2526 * 2527 */ 2528 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2529 size_t size, loff_t *pos) 2530 { 2531 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2532 struct drm_connector *connector = &aconnector->base; 2533 struct drm_device *dev = connector->dev; 2534 struct dm_connector_state *state; 2535 ssize_t result = 0; 2536 char *rd_buf = NULL; 2537 char *rd_buf_ptr = NULL; 2538 const uint32_t rd_buf_size = 10; 2539 int r; 2540 2541 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2542 2543 if (!rd_buf) 2544 return -ENOMEM; 2545 2546 mutex_lock(&dev->mode_config.mutex); 2547 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2548 2549 if (connector->state == NULL) 2550 goto unlock; 2551 2552 state = to_dm_connector_state(connector->state); 2553 2554 rd_buf_ptr = rd_buf; 2555 snprintf(rd_buf_ptr, rd_buf_size, 2556 "%u\n", 2557 state->base.max_requested_bpc); 2558 2559 while (size) { 2560 if (*pos >= rd_buf_size) 2561 break; 2562 2563 r = put_user(*(rd_buf + result), buf); 2564 if (r) { 2565 result = r; /* r = -EFAULT */ 2566 goto unlock; 2567 } 2568 buf += 1; 2569 size -= 1; 2570 *pos += 1; 2571 result += 1; 2572 } 2573 unlock: 2574 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2575 mutex_unlock(&dev->mode_config.mutex); 2576 kfree(rd_buf); 2577 return result; 2578 } 2579 2580 2581 /* 2582 * function description: Set max_requested_bpc property on the connector 2583 * 2584 * This function will not force the input BPC on connector, it will only 2585 * change the max value. This is equivalent to setting max_bpc through 2586 * xrandr. 2587 * 2588 * The BPC value written must be >= 6 and <= 16. Values outside of this 2589 * range will result in errors. 2590 * 2591 * BPC values: 2592 * 0x6 - 6 BPC 2593 * 0x8 - 8 BPC 2594 * 0xa - 10 BPC 2595 * 0xc - 12 BPC 2596 * 0x10 - 16 BPC 2597 * 2598 * Write the max_bpc in the following way: 2599 * 2600 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2601 * 2602 */ 2603 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2604 size_t size, loff_t *pos) 2605 { 2606 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2607 struct drm_connector *connector = &aconnector->base; 2608 struct dm_connector_state *state; 2609 struct drm_device *dev = connector->dev; 2610 char *wr_buf = NULL; 2611 uint32_t wr_buf_size = 42; 2612 int max_param_num = 1; 2613 long param[1] = {0}; 2614 uint8_t param_nums = 0; 2615 2616 if (size == 0) 2617 return -EINVAL; 2618 2619 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2620 2621 if (!wr_buf) { 2622 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2623 return -ENOSPC; 2624 } 2625 2626 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2627 (long *)param, buf, 2628 max_param_num, 2629 ¶m_nums)) { 2630 kfree(wr_buf); 2631 return -EINVAL; 2632 } 2633 2634 if (param_nums <= 0) { 2635 DRM_DEBUG_DRIVER("user data not be read\n"); 2636 kfree(wr_buf); 2637 return -EINVAL; 2638 } 2639 2640 if (param[0] < 6 || param[0] > 16) { 2641 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2642 kfree(wr_buf); 2643 return -EINVAL; 2644 } 2645 2646 mutex_lock(&dev->mode_config.mutex); 2647 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2648 2649 if (connector->state == NULL) 2650 goto unlock; 2651 2652 state = to_dm_connector_state(connector->state); 2653 state->base.max_requested_bpc = param[0]; 2654 unlock: 2655 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2656 mutex_unlock(&dev->mode_config.mutex); 2657 2658 kfree(wr_buf); 2659 return size; 2660 } 2661 2662 /* 2663 * IPS status. Read only. 2664 * 2665 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status 2666 */ 2667 static int ips_status_show(struct seq_file *m, void *unused) 2668 { 2669 struct amdgpu_device *adev = m->private; 2670 struct dc *dc = adev->dm.dc; 2671 struct dc_dmub_srv *dc_dmub_srv; 2672 2673 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips); 2674 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed); 2675 2676 if (adev->dm.idle_workqueue) { 2677 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable); 2678 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running); 2679 } 2680 2681 dc_dmub_srv = dc->ctx->dmub_srv; 2682 if (dc_dmub_srv && dc_dmub_srv->dmub) { 2683 uint32_t rcg_count, ips1_count, ips2_count; 2684 volatile const struct dmub_shared_state_ips_fw *ips_fw = 2685 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 2686 rcg_count = ips_fw->rcg_entry_count; 2687 ips1_count = ips_fw->ips1_entry_count; 2688 ips2_count = ips_fw->ips2_entry_count; 2689 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n", 2690 rcg_count, 2691 ips1_count, 2692 ips2_count); 2693 rcg_count = ips_fw->rcg_exit_count; 2694 ips1_count = ips_fw->ips1_exit_count; 2695 ips2_count = ips_fw->ips2_exit_count; 2696 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u", 2697 rcg_count, 2698 ips1_count, 2699 ips2_count); 2700 seq_puts(m, "\n"); 2701 } 2702 return 0; 2703 } 2704 2705 /* 2706 * Backlight at this moment. Read only. 2707 * As written to display, taking ABM and backlight lut into account. 2708 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2709 * 2710 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2711 */ 2712 static int current_backlight_show(struct seq_file *m, void *unused) 2713 { 2714 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2715 struct dc_link *link = aconnector->dc_link; 2716 unsigned int backlight; 2717 2718 backlight = dc_link_get_backlight_level(link); 2719 seq_printf(m, "0x%x\n", backlight); 2720 2721 return 0; 2722 } 2723 2724 /* 2725 * Backlight value that is being approached. Read only. 2726 * As written to display, taking ABM and backlight lut into account. 2727 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2728 * 2729 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2730 */ 2731 static int target_backlight_show(struct seq_file *m, void *unused) 2732 { 2733 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2734 struct dc_link *link = aconnector->dc_link; 2735 unsigned int backlight; 2736 2737 backlight = dc_link_get_target_backlight_pwm(link); 2738 seq_printf(m, "0x%x\n", backlight); 2739 2740 return 0; 2741 } 2742 2743 /* 2744 * function description: Determine if the connector is mst connector 2745 * 2746 * This function helps to determine whether a connector is a mst connector. 2747 * - "root" stands for the root connector of the topology 2748 * - "branch" stands for branch device of the topology 2749 * - "end" stands for leaf node connector of the topology 2750 * - "no" stands for the connector is not a device of a mst topology 2751 * Access it with the following command: 2752 * 2753 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2754 * 2755 */ 2756 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2757 { 2758 struct drm_connector *connector = m->private; 2759 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2760 struct drm_dp_mst_topology_mgr *mgr = NULL; 2761 struct drm_dp_mst_port *port = NULL; 2762 char *role = NULL; 2763 2764 mutex_lock(&aconnector->hpd_lock); 2765 2766 if (aconnector->mst_mgr.mst_state) { 2767 role = "root"; 2768 } else if (aconnector->mst_root && 2769 aconnector->mst_root->mst_mgr.mst_state) { 2770 2771 role = "end"; 2772 2773 mgr = &aconnector->mst_root->mst_mgr; 2774 port = aconnector->mst_output_port; 2775 2776 drm_modeset_lock(&mgr->base.lock, NULL); 2777 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2778 port->mcs) 2779 role = "branch"; 2780 drm_modeset_unlock(&mgr->base.lock); 2781 2782 } else { 2783 role = "no"; 2784 } 2785 2786 seq_printf(m, "%s\n", role); 2787 2788 mutex_unlock(&aconnector->hpd_lock); 2789 2790 return 0; 2791 } 2792 2793 /* 2794 * function description: Read out the mst progress status 2795 * 2796 * This function helps to determine the mst progress status of 2797 * a mst connector. 2798 * 2799 * Access it with the following command: 2800 * 2801 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2802 * 2803 */ 2804 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2805 { 2806 struct drm_connector *connector = m->private; 2807 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2808 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2809 int i; 2810 2811 mutex_lock(&aconnector->hpd_lock); 2812 mutex_lock(&adev->dm.dc_lock); 2813 2814 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2815 seq_puts(m, "disabled\n"); 2816 } else { 2817 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2818 seq_printf(m, "%s:%s\n", 2819 mst_progress_status[i], 2820 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2821 } 2822 2823 mutex_unlock(&adev->dm.dc_lock); 2824 mutex_unlock(&aconnector->hpd_lock); 2825 2826 return 0; 2827 } 2828 2829 /* 2830 * Reports whether the connected display is a USB4 DPIA tunneled display 2831 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2832 */ 2833 static int is_dpia_link_show(struct seq_file *m, void *data) 2834 { 2835 struct drm_connector *connector = m->private; 2836 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2837 struct dc_link *link = aconnector->dc_link; 2838 2839 if (connector->status != connector_status_connected) 2840 return -ENODEV; 2841 2842 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2843 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2844 2845 return 0; 2846 } 2847 2848 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2849 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2850 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2851 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2852 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2853 DEFINE_SHOW_ATTRIBUTE(internal_display); 2854 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); 2855 DEFINE_SHOW_ATTRIBUTE(replay_capability); 2856 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2857 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2858 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2859 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2860 2861 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2862 .owner = THIS_MODULE, 2863 .read = dp_dsc_clock_en_read, 2864 .write = dp_dsc_clock_en_write, 2865 .llseek = default_llseek 2866 }; 2867 2868 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2869 .owner = THIS_MODULE, 2870 .read = dp_dsc_slice_width_read, 2871 .write = dp_dsc_slice_width_write, 2872 .llseek = default_llseek 2873 }; 2874 2875 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2876 .owner = THIS_MODULE, 2877 .read = dp_dsc_slice_height_read, 2878 .write = dp_dsc_slice_height_write, 2879 .llseek = default_llseek 2880 }; 2881 2882 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2883 .owner = THIS_MODULE, 2884 .read = dp_dsc_bits_per_pixel_read, 2885 .write = dp_dsc_bits_per_pixel_write, 2886 .llseek = default_llseek 2887 }; 2888 2889 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2890 .owner = THIS_MODULE, 2891 .read = dp_dsc_pic_width_read, 2892 .llseek = default_llseek 2893 }; 2894 2895 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2896 .owner = THIS_MODULE, 2897 .read = dp_dsc_pic_height_read, 2898 .llseek = default_llseek 2899 }; 2900 2901 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2902 .owner = THIS_MODULE, 2903 .read = dp_dsc_chunk_size_read, 2904 .llseek = default_llseek 2905 }; 2906 2907 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2908 .owner = THIS_MODULE, 2909 .read = dp_dsc_slice_bpg_offset_read, 2910 .llseek = default_llseek 2911 }; 2912 2913 static const struct file_operations trigger_hotplug_debugfs_fops = { 2914 .owner = THIS_MODULE, 2915 .write = trigger_hotplug, 2916 .llseek = default_llseek 2917 }; 2918 2919 static const struct file_operations dp_link_settings_debugfs_fops = { 2920 .owner = THIS_MODULE, 2921 .read = dp_link_settings_read, 2922 .write = dp_link_settings_write, 2923 .llseek = default_llseek 2924 }; 2925 2926 static const struct file_operations dp_phy_settings_debugfs_fop = { 2927 .owner = THIS_MODULE, 2928 .read = dp_phy_settings_read, 2929 .write = dp_phy_settings_write, 2930 .llseek = default_llseek 2931 }; 2932 2933 static const struct file_operations dp_phy_test_pattern_fops = { 2934 .owner = THIS_MODULE, 2935 .write = dp_phy_test_pattern_debugfs_write, 2936 .llseek = default_llseek 2937 }; 2938 2939 static const struct file_operations sdp_message_fops = { 2940 .owner = THIS_MODULE, 2941 .write = dp_sdp_message_debugfs_write, 2942 .llseek = default_llseek 2943 }; 2944 2945 static const struct file_operations dp_max_bpc_debugfs_fops = { 2946 .owner = THIS_MODULE, 2947 .read = dp_max_bpc_read, 2948 .write = dp_max_bpc_write, 2949 .llseek = default_llseek 2950 }; 2951 2952 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2953 .owner = THIS_MODULE, 2954 .write = dp_dsc_passthrough_set, 2955 .llseek = default_llseek 2956 }; 2957 2958 static const struct file_operations dp_mst_link_settings_debugfs_fops = { 2959 .owner = THIS_MODULE, 2960 .write = dp_mst_link_setting, 2961 .llseek = default_llseek 2962 }; 2963 2964 static const struct { 2965 char *name; 2966 const struct file_operations *fops; 2967 } dp_debugfs_entries[] = { 2968 {"link_settings", &dp_link_settings_debugfs_fops}, 2969 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2970 {"lttpr_status", &dp_lttpr_status_fops}, 2971 {"test_pattern", &dp_phy_test_pattern_fops}, 2972 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2973 {"sdp_message", &sdp_message_fops}, 2974 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2975 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2976 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2977 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2978 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2979 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2980 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2981 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2982 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2983 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2984 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2985 {"is_mst_connector", &dp_is_mst_connector_fops}, 2986 {"mst_progress_status", &dp_mst_progress_status_fops}, 2987 {"is_dpia_link", &is_dpia_link_fops}, 2988 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} 2989 }; 2990 2991 static const struct { 2992 char *name; 2993 const struct file_operations *fops; 2994 } hdmi_debugfs_entries[] = { 2995 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2996 }; 2997 2998 /* 2999 * Force YUV420 output if available from the given mode 3000 */ 3001 static int force_yuv420_output_set(void *data, u64 val) 3002 { 3003 struct amdgpu_dm_connector *connector = data; 3004 3005 connector->force_yuv420_output = (bool)val; 3006 3007 return 0; 3008 } 3009 3010 /* 3011 * Check if YUV420 is forced when available from the given mode 3012 */ 3013 static int force_yuv420_output_get(void *data, u64 *val) 3014 { 3015 struct amdgpu_dm_connector *connector = data; 3016 3017 *val = connector->force_yuv420_output; 3018 3019 return 0; 3020 } 3021 3022 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 3023 force_yuv420_output_set, "%llu\n"); 3024 3025 /* 3026 * Read Replay state 3027 */ 3028 static int replay_get_state(void *data, u64 *val) 3029 { 3030 struct amdgpu_dm_connector *connector = data; 3031 struct dc_link *link = connector->dc_link; 3032 uint64_t state = REPLAY_STATE_INVALID; 3033 3034 dc_link_get_replay_state(link, &state); 3035 3036 *val = state; 3037 3038 return 0; 3039 } 3040 3041 /* 3042 * Read PSR state 3043 */ 3044 static int psr_get(void *data, u64 *val) 3045 { 3046 struct amdgpu_dm_connector *connector = data; 3047 struct dc_link *link = connector->dc_link; 3048 enum dc_psr_state state = PSR_STATE0; 3049 3050 dc_link_get_psr_state(link, &state); 3051 3052 *val = state; 3053 3054 return 0; 3055 } 3056 3057 /* 3058 * Read PSR state residency 3059 */ 3060 static int psr_read_residency(void *data, u64 *val) 3061 { 3062 struct amdgpu_dm_connector *connector = data; 3063 struct dc_link *link = connector->dc_link; 3064 u32 residency = 0; 3065 3066 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY); 3067 3068 *val = (u64)residency; 3069 3070 return 0; 3071 } 3072 3073 /* read allow_edp_hotplug_detection */ 3074 static int allow_edp_hotplug_detection_get(void *data, u64 *val) 3075 { 3076 struct amdgpu_dm_connector *aconnector = data; 3077 struct drm_connector *connector = &aconnector->base; 3078 struct drm_device *dev = connector->dev; 3079 struct amdgpu_device *adev = drm_to_adev(dev); 3080 3081 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 3082 3083 return 0; 3084 } 3085 3086 /* set allow_edp_hotplug_detection */ 3087 static int allow_edp_hotplug_detection_set(void *data, u64 val) 3088 { 3089 struct amdgpu_dm_connector *aconnector = data; 3090 struct drm_connector *connector = &aconnector->base; 3091 struct drm_device *dev = connector->dev; 3092 struct amdgpu_device *adev = drm_to_adev(dev); 3093 3094 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 3095 3096 return 0; 3097 } 3098 3099 /* check if kernel disallow eDP enter psr state 3100 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3101 * 0: allow edp enter psr; 1: disallow 3102 */ 3103 static int disallow_edp_enter_psr_get(void *data, u64 *val) 3104 { 3105 struct amdgpu_dm_connector *aconnector = data; 3106 3107 *val = (u64) aconnector->disallow_edp_enter_psr; 3108 return 0; 3109 } 3110 3111 /* set kernel disallow eDP enter psr state 3112 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3113 * 0: allow edp enter psr; 1: disallow 3114 * 3115 * usage: test app read crc from PSR eDP rx. 3116 * 3117 * during kernel boot up, kernel write dpcd 0x170 = 5. 3118 * this notify eDP rx psr enable and let rx check crc. 3119 * rx fw will start checking crc for rx internal logic. 3120 * crc read count within dpcd 0x246 is not updated and 3121 * value is 0. when eDP tx driver wants to read rx crc 3122 * from dpcd 0x246, 0x270, read count 0 lead tx driver 3123 * timeout. 3124 * 3125 * to avoid this, we add this debugfs to let test app to disbable 3126 * rx crc checking for rx internal logic. then test app can read 3127 * non-zero crc read count. 3128 * 3129 * expected app sequence is as below: 3130 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. 3131 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3132 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but 3133 * without dpcd 0x170 = 5. 3134 * 4. read crc from rx dpcd 0x270, 0x246, etc. 3135 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr. 3136 * this will let eDP back to normal with psr setup dpcd 0x170 = 5. 3137 */ 3138 static int disallow_edp_enter_psr_set(void *data, u64 val) 3139 { 3140 struct amdgpu_dm_connector *aconnector = data; 3141 3142 aconnector->disallow_edp_enter_psr = val ? true : false; 3143 return 0; 3144 } 3145 3146 static int dmub_trace_mask_set(void *data, u64 val) 3147 { 3148 struct amdgpu_device *adev = data; 3149 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3150 enum dmub_gpint_command cmd; 3151 u64 mask = 0xffff; 3152 u8 shift = 0; 3153 u32 res; 3154 int i; 3155 3156 if (!srv->fw_version) 3157 return -EINVAL; 3158 3159 for (i = 0; i < 4; i++) { 3160 res = (val & mask) >> shift; 3161 3162 switch (i) { 3163 case 0: 3164 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0; 3165 break; 3166 case 1: 3167 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1; 3168 break; 3169 case 2: 3170 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2; 3171 break; 3172 case 3: 3173 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3; 3174 break; 3175 } 3176 3177 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT)) 3178 return -EIO; 3179 3180 usleep_range(100, 1000); 3181 3182 mask <<= 16; 3183 shift += 16; 3184 } 3185 3186 return 0; 3187 } 3188 3189 static int dmub_trace_mask_show(void *data, u64 *val) 3190 { 3191 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0; 3192 struct amdgpu_device *adev = data; 3193 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3194 u8 shift = 0; 3195 u64 raw = 0; 3196 u64 res = 0; 3197 int i = 0; 3198 3199 if (!srv->fw_version) 3200 return -EINVAL; 3201 3202 while (i < 4) { 3203 uint32_t response; 3204 3205 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 3206 return -EIO; 3207 3208 raw = response; 3209 usleep_range(100, 1000); 3210 3211 cmd++; 3212 res |= (raw << shift); 3213 shift += 16; 3214 i++; 3215 } 3216 3217 *val = res; 3218 3219 return 0; 3220 } 3221 3222 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, 3223 dmub_trace_mask_set, "0x%llx\n"); 3224 3225 /* 3226 * Set dmcub trace event IRQ enable or disable. 3227 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3228 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3229 */ 3230 static int dmcub_trace_event_state_set(void *data, u64 val) 3231 { 3232 struct amdgpu_device *adev = data; 3233 3234 if (val == 1 || val == 0) { 3235 dc_dmub_trace_event_control(adev->dm.dc, val); 3236 adev->dm.dmcub_trace_event_en = (bool)val; 3237 } else 3238 return 0; 3239 3240 return 0; 3241 } 3242 3243 /* 3244 * The interface doesn't need get function, so it will return the 3245 * value of zero 3246 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3247 */ 3248 static int dmcub_trace_event_state_get(void *data, u64 *val) 3249 { 3250 struct amdgpu_device *adev = data; 3251 3252 *val = adev->dm.dmcub_trace_event_en; 3253 return 0; 3254 } 3255 3256 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 3257 dmcub_trace_event_state_set, "%llu\n"); 3258 3259 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n"); 3260 3261 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 3262 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 3263 "%llu\n"); 3264 3265 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 3266 allow_edp_hotplug_detection_get, 3267 allow_edp_hotplug_detection_set, "%llu\n"); 3268 3269 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, 3270 disallow_edp_enter_psr_get, 3271 disallow_edp_enter_psr_set, "%llu\n"); 3272 3273 DEFINE_SHOW_ATTRIBUTE(current_backlight); 3274 DEFINE_SHOW_ATTRIBUTE(target_backlight); 3275 DEFINE_SHOW_ATTRIBUTE(ips_status); 3276 3277 static const struct { 3278 char *name; 3279 const struct file_operations *fops; 3280 } connector_debugfs_entries[] = { 3281 {"force_yuv420_output", &force_yuv420_output_fops}, 3282 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 3283 {"internal_display", &internal_display_fops}, 3284 {"odm_combine_segments", &odm_combine_segments_fops} 3285 }; 3286 3287 /* 3288 * Returns supported customized link rates by this eDP panel. 3289 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3290 */ 3291 static int edp_ilr_show(struct seq_file *m, void *unused) 3292 { 3293 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 3294 struct dc_link *link = aconnector->dc_link; 3295 uint8_t supported_link_rates[16]; 3296 uint32_t link_rate_in_khz; 3297 uint32_t entry = 0; 3298 uint8_t dpcd_rev; 3299 3300 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 3301 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3302 supported_link_rates, sizeof(supported_link_rates)); 3303 3304 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3305 3306 if (dpcd_rev >= DP_DPCD_REV_13 && 3307 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 3308 3309 for (entry = 0; entry < 16; entry += 2) { 3310 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 3311 supported_link_rates[entry]) * 200; 3312 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 3313 } 3314 } else { 3315 seq_puts(m, "ILR is not supported by this eDP panel.\n"); 3316 } 3317 3318 return 0; 3319 } 3320 3321 /* 3322 * Set supported customized link rate to eDP panel. 3323 * 3324 * echo <lane_count> <link_rate option> > ilr_setting 3325 * 3326 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 3327 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3328 * to set 4 lanes and 2.16 GHz 3329 */ 3330 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 3331 size_t size, loff_t *pos) 3332 { 3333 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 3334 struct dc_link *link = connector->dc_link; 3335 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3336 struct dc *dc = (struct dc *)link->dc; 3337 struct dc_link_settings prefer_link_settings; 3338 char *wr_buf = NULL; 3339 const uint32_t wr_buf_size = 40; 3340 /* 0: lane_count; 1: link_rate */ 3341 int max_param_num = 2; 3342 uint8_t param_nums = 0; 3343 long param[2]; 3344 bool valid_input = true; 3345 3346 if (size == 0) 3347 return -EINVAL; 3348 3349 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 3350 if (!wr_buf) 3351 return -ENOMEM; 3352 3353 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 3354 (long *)param, buf, 3355 max_param_num, 3356 ¶m_nums)) { 3357 kfree(wr_buf); 3358 return -EINVAL; 3359 } 3360 3361 if (param_nums <= 0) { 3362 kfree(wr_buf); 3363 return -EINVAL; 3364 } 3365 3366 switch (param[0]) { 3367 case LANE_COUNT_ONE: 3368 case LANE_COUNT_TWO: 3369 case LANE_COUNT_FOUR: 3370 break; 3371 default: 3372 valid_input = false; 3373 break; 3374 } 3375 3376 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 3377 valid_input = false; 3378 3379 if (!valid_input) { 3380 kfree(wr_buf); 3381 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 3382 prefer_link_settings.use_link_rate_set = false; 3383 mutex_lock(&adev->dm.dc_lock); 3384 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 3385 mutex_unlock(&adev->dm.dc_lock); 3386 return size; 3387 } 3388 3389 /* save user force lane_count, link_rate to preferred settings 3390 * spread spectrum will not be changed 3391 */ 3392 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3393 prefer_link_settings.lane_count = param[0]; 3394 prefer_link_settings.use_link_rate_set = true; 3395 prefer_link_settings.link_rate_set = param[1]; 3396 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3397 3398 mutex_lock(&adev->dm.dc_lock); 3399 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3400 NULL, link, false); 3401 mutex_unlock(&adev->dm.dc_lock); 3402 3403 kfree(wr_buf); 3404 return size; 3405 } 3406 3407 static int edp_ilr_open(struct inode *inode, struct file *file) 3408 { 3409 return single_open(file, edp_ilr_show, inode->i_private); 3410 } 3411 3412 static const struct file_operations edp_ilr_debugfs_fops = { 3413 .owner = THIS_MODULE, 3414 .open = edp_ilr_open, 3415 .read = seq_read, 3416 .llseek = seq_lseek, 3417 .release = single_release, 3418 .write = edp_ilr_write 3419 }; 3420 3421 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3422 { 3423 int i; 3424 struct dentry *dir = connector->base.debugfs_entry; 3425 3426 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3427 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3428 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3429 debugfs_create_file(dp_debugfs_entries[i].name, 3430 0644, dir, connector, 3431 dp_debugfs_entries[i].fops); 3432 } 3433 } 3434 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3435 debugfs_create_file("replay_capability", 0444, dir, connector, 3436 &replay_capability_fops); 3437 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops); 3438 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3439 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3440 debugfs_create_file_unsafe("psr_residency", 0444, dir, 3441 connector, &psr_residency_fops); 3442 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3443 ¤t_backlight_fops); 3444 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3445 &target_backlight_fops); 3446 debugfs_create_file("ilr_setting", 0644, dir, connector, 3447 &edp_ilr_debugfs_fops); 3448 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3449 &allow_edp_hotplug_detection_fops); 3450 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, 3451 &disallow_edp_enter_psr_fops); 3452 } 3453 3454 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3455 debugfs_create_file(connector_debugfs_entries[i].name, 3456 0644, dir, connector, 3457 connector_debugfs_entries[i].fops); 3458 } 3459 3460 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3461 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3462 debugfs_create_file(hdmi_debugfs_entries[i].name, 3463 0644, dir, connector, 3464 hdmi_debugfs_entries[i].fops); 3465 } 3466 } 3467 } 3468 3469 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3470 /* 3471 * Set crc window coordinate x start 3472 */ 3473 static int crc_win_x_start_set(void *data, u64 val) 3474 { 3475 struct drm_crtc *crtc = data; 3476 struct drm_device *drm_dev = crtc->dev; 3477 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3478 3479 spin_lock_irq(&drm_dev->event_lock); 3480 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3481 acrtc->dm_irq_params.window_param.update_win = false; 3482 spin_unlock_irq(&drm_dev->event_lock); 3483 3484 return 0; 3485 } 3486 3487 /* 3488 * Get crc window coordinate x start 3489 */ 3490 static int crc_win_x_start_get(void *data, u64 *val) 3491 { 3492 struct drm_crtc *crtc = data; 3493 struct drm_device *drm_dev = crtc->dev; 3494 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3495 3496 spin_lock_irq(&drm_dev->event_lock); 3497 *val = acrtc->dm_irq_params.window_param.x_start; 3498 spin_unlock_irq(&drm_dev->event_lock); 3499 3500 return 0; 3501 } 3502 3503 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3504 crc_win_x_start_set, "%llu\n"); 3505 3506 3507 /* 3508 * Set crc window coordinate y start 3509 */ 3510 static int crc_win_y_start_set(void *data, u64 val) 3511 { 3512 struct drm_crtc *crtc = data; 3513 struct drm_device *drm_dev = crtc->dev; 3514 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3515 3516 spin_lock_irq(&drm_dev->event_lock); 3517 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3518 acrtc->dm_irq_params.window_param.update_win = false; 3519 spin_unlock_irq(&drm_dev->event_lock); 3520 3521 return 0; 3522 } 3523 3524 /* 3525 * Get crc window coordinate y start 3526 */ 3527 static int crc_win_y_start_get(void *data, u64 *val) 3528 { 3529 struct drm_crtc *crtc = data; 3530 struct drm_device *drm_dev = crtc->dev; 3531 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3532 3533 spin_lock_irq(&drm_dev->event_lock); 3534 *val = acrtc->dm_irq_params.window_param.y_start; 3535 spin_unlock_irq(&drm_dev->event_lock); 3536 3537 return 0; 3538 } 3539 3540 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3541 crc_win_y_start_set, "%llu\n"); 3542 3543 /* 3544 * Set crc window coordinate x end 3545 */ 3546 static int crc_win_x_end_set(void *data, u64 val) 3547 { 3548 struct drm_crtc *crtc = data; 3549 struct drm_device *drm_dev = crtc->dev; 3550 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3551 3552 spin_lock_irq(&drm_dev->event_lock); 3553 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3554 acrtc->dm_irq_params.window_param.update_win = false; 3555 spin_unlock_irq(&drm_dev->event_lock); 3556 3557 return 0; 3558 } 3559 3560 /* 3561 * Get crc window coordinate x end 3562 */ 3563 static int crc_win_x_end_get(void *data, u64 *val) 3564 { 3565 struct drm_crtc *crtc = data; 3566 struct drm_device *drm_dev = crtc->dev; 3567 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3568 3569 spin_lock_irq(&drm_dev->event_lock); 3570 *val = acrtc->dm_irq_params.window_param.x_end; 3571 spin_unlock_irq(&drm_dev->event_lock); 3572 3573 return 0; 3574 } 3575 3576 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3577 crc_win_x_end_set, "%llu\n"); 3578 3579 /* 3580 * Set crc window coordinate y end 3581 */ 3582 static int crc_win_y_end_set(void *data, u64 val) 3583 { 3584 struct drm_crtc *crtc = data; 3585 struct drm_device *drm_dev = crtc->dev; 3586 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3587 3588 spin_lock_irq(&drm_dev->event_lock); 3589 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3590 acrtc->dm_irq_params.window_param.update_win = false; 3591 spin_unlock_irq(&drm_dev->event_lock); 3592 3593 return 0; 3594 } 3595 3596 /* 3597 * Get crc window coordinate y end 3598 */ 3599 static int crc_win_y_end_get(void *data, u64 *val) 3600 { 3601 struct drm_crtc *crtc = data; 3602 struct drm_device *drm_dev = crtc->dev; 3603 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3604 3605 spin_lock_irq(&drm_dev->event_lock); 3606 *val = acrtc->dm_irq_params.window_param.y_end; 3607 spin_unlock_irq(&drm_dev->event_lock); 3608 3609 return 0; 3610 } 3611 3612 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3613 crc_win_y_end_set, "%llu\n"); 3614 /* 3615 * Trigger to commit crc window 3616 */ 3617 static int crc_win_update_set(void *data, u64 val) 3618 { 3619 struct drm_crtc *crtc = data; 3620 struct amdgpu_crtc *acrtc; 3621 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3622 3623 if (val) { 3624 acrtc = to_amdgpu_crtc(crtc); 3625 mutex_lock(&adev->dm.dc_lock); 3626 /* PSR may write to OTG CRC window control register, 3627 * so close it before starting secure_display. 3628 */ 3629 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3630 3631 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3632 3633 acrtc->dm_irq_params.window_param.activated = true; 3634 acrtc->dm_irq_params.window_param.update_win = true; 3635 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3636 3637 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3638 mutex_unlock(&adev->dm.dc_lock); 3639 } 3640 3641 return 0; 3642 } 3643 3644 /* 3645 * Get crc window update flag 3646 */ 3647 static int crc_win_update_get(void *data, u64 *val) 3648 { 3649 *val = 0; 3650 return 0; 3651 } 3652 3653 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3654 crc_win_update_set, "%llu\n"); 3655 #endif 3656 void crtc_debugfs_init(struct drm_crtc *crtc) 3657 { 3658 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3659 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3660 3661 if (!dir) 3662 return; 3663 3664 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3665 &crc_win_x_start_fops); 3666 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3667 &crc_win_y_start_fops); 3668 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3669 &crc_win_x_end_fops); 3670 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3671 &crc_win_y_end_fops); 3672 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3673 &crc_win_update_fops); 3674 dput(dir); 3675 #endif 3676 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3677 crtc, &amdgpu_current_bpc_fops); 3678 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 3679 crtc, &amdgpu_current_colorspace_fops); 3680 } 3681 3682 /* 3683 * Writes DTN log state to the user supplied buffer. 3684 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3685 */ 3686 static ssize_t dtn_log_read( 3687 struct file *f, 3688 char __user *buf, 3689 size_t size, 3690 loff_t *pos) 3691 { 3692 struct amdgpu_device *adev = file_inode(f)->i_private; 3693 struct dc *dc = adev->dm.dc; 3694 struct dc_log_buffer_ctx log_ctx = { 0 }; 3695 ssize_t result = 0; 3696 3697 if (!buf || !size) 3698 return -EINVAL; 3699 3700 if (!dc->hwss.log_hw_state) 3701 return 0; 3702 3703 dc->hwss.log_hw_state(dc, &log_ctx); 3704 3705 if (*pos < log_ctx.pos) { 3706 size_t to_copy = log_ctx.pos - *pos; 3707 3708 to_copy = min(to_copy, size); 3709 3710 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3711 *pos += to_copy; 3712 result = to_copy; 3713 } 3714 } 3715 3716 kfree(log_ctx.buf); 3717 3718 return result; 3719 } 3720 3721 /* 3722 * Writes DTN log state to dmesg when triggered via a write. 3723 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3724 */ 3725 static ssize_t dtn_log_write( 3726 struct file *f, 3727 const char __user *buf, 3728 size_t size, 3729 loff_t *pos) 3730 { 3731 struct amdgpu_device *adev = file_inode(f)->i_private; 3732 struct dc *dc = adev->dm.dc; 3733 3734 /* Write triggers log output via dmesg. */ 3735 if (size == 0) 3736 return 0; 3737 3738 if (dc->hwss.log_hw_state) 3739 dc->hwss.log_hw_state(dc, NULL); 3740 3741 return size; 3742 } 3743 3744 static int mst_topo_show(struct seq_file *m, void *unused) 3745 { 3746 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3747 struct drm_device *dev = adev_to_drm(adev); 3748 struct drm_connector *connector; 3749 struct drm_connector_list_iter conn_iter; 3750 struct amdgpu_dm_connector *aconnector; 3751 3752 drm_connector_list_iter_begin(dev, &conn_iter); 3753 drm_for_each_connector_iter(connector, &conn_iter) { 3754 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3755 continue; 3756 3757 aconnector = to_amdgpu_dm_connector(connector); 3758 3759 /* Ensure we're only dumping the topology of a root mst node */ 3760 if (!aconnector->mst_mgr.mst_state) 3761 continue; 3762 3763 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3764 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3765 } 3766 drm_connector_list_iter_end(&conn_iter); 3767 3768 return 0; 3769 } 3770 3771 /* 3772 * Sets trigger hpd for MST topologies. 3773 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3774 * All topologies will be disconnected if val of 0 is set . 3775 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3776 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3777 */ 3778 static int trigger_hpd_mst_set(void *data, u64 val) 3779 { 3780 struct amdgpu_device *adev = data; 3781 struct drm_device *dev = adev_to_drm(adev); 3782 struct drm_connector_list_iter iter; 3783 struct amdgpu_dm_connector *aconnector; 3784 struct drm_connector *connector; 3785 struct dc_link *link = NULL; 3786 int ret; 3787 3788 if (val == 1) { 3789 drm_connector_list_iter_begin(dev, &iter); 3790 drm_for_each_connector_iter(connector, &iter) { 3791 aconnector = to_amdgpu_dm_connector(connector); 3792 if (aconnector->dc_link->type == dc_connection_mst_branch && 3793 aconnector->mst_mgr.aux) { 3794 mutex_lock(&adev->dm.dc_lock); 3795 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3796 mutex_unlock(&adev->dm.dc_lock); 3797 3798 if (!ret) 3799 DRM_ERROR("DM_MST: Failed to detect dc link!"); 3800 3801 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3802 if (ret < 0) 3803 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 3804 } 3805 } 3806 } else if (val == 0) { 3807 drm_connector_list_iter_begin(dev, &iter); 3808 drm_for_each_connector_iter(connector, &iter) { 3809 aconnector = to_amdgpu_dm_connector(connector); 3810 if (!aconnector->dc_link) 3811 continue; 3812 3813 if (!aconnector->mst_root) 3814 continue; 3815 3816 link = aconnector->dc_link; 3817 dc_link_dp_receiver_power_ctrl(link, false); 3818 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3819 link->mst_stream_alloc_table.stream_count = 0; 3820 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3821 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3822 } 3823 } else { 3824 return 0; 3825 } 3826 drm_kms_helper_hotplug_event(dev); 3827 3828 return 0; 3829 } 3830 3831 /* 3832 * The interface doesn't need get function, so it will return the 3833 * value of zero 3834 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3835 */ 3836 static int trigger_hpd_mst_get(void *data, u64 *val) 3837 { 3838 *val = 0; 3839 return 0; 3840 } 3841 3842 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3843 trigger_hpd_mst_set, "%llu\n"); 3844 3845 3846 /* 3847 * Sets the force_timing_sync debug option from the given string. 3848 * All connected displays will be force synchronized immediately. 3849 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3850 */ 3851 static int force_timing_sync_set(void *data, u64 val) 3852 { 3853 struct amdgpu_device *adev = data; 3854 3855 adev->dm.force_timing_sync = (bool)val; 3856 3857 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3858 3859 return 0; 3860 } 3861 3862 /* 3863 * Gets the force_timing_sync debug option value into the given buffer. 3864 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3865 */ 3866 static int force_timing_sync_get(void *data, u64 *val) 3867 { 3868 struct amdgpu_device *adev = data; 3869 3870 *val = adev->dm.force_timing_sync; 3871 3872 return 0; 3873 } 3874 3875 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3876 force_timing_sync_set, "%llu\n"); 3877 3878 3879 /* 3880 * Disables all HPD and HPD RX interrupt handling in the 3881 * driver when set to 1. Default is 0. 3882 */ 3883 static int disable_hpd_set(void *data, u64 val) 3884 { 3885 struct amdgpu_device *adev = data; 3886 3887 adev->dm.disable_hpd_irq = (bool)val; 3888 3889 return 0; 3890 } 3891 3892 3893 /* 3894 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3895 * 0 otherwise. 3896 */ 3897 static int disable_hpd_get(void *data, u64 *val) 3898 { 3899 struct amdgpu_device *adev = data; 3900 3901 *val = adev->dm.disable_hpd_irq; 3902 3903 return 0; 3904 } 3905 3906 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3907 disable_hpd_set, "%llu\n"); 3908 3909 /* 3910 * Prints hardware capabilities. These are used for IGT testing. 3911 */ 3912 static int capabilities_show(struct seq_file *m, void *unused) 3913 { 3914 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3915 struct dc *dc = adev->dm.dc; 3916 bool mall_supported = dc->caps.mall_size_total; 3917 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us; 3918 unsigned int mall_in_use = false; 3919 unsigned int subvp_in_use = false; 3920 3921 struct hubbub *hubbub = dc->res_pool->hubbub; 3922 3923 if (hubbub->funcs->get_mall_en) 3924 hubbub->funcs->get_mall_en(hubbub, &mall_in_use); 3925 3926 if (dc->cap_funcs.get_subvp_en) 3927 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state); 3928 3929 seq_printf(m, "mall supported: %s, enabled: %s\n", 3930 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no"); 3931 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n", 3932 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no"); 3933 3934 return 0; 3935 } 3936 3937 DEFINE_SHOW_ATTRIBUTE(capabilities); 3938 3939 /* 3940 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3941 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3942 */ 3943 static int dp_force_sst_set(void *data, u64 val) 3944 { 3945 struct amdgpu_device *adev = data; 3946 3947 adev->dm.dc->debug.set_mst_en_for_sst = val; 3948 3949 return 0; 3950 } 3951 3952 static int dp_force_sst_get(void *data, u64 *val) 3953 { 3954 struct amdgpu_device *adev = data; 3955 3956 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3957 3958 return 0; 3959 } 3960 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3961 dp_force_sst_set, "%llu\n"); 3962 3963 /* 3964 * Force DP2 sequence without VESA certified cable. 3965 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3966 */ 3967 static int dp_ignore_cable_id_set(void *data, u64 val) 3968 { 3969 struct amdgpu_device *adev = data; 3970 3971 adev->dm.dc->debug.ignore_cable_id = val; 3972 3973 return 0; 3974 } 3975 3976 static int dp_ignore_cable_id_get(void *data, u64 *val) 3977 { 3978 struct amdgpu_device *adev = data; 3979 3980 *val = adev->dm.dc->debug.ignore_cable_id; 3981 3982 return 0; 3983 } 3984 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3985 dp_ignore_cable_id_set, "%llu\n"); 3986 3987 /* 3988 * Sets the DC visual confirm debug option from the given string. 3989 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3990 */ 3991 static int visual_confirm_set(void *data, u64 val) 3992 { 3993 struct amdgpu_device *adev = data; 3994 3995 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3996 3997 return 0; 3998 } 3999 4000 /* 4001 * Reads the DC visual confirm debug option value into the given buffer. 4002 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 4003 */ 4004 static int visual_confirm_get(void *data, u64 *val) 4005 { 4006 struct amdgpu_device *adev = data; 4007 4008 *val = adev->dm.dc->debug.visual_confirm; 4009 4010 return 0; 4011 } 4012 4013 DEFINE_SHOW_ATTRIBUTE(mst_topo); 4014 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 4015 visual_confirm_set, "%llu\n"); 4016 4017 4018 /* 4019 * Sets the DC skip_detection_link_training debug option from the given string. 4020 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 4021 */ 4022 static int skip_detection_link_training_set(void *data, u64 val) 4023 { 4024 struct amdgpu_device *adev = data; 4025 4026 if (val == 0) 4027 adev->dm.dc->debug.skip_detection_link_training = false; 4028 else 4029 adev->dm.dc->debug.skip_detection_link_training = true; 4030 4031 return 0; 4032 } 4033 4034 /* 4035 * Reads the DC skip_detection_link_training debug option value into the given buffer. 4036 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 4037 */ 4038 static int skip_detection_link_training_get(void *data, u64 *val) 4039 { 4040 struct amdgpu_device *adev = data; 4041 4042 *val = adev->dm.dc->debug.skip_detection_link_training; 4043 4044 return 0; 4045 } 4046 4047 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 4048 skip_detection_link_training_get, 4049 skip_detection_link_training_set, "%llu\n"); 4050 4051 /* 4052 * Dumps the DCC_EN bit for each pipe. 4053 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 4054 */ 4055 static ssize_t dcc_en_bits_read( 4056 struct file *f, 4057 char __user *buf, 4058 size_t size, 4059 loff_t *pos) 4060 { 4061 struct amdgpu_device *adev = file_inode(f)->i_private; 4062 struct dc *dc = adev->dm.dc; 4063 char *rd_buf = NULL; 4064 const uint32_t rd_buf_size = 32; 4065 uint32_t result = 0; 4066 int offset = 0; 4067 int num_pipes = dc->res_pool->pipe_count; 4068 int *dcc_en_bits; 4069 int i, r; 4070 4071 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 4072 if (!dcc_en_bits) 4073 return -ENOMEM; 4074 4075 if (!dc->hwss.get_dcc_en_bits) { 4076 kfree(dcc_en_bits); 4077 return 0; 4078 } 4079 4080 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 4081 4082 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 4083 if (!rd_buf) { 4084 kfree(dcc_en_bits); 4085 return -ENOMEM; 4086 } 4087 4088 for (i = 0; i < num_pipes; i++) 4089 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 4090 "%d ", dcc_en_bits[i]); 4091 rd_buf[strlen(rd_buf)] = '\n'; 4092 4093 kfree(dcc_en_bits); 4094 4095 while (size) { 4096 if (*pos >= rd_buf_size) 4097 break; 4098 r = put_user(*(rd_buf + result), buf); 4099 if (r) { 4100 kfree(rd_buf); 4101 return r; /* r = -EFAULT */ 4102 } 4103 buf += 1; 4104 size -= 1; 4105 *pos += 1; 4106 result += 1; 4107 } 4108 4109 kfree(rd_buf); 4110 return result; 4111 } 4112 4113 void dtn_debugfs_init(struct amdgpu_device *adev) 4114 { 4115 static const struct file_operations dtn_log_fops = { 4116 .owner = THIS_MODULE, 4117 .read = dtn_log_read, 4118 .write = dtn_log_write, 4119 .llseek = default_llseek 4120 }; 4121 static const struct file_operations dcc_en_bits_fops = { 4122 .owner = THIS_MODULE, 4123 .read = dcc_en_bits_read, 4124 .llseek = default_llseek 4125 }; 4126 4127 struct drm_minor *minor = adev_to_drm(adev)->primary; 4128 struct dentry *root = minor->debugfs_root; 4129 4130 debugfs_create_file("amdgpu_mst_topology", 0444, root, 4131 adev, &mst_topo_fops); 4132 debugfs_create_file("amdgpu_dm_capabilities", 0444, root, 4133 adev, &capabilities_fops); 4134 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 4135 &dtn_log_fops); 4136 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 4137 &dp_set_mst_en_for_sst_ops); 4138 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 4139 &dp_ignore_cable_id_ops); 4140 4141 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 4142 &visual_confirm_fops); 4143 4144 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 4145 &skip_detection_link_training_fops); 4146 4147 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 4148 adev, &dmub_tracebuffer_fops); 4149 4150 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 4151 adev, &dmub_fw_state_fops); 4152 4153 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 4154 adev, &force_timing_sync_ops); 4155 4156 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root, 4157 adev, &dmub_trace_mask_fops); 4158 4159 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 4160 adev, &dmcub_trace_event_state_fops); 4161 4162 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 4163 adev, &trigger_hpd_mst_ops); 4164 4165 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 4166 &dcc_en_bits_fops); 4167 4168 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 4169 &disable_hpd_ops); 4170 4171 if (adev->dm.dc->caps.ips_support) 4172 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, 4173 &ips_status_fops); 4174 } 4175