1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/uaccess.h> 27 #include <drm/drm_drv.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 41 struct dmub_debugfs_trace_header { 42 uint32_t entry_count; 43 uint32_t reserved[3]; 44 }; 45 46 struct dmub_debugfs_trace_entry { 47 uint32_t trace_code; 48 uint32_t tick_count; 49 uint32_t param0; 50 uint32_t param1; 51 }; 52 53 static inline const char *yesno(bool v) 54 { 55 return v ? "yes" : "no"; 56 } 57 58 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 59 * 60 * Function takes in attributes passed to debugfs write entry 61 * and writes into param array. 62 * The user passes max_param_num to identify maximum number of 63 * parameters that could be parsed. 64 * 65 */ 66 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 67 long *param, const char __user *buf, 68 int max_param_num, 69 uint8_t *param_nums) 70 { 71 char *wr_buf_ptr = NULL; 72 uint32_t wr_buf_count = 0; 73 int r; 74 char *sub_str = NULL; 75 const char delimiter[3] = {' ', '\n', '\0'}; 76 uint8_t param_index = 0; 77 78 *param_nums = 0; 79 80 wr_buf_ptr = wr_buf; 81 82 r = copy_from_user(wr_buf_ptr, buf, wr_buf_size); 83 84 /* r is bytes not be copied */ 85 if (r >= wr_buf_size) { 86 DRM_DEBUG_DRIVER("user data not be read\n"); 87 return -EINVAL; 88 } 89 90 /* check number of parameters. isspace could not differ space and \n */ 91 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 92 /* skip space*/ 93 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 94 wr_buf_ptr++; 95 wr_buf_count++; 96 } 97 98 if (wr_buf_count == wr_buf_size) 99 break; 100 101 /* skip non-space*/ 102 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 103 wr_buf_ptr++; 104 wr_buf_count++; 105 } 106 107 (*param_nums)++; 108 109 if (wr_buf_count == wr_buf_size) 110 break; 111 } 112 113 if (*param_nums > max_param_num) 114 *param_nums = max_param_num; 115 116 wr_buf_ptr = wr_buf; /* reset buf pointer */ 117 wr_buf_count = 0; /* number of char already checked */ 118 119 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 120 wr_buf_ptr++; 121 wr_buf_count++; 122 } 123 124 while (param_index < *param_nums) { 125 /* after strsep, wr_buf_ptr will be moved to after space */ 126 sub_str = strsep(&wr_buf_ptr, delimiter); 127 128 r = kstrtol(sub_str, 16, &(param[param_index])); 129 130 if (r) 131 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 132 133 param_index++; 134 } 135 136 return 0; 137 } 138 139 /* function description 140 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 141 * 142 * valid lane count value: 1, 2, 4 143 * valid link rate value: 144 * 06h = 1.62Gbps per lane 145 * 0Ah = 2.7Gbps per lane 146 * 0Ch = 3.24Gbps per lane 147 * 14h = 5.4Gbps per lane 148 * 1Eh = 8.1Gbps per lane 149 * 150 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 151 * 152 * --- to get dp configuration 153 * 154 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * It will list current, verified, reported, preferred dp configuration. 157 * current -- for current video mode 158 * verified --- maximum configuration which pass link training 159 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 160 * preferred --- user force settings 161 * 162 * --- set (or force) dp configuration 163 * 164 * echo <lane_count> <link_rate> > link_settings 165 * 166 * for example, to force to 2 lane, 2.7GHz, 167 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 168 * 169 * spread_spectrum could not be changed dynamically. 170 * 171 * in case invalid lane count, link rate are force, no hw programming will be 172 * done. please check link settings after force operation to see if HW get 173 * programming. 174 * 175 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 176 * 177 * check current and preferred settings. 178 * 179 */ 180 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 181 size_t size, loff_t *pos) 182 { 183 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 184 struct dc_link *link = connector->dc_link; 185 char *rd_buf = NULL; 186 char *rd_buf_ptr = NULL; 187 const uint32_t rd_buf_size = 100; 188 uint32_t result = 0; 189 uint8_t str_len = 0; 190 int r; 191 192 if (*pos & 3 || size & 3) 193 return -EINVAL; 194 195 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 196 if (!rd_buf) 197 return 0; 198 199 rd_buf_ptr = rd_buf; 200 201 str_len = strlen("Current: %d 0x%x %d "); 202 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 203 link->cur_link_settings.lane_count, 204 link->cur_link_settings.link_rate, 205 link->cur_link_settings.link_spread); 206 rd_buf_ptr += str_len; 207 208 str_len = strlen("Verified: %d 0x%x %d "); 209 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 210 link->verified_link_cap.lane_count, 211 link->verified_link_cap.link_rate, 212 link->verified_link_cap.link_spread); 213 rd_buf_ptr += str_len; 214 215 str_len = strlen("Reported: %d 0x%x %d "); 216 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 217 link->reported_link_cap.lane_count, 218 link->reported_link_cap.link_rate, 219 link->reported_link_cap.link_spread); 220 rd_buf_ptr += str_len; 221 222 str_len = strlen("Preferred: %d 0x%x %d "); 223 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 224 link->preferred_link_setting.lane_count, 225 link->preferred_link_setting.link_rate, 226 link->preferred_link_setting.link_spread); 227 228 while (size) { 229 if (*pos >= rd_buf_size) 230 break; 231 232 r = put_user(*(rd_buf + result), buf); 233 if (r) 234 return r; /* r = -EFAULT */ 235 236 buf += 1; 237 size -= 1; 238 *pos += 1; 239 result += 1; 240 } 241 242 kfree(rd_buf); 243 return result; 244 } 245 246 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 247 size_t size, loff_t *pos) 248 { 249 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 250 struct dc_link *link = connector->dc_link; 251 struct dc_link_settings prefer_link_settings; 252 char *wr_buf = NULL; 253 const uint32_t wr_buf_size = 40; 254 /* 0: lane_count; 1: link_rate */ 255 int max_param_num = 2; 256 uint8_t param_nums = 0; 257 long param[2]; 258 bool valid_input = true; 259 260 if (size == 0) 261 return -EINVAL; 262 263 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 264 if (!wr_buf) 265 return -ENOSPC; 266 267 if (parse_write_buffer_into_params(wr_buf, size, 268 (long *)param, buf, 269 max_param_num, 270 ¶m_nums)) { 271 kfree(wr_buf); 272 return -EINVAL; 273 } 274 275 if (param_nums <= 0) { 276 kfree(wr_buf); 277 DRM_DEBUG_DRIVER("user data not be read\n"); 278 return -EINVAL; 279 } 280 281 switch (param[0]) { 282 case LANE_COUNT_ONE: 283 case LANE_COUNT_TWO: 284 case LANE_COUNT_FOUR: 285 break; 286 default: 287 valid_input = false; 288 break; 289 } 290 291 switch (param[1]) { 292 case LINK_RATE_LOW: 293 case LINK_RATE_HIGH: 294 case LINK_RATE_RBR2: 295 case LINK_RATE_HIGH2: 296 case LINK_RATE_HIGH3: 297 break; 298 default: 299 valid_input = false; 300 break; 301 } 302 303 if (!valid_input) { 304 kfree(wr_buf); 305 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 306 return size; 307 } 308 309 /* save user force lane_count, link_rate to preferred settings 310 * spread spectrum will not be changed 311 */ 312 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 313 prefer_link_settings.use_link_rate_set = false; 314 prefer_link_settings.lane_count = param[0]; 315 prefer_link_settings.link_rate = param[1]; 316 317 dp_retrain_link_dp_test(link, &prefer_link_settings, false); 318 319 kfree(wr_buf); 320 return size; 321 } 322 323 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 324 * post-cursor2 (defined by VESA DP specification) 325 * 326 * valid values 327 * voltage swing: 0,1,2,3 328 * pre-emphasis : 0,1,2,3 329 * post cursor2 : 0,1,2,3 330 * 331 * 332 * how to use this debugfs 333 * 334 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 335 * 336 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 337 * 338 * To figure out which DP-x is the display for DP to be check, 339 * cd DP-x 340 * ls -ll 341 * There should be debugfs file, like link_settings, phy_settings. 342 * cat link_settings 343 * from lane_count, link_rate to figure which DP-x is for display to be worked 344 * on 345 * 346 * To get current DP PHY settings, 347 * cat phy_settings 348 * 349 * To change DP PHY settings, 350 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 351 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 352 * 0, 353 * echo 2 3 0 > phy_settings 354 * 355 * To check if change be applied, get current phy settings by 356 * cat phy_settings 357 * 358 * In case invalid values are set by user, like 359 * echo 1 4 0 > phy_settings 360 * 361 * HW will NOT be programmed by these settings. 362 * cat phy_settings will show the previous valid settings. 363 */ 364 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 365 size_t size, loff_t *pos) 366 { 367 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 368 struct dc_link *link = connector->dc_link; 369 char *rd_buf = NULL; 370 const uint32_t rd_buf_size = 20; 371 uint32_t result = 0; 372 int r; 373 374 if (*pos & 3 || size & 3) 375 return -EINVAL; 376 377 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 378 if (!rd_buf) 379 return -EINVAL; 380 381 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 382 link->cur_lane_setting.VOLTAGE_SWING, 383 link->cur_lane_setting.PRE_EMPHASIS, 384 link->cur_lane_setting.POST_CURSOR2); 385 386 while (size) { 387 if (*pos >= rd_buf_size) 388 break; 389 390 r = put_user((*(rd_buf + result)), buf); 391 if (r) 392 return r; /* r = -EFAULT */ 393 394 buf += 1; 395 size -= 1; 396 *pos += 1; 397 result += 1; 398 } 399 400 kfree(rd_buf); 401 return result; 402 } 403 404 static int dp_lttpr_status_show(struct seq_file *m, void *d) 405 { 406 char *data; 407 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 408 struct dc_link *link = connector->dc_link; 409 uint32_t read_size = 1; 410 uint8_t repeater_count = 0; 411 412 data = kzalloc(read_size, GFP_KERNEL); 413 if (!data) 414 return 0; 415 416 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 417 418 switch ((uint8_t)*data) { 419 case 0x80: 420 repeater_count = 1; 421 break; 422 case 0x40: 423 repeater_count = 2; 424 break; 425 case 0x20: 426 repeater_count = 3; 427 break; 428 case 0x10: 429 repeater_count = 4; 430 break; 431 case 0x8: 432 repeater_count = 5; 433 break; 434 case 0x4: 435 repeater_count = 6; 436 break; 437 case 0x2: 438 repeater_count = 7; 439 break; 440 case 0x1: 441 repeater_count = 8; 442 break; 443 case 0x0: 444 repeater_count = 0; 445 break; 446 default: 447 repeater_count = (uint8_t)*data; 448 break; 449 } 450 451 seq_printf(m, "phy repeater count: %d\n", repeater_count); 452 453 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 454 455 if ((uint8_t)*data == 0x55) 456 seq_printf(m, "phy repeater mode: transparent\n"); 457 else if ((uint8_t)*data == 0xAA) 458 seq_printf(m, "phy repeater mode: non-transparent\n"); 459 else if ((uint8_t)*data == 0x00) 460 seq_printf(m, "phy repeater mode: non lttpr\n"); 461 else 462 seq_printf(m, "phy repeater mode: read error\n"); 463 464 kfree(data); 465 return 0; 466 } 467 468 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 469 size_t size, loff_t *pos) 470 { 471 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 472 struct dc_link *link = connector->dc_link; 473 struct dc *dc = (struct dc *)link->dc; 474 char *wr_buf = NULL; 475 uint32_t wr_buf_size = 40; 476 long param[3]; 477 bool use_prefer_link_setting; 478 struct link_training_settings link_lane_settings; 479 int max_param_num = 3; 480 uint8_t param_nums = 0; 481 int r = 0; 482 483 484 if (size == 0) 485 return -EINVAL; 486 487 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 488 if (!wr_buf) 489 return -ENOSPC; 490 491 if (parse_write_buffer_into_params(wr_buf, size, 492 (long *)param, buf, 493 max_param_num, 494 ¶m_nums)) { 495 kfree(wr_buf); 496 return -EINVAL; 497 } 498 499 if (param_nums <= 0) { 500 kfree(wr_buf); 501 DRM_DEBUG_DRIVER("user data not be read\n"); 502 return -EINVAL; 503 } 504 505 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 506 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 507 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 508 kfree(wr_buf); 509 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 510 return size; 511 } 512 513 /* get link settings: lane count, link rate */ 514 use_prefer_link_setting = 515 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 516 (link->test_pattern_enabled)); 517 518 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 519 520 if (use_prefer_link_setting) { 521 link_lane_settings.link_settings.lane_count = 522 link->preferred_link_setting.lane_count; 523 link_lane_settings.link_settings.link_rate = 524 link->preferred_link_setting.link_rate; 525 link_lane_settings.link_settings.link_spread = 526 link->preferred_link_setting.link_spread; 527 } else { 528 link_lane_settings.link_settings.lane_count = 529 link->cur_link_settings.lane_count; 530 link_lane_settings.link_settings.link_rate = 531 link->cur_link_settings.link_rate; 532 link_lane_settings.link_settings.link_spread = 533 link->cur_link_settings.link_spread; 534 } 535 536 /* apply phy settings from user */ 537 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 538 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 539 (enum dc_voltage_swing) (param[0]); 540 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 541 (enum dc_pre_emphasis) (param[1]); 542 link_lane_settings.lane_settings[r].POST_CURSOR2 = 543 (enum dc_post_cursor2) (param[2]); 544 } 545 546 /* program ASIC registers and DPCD registers */ 547 dc_link_set_drive_settings(dc, &link_lane_settings, link); 548 549 kfree(wr_buf); 550 return size; 551 } 552 553 /* function description 554 * 555 * set PHY layer or Link layer test pattern 556 * PHY test pattern is used for PHY SI check. 557 * Link layer test will not affect PHY SI. 558 * 559 * Reset Test Pattern: 560 * 0 = DP_TEST_PATTERN_VIDEO_MODE 561 * 562 * PHY test pattern supported: 563 * 1 = DP_TEST_PATTERN_D102 564 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 565 * 3 = DP_TEST_PATTERN_PRBS7 566 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 567 * 5 = DP_TEST_PATTERN_CP2520_1 568 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 569 * 7 = DP_TEST_PATTERN_CP2520_3 570 * 571 * DP PHY Link Training Patterns 572 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 573 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 574 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 575 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 576 * 577 * DP Link Layer Test pattern 578 * c = DP_TEST_PATTERN_COLOR_SQUARES 579 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 580 * e = DP_TEST_PATTERN_VERTICAL_BARS 581 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 582 * 10= DP_TEST_PATTERN_COLOR_RAMP 583 * 584 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 585 * 586 * --- set test pattern 587 * echo <test pattern #> > test_pattern 588 * 589 * If test pattern # is not supported, NO HW programming will be done. 590 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 591 * for the user pattern. input 10 bytes data are separated by space 592 * 593 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 594 * 595 * --- reset test pattern 596 * echo 0 > test_pattern 597 * 598 * --- HPD detection is disabled when set PHY test pattern 599 * 600 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 601 * is disable. User could unplug DP display from DP connected and plug scope to 602 * check test pattern PHY SI. 603 * If there is need unplug scope and plug DP display back, do steps below: 604 * echo 0 > phy_test_pattern 605 * unplug scope 606 * plug DP display. 607 * 608 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 609 * driver could detect "unplug scope" and "plug DP display" 610 */ 611 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 612 size_t size, loff_t *pos) 613 { 614 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 615 struct dc_link *link = connector->dc_link; 616 char *wr_buf = NULL; 617 uint32_t wr_buf_size = 100; 618 long param[11] = {0x0}; 619 int max_param_num = 11; 620 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 621 bool disable_hpd = false; 622 bool valid_test_pattern = false; 623 uint8_t param_nums = 0; 624 /* init with default 80bit custom pattern */ 625 uint8_t custom_pattern[10] = { 626 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 627 0x1f, 0x7c, 0xf0, 0xc1, 0x07 628 }; 629 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 630 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 631 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 632 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 633 struct link_training_settings link_training_settings; 634 int i; 635 636 if (size == 0) 637 return -EINVAL; 638 639 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 640 if (!wr_buf) 641 return -ENOSPC; 642 643 if (parse_write_buffer_into_params(wr_buf, size, 644 (long *)param, buf, 645 max_param_num, 646 ¶m_nums)) { 647 kfree(wr_buf); 648 return -EINVAL; 649 } 650 651 if (param_nums <= 0) { 652 kfree(wr_buf); 653 DRM_DEBUG_DRIVER("user data not be read\n"); 654 return -EINVAL; 655 } 656 657 658 test_pattern = param[0]; 659 660 switch (test_pattern) { 661 case DP_TEST_PATTERN_VIDEO_MODE: 662 case DP_TEST_PATTERN_COLOR_SQUARES: 663 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 664 case DP_TEST_PATTERN_VERTICAL_BARS: 665 case DP_TEST_PATTERN_HORIZONTAL_BARS: 666 case DP_TEST_PATTERN_COLOR_RAMP: 667 valid_test_pattern = true; 668 break; 669 670 case DP_TEST_PATTERN_D102: 671 case DP_TEST_PATTERN_SYMBOL_ERROR: 672 case DP_TEST_PATTERN_PRBS7: 673 case DP_TEST_PATTERN_80BIT_CUSTOM: 674 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 675 case DP_TEST_PATTERN_TRAINING_PATTERN4: 676 disable_hpd = true; 677 valid_test_pattern = true; 678 break; 679 680 default: 681 valid_test_pattern = false; 682 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 683 break; 684 } 685 686 if (!valid_test_pattern) { 687 kfree(wr_buf); 688 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 689 return size; 690 } 691 692 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 693 for (i = 0; i < 10; i++) { 694 if ((uint8_t) param[i + 1] != 0x0) 695 break; 696 } 697 698 if (i < 10) { 699 /* not use default value */ 700 for (i = 0; i < 10; i++) 701 custom_pattern[i] = (uint8_t) param[i + 1]; 702 } 703 } 704 705 /* Usage: set DP physical test pattern using debugfs with normal DP 706 * panel. Then plug out DP panel and connect a scope to measure 707 * For normal video mode and test pattern generated from CRCT, 708 * they are visibile to user. So do not disable HPD. 709 * Video Mode is also set to clear the test pattern, so enable HPD 710 * because it might have been disabled after a test pattern was set. 711 * AUX depends on HPD * sequence dependent, do not move! 712 */ 713 if (!disable_hpd) 714 dc_link_enable_hpd(link); 715 716 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 717 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 718 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 719 720 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 721 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 722 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 723 724 link_training_settings.link_settings = cur_link_settings; 725 726 727 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 728 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 729 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 730 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 731 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 732 link_training_settings.link_settings = prefer_link_settings; 733 } 734 735 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 736 link_training_settings.lane_settings[i] = link->cur_lane_setting; 737 738 dc_link_set_test_pattern( 739 link, 740 test_pattern, 741 DP_TEST_PATTERN_COLOR_SPACE_RGB, 742 &link_training_settings, 743 custom_pattern, 744 10); 745 746 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 747 * Then plug out DP panel and connect a scope to measure DP PHY signal. 748 * Need disable interrupt to avoid SW driver disable DP output. This is 749 * done after the test pattern is set. 750 */ 751 if (valid_test_pattern && disable_hpd) 752 dc_link_disable_hpd(link); 753 754 kfree(wr_buf); 755 756 return size; 757 } 758 759 /* 760 * Returns the DMCUB tracebuffer contents. 761 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 762 */ 763 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 764 { 765 struct amdgpu_device *adev = m->private; 766 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 767 struct dmub_debugfs_trace_entry *entries; 768 uint8_t *tbuf_base; 769 uint32_t tbuf_size, max_entries, num_entries, i; 770 771 if (!fb_info) 772 return 0; 773 774 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 775 if (!tbuf_base) 776 return 0; 777 778 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 779 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 780 sizeof(struct dmub_debugfs_trace_entry); 781 782 num_entries = 783 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 784 785 num_entries = min(num_entries, max_entries); 786 787 entries = (struct dmub_debugfs_trace_entry 788 *)(tbuf_base + 789 sizeof(struct dmub_debugfs_trace_header)); 790 791 for (i = 0; i < num_entries; ++i) { 792 struct dmub_debugfs_trace_entry *entry = &entries[i]; 793 794 seq_printf(m, 795 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 796 entry->trace_code, entry->tick_count, entry->param0, 797 entry->param1); 798 } 799 800 return 0; 801 } 802 803 /* 804 * Returns the DMCUB firmware state contents. 805 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 806 */ 807 static int dmub_fw_state_show(struct seq_file *m, void *data) 808 { 809 struct amdgpu_device *adev = m->private; 810 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 811 uint8_t *state_base; 812 uint32_t state_size; 813 814 if (!fb_info) 815 return 0; 816 817 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 818 if (!state_base) 819 return 0; 820 821 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 822 823 return seq_write(m, state_base, state_size); 824 } 825 826 /* 827 * Returns the current and maximum output bpc for the connector. 828 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 829 */ 830 static int output_bpc_show(struct seq_file *m, void *data) 831 { 832 struct drm_connector *connector = m->private; 833 struct drm_device *dev = connector->dev; 834 struct drm_crtc *crtc = NULL; 835 struct dm_crtc_state *dm_crtc_state = NULL; 836 int res = -ENODEV; 837 unsigned int bpc; 838 839 mutex_lock(&dev->mode_config.mutex); 840 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 841 842 if (connector->state == NULL) 843 goto unlock; 844 845 crtc = connector->state->crtc; 846 if (crtc == NULL) 847 goto unlock; 848 849 drm_modeset_lock(&crtc->mutex, NULL); 850 if (crtc->state == NULL) 851 goto unlock; 852 853 dm_crtc_state = to_dm_crtc_state(crtc->state); 854 if (dm_crtc_state->stream == NULL) 855 goto unlock; 856 857 switch (dm_crtc_state->stream->timing.display_color_depth) { 858 case COLOR_DEPTH_666: 859 bpc = 6; 860 break; 861 case COLOR_DEPTH_888: 862 bpc = 8; 863 break; 864 case COLOR_DEPTH_101010: 865 bpc = 10; 866 break; 867 case COLOR_DEPTH_121212: 868 bpc = 12; 869 break; 870 case COLOR_DEPTH_161616: 871 bpc = 16; 872 break; 873 default: 874 goto unlock; 875 } 876 877 seq_printf(m, "Current: %u\n", bpc); 878 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 879 res = 0; 880 881 unlock: 882 if (crtc) 883 drm_modeset_unlock(&crtc->mutex); 884 885 drm_modeset_unlock(&dev->mode_config.connection_mutex); 886 mutex_unlock(&dev->mode_config.mutex); 887 888 return res; 889 } 890 891 /* 892 * Example usage: 893 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 894 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 895 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 896 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 897 */ 898 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 899 size_t size, loff_t *pos) 900 { 901 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 902 char *wr_buf = NULL; 903 uint32_t wr_buf_size = 42; 904 int max_param_num = 1; 905 long param; 906 uint8_t param_nums = 0; 907 908 if (size == 0) 909 return -EINVAL; 910 911 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 912 913 if (!wr_buf) { 914 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 915 return -ENOSPC; 916 } 917 918 if (parse_write_buffer_into_params(wr_buf, size, 919 ¶m, buf, 920 max_param_num, 921 ¶m_nums)) { 922 kfree(wr_buf); 923 return -EINVAL; 924 } 925 926 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 927 928 kfree(wr_buf); 929 return 0; 930 } 931 932 #ifdef CONFIG_DRM_AMD_DC_HDCP 933 /* 934 * Returns the HDCP capability of the Display (1.4 for now). 935 * 936 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 937 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 938 * 939 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 940 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 941 */ 942 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 943 { 944 struct drm_connector *connector = m->private; 945 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 946 bool hdcp_cap, hdcp2_cap; 947 948 if (connector->status != connector_status_connected) 949 return -ENODEV; 950 951 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 952 953 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 954 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 955 956 957 if (hdcp_cap) 958 seq_printf(m, "%s ", "HDCP1.4"); 959 if (hdcp2_cap) 960 seq_printf(m, "%s ", "HDCP2.2"); 961 962 if (!hdcp_cap && !hdcp2_cap) 963 seq_printf(m, "%s ", "None"); 964 965 seq_puts(m, "\n"); 966 967 return 0; 968 } 969 #endif 970 971 /* 972 * Returns whether the connected display is internal and not hotpluggable. 973 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 974 */ 975 static int internal_display_show(struct seq_file *m, void *data) 976 { 977 struct drm_connector *connector = m->private; 978 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 979 struct dc_link *link = aconnector->dc_link; 980 981 seq_printf(m, "Internal: %u\n", link->is_internal_display); 982 983 return 0; 984 } 985 986 /* function description 987 * 988 * generic SDP message access for testing 989 * 990 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 991 * 992 * SDP header 993 * Hb0 : Secondary-Data Packet ID 994 * Hb1 : Secondary-Data Packet type 995 * Hb2 : Secondary-Data-packet-specific header, Byte 0 996 * Hb3 : Secondary-Data-packet-specific header, Byte 1 997 * 998 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 999 */ 1000 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1001 size_t size, loff_t *pos) 1002 { 1003 int r; 1004 uint8_t data[36]; 1005 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1006 struct dm_crtc_state *acrtc_state; 1007 uint32_t write_size = 36; 1008 1009 if (connector->base.status != connector_status_connected) 1010 return -ENODEV; 1011 1012 if (size == 0) 1013 return 0; 1014 1015 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1016 1017 r = copy_from_user(data, buf, write_size); 1018 1019 write_size -= r; 1020 1021 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1022 1023 return write_size; 1024 } 1025 1026 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1027 size_t size, loff_t *pos) 1028 { 1029 int r; 1030 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1031 1032 if (size < sizeof(connector->debugfs_dpcd_address)) 1033 return -EINVAL; 1034 1035 r = copy_from_user(&connector->debugfs_dpcd_address, 1036 buf, sizeof(connector->debugfs_dpcd_address)); 1037 1038 return size - r; 1039 } 1040 1041 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1042 size_t size, loff_t *pos) 1043 { 1044 int r; 1045 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1046 1047 if (size < sizeof(connector->debugfs_dpcd_size)) 1048 return -EINVAL; 1049 1050 r = copy_from_user(&connector->debugfs_dpcd_size, 1051 buf, sizeof(connector->debugfs_dpcd_size)); 1052 1053 if (connector->debugfs_dpcd_size > 256) 1054 connector->debugfs_dpcd_size = 0; 1055 1056 return size - r; 1057 } 1058 1059 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1060 size_t size, loff_t *pos) 1061 { 1062 int r; 1063 char *data; 1064 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1065 struct dc_link *link = connector->dc_link; 1066 uint32_t write_size = connector->debugfs_dpcd_size; 1067 1068 if (!write_size || size < write_size) 1069 return -EINVAL; 1070 1071 data = kzalloc(write_size, GFP_KERNEL); 1072 if (!data) 1073 return 0; 1074 1075 r = copy_from_user(data, buf, write_size); 1076 1077 dm_helpers_dp_write_dpcd(link->ctx, link, 1078 connector->debugfs_dpcd_address, data, write_size - r); 1079 kfree(data); 1080 return write_size - r; 1081 } 1082 1083 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1084 size_t size, loff_t *pos) 1085 { 1086 int r; 1087 char *data; 1088 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1089 struct dc_link *link = connector->dc_link; 1090 uint32_t read_size = connector->debugfs_dpcd_size; 1091 1092 if (!read_size || size < read_size) 1093 return 0; 1094 1095 data = kzalloc(read_size, GFP_KERNEL); 1096 if (!data) 1097 return 0; 1098 1099 dm_helpers_dp_read_dpcd(link->ctx, link, 1100 connector->debugfs_dpcd_address, data, read_size); 1101 1102 r = copy_to_user(buf, data, read_size); 1103 1104 kfree(data); 1105 return read_size - r; 1106 } 1107 1108 /* function: Read link's DSC & FEC capabilities 1109 * 1110 * 1111 * Access it with the following command (you need to specify 1112 * connector like DP-1): 1113 * 1114 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1115 * 1116 */ 1117 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1118 { 1119 struct drm_connector *connector = m->private; 1120 struct drm_modeset_acquire_ctx ctx; 1121 struct drm_device *dev = connector->dev; 1122 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1123 int ret = 0; 1124 bool try_again = false; 1125 bool is_fec_supported = false; 1126 bool is_dsc_supported = false; 1127 struct dpcd_caps dpcd_caps; 1128 1129 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1130 do { 1131 try_again = false; 1132 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1133 if (ret) { 1134 if (ret == -EDEADLK) { 1135 ret = drm_modeset_backoff(&ctx); 1136 if (!ret) { 1137 try_again = true; 1138 continue; 1139 } 1140 } 1141 break; 1142 } 1143 if (connector->status != connector_status_connected) { 1144 ret = -ENODEV; 1145 break; 1146 } 1147 dpcd_caps = aconnector->dc_link->dpcd_caps; 1148 if (aconnector->port) { 1149 /* aconnector sets dsc_aux during get_modes call 1150 * if MST connector has it means it can either 1151 * enable DSC on the sink device or on MST branch 1152 * its connected to. 1153 */ 1154 if (aconnector->dsc_aux) { 1155 is_fec_supported = true; 1156 is_dsc_supported = true; 1157 } 1158 } else { 1159 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1160 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1161 } 1162 } while (try_again); 1163 1164 drm_modeset_drop_locks(&ctx); 1165 drm_modeset_acquire_fini(&ctx); 1166 1167 seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported)); 1168 seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported)); 1169 1170 return ret; 1171 } 1172 1173 /* function: Trigger virtual HPD redetection on connector 1174 * 1175 * This function will perform link rediscovery, link disable 1176 * and enable, and dm connector state update. 1177 * 1178 * Retrigger HPD on an existing connector by echoing 1 into 1179 * its respectful "trigger_hotplug" debugfs entry: 1180 * 1181 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1182 * 1183 * This function can perform HPD unplug: 1184 * 1185 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1186 * 1187 */ 1188 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1189 size_t size, loff_t *pos) 1190 { 1191 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1192 struct drm_connector *connector = &aconnector->base; 1193 struct dc_link *link = NULL; 1194 struct drm_device *dev = connector->dev; 1195 struct drm_modeset_acquire_ctx ctx; 1196 enum dc_connection_type new_connection_type = dc_connection_none; 1197 char *wr_buf = NULL; 1198 uint32_t wr_buf_size = 42; 1199 int max_param_num = 1; 1200 long param[1] = {0}; 1201 uint8_t param_nums = 0; 1202 int ret; 1203 1204 if (!aconnector || !aconnector->dc_link) 1205 return -EINVAL; 1206 1207 if (size == 0) 1208 return -EINVAL; 1209 1210 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1211 1212 if (!wr_buf) { 1213 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1214 return -ENOSPC; 1215 } 1216 1217 if (parse_write_buffer_into_params(wr_buf, size, 1218 (long *)param, buf, 1219 max_param_num, 1220 ¶m_nums)) { 1221 kfree(wr_buf); 1222 return -EINVAL; 1223 } 1224 1225 if (param_nums <= 0) { 1226 DRM_DEBUG_DRIVER("user data not be read\n"); 1227 kfree(wr_buf); 1228 return -EINVAL; 1229 } 1230 1231 if (param[0] == 1) { 1232 mutex_lock(&aconnector->hpd_lock); 1233 1234 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1235 new_connection_type != dc_connection_none) 1236 goto unlock; 1237 1238 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1239 goto unlock; 1240 1241 amdgpu_dm_update_connector_after_detect(aconnector); 1242 } else if (param[0] == 0) { 1243 if (!aconnector->dc_link) 1244 goto unlock; 1245 1246 link = aconnector->dc_link; 1247 1248 if (link->local_sink) { 1249 dc_sink_release(link->local_sink); 1250 link->local_sink = NULL; 1251 } 1252 1253 link->dpcd_sink_count = 0; 1254 link->type = dc_connection_none; 1255 link->dongle_max_pix_clk = 0; 1256 1257 amdgpu_dm_update_connector_after_detect(aconnector); 1258 1259 } else { 1260 goto unlock; 1261 } 1262 1263 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); 1264 dm_restore_drm_connector_state(dev, connector); 1265 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); 1266 1267 if (ret) 1268 return ret; 1269 1270 drm_kms_helper_hotplug_event(dev); 1271 1272 unlock: 1273 mutex_unlock(&aconnector->hpd_lock); 1274 1275 kfree(wr_buf); 1276 return size; 1277 } 1278 1279 /* function: read DSC status on the connector 1280 * 1281 * The read function: dp_dsc_clock_en_read 1282 * returns current status of DSC clock on the connector. 1283 * The return is a boolean flag: 1 or 0. 1284 * 1285 * Access it with the following command (you need to specify 1286 * connector like DP-1): 1287 * 1288 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1289 * 1290 * Expected output: 1291 * 1 - means that DSC is currently enabled 1292 * 0 - means that DSC is disabled 1293 */ 1294 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1295 size_t size, loff_t *pos) 1296 { 1297 char *rd_buf = NULL; 1298 char *rd_buf_ptr = NULL; 1299 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1300 struct display_stream_compressor *dsc; 1301 struct dcn_dsc_state dsc_state = {0}; 1302 const uint32_t rd_buf_size = 10; 1303 struct pipe_ctx *pipe_ctx; 1304 ssize_t result = 0; 1305 int i, r, str_len = 30; 1306 1307 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1308 1309 if (!rd_buf) 1310 return -ENOMEM; 1311 1312 rd_buf_ptr = rd_buf; 1313 1314 for (i = 0; i < MAX_PIPES; i++) { 1315 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1316 if (pipe_ctx && pipe_ctx->stream && 1317 pipe_ctx->stream->link == aconnector->dc_link) 1318 break; 1319 } 1320 1321 if (!pipe_ctx) 1322 return -ENXIO; 1323 1324 dsc = pipe_ctx->stream_res.dsc; 1325 if (dsc) 1326 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1327 1328 snprintf(rd_buf_ptr, str_len, 1329 "%d\n", 1330 dsc_state.dsc_clock_en); 1331 rd_buf_ptr += str_len; 1332 1333 while (size) { 1334 if (*pos >= rd_buf_size) 1335 break; 1336 1337 r = put_user(*(rd_buf + result), buf); 1338 if (r) 1339 return r; /* r = -EFAULT */ 1340 1341 buf += 1; 1342 size -= 1; 1343 *pos += 1; 1344 result += 1; 1345 } 1346 1347 kfree(rd_buf); 1348 return result; 1349 } 1350 1351 /* function: write force DSC on the connector 1352 * 1353 * The write function: dp_dsc_clock_en_write 1354 * enables to force DSC on the connector. 1355 * User can write to either force enable or force disable DSC 1356 * on the next modeset or set it to driver default 1357 * 1358 * Accepted inputs: 1359 * 0 - default DSC enablement policy 1360 * 1 - force enable DSC on the connector 1361 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1362 * 1363 * Writing DSC settings is done with the following command: 1364 * - To force enable DSC (you need to specify 1365 * connector like DP-1): 1366 * 1367 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1368 * 1369 * - To return to default state set the flag to zero and 1370 * let driver deal with DSC automatically 1371 * (you need to specify connector like DP-1): 1372 * 1373 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1374 * 1375 */ 1376 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1377 size_t size, loff_t *pos) 1378 { 1379 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1380 struct drm_connector *connector = &aconnector->base; 1381 struct drm_device *dev = connector->dev; 1382 struct drm_crtc *crtc = NULL; 1383 struct dm_crtc_state *dm_crtc_state = NULL; 1384 struct pipe_ctx *pipe_ctx; 1385 int i; 1386 char *wr_buf = NULL; 1387 uint32_t wr_buf_size = 42; 1388 int max_param_num = 1; 1389 long param[1] = {0}; 1390 uint8_t param_nums = 0; 1391 1392 if (size == 0) 1393 return -EINVAL; 1394 1395 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1396 1397 if (!wr_buf) { 1398 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1399 return -ENOSPC; 1400 } 1401 1402 if (parse_write_buffer_into_params(wr_buf, size, 1403 (long *)param, buf, 1404 max_param_num, 1405 ¶m_nums)) { 1406 kfree(wr_buf); 1407 return -EINVAL; 1408 } 1409 1410 if (param_nums <= 0) { 1411 DRM_DEBUG_DRIVER("user data not be read\n"); 1412 kfree(wr_buf); 1413 return -EINVAL; 1414 } 1415 1416 for (i = 0; i < MAX_PIPES; i++) { 1417 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1418 if (pipe_ctx && pipe_ctx->stream && 1419 pipe_ctx->stream->link == aconnector->dc_link) 1420 break; 1421 } 1422 1423 if (!pipe_ctx || !pipe_ctx->stream) 1424 goto done; 1425 1426 // Get CRTC state 1427 mutex_lock(&dev->mode_config.mutex); 1428 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1429 1430 if (connector->state == NULL) 1431 goto unlock; 1432 1433 crtc = connector->state->crtc; 1434 if (crtc == NULL) 1435 goto unlock; 1436 1437 drm_modeset_lock(&crtc->mutex, NULL); 1438 if (crtc->state == NULL) 1439 goto unlock; 1440 1441 dm_crtc_state = to_dm_crtc_state(crtc->state); 1442 if (dm_crtc_state->stream == NULL) 1443 goto unlock; 1444 1445 if (param[0] == 1) 1446 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1447 else if (param[0] == 2) 1448 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1449 else 1450 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1451 1452 dm_crtc_state->dsc_force_changed = true; 1453 1454 unlock: 1455 if (crtc) 1456 drm_modeset_unlock(&crtc->mutex); 1457 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1458 mutex_unlock(&dev->mode_config.mutex); 1459 1460 done: 1461 kfree(wr_buf); 1462 return size; 1463 } 1464 1465 /* function: read DSC slice width parameter on the connector 1466 * 1467 * The read function: dp_dsc_slice_width_read 1468 * returns dsc slice width used in the current configuration 1469 * The return is an integer: 0 or other positive number 1470 * 1471 * Access the status with the following command: 1472 * 1473 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1474 * 1475 * 0 - means that DSC is disabled 1476 * 1477 * Any other number more than zero represents the 1478 * slice width currently used by DSC in pixels 1479 * 1480 */ 1481 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1482 size_t size, loff_t *pos) 1483 { 1484 char *rd_buf = NULL; 1485 char *rd_buf_ptr = NULL; 1486 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1487 struct display_stream_compressor *dsc; 1488 struct dcn_dsc_state dsc_state = {0}; 1489 const uint32_t rd_buf_size = 100; 1490 struct pipe_ctx *pipe_ctx; 1491 ssize_t result = 0; 1492 int i, r, str_len = 30; 1493 1494 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1495 1496 if (!rd_buf) 1497 return -ENOMEM; 1498 1499 rd_buf_ptr = rd_buf; 1500 1501 for (i = 0; i < MAX_PIPES; i++) { 1502 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1503 if (pipe_ctx && pipe_ctx->stream && 1504 pipe_ctx->stream->link == aconnector->dc_link) 1505 break; 1506 } 1507 1508 if (!pipe_ctx) 1509 return -ENXIO; 1510 1511 dsc = pipe_ctx->stream_res.dsc; 1512 if (dsc) 1513 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1514 1515 snprintf(rd_buf_ptr, str_len, 1516 "%d\n", 1517 dsc_state.dsc_slice_width); 1518 rd_buf_ptr += str_len; 1519 1520 while (size) { 1521 if (*pos >= rd_buf_size) 1522 break; 1523 1524 r = put_user(*(rd_buf + result), buf); 1525 if (r) 1526 return r; /* r = -EFAULT */ 1527 1528 buf += 1; 1529 size -= 1; 1530 *pos += 1; 1531 result += 1; 1532 } 1533 1534 kfree(rd_buf); 1535 return result; 1536 } 1537 1538 /* function: write DSC slice width parameter 1539 * 1540 * The write function: dp_dsc_slice_width_write 1541 * overwrites automatically generated DSC configuration 1542 * of slice width. 1543 * 1544 * The user has to write the slice width divisible by the 1545 * picture width. 1546 * 1547 * Also the user has to write width in hexidecimal 1548 * rather than in decimal. 1549 * 1550 * Writing DSC settings is done with the following command: 1551 * - To force overwrite slice width: (example sets to 1920 pixels) 1552 * 1553 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1554 * 1555 * - To stop overwriting and let driver find the optimal size, 1556 * set the width to zero: 1557 * 1558 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1559 * 1560 */ 1561 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1562 size_t size, loff_t *pos) 1563 { 1564 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1565 struct pipe_ctx *pipe_ctx; 1566 struct drm_connector *connector = &aconnector->base; 1567 struct drm_device *dev = connector->dev; 1568 struct drm_crtc *crtc = NULL; 1569 struct dm_crtc_state *dm_crtc_state = NULL; 1570 int i; 1571 char *wr_buf = NULL; 1572 uint32_t wr_buf_size = 42; 1573 int max_param_num = 1; 1574 long param[1] = {0}; 1575 uint8_t param_nums = 0; 1576 1577 if (size == 0) 1578 return -EINVAL; 1579 1580 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1581 1582 if (!wr_buf) { 1583 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1584 return -ENOSPC; 1585 } 1586 1587 if (parse_write_buffer_into_params(wr_buf, size, 1588 (long *)param, buf, 1589 max_param_num, 1590 ¶m_nums)) { 1591 kfree(wr_buf); 1592 return -EINVAL; 1593 } 1594 1595 if (param_nums <= 0) { 1596 DRM_DEBUG_DRIVER("user data not be read\n"); 1597 kfree(wr_buf); 1598 return -EINVAL; 1599 } 1600 1601 for (i = 0; i < MAX_PIPES; i++) { 1602 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1603 if (pipe_ctx && pipe_ctx->stream && 1604 pipe_ctx->stream->link == aconnector->dc_link) 1605 break; 1606 } 1607 1608 if (!pipe_ctx || !pipe_ctx->stream) 1609 goto done; 1610 1611 // Safely get CRTC state 1612 mutex_lock(&dev->mode_config.mutex); 1613 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1614 1615 if (connector->state == NULL) 1616 goto unlock; 1617 1618 crtc = connector->state->crtc; 1619 if (crtc == NULL) 1620 goto unlock; 1621 1622 drm_modeset_lock(&crtc->mutex, NULL); 1623 if (crtc->state == NULL) 1624 goto unlock; 1625 1626 dm_crtc_state = to_dm_crtc_state(crtc->state); 1627 if (dm_crtc_state->stream == NULL) 1628 goto unlock; 1629 1630 if (param[0] > 0) 1631 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1632 pipe_ctx->stream->timing.h_addressable, 1633 param[0]); 1634 else 1635 aconnector->dsc_settings.dsc_num_slices_h = 0; 1636 1637 dm_crtc_state->dsc_force_changed = true; 1638 1639 unlock: 1640 if (crtc) 1641 drm_modeset_unlock(&crtc->mutex); 1642 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1643 mutex_unlock(&dev->mode_config.mutex); 1644 1645 done: 1646 kfree(wr_buf); 1647 return size; 1648 } 1649 1650 /* function: read DSC slice height parameter on the connector 1651 * 1652 * The read function: dp_dsc_slice_height_read 1653 * returns dsc slice height used in the current configuration 1654 * The return is an integer: 0 or other positive number 1655 * 1656 * Access the status with the following command: 1657 * 1658 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1659 * 1660 * 0 - means that DSC is disabled 1661 * 1662 * Any other number more than zero represents the 1663 * slice height currently used by DSC in pixels 1664 * 1665 */ 1666 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1667 size_t size, loff_t *pos) 1668 { 1669 char *rd_buf = NULL; 1670 char *rd_buf_ptr = NULL; 1671 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1672 struct display_stream_compressor *dsc; 1673 struct dcn_dsc_state dsc_state = {0}; 1674 const uint32_t rd_buf_size = 100; 1675 struct pipe_ctx *pipe_ctx; 1676 ssize_t result = 0; 1677 int i, r, str_len = 30; 1678 1679 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1680 1681 if (!rd_buf) 1682 return -ENOMEM; 1683 1684 rd_buf_ptr = rd_buf; 1685 1686 for (i = 0; i < MAX_PIPES; i++) { 1687 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1688 if (pipe_ctx && pipe_ctx->stream && 1689 pipe_ctx->stream->link == aconnector->dc_link) 1690 break; 1691 } 1692 1693 if (!pipe_ctx) 1694 return -ENXIO; 1695 1696 dsc = pipe_ctx->stream_res.dsc; 1697 if (dsc) 1698 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1699 1700 snprintf(rd_buf_ptr, str_len, 1701 "%d\n", 1702 dsc_state.dsc_slice_height); 1703 rd_buf_ptr += str_len; 1704 1705 while (size) { 1706 if (*pos >= rd_buf_size) 1707 break; 1708 1709 r = put_user(*(rd_buf + result), buf); 1710 if (r) 1711 return r; /* r = -EFAULT */ 1712 1713 buf += 1; 1714 size -= 1; 1715 *pos += 1; 1716 result += 1; 1717 } 1718 1719 kfree(rd_buf); 1720 return result; 1721 } 1722 1723 /* function: write DSC slice height parameter 1724 * 1725 * The write function: dp_dsc_slice_height_write 1726 * overwrites automatically generated DSC configuration 1727 * of slice height. 1728 * 1729 * The user has to write the slice height divisible by the 1730 * picture height. 1731 * 1732 * Also the user has to write height in hexidecimal 1733 * rather than in decimal. 1734 * 1735 * Writing DSC settings is done with the following command: 1736 * - To force overwrite slice height (example sets to 128 pixels): 1737 * 1738 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1739 * 1740 * - To stop overwriting and let driver find the optimal size, 1741 * set the height to zero: 1742 * 1743 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1744 * 1745 */ 1746 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1747 size_t size, loff_t *pos) 1748 { 1749 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1750 struct drm_connector *connector = &aconnector->base; 1751 struct drm_device *dev = connector->dev; 1752 struct drm_crtc *crtc = NULL; 1753 struct dm_crtc_state *dm_crtc_state = NULL; 1754 struct pipe_ctx *pipe_ctx; 1755 int i; 1756 char *wr_buf = NULL; 1757 uint32_t wr_buf_size = 42; 1758 int max_param_num = 1; 1759 uint8_t param_nums = 0; 1760 long param[1] = {0}; 1761 1762 if (size == 0) 1763 return -EINVAL; 1764 1765 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1766 1767 if (!wr_buf) { 1768 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1769 return -ENOSPC; 1770 } 1771 1772 if (parse_write_buffer_into_params(wr_buf, size, 1773 (long *)param, buf, 1774 max_param_num, 1775 ¶m_nums)) { 1776 kfree(wr_buf); 1777 return -EINVAL; 1778 } 1779 1780 if (param_nums <= 0) { 1781 DRM_DEBUG_DRIVER("user data not be read\n"); 1782 kfree(wr_buf); 1783 return -EINVAL; 1784 } 1785 1786 for (i = 0; i < MAX_PIPES; i++) { 1787 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1788 if (pipe_ctx && pipe_ctx->stream && 1789 pipe_ctx->stream->link == aconnector->dc_link) 1790 break; 1791 } 1792 1793 if (!pipe_ctx || !pipe_ctx->stream) 1794 goto done; 1795 1796 // Get CRTC state 1797 mutex_lock(&dev->mode_config.mutex); 1798 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1799 1800 if (connector->state == NULL) 1801 goto unlock; 1802 1803 crtc = connector->state->crtc; 1804 if (crtc == NULL) 1805 goto unlock; 1806 1807 drm_modeset_lock(&crtc->mutex, NULL); 1808 if (crtc->state == NULL) 1809 goto unlock; 1810 1811 dm_crtc_state = to_dm_crtc_state(crtc->state); 1812 if (dm_crtc_state->stream == NULL) 1813 goto unlock; 1814 1815 if (param[0] > 0) 1816 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1817 pipe_ctx->stream->timing.v_addressable, 1818 param[0]); 1819 else 1820 aconnector->dsc_settings.dsc_num_slices_v = 0; 1821 1822 dm_crtc_state->dsc_force_changed = true; 1823 1824 unlock: 1825 if (crtc) 1826 drm_modeset_unlock(&crtc->mutex); 1827 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1828 mutex_unlock(&dev->mode_config.mutex); 1829 1830 done: 1831 kfree(wr_buf); 1832 return size; 1833 } 1834 1835 /* function: read DSC target rate on the connector in bits per pixel 1836 * 1837 * The read function: dp_dsc_bits_per_pixel_read 1838 * returns target rate of compression in bits per pixel 1839 * The return is an integer: 0 or other positive integer 1840 * 1841 * Access it with the following command: 1842 * 1843 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1844 * 1845 * 0 - means that DSC is disabled 1846 */ 1847 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1848 size_t size, loff_t *pos) 1849 { 1850 char *rd_buf = NULL; 1851 char *rd_buf_ptr = NULL; 1852 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1853 struct display_stream_compressor *dsc; 1854 struct dcn_dsc_state dsc_state = {0}; 1855 const uint32_t rd_buf_size = 100; 1856 struct pipe_ctx *pipe_ctx; 1857 ssize_t result = 0; 1858 int i, r, str_len = 30; 1859 1860 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1861 1862 if (!rd_buf) 1863 return -ENOMEM; 1864 1865 rd_buf_ptr = rd_buf; 1866 1867 for (i = 0; i < MAX_PIPES; i++) { 1868 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1869 if (pipe_ctx && pipe_ctx->stream && 1870 pipe_ctx->stream->link == aconnector->dc_link) 1871 break; 1872 } 1873 1874 if (!pipe_ctx) 1875 return -ENXIO; 1876 1877 dsc = pipe_ctx->stream_res.dsc; 1878 if (dsc) 1879 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1880 1881 snprintf(rd_buf_ptr, str_len, 1882 "%d\n", 1883 dsc_state.dsc_bits_per_pixel); 1884 rd_buf_ptr += str_len; 1885 1886 while (size) { 1887 if (*pos >= rd_buf_size) 1888 break; 1889 1890 r = put_user(*(rd_buf + result), buf); 1891 if (r) 1892 return r; /* r = -EFAULT */ 1893 1894 buf += 1; 1895 size -= 1; 1896 *pos += 1; 1897 result += 1; 1898 } 1899 1900 kfree(rd_buf); 1901 return result; 1902 } 1903 1904 /* function: write DSC target rate in bits per pixel 1905 * 1906 * The write function: dp_dsc_bits_per_pixel_write 1907 * overwrites automatically generated DSC configuration 1908 * of DSC target bit rate. 1909 * 1910 * Also the user has to write bpp in hexidecimal 1911 * rather than in decimal. 1912 * 1913 * Writing DSC settings is done with the following command: 1914 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1915 * 1916 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1917 * 1918 * - To stop overwriting and let driver find the optimal rate, 1919 * set the rate to zero: 1920 * 1921 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1922 * 1923 */ 1924 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1925 size_t size, loff_t *pos) 1926 { 1927 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1928 struct drm_connector *connector = &aconnector->base; 1929 struct drm_device *dev = connector->dev; 1930 struct drm_crtc *crtc = NULL; 1931 struct dm_crtc_state *dm_crtc_state = NULL; 1932 struct pipe_ctx *pipe_ctx; 1933 int i; 1934 char *wr_buf = NULL; 1935 uint32_t wr_buf_size = 42; 1936 int max_param_num = 1; 1937 uint8_t param_nums = 0; 1938 long param[1] = {0}; 1939 1940 if (size == 0) 1941 return -EINVAL; 1942 1943 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1944 1945 if (!wr_buf) { 1946 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1947 return -ENOSPC; 1948 } 1949 1950 if (parse_write_buffer_into_params(wr_buf, size, 1951 (long *)param, buf, 1952 max_param_num, 1953 ¶m_nums)) { 1954 kfree(wr_buf); 1955 return -EINVAL; 1956 } 1957 1958 if (param_nums <= 0) { 1959 DRM_DEBUG_DRIVER("user data not be read\n"); 1960 kfree(wr_buf); 1961 return -EINVAL; 1962 } 1963 1964 for (i = 0; i < MAX_PIPES; i++) { 1965 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1966 if (pipe_ctx && pipe_ctx->stream && 1967 pipe_ctx->stream->link == aconnector->dc_link) 1968 break; 1969 } 1970 1971 if (!pipe_ctx || !pipe_ctx->stream) 1972 goto done; 1973 1974 // Get CRTC state 1975 mutex_lock(&dev->mode_config.mutex); 1976 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1977 1978 if (connector->state == NULL) 1979 goto unlock; 1980 1981 crtc = connector->state->crtc; 1982 if (crtc == NULL) 1983 goto unlock; 1984 1985 drm_modeset_lock(&crtc->mutex, NULL); 1986 if (crtc->state == NULL) 1987 goto unlock; 1988 1989 dm_crtc_state = to_dm_crtc_state(crtc->state); 1990 if (dm_crtc_state->stream == NULL) 1991 goto unlock; 1992 1993 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 1994 1995 dm_crtc_state->dsc_force_changed = true; 1996 1997 unlock: 1998 if (crtc) 1999 drm_modeset_unlock(&crtc->mutex); 2000 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2001 mutex_unlock(&dev->mode_config.mutex); 2002 2003 done: 2004 kfree(wr_buf); 2005 return size; 2006 } 2007 2008 /* function: read DSC picture width parameter on the connector 2009 * 2010 * The read function: dp_dsc_pic_width_read 2011 * returns dsc picture width used in the current configuration 2012 * It is the same as h_addressable of the current 2013 * display's timing 2014 * The return is an integer: 0 or other positive integer 2015 * If 0 then DSC is disabled. 2016 * 2017 * Access it with the following command: 2018 * 2019 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2020 * 2021 * 0 - means that DSC is disabled 2022 */ 2023 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2024 size_t size, loff_t *pos) 2025 { 2026 char *rd_buf = NULL; 2027 char *rd_buf_ptr = NULL; 2028 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2029 struct display_stream_compressor *dsc; 2030 struct dcn_dsc_state dsc_state = {0}; 2031 const uint32_t rd_buf_size = 100; 2032 struct pipe_ctx *pipe_ctx; 2033 ssize_t result = 0; 2034 int i, r, str_len = 30; 2035 2036 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2037 2038 if (!rd_buf) 2039 return -ENOMEM; 2040 2041 rd_buf_ptr = rd_buf; 2042 2043 for (i = 0; i < MAX_PIPES; i++) { 2044 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2045 if (pipe_ctx && pipe_ctx->stream && 2046 pipe_ctx->stream->link == aconnector->dc_link) 2047 break; 2048 } 2049 2050 if (!pipe_ctx) 2051 return -ENXIO; 2052 2053 dsc = pipe_ctx->stream_res.dsc; 2054 if (dsc) 2055 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2056 2057 snprintf(rd_buf_ptr, str_len, 2058 "%d\n", 2059 dsc_state.dsc_pic_width); 2060 rd_buf_ptr += str_len; 2061 2062 while (size) { 2063 if (*pos >= rd_buf_size) 2064 break; 2065 2066 r = put_user(*(rd_buf + result), buf); 2067 if (r) 2068 return r; /* r = -EFAULT */ 2069 2070 buf += 1; 2071 size -= 1; 2072 *pos += 1; 2073 result += 1; 2074 } 2075 2076 kfree(rd_buf); 2077 return result; 2078 } 2079 2080 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2081 size_t size, loff_t *pos) 2082 { 2083 char *rd_buf = NULL; 2084 char *rd_buf_ptr = NULL; 2085 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2086 struct display_stream_compressor *dsc; 2087 struct dcn_dsc_state dsc_state = {0}; 2088 const uint32_t rd_buf_size = 100; 2089 struct pipe_ctx *pipe_ctx; 2090 ssize_t result = 0; 2091 int i, r, str_len = 30; 2092 2093 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2094 2095 if (!rd_buf) 2096 return -ENOMEM; 2097 2098 rd_buf_ptr = rd_buf; 2099 2100 for (i = 0; i < MAX_PIPES; i++) { 2101 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2102 if (pipe_ctx && pipe_ctx->stream && 2103 pipe_ctx->stream->link == aconnector->dc_link) 2104 break; 2105 } 2106 2107 if (!pipe_ctx) 2108 return -ENXIO; 2109 2110 dsc = pipe_ctx->stream_res.dsc; 2111 if (dsc) 2112 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2113 2114 snprintf(rd_buf_ptr, str_len, 2115 "%d\n", 2116 dsc_state.dsc_pic_height); 2117 rd_buf_ptr += str_len; 2118 2119 while (size) { 2120 if (*pos >= rd_buf_size) 2121 break; 2122 2123 r = put_user(*(rd_buf + result), buf); 2124 if (r) 2125 return r; /* r = -EFAULT */ 2126 2127 buf += 1; 2128 size -= 1; 2129 *pos += 1; 2130 result += 1; 2131 } 2132 2133 kfree(rd_buf); 2134 return result; 2135 } 2136 2137 /* function: read DSC chunk size parameter on the connector 2138 * 2139 * The read function: dp_dsc_chunk_size_read 2140 * returns dsc chunk size set in the current configuration 2141 * The value is calculated automatically by DSC code 2142 * and depends on slice parameters and bpp target rate 2143 * The return is an integer: 0 or other positive integer 2144 * If 0 then DSC is disabled. 2145 * 2146 * Access it with the following command: 2147 * 2148 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2149 * 2150 * 0 - means that DSC is disabled 2151 */ 2152 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2153 size_t size, loff_t *pos) 2154 { 2155 char *rd_buf = NULL; 2156 char *rd_buf_ptr = NULL; 2157 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2158 struct display_stream_compressor *dsc; 2159 struct dcn_dsc_state dsc_state = {0}; 2160 const uint32_t rd_buf_size = 100; 2161 struct pipe_ctx *pipe_ctx; 2162 ssize_t result = 0; 2163 int i, r, str_len = 30; 2164 2165 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2166 2167 if (!rd_buf) 2168 return -ENOMEM; 2169 2170 rd_buf_ptr = rd_buf; 2171 2172 for (i = 0; i < MAX_PIPES; i++) { 2173 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2174 if (pipe_ctx && pipe_ctx->stream && 2175 pipe_ctx->stream->link == aconnector->dc_link) 2176 break; 2177 } 2178 2179 if (!pipe_ctx) 2180 return -ENXIO; 2181 2182 dsc = pipe_ctx->stream_res.dsc; 2183 if (dsc) 2184 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2185 2186 snprintf(rd_buf_ptr, str_len, 2187 "%d\n", 2188 dsc_state.dsc_chunk_size); 2189 rd_buf_ptr += str_len; 2190 2191 while (size) { 2192 if (*pos >= rd_buf_size) 2193 break; 2194 2195 r = put_user(*(rd_buf + result), buf); 2196 if (r) 2197 return r; /* r = -EFAULT */ 2198 2199 buf += 1; 2200 size -= 1; 2201 *pos += 1; 2202 result += 1; 2203 } 2204 2205 kfree(rd_buf); 2206 return result; 2207 } 2208 2209 /* function: read DSC slice bpg offset on the connector 2210 * 2211 * The read function: dp_dsc_slice_bpg_offset_read 2212 * returns dsc bpg slice offset set in the current configuration 2213 * The value is calculated automatically by DSC code 2214 * and depends on slice parameters and bpp target rate 2215 * The return is an integer: 0 or other positive integer 2216 * If 0 then DSC is disabled. 2217 * 2218 * Access it with the following command: 2219 * 2220 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2221 * 2222 * 0 - means that DSC is disabled 2223 */ 2224 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2225 size_t size, loff_t *pos) 2226 { 2227 char *rd_buf = NULL; 2228 char *rd_buf_ptr = NULL; 2229 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2230 struct display_stream_compressor *dsc; 2231 struct dcn_dsc_state dsc_state = {0}; 2232 const uint32_t rd_buf_size = 100; 2233 struct pipe_ctx *pipe_ctx; 2234 ssize_t result = 0; 2235 int i, r, str_len = 30; 2236 2237 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2238 2239 if (!rd_buf) 2240 return -ENOMEM; 2241 2242 rd_buf_ptr = rd_buf; 2243 2244 for (i = 0; i < MAX_PIPES; i++) { 2245 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2246 if (pipe_ctx && pipe_ctx->stream && 2247 pipe_ctx->stream->link == aconnector->dc_link) 2248 break; 2249 } 2250 2251 if (!pipe_ctx) 2252 return -ENXIO; 2253 2254 dsc = pipe_ctx->stream_res.dsc; 2255 if (dsc) 2256 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2257 2258 snprintf(rd_buf_ptr, str_len, 2259 "%d\n", 2260 dsc_state.dsc_slice_bpg_offset); 2261 rd_buf_ptr += str_len; 2262 2263 while (size) { 2264 if (*pos >= rd_buf_size) 2265 break; 2266 2267 r = put_user(*(rd_buf + result), buf); 2268 if (r) 2269 return r; /* r = -EFAULT */ 2270 2271 buf += 1; 2272 size -= 1; 2273 *pos += 1; 2274 result += 1; 2275 } 2276 2277 kfree(rd_buf); 2278 return result; 2279 } 2280 2281 2282 /* 2283 * function description: Read max_requested_bpc property from the connector 2284 * 2285 * Access it with the following command: 2286 * 2287 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2288 * 2289 */ 2290 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2291 size_t size, loff_t *pos) 2292 { 2293 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2294 struct drm_connector *connector = &aconnector->base; 2295 struct drm_device *dev = connector->dev; 2296 struct dm_connector_state *state; 2297 ssize_t result = 0; 2298 char *rd_buf = NULL; 2299 char *rd_buf_ptr = NULL; 2300 const uint32_t rd_buf_size = 10; 2301 int r; 2302 2303 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2304 2305 if (!rd_buf) 2306 return -ENOMEM; 2307 2308 mutex_lock(&dev->mode_config.mutex); 2309 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2310 2311 if (connector->state == NULL) 2312 goto unlock; 2313 2314 state = to_dm_connector_state(connector->state); 2315 2316 rd_buf_ptr = rd_buf; 2317 snprintf(rd_buf_ptr, rd_buf_size, 2318 "%u\n", 2319 state->base.max_requested_bpc); 2320 2321 while (size) { 2322 if (*pos >= rd_buf_size) 2323 break; 2324 2325 r = put_user(*(rd_buf + result), buf); 2326 if (r) { 2327 result = r; /* r = -EFAULT */ 2328 goto unlock; 2329 } 2330 buf += 1; 2331 size -= 1; 2332 *pos += 1; 2333 result += 1; 2334 } 2335 unlock: 2336 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2337 mutex_unlock(&dev->mode_config.mutex); 2338 kfree(rd_buf); 2339 return result; 2340 } 2341 2342 2343 /* 2344 * function description: Set max_requested_bpc property on the connector 2345 * 2346 * This function will not force the input BPC on connector, it will only 2347 * change the max value. This is equivalent to setting max_bpc through 2348 * xrandr. 2349 * 2350 * The BPC value written must be >= 6 and <= 16. Values outside of this 2351 * range will result in errors. 2352 * 2353 * BPC values: 2354 * 0x6 - 6 BPC 2355 * 0x8 - 8 BPC 2356 * 0xa - 10 BPC 2357 * 0xc - 12 BPC 2358 * 0x10 - 16 BPC 2359 * 2360 * Write the max_bpc in the following way: 2361 * 2362 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2363 * 2364 */ 2365 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2366 size_t size, loff_t *pos) 2367 { 2368 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2369 struct drm_connector *connector = &aconnector->base; 2370 struct dm_connector_state *state; 2371 struct drm_device *dev = connector->dev; 2372 char *wr_buf = NULL; 2373 uint32_t wr_buf_size = 42; 2374 int max_param_num = 1; 2375 long param[1] = {0}; 2376 uint8_t param_nums = 0; 2377 2378 if (size == 0) 2379 return -EINVAL; 2380 2381 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2382 2383 if (!wr_buf) { 2384 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2385 return -ENOSPC; 2386 } 2387 2388 if (parse_write_buffer_into_params(wr_buf, size, 2389 (long *)param, buf, 2390 max_param_num, 2391 ¶m_nums)) { 2392 kfree(wr_buf); 2393 return -EINVAL; 2394 } 2395 2396 if (param_nums <= 0) { 2397 DRM_DEBUG_DRIVER("user data not be read\n"); 2398 kfree(wr_buf); 2399 return -EINVAL; 2400 } 2401 2402 if (param[0] < 6 || param[0] > 16) { 2403 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2404 kfree(wr_buf); 2405 return -EINVAL; 2406 } 2407 2408 mutex_lock(&dev->mode_config.mutex); 2409 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2410 2411 if (connector->state == NULL) 2412 goto unlock; 2413 2414 state = to_dm_connector_state(connector->state); 2415 state->base.max_requested_bpc = param[0]; 2416 unlock: 2417 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2418 mutex_unlock(&dev->mode_config.mutex); 2419 2420 kfree(wr_buf); 2421 return size; 2422 } 2423 2424 /* 2425 * Backlight at this moment. Read only. 2426 * As written to display, taking ABM and backlight lut into account. 2427 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2428 * 2429 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2430 */ 2431 static int current_backlight_show(struct seq_file *m, void *unused) 2432 { 2433 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2434 struct dc_link *link = aconnector->dc_link; 2435 unsigned int backlight; 2436 2437 backlight = dc_link_get_backlight_level(link); 2438 seq_printf(m, "0x%x\n", backlight); 2439 2440 return 0; 2441 } 2442 2443 /* 2444 * Backlight value that is being approached. Read only. 2445 * As written to display, taking ABM and backlight lut into account. 2446 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2447 * 2448 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2449 */ 2450 static int target_backlight_show(struct seq_file *m, void *unused) 2451 { 2452 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2453 struct dc_link *link = aconnector->dc_link; 2454 unsigned int backlight; 2455 2456 backlight = dc_link_get_target_backlight_pwm(link); 2457 seq_printf(m, "0x%x\n", backlight); 2458 2459 return 0; 2460 } 2461 2462 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2463 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2464 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2465 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2466 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2467 #ifdef CONFIG_DRM_AMD_DC_HDCP 2468 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2469 #endif 2470 DEFINE_SHOW_ATTRIBUTE(internal_display); 2471 2472 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2473 .owner = THIS_MODULE, 2474 .read = dp_dsc_clock_en_read, 2475 .write = dp_dsc_clock_en_write, 2476 .llseek = default_llseek 2477 }; 2478 2479 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2480 .owner = THIS_MODULE, 2481 .read = dp_dsc_slice_width_read, 2482 .write = dp_dsc_slice_width_write, 2483 .llseek = default_llseek 2484 }; 2485 2486 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2487 .owner = THIS_MODULE, 2488 .read = dp_dsc_slice_height_read, 2489 .write = dp_dsc_slice_height_write, 2490 .llseek = default_llseek 2491 }; 2492 2493 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2494 .owner = THIS_MODULE, 2495 .read = dp_dsc_bits_per_pixel_read, 2496 .write = dp_dsc_bits_per_pixel_write, 2497 .llseek = default_llseek 2498 }; 2499 2500 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2501 .owner = THIS_MODULE, 2502 .read = dp_dsc_pic_width_read, 2503 .llseek = default_llseek 2504 }; 2505 2506 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2507 .owner = THIS_MODULE, 2508 .read = dp_dsc_pic_height_read, 2509 .llseek = default_llseek 2510 }; 2511 2512 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2513 .owner = THIS_MODULE, 2514 .read = dp_dsc_chunk_size_read, 2515 .llseek = default_llseek 2516 }; 2517 2518 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2519 .owner = THIS_MODULE, 2520 .read = dp_dsc_slice_bpg_offset_read, 2521 .llseek = default_llseek 2522 }; 2523 2524 static const struct file_operations trigger_hotplug_debugfs_fops = { 2525 .owner = THIS_MODULE, 2526 .write = trigger_hotplug, 2527 .llseek = default_llseek 2528 }; 2529 2530 static const struct file_operations dp_link_settings_debugfs_fops = { 2531 .owner = THIS_MODULE, 2532 .read = dp_link_settings_read, 2533 .write = dp_link_settings_write, 2534 .llseek = default_llseek 2535 }; 2536 2537 static const struct file_operations dp_phy_settings_debugfs_fop = { 2538 .owner = THIS_MODULE, 2539 .read = dp_phy_settings_read, 2540 .write = dp_phy_settings_write, 2541 .llseek = default_llseek 2542 }; 2543 2544 static const struct file_operations dp_phy_test_pattern_fops = { 2545 .owner = THIS_MODULE, 2546 .write = dp_phy_test_pattern_debugfs_write, 2547 .llseek = default_llseek 2548 }; 2549 2550 static const struct file_operations sdp_message_fops = { 2551 .owner = THIS_MODULE, 2552 .write = dp_sdp_message_debugfs_write, 2553 .llseek = default_llseek 2554 }; 2555 2556 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2557 .owner = THIS_MODULE, 2558 .write = dp_dpcd_address_write, 2559 .llseek = default_llseek 2560 }; 2561 2562 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2563 .owner = THIS_MODULE, 2564 .write = dp_dpcd_size_write, 2565 .llseek = default_llseek 2566 }; 2567 2568 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2569 .owner = THIS_MODULE, 2570 .read = dp_dpcd_data_read, 2571 .write = dp_dpcd_data_write, 2572 .llseek = default_llseek 2573 }; 2574 2575 static const struct file_operations dp_max_bpc_debugfs_fops = { 2576 .owner = THIS_MODULE, 2577 .read = dp_max_bpc_read, 2578 .write = dp_max_bpc_write, 2579 .llseek = default_llseek 2580 }; 2581 2582 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2583 .owner = THIS_MODULE, 2584 .write = dp_dsc_passthrough_set, 2585 .llseek = default_llseek 2586 }; 2587 2588 static const struct { 2589 char *name; 2590 const struct file_operations *fops; 2591 } dp_debugfs_entries[] = { 2592 {"link_settings", &dp_link_settings_debugfs_fops}, 2593 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2594 {"lttpr_status", &dp_lttpr_status_fops}, 2595 {"test_pattern", &dp_phy_test_pattern_fops}, 2596 #ifdef CONFIG_DRM_AMD_DC_HDCP 2597 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2598 #endif 2599 {"sdp_message", &sdp_message_fops}, 2600 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2601 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2602 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2603 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2604 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2605 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2606 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2607 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2608 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2609 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2610 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2611 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2612 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2613 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2614 }; 2615 2616 #ifdef CONFIG_DRM_AMD_DC_HDCP 2617 static const struct { 2618 char *name; 2619 const struct file_operations *fops; 2620 } hdmi_debugfs_entries[] = { 2621 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2622 }; 2623 #endif 2624 /* 2625 * Force YUV420 output if available from the given mode 2626 */ 2627 static int force_yuv420_output_set(void *data, u64 val) 2628 { 2629 struct amdgpu_dm_connector *connector = data; 2630 2631 connector->force_yuv420_output = (bool)val; 2632 2633 return 0; 2634 } 2635 2636 /* 2637 * Check if YUV420 is forced when available from the given mode 2638 */ 2639 static int force_yuv420_output_get(void *data, u64 *val) 2640 { 2641 struct amdgpu_dm_connector *connector = data; 2642 2643 *val = connector->force_yuv420_output; 2644 2645 return 0; 2646 } 2647 2648 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2649 force_yuv420_output_set, "%llu\n"); 2650 2651 /* 2652 * Read PSR state 2653 */ 2654 static int psr_get(void *data, u64 *val) 2655 { 2656 struct amdgpu_dm_connector *connector = data; 2657 struct dc_link *link = connector->dc_link; 2658 enum dc_psr_state state = PSR_STATE0; 2659 2660 dc_link_get_psr_state(link, &state); 2661 2662 *val = state; 2663 2664 return 0; 2665 } 2666 2667 /* 2668 * Set dmcub trace event IRQ enable or disable. 2669 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2670 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2671 */ 2672 static int dmcub_trace_event_state_set(void *data, u64 val) 2673 { 2674 struct amdgpu_device *adev = data; 2675 2676 if (val == 1 || val == 0) { 2677 dc_dmub_trace_event_control(adev->dm.dc, val); 2678 adev->dm.dmcub_trace_event_en = (bool)val; 2679 } else 2680 return 0; 2681 2682 return 0; 2683 } 2684 2685 /* 2686 * The interface doesn't need get function, so it will return the 2687 * value of zero 2688 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2689 */ 2690 static int dmcub_trace_event_state_get(void *data, u64 *val) 2691 { 2692 struct amdgpu_device *adev = data; 2693 2694 *val = adev->dm.dmcub_trace_event_en; 2695 return 0; 2696 } 2697 2698 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2699 dmcub_trace_event_state_set, "%llu\n"); 2700 2701 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2702 2703 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2704 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2705 2706 static const struct { 2707 char *name; 2708 const struct file_operations *fops; 2709 } connector_debugfs_entries[] = { 2710 {"force_yuv420_output", &force_yuv420_output_fops}, 2711 {"output_bpc", &output_bpc_fops}, 2712 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2713 {"internal_display", &internal_display_fops} 2714 }; 2715 2716 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2717 { 2718 int i; 2719 struct dentry *dir = connector->base.debugfs_entry; 2720 2721 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2722 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2723 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2724 debugfs_create_file(dp_debugfs_entries[i].name, 2725 0644, dir, connector, 2726 dp_debugfs_entries[i].fops); 2727 } 2728 } 2729 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2730 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2731 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2732 ¤t_backlight_fops); 2733 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2734 &target_backlight_fops); 2735 } 2736 2737 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2738 debugfs_create_file(connector_debugfs_entries[i].name, 2739 0644, dir, connector, 2740 connector_debugfs_entries[i].fops); 2741 } 2742 2743 connector->debugfs_dpcd_address = 0; 2744 connector->debugfs_dpcd_size = 0; 2745 2746 #ifdef CONFIG_DRM_AMD_DC_HDCP 2747 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2748 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2749 debugfs_create_file(hdmi_debugfs_entries[i].name, 2750 0644, dir, connector, 2751 hdmi_debugfs_entries[i].fops); 2752 } 2753 } 2754 #endif 2755 } 2756 2757 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2758 /* 2759 * Set crc window coordinate x start 2760 */ 2761 static int crc_win_x_start_set(void *data, u64 val) 2762 { 2763 struct drm_crtc *crtc = data; 2764 struct drm_device *drm_dev = crtc->dev; 2765 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2766 2767 spin_lock_irq(&drm_dev->event_lock); 2768 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2769 acrtc->dm_irq_params.crc_window.update_win = false; 2770 spin_unlock_irq(&drm_dev->event_lock); 2771 2772 return 0; 2773 } 2774 2775 /* 2776 * Get crc window coordinate x start 2777 */ 2778 static int crc_win_x_start_get(void *data, u64 *val) 2779 { 2780 struct drm_crtc *crtc = data; 2781 struct drm_device *drm_dev = crtc->dev; 2782 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2783 2784 spin_lock_irq(&drm_dev->event_lock); 2785 *val = acrtc->dm_irq_params.crc_window.x_start; 2786 spin_unlock_irq(&drm_dev->event_lock); 2787 2788 return 0; 2789 } 2790 2791 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 2792 crc_win_x_start_set, "%llu\n"); 2793 2794 2795 /* 2796 * Set crc window coordinate y start 2797 */ 2798 static int crc_win_y_start_set(void *data, u64 val) 2799 { 2800 struct drm_crtc *crtc = data; 2801 struct drm_device *drm_dev = crtc->dev; 2802 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2803 2804 spin_lock_irq(&drm_dev->event_lock); 2805 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 2806 acrtc->dm_irq_params.crc_window.update_win = false; 2807 spin_unlock_irq(&drm_dev->event_lock); 2808 2809 return 0; 2810 } 2811 2812 /* 2813 * Get crc window coordinate y start 2814 */ 2815 static int crc_win_y_start_get(void *data, u64 *val) 2816 { 2817 struct drm_crtc *crtc = data; 2818 struct drm_device *drm_dev = crtc->dev; 2819 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2820 2821 spin_lock_irq(&drm_dev->event_lock); 2822 *val = acrtc->dm_irq_params.crc_window.y_start; 2823 spin_unlock_irq(&drm_dev->event_lock); 2824 2825 return 0; 2826 } 2827 2828 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 2829 crc_win_y_start_set, "%llu\n"); 2830 2831 /* 2832 * Set crc window coordinate x end 2833 */ 2834 static int crc_win_x_end_set(void *data, u64 val) 2835 { 2836 struct drm_crtc *crtc = data; 2837 struct drm_device *drm_dev = crtc->dev; 2838 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2839 2840 spin_lock_irq(&drm_dev->event_lock); 2841 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 2842 acrtc->dm_irq_params.crc_window.update_win = false; 2843 spin_unlock_irq(&drm_dev->event_lock); 2844 2845 return 0; 2846 } 2847 2848 /* 2849 * Get crc window coordinate x end 2850 */ 2851 static int crc_win_x_end_get(void *data, u64 *val) 2852 { 2853 struct drm_crtc *crtc = data; 2854 struct drm_device *drm_dev = crtc->dev; 2855 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2856 2857 spin_lock_irq(&drm_dev->event_lock); 2858 *val = acrtc->dm_irq_params.crc_window.x_end; 2859 spin_unlock_irq(&drm_dev->event_lock); 2860 2861 return 0; 2862 } 2863 2864 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 2865 crc_win_x_end_set, "%llu\n"); 2866 2867 /* 2868 * Set crc window coordinate y end 2869 */ 2870 static int crc_win_y_end_set(void *data, u64 val) 2871 { 2872 struct drm_crtc *crtc = data; 2873 struct drm_device *drm_dev = crtc->dev; 2874 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2875 2876 spin_lock_irq(&drm_dev->event_lock); 2877 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 2878 acrtc->dm_irq_params.crc_window.update_win = false; 2879 spin_unlock_irq(&drm_dev->event_lock); 2880 2881 return 0; 2882 } 2883 2884 /* 2885 * Get crc window coordinate y end 2886 */ 2887 static int crc_win_y_end_get(void *data, u64 *val) 2888 { 2889 struct drm_crtc *crtc = data; 2890 struct drm_device *drm_dev = crtc->dev; 2891 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2892 2893 spin_lock_irq(&drm_dev->event_lock); 2894 *val = acrtc->dm_irq_params.crc_window.y_end; 2895 spin_unlock_irq(&drm_dev->event_lock); 2896 2897 return 0; 2898 } 2899 2900 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 2901 crc_win_y_end_set, "%llu\n"); 2902 /* 2903 * Trigger to commit crc window 2904 */ 2905 static int crc_win_update_set(void *data, u64 val) 2906 { 2907 struct drm_crtc *new_crtc = data; 2908 struct drm_crtc *old_crtc = NULL; 2909 struct amdgpu_crtc *new_acrtc, *old_acrtc; 2910 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 2911 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 2912 2913 if (val) { 2914 spin_lock_irq(&adev_to_drm(adev)->event_lock); 2915 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 2916 if (crc_rd_wrk && crc_rd_wrk->crtc) { 2917 old_crtc = crc_rd_wrk->crtc; 2918 old_acrtc = to_amdgpu_crtc(old_crtc); 2919 } 2920 new_acrtc = to_amdgpu_crtc(new_crtc); 2921 2922 if (old_crtc && old_crtc != new_crtc) { 2923 old_acrtc->dm_irq_params.crc_window.activated = false; 2924 old_acrtc->dm_irq_params.crc_window.update_win = false; 2925 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2926 2927 new_acrtc->dm_irq_params.crc_window.activated = true; 2928 new_acrtc->dm_irq_params.crc_window.update_win = true; 2929 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2930 crc_rd_wrk->crtc = new_crtc; 2931 } else { 2932 new_acrtc->dm_irq_params.crc_window.activated = true; 2933 new_acrtc->dm_irq_params.crc_window.update_win = true; 2934 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 2935 crc_rd_wrk->crtc = new_crtc; 2936 } 2937 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 2938 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 2939 } 2940 2941 return 0; 2942 } 2943 2944 /* 2945 * Get crc window update flag 2946 */ 2947 static int crc_win_update_get(void *data, u64 *val) 2948 { 2949 *val = 0; 2950 return 0; 2951 } 2952 2953 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 2954 crc_win_update_set, "%llu\n"); 2955 2956 void crtc_debugfs_init(struct drm_crtc *crtc) 2957 { 2958 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 2959 2960 if (!dir) 2961 return; 2962 2963 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 2964 &crc_win_x_start_fops); 2965 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 2966 &crc_win_y_start_fops); 2967 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 2968 &crc_win_x_end_fops); 2969 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 2970 &crc_win_y_end_fops); 2971 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 2972 &crc_win_update_fops); 2973 2974 } 2975 #endif 2976 /* 2977 * Writes DTN log state to the user supplied buffer. 2978 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 2979 */ 2980 static ssize_t dtn_log_read( 2981 struct file *f, 2982 char __user *buf, 2983 size_t size, 2984 loff_t *pos) 2985 { 2986 struct amdgpu_device *adev = file_inode(f)->i_private; 2987 struct dc *dc = adev->dm.dc; 2988 struct dc_log_buffer_ctx log_ctx = { 0 }; 2989 ssize_t result = 0; 2990 2991 if (!buf || !size) 2992 return -EINVAL; 2993 2994 if (!dc->hwss.log_hw_state) 2995 return 0; 2996 2997 dc->hwss.log_hw_state(dc, &log_ctx); 2998 2999 if (*pos < log_ctx.pos) { 3000 size_t to_copy = log_ctx.pos - *pos; 3001 3002 to_copy = min(to_copy, size); 3003 3004 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3005 *pos += to_copy; 3006 result = to_copy; 3007 } 3008 } 3009 3010 kfree(log_ctx.buf); 3011 3012 return result; 3013 } 3014 3015 /* 3016 * Writes DTN log state to dmesg when triggered via a write. 3017 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3018 */ 3019 static ssize_t dtn_log_write( 3020 struct file *f, 3021 const char __user *buf, 3022 size_t size, 3023 loff_t *pos) 3024 { 3025 struct amdgpu_device *adev = file_inode(f)->i_private; 3026 struct dc *dc = adev->dm.dc; 3027 3028 /* Write triggers log output via dmesg. */ 3029 if (size == 0) 3030 return 0; 3031 3032 if (dc->hwss.log_hw_state) 3033 dc->hwss.log_hw_state(dc, NULL); 3034 3035 return size; 3036 } 3037 3038 static int mst_topo_show(struct seq_file *m, void *unused) 3039 { 3040 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3041 struct drm_device *dev = adev_to_drm(adev); 3042 struct drm_connector *connector; 3043 struct drm_connector_list_iter conn_iter; 3044 struct amdgpu_dm_connector *aconnector; 3045 3046 drm_connector_list_iter_begin(dev, &conn_iter); 3047 drm_for_each_connector_iter(connector, &conn_iter) { 3048 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3049 continue; 3050 3051 aconnector = to_amdgpu_dm_connector(connector); 3052 3053 /* Ensure we're only dumping the topology of a root mst node */ 3054 if (!aconnector->mst_mgr.mst_state) 3055 continue; 3056 3057 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3058 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3059 } 3060 drm_connector_list_iter_end(&conn_iter); 3061 3062 return 0; 3063 } 3064 3065 /* 3066 * Sets trigger hpd for MST topologies. 3067 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3068 * All topologies will be disconnected if val of 0 is set . 3069 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3070 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3071 */ 3072 static int trigger_hpd_mst_set(void *data, u64 val) 3073 { 3074 struct amdgpu_device *adev = data; 3075 struct drm_device *dev = adev_to_drm(adev); 3076 struct drm_connector_list_iter iter; 3077 struct amdgpu_dm_connector *aconnector; 3078 struct drm_connector *connector; 3079 struct dc_link *link = NULL; 3080 3081 if (val == 1) { 3082 drm_connector_list_iter_begin(dev, &iter); 3083 drm_for_each_connector_iter(connector, &iter) { 3084 aconnector = to_amdgpu_dm_connector(connector); 3085 if (aconnector->dc_link->type == dc_connection_mst_branch && 3086 aconnector->mst_mgr.aux) { 3087 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3088 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3089 } 3090 } 3091 } else if (val == 0) { 3092 drm_connector_list_iter_begin(dev, &iter); 3093 drm_for_each_connector_iter(connector, &iter) { 3094 aconnector = to_amdgpu_dm_connector(connector); 3095 if (!aconnector->dc_link) 3096 continue; 3097 3098 if (!aconnector->mst_port) 3099 continue; 3100 3101 link = aconnector->dc_link; 3102 dp_receiver_power_ctrl(link, false); 3103 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3104 link->mst_stream_alloc_table.stream_count = 0; 3105 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3106 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3107 } 3108 } else { 3109 return 0; 3110 } 3111 drm_kms_helper_hotplug_event(dev); 3112 3113 return 0; 3114 } 3115 3116 /* 3117 * The interface doesn't need get function, so it will return the 3118 * value of zero 3119 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3120 */ 3121 static int trigger_hpd_mst_get(void *data, u64 *val) 3122 { 3123 *val = 0; 3124 return 0; 3125 } 3126 3127 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3128 trigger_hpd_mst_set, "%llu\n"); 3129 3130 3131 /* 3132 * Sets the force_timing_sync debug option from the given string. 3133 * All connected displays will be force synchronized immediately. 3134 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3135 */ 3136 static int force_timing_sync_set(void *data, u64 val) 3137 { 3138 struct amdgpu_device *adev = data; 3139 3140 adev->dm.force_timing_sync = (bool)val; 3141 3142 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3143 3144 return 0; 3145 } 3146 3147 /* 3148 * Gets the force_timing_sync debug option value into the given buffer. 3149 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3150 */ 3151 static int force_timing_sync_get(void *data, u64 *val) 3152 { 3153 struct amdgpu_device *adev = data; 3154 3155 *val = adev->dm.force_timing_sync; 3156 3157 return 0; 3158 } 3159 3160 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3161 force_timing_sync_set, "%llu\n"); 3162 3163 3164 /* 3165 * Disables all HPD and HPD RX interrupt handling in the 3166 * driver when set to 1. Default is 0. 3167 */ 3168 static int disable_hpd_set(void *data, u64 val) 3169 { 3170 struct amdgpu_device *adev = data; 3171 3172 adev->dm.disable_hpd_irq = (bool)val; 3173 3174 return 0; 3175 } 3176 3177 3178 /* 3179 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3180 * 0 otherwise. 3181 */ 3182 static int disable_hpd_get(void *data, u64 *val) 3183 { 3184 struct amdgpu_device *adev = data; 3185 3186 *val = adev->dm.disable_hpd_irq; 3187 3188 return 0; 3189 } 3190 3191 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3192 disable_hpd_set, "%llu\n"); 3193 3194 /* 3195 * Sets the DC visual confirm debug option from the given string. 3196 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3197 */ 3198 static int visual_confirm_set(void *data, u64 val) 3199 { 3200 struct amdgpu_device *adev = data; 3201 3202 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3203 3204 return 0; 3205 } 3206 3207 /* 3208 * Reads the DC visual confirm debug option value into the given buffer. 3209 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3210 */ 3211 static int visual_confirm_get(void *data, u64 *val) 3212 { 3213 struct amdgpu_device *adev = data; 3214 3215 *val = adev->dm.dc->debug.visual_confirm; 3216 3217 return 0; 3218 } 3219 3220 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3221 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3222 visual_confirm_set, "%llu\n"); 3223 3224 /* 3225 * Dumps the DCC_EN bit for each pipe. 3226 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3227 */ 3228 static ssize_t dcc_en_bits_read( 3229 struct file *f, 3230 char __user *buf, 3231 size_t size, 3232 loff_t *pos) 3233 { 3234 struct amdgpu_device *adev = file_inode(f)->i_private; 3235 struct dc *dc = adev->dm.dc; 3236 char *rd_buf = NULL; 3237 const uint32_t rd_buf_size = 32; 3238 uint32_t result = 0; 3239 int offset = 0; 3240 int num_pipes = dc->res_pool->pipe_count; 3241 int *dcc_en_bits; 3242 int i, r; 3243 3244 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3245 if (!dcc_en_bits) 3246 return -ENOMEM; 3247 3248 if (!dc->hwss.get_dcc_en_bits) { 3249 kfree(dcc_en_bits); 3250 return 0; 3251 } 3252 3253 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3254 3255 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3256 if (!rd_buf) 3257 return -ENOMEM; 3258 3259 for (i = 0; i < num_pipes; i++) 3260 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3261 "%d ", dcc_en_bits[i]); 3262 rd_buf[strlen(rd_buf)] = '\n'; 3263 3264 kfree(dcc_en_bits); 3265 3266 while (size) { 3267 if (*pos >= rd_buf_size) 3268 break; 3269 r = put_user(*(rd_buf + result), buf); 3270 if (r) 3271 return r; /* r = -EFAULT */ 3272 buf += 1; 3273 size -= 1; 3274 *pos += 1; 3275 result += 1; 3276 } 3277 3278 kfree(rd_buf); 3279 return result; 3280 } 3281 3282 void dtn_debugfs_init(struct amdgpu_device *adev) 3283 { 3284 static const struct file_operations dtn_log_fops = { 3285 .owner = THIS_MODULE, 3286 .read = dtn_log_read, 3287 .write = dtn_log_write, 3288 .llseek = default_llseek 3289 }; 3290 static const struct file_operations dcc_en_bits_fops = { 3291 .owner = THIS_MODULE, 3292 .read = dcc_en_bits_read, 3293 .llseek = default_llseek 3294 }; 3295 3296 struct drm_minor *minor = adev_to_drm(adev)->primary; 3297 struct dentry *root = minor->debugfs_root; 3298 3299 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3300 adev, &mst_topo_fops); 3301 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3302 &dtn_log_fops); 3303 3304 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3305 &visual_confirm_fops); 3306 3307 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3308 adev, &dmub_tracebuffer_fops); 3309 3310 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3311 adev, &dmub_fw_state_fops); 3312 3313 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3314 adev, &force_timing_sync_ops); 3315 3316 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3317 adev, &dmcub_trace_event_state_fops); 3318 3319 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3320 adev, &trigger_hpd_mst_ops); 3321 3322 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3323 &dcc_en_bits_fops); 3324 3325 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3326 &disable_hpd_ops); 3327 3328 } 3329