1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "link/protocols/link_dp_capability.h" 40 41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42 #include "amdgpu_dm_psr.h" 43 #endif 44 45 struct dmub_debugfs_trace_header { 46 uint32_t entry_count; 47 uint32_t reserved[3]; 48 }; 49 50 struct dmub_debugfs_trace_entry { 51 uint32_t trace_code; 52 uint32_t tick_count; 53 uint32_t param0; 54 uint32_t param1; 55 }; 56 57 static const char *const mst_progress_status[] = { 58 "probe", 59 "remote_edid", 60 "allocate_new_payload", 61 "clear_allocated_payload", 62 }; 63 64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 65 * 66 * Function takes in attributes passed to debugfs write entry 67 * and writes into param array. 68 * The user passes max_param_num to identify maximum number of 69 * parameters that could be parsed. 70 * 71 */ 72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 73 long *param, const char __user *buf, 74 int max_param_num, 75 uint8_t *param_nums) 76 { 77 char *wr_buf_ptr = NULL; 78 uint32_t wr_buf_count = 0; 79 int r; 80 char *sub_str = NULL; 81 const char delimiter[3] = {' ', '\n', '\0'}; 82 uint8_t param_index = 0; 83 84 *param_nums = 0; 85 86 wr_buf_ptr = wr_buf; 87 88 /* r is bytes not be copied */ 89 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 90 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 91 return -EFAULT; 92 } 93 94 /* check number of parameters. isspace could not differ space and \n */ 95 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 96 /* skip space*/ 97 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 98 wr_buf_ptr++; 99 wr_buf_count++; 100 } 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 105 /* skip non-space*/ 106 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 107 wr_buf_ptr++; 108 wr_buf_count++; 109 } 110 111 (*param_nums)++; 112 113 if (wr_buf_count == wr_buf_size) 114 break; 115 } 116 117 if (*param_nums > max_param_num) 118 *param_nums = max_param_num; 119 120 wr_buf_ptr = wr_buf; /* reset buf pointer */ 121 wr_buf_count = 0; /* number of char already checked */ 122 123 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 124 wr_buf_ptr++; 125 wr_buf_count++; 126 } 127 128 while (param_index < *param_nums) { 129 /* after strsep, wr_buf_ptr will be moved to after space */ 130 sub_str = strsep(&wr_buf_ptr, delimiter); 131 132 r = kstrtol(sub_str, 16, &(param[param_index])); 133 134 if (r) 135 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 136 137 param_index++; 138 } 139 140 return 0; 141 } 142 143 /* function description 144 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 145 * 146 * valid lane count value: 1, 2, 4 147 * valid link rate value: 148 * 06h = 1.62Gbps per lane 149 * 0Ah = 2.7Gbps per lane 150 * 0Ch = 3.24Gbps per lane 151 * 14h = 5.4Gbps per lane 152 * 1Eh = 8.1Gbps per lane 153 * 154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * --- to get dp configuration 157 * 158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 159 * 160 * It will list current, verified, reported, preferred dp configuration. 161 * current -- for current video mode 162 * verified --- maximum configuration which pass link training 163 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 164 * preferred --- user force settings 165 * 166 * --- set (or force) dp configuration 167 * 168 * echo <lane_count> <link_rate> > link_settings 169 * 170 * for example, to force to 2 lane, 2.7GHz, 171 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 172 * 173 * spread_spectrum could not be changed dynamically. 174 * 175 * in case invalid lane count, link rate are force, no hw programming will be 176 * done. please check link settings after force operation to see if HW get 177 * programming. 178 * 179 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 180 * 181 * check current and preferred settings. 182 * 183 */ 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 185 size_t size, loff_t *pos) 186 { 187 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 188 struct dc_link *link = connector->dc_link; 189 char *rd_buf = NULL; 190 char *rd_buf_ptr = NULL; 191 const uint32_t rd_buf_size = 100; 192 uint32_t result = 0; 193 uint8_t str_len = 0; 194 int r; 195 196 if (*pos & 3 || size & 3) 197 return -EINVAL; 198 199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 200 if (!rd_buf) 201 return 0; 202 203 rd_buf_ptr = rd_buf; 204 205 str_len = strlen("Current: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 207 link->cur_link_settings.lane_count, 208 link->cur_link_settings.link_rate, 209 link->cur_link_settings.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Verified: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 214 link->verified_link_cap.lane_count, 215 link->verified_link_cap.link_rate, 216 link->verified_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Reported: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 221 link->reported_link_cap.lane_count, 222 link->reported_link_cap.link_rate, 223 link->reported_link_cap.link_spread); 224 rd_buf_ptr += str_len; 225 226 str_len = strlen("Preferred: %d 0x%x %d "); 227 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 228 link->preferred_link_setting.lane_count, 229 link->preferred_link_setting.link_rate, 230 link->preferred_link_setting.link_spread); 231 232 while (size) { 233 if (*pos >= rd_buf_size) 234 break; 235 236 r = put_user(*(rd_buf + result), buf); 237 if (r) { 238 kfree(rd_buf); 239 return r; /* r = -EFAULT */ 240 } 241 242 buf += 1; 243 size -= 1; 244 *pos += 1; 245 result += 1; 246 } 247 248 kfree(rd_buf); 249 return result; 250 } 251 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 253 size_t size, loff_t *pos) 254 { 255 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 256 struct dc_link *link = connector->dc_link; 257 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 258 struct dc *dc = (struct dc *)link->dc; 259 struct dc_link_settings prefer_link_settings; 260 char *wr_buf = NULL; 261 const uint32_t wr_buf_size = 40; 262 /* 0: lane_count; 1: link_rate */ 263 int max_param_num = 2; 264 uint8_t param_nums = 0; 265 long param[2]; 266 bool valid_input = true; 267 268 if (size == 0) 269 return -EINVAL; 270 271 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 272 if (!wr_buf) 273 return -ENOSPC; 274 275 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 276 (long *)param, buf, 277 max_param_num, 278 ¶m_nums)) { 279 kfree(wr_buf); 280 return -EINVAL; 281 } 282 283 if (param_nums <= 0) { 284 kfree(wr_buf); 285 DRM_DEBUG_DRIVER("user data not be read\n"); 286 return -EINVAL; 287 } 288 289 switch (param[0]) { 290 case LANE_COUNT_ONE: 291 case LANE_COUNT_TWO: 292 case LANE_COUNT_FOUR: 293 break; 294 default: 295 valid_input = false; 296 break; 297 } 298 299 switch (param[1]) { 300 case LINK_RATE_LOW: 301 case LINK_RATE_HIGH: 302 case LINK_RATE_RBR2: 303 case LINK_RATE_HIGH2: 304 case LINK_RATE_HIGH3: 305 case LINK_RATE_UHBR10: 306 case LINK_RATE_UHBR13_5: 307 case LINK_RATE_UHBR20: 308 break; 309 default: 310 valid_input = false; 311 break; 312 } 313 314 if (!valid_input) { 315 kfree(wr_buf); 316 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 317 mutex_lock(&adev->dm.dc_lock); 318 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 319 mutex_unlock(&adev->dm.dc_lock); 320 return size; 321 } 322 323 /* save user force lane_count, link_rate to preferred settings 324 * spread spectrum will not be changed 325 */ 326 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 327 prefer_link_settings.use_link_rate_set = false; 328 prefer_link_settings.lane_count = param[0]; 329 prefer_link_settings.link_rate = param[1]; 330 331 mutex_lock(&adev->dm.dc_lock); 332 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 333 mutex_unlock(&adev->dm.dc_lock); 334 335 kfree(wr_buf); 336 return size; 337 } 338 339 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) 340 { 341 bool is_end_device = false; 342 struct drm_dp_mst_topology_mgr *mgr = NULL; 343 struct drm_dp_mst_port *port = NULL; 344 345 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) { 346 mgr = &aconnector->mst_root->mst_mgr; 347 port = aconnector->mst_output_port; 348 349 drm_modeset_lock(&mgr->base.lock, NULL); 350 if (port->pdt == DP_PEER_DEVICE_SST_SINK || 351 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) 352 is_end_device = true; 353 drm_modeset_unlock(&mgr->base.lock); 354 } 355 356 return is_end_device; 357 } 358 359 /* Change MST link setting 360 * 361 * valid lane count value: 1, 2, 4 362 * valid link rate value: 363 * 06h = 1.62Gbps per lane 364 * 0Ah = 2.7Gbps per lane 365 * 0Ch = 3.24Gbps per lane 366 * 14h = 5.4Gbps per lane 367 * 1Eh = 8.1Gbps per lane 368 * 3E8h = 10.0Gbps per lane 369 * 546h = 13.5Gbps per lane 370 * 7D0h = 20.0Gbps per lane 371 * 372 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings 373 * 374 * for example, to force to 2 lane, 10.0GHz, 375 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings 376 * 377 * Valid input will trigger hotplug event to get new link setting applied 378 * Invalid input will trigger training setting reset 379 * 380 * The usage can be referred to link_settings entry 381 * 382 */ 383 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, 384 size_t size, loff_t *pos) 385 { 386 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 387 struct dc_link *link = aconnector->dc_link; 388 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 389 struct dc *dc = (struct dc *)link->dc; 390 struct dc_link_settings prefer_link_settings; 391 char *wr_buf = NULL; 392 const uint32_t wr_buf_size = 40; 393 /* 0: lane_count; 1: link_rate */ 394 int max_param_num = 2; 395 uint8_t param_nums = 0; 396 long param[2]; 397 bool valid_input = true; 398 399 if (!dp_mst_is_end_device(aconnector)) 400 return -EINVAL; 401 402 if (size == 0) 403 return -EINVAL; 404 405 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 406 if (!wr_buf) 407 return -ENOSPC; 408 409 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 410 (long *)param, buf, 411 max_param_num, 412 ¶m_nums)) { 413 kfree(wr_buf); 414 return -EINVAL; 415 } 416 417 if (param_nums <= 0) { 418 kfree(wr_buf); 419 DRM_DEBUG_DRIVER("user data not be read\n"); 420 return -EINVAL; 421 } 422 423 switch (param[0]) { 424 case LANE_COUNT_ONE: 425 case LANE_COUNT_TWO: 426 case LANE_COUNT_FOUR: 427 break; 428 default: 429 valid_input = false; 430 break; 431 } 432 433 switch (param[1]) { 434 case LINK_RATE_LOW: 435 case LINK_RATE_HIGH: 436 case LINK_RATE_RBR2: 437 case LINK_RATE_HIGH2: 438 case LINK_RATE_HIGH3: 439 case LINK_RATE_UHBR10: 440 case LINK_RATE_UHBR13_5: 441 case LINK_RATE_UHBR20: 442 break; 443 default: 444 valid_input = false; 445 break; 446 } 447 448 if (!valid_input) { 449 kfree(wr_buf); 450 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 451 mutex_lock(&adev->dm.dc_lock); 452 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 453 mutex_unlock(&adev->dm.dc_lock); 454 return -EINVAL; 455 } 456 457 /* save user force lane_count, link_rate to preferred settings 458 * spread spectrum will not be changed 459 */ 460 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 461 prefer_link_settings.use_link_rate_set = false; 462 prefer_link_settings.lane_count = param[0]; 463 prefer_link_settings.link_rate = param[1]; 464 465 /* skip immediate retrain, and train to new link setting after hotplug event triggered */ 466 mutex_lock(&adev->dm.dc_lock); 467 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 468 mutex_unlock(&adev->dm.dc_lock); 469 470 mutex_lock(&aconnector->base.dev->mode_config.mutex); 471 aconnector->base.force = DRM_FORCE_OFF; 472 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 473 drm_kms_helper_hotplug_event(aconnector->base.dev); 474 475 msleep(100); 476 477 mutex_lock(&aconnector->base.dev->mode_config.mutex); 478 aconnector->base.force = DRM_FORCE_UNSPECIFIED; 479 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 480 drm_kms_helper_hotplug_event(aconnector->base.dev); 481 482 kfree(wr_buf); 483 return size; 484 } 485 486 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 487 * post-cursor2 (defined by VESA DP specification) 488 * 489 * valid values 490 * voltage swing: 0,1,2,3 491 * pre-emphasis : 0,1,2,3 492 * post cursor2 : 0,1,2,3 493 * 494 * 495 * how to use this debugfs 496 * 497 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 498 * 499 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 500 * 501 * To figure out which DP-x is the display for DP to be check, 502 * cd DP-x 503 * ls -ll 504 * There should be debugfs file, like link_settings, phy_settings. 505 * cat link_settings 506 * from lane_count, link_rate to figure which DP-x is for display to be worked 507 * on 508 * 509 * To get current DP PHY settings, 510 * cat phy_settings 511 * 512 * To change DP PHY settings, 513 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 514 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 515 * 0, 516 * echo 2 3 0 > phy_settings 517 * 518 * To check if change be applied, get current phy settings by 519 * cat phy_settings 520 * 521 * In case invalid values are set by user, like 522 * echo 1 4 0 > phy_settings 523 * 524 * HW will NOT be programmed by these settings. 525 * cat phy_settings will show the previous valid settings. 526 */ 527 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 528 size_t size, loff_t *pos) 529 { 530 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 531 struct dc_link *link = connector->dc_link; 532 char *rd_buf = NULL; 533 const uint32_t rd_buf_size = 20; 534 uint32_t result = 0; 535 int r; 536 537 if (*pos & 3 || size & 3) 538 return -EINVAL; 539 540 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 541 if (!rd_buf) 542 return -EINVAL; 543 544 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 545 link->cur_lane_setting[0].VOLTAGE_SWING, 546 link->cur_lane_setting[0].PRE_EMPHASIS, 547 link->cur_lane_setting[0].POST_CURSOR2); 548 549 while (size) { 550 if (*pos >= rd_buf_size) 551 break; 552 553 r = put_user((*(rd_buf + result)), buf); 554 if (r) { 555 kfree(rd_buf); 556 return r; /* r = -EFAULT */ 557 } 558 559 buf += 1; 560 size -= 1; 561 *pos += 1; 562 result += 1; 563 } 564 565 kfree(rd_buf); 566 return result; 567 } 568 569 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 570 { 571 struct drm_connector *connector = m->private; 572 struct amdgpu_dm_connector *aconnector = 573 to_amdgpu_dm_connector(connector); 574 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 575 576 if (connector->status != connector_status_connected) 577 return -ENODEV; 578 579 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 580 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 581 caps.phy_repeater_cnt); 582 583 seq_puts(m, "phy repeater mode: "); 584 585 switch (caps.mode) { 586 case DP_PHY_REPEATER_MODE_TRANSPARENT: 587 seq_puts(m, "transparent"); 588 break; 589 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 590 seq_puts(m, "non-transparent"); 591 break; 592 case 0x00: 593 seq_puts(m, "non lttpr"); 594 break; 595 default: 596 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 597 break; 598 } 599 600 seq_puts(m, "\n"); 601 return 0; 602 } 603 604 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 605 size_t size, loff_t *pos) 606 { 607 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 608 struct dc_link *link = connector->dc_link; 609 struct dc *dc = (struct dc *)link->dc; 610 char *wr_buf = NULL; 611 uint32_t wr_buf_size = 40; 612 long param[3]; 613 bool use_prefer_link_setting; 614 struct link_training_settings link_lane_settings; 615 int max_param_num = 3; 616 uint8_t param_nums = 0; 617 int r = 0; 618 619 620 if (size == 0) 621 return -EINVAL; 622 623 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 624 if (!wr_buf) 625 return -ENOSPC; 626 627 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 628 (long *)param, buf, 629 max_param_num, 630 ¶m_nums)) { 631 kfree(wr_buf); 632 return -EINVAL; 633 } 634 635 if (param_nums <= 0) { 636 kfree(wr_buf); 637 DRM_DEBUG_DRIVER("user data not be read\n"); 638 return -EINVAL; 639 } 640 641 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 642 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 643 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 644 kfree(wr_buf); 645 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 646 return size; 647 } 648 649 /* get link settings: lane count, link rate */ 650 use_prefer_link_setting = 651 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 652 (link->test_pattern_enabled)); 653 654 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 655 656 if (use_prefer_link_setting) { 657 link_lane_settings.link_settings.lane_count = 658 link->preferred_link_setting.lane_count; 659 link_lane_settings.link_settings.link_rate = 660 link->preferred_link_setting.link_rate; 661 link_lane_settings.link_settings.link_spread = 662 link->preferred_link_setting.link_spread; 663 } else { 664 link_lane_settings.link_settings.lane_count = 665 link->cur_link_settings.lane_count; 666 link_lane_settings.link_settings.link_rate = 667 link->cur_link_settings.link_rate; 668 link_lane_settings.link_settings.link_spread = 669 link->cur_link_settings.link_spread; 670 } 671 672 /* apply phy settings from user */ 673 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 674 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 675 (enum dc_voltage_swing) (param[0]); 676 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 677 (enum dc_pre_emphasis) (param[1]); 678 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 679 (enum dc_post_cursor2) (param[2]); 680 } 681 682 /* program ASIC registers and DPCD registers */ 683 dc_link_set_drive_settings(dc, &link_lane_settings, link); 684 685 kfree(wr_buf); 686 return size; 687 } 688 689 /* function description 690 * 691 * set PHY layer or Link layer test pattern 692 * PHY test pattern is used for PHY SI check. 693 * Link layer test will not affect PHY SI. 694 * 695 * Reset Test Pattern: 696 * 0 = DP_TEST_PATTERN_VIDEO_MODE 697 * 698 * PHY test pattern supported: 699 * 1 = DP_TEST_PATTERN_D102 700 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 701 * 3 = DP_TEST_PATTERN_PRBS7 702 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 703 * 5 = DP_TEST_PATTERN_CP2520_1 704 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 705 * 7 = DP_TEST_PATTERN_CP2520_3 706 * 707 * DP PHY Link Training Patterns 708 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 709 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 710 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 711 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 712 * 713 * DP Link Layer Test pattern 714 * c = DP_TEST_PATTERN_COLOR_SQUARES 715 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 716 * e = DP_TEST_PATTERN_VERTICAL_BARS 717 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 718 * 10= DP_TEST_PATTERN_COLOR_RAMP 719 * 720 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 721 * 722 * --- set test pattern 723 * echo <test pattern #> > test_pattern 724 * 725 * If test pattern # is not supported, NO HW programming will be done. 726 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 727 * for the user pattern. input 10 bytes data are separated by space 728 * 729 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 730 * 731 * --- reset test pattern 732 * echo 0 > test_pattern 733 * 734 * --- HPD detection is disabled when set PHY test pattern 735 * 736 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 737 * is disable. User could unplug DP display from DP connected and plug scope to 738 * check test pattern PHY SI. 739 * If there is need unplug scope and plug DP display back, do steps below: 740 * echo 0 > phy_test_pattern 741 * unplug scope 742 * plug DP display. 743 * 744 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 745 * driver could detect "unplug scope" and "plug DP display" 746 */ 747 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 748 size_t size, loff_t *pos) 749 { 750 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 751 struct dc_link *link = connector->dc_link; 752 char *wr_buf = NULL; 753 uint32_t wr_buf_size = 100; 754 long param[11] = {0x0}; 755 int max_param_num = 11; 756 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 757 bool disable_hpd = false; 758 bool valid_test_pattern = false; 759 uint8_t param_nums = 0; 760 /* init with default 80bit custom pattern */ 761 uint8_t custom_pattern[10] = { 762 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 763 0x1f, 0x7c, 0xf0, 0xc1, 0x07 764 }; 765 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 766 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 767 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 768 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 769 struct link_training_settings link_training_settings; 770 int i; 771 772 if (size == 0) 773 return -EINVAL; 774 775 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 776 if (!wr_buf) 777 return -ENOSPC; 778 779 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 780 (long *)param, buf, 781 max_param_num, 782 ¶m_nums)) { 783 kfree(wr_buf); 784 return -EINVAL; 785 } 786 787 if (param_nums <= 0) { 788 kfree(wr_buf); 789 DRM_DEBUG_DRIVER("user data not be read\n"); 790 return -EINVAL; 791 } 792 793 794 test_pattern = param[0]; 795 796 switch (test_pattern) { 797 case DP_TEST_PATTERN_VIDEO_MODE: 798 case DP_TEST_PATTERN_COLOR_SQUARES: 799 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 800 case DP_TEST_PATTERN_VERTICAL_BARS: 801 case DP_TEST_PATTERN_HORIZONTAL_BARS: 802 case DP_TEST_PATTERN_COLOR_RAMP: 803 valid_test_pattern = true; 804 break; 805 806 case DP_TEST_PATTERN_D102: 807 case DP_TEST_PATTERN_SYMBOL_ERROR: 808 case DP_TEST_PATTERN_PRBS7: 809 case DP_TEST_PATTERN_80BIT_CUSTOM: 810 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 811 case DP_TEST_PATTERN_TRAINING_PATTERN4: 812 disable_hpd = true; 813 valid_test_pattern = true; 814 break; 815 816 default: 817 valid_test_pattern = false; 818 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 819 break; 820 } 821 822 if (!valid_test_pattern) { 823 kfree(wr_buf); 824 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 825 return size; 826 } 827 828 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 829 for (i = 0; i < 10; i++) { 830 if ((uint8_t) param[i + 1] != 0x0) 831 break; 832 } 833 834 if (i < 10) { 835 /* not use default value */ 836 for (i = 0; i < 10; i++) 837 custom_pattern[i] = (uint8_t) param[i + 1]; 838 } 839 } 840 841 /* Usage: set DP physical test pattern using debugfs with normal DP 842 * panel. Then plug out DP panel and connect a scope to measure 843 * For normal video mode and test pattern generated from CRCT, 844 * they are visibile to user. So do not disable HPD. 845 * Video Mode is also set to clear the test pattern, so enable HPD 846 * because it might have been disabled after a test pattern was set. 847 * AUX depends on HPD * sequence dependent, do not move! 848 */ 849 if (!disable_hpd) 850 dc_link_enable_hpd(link); 851 852 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 853 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 854 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 855 856 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 857 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 858 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 859 860 link_training_settings.link_settings = cur_link_settings; 861 862 863 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 864 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 865 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 866 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 867 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 868 link_training_settings.link_settings = prefer_link_settings; 869 } 870 871 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 872 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 873 874 dc_link_dp_set_test_pattern( 875 link, 876 test_pattern, 877 DP_TEST_PATTERN_COLOR_SPACE_RGB, 878 &link_training_settings, 879 custom_pattern, 880 10); 881 882 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 883 * Then plug out DP panel and connect a scope to measure DP PHY signal. 884 * Need disable interrupt to avoid SW driver disable DP output. This is 885 * done after the test pattern is set. 886 */ 887 if (valid_test_pattern && disable_hpd) 888 dc_link_disable_hpd(link); 889 890 kfree(wr_buf); 891 892 return size; 893 } 894 895 /* 896 * Returns the DMCUB tracebuffer contents. 897 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 898 */ 899 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 900 { 901 struct amdgpu_device *adev = m->private; 902 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 903 struct dmub_debugfs_trace_entry *entries; 904 uint8_t *tbuf_base; 905 uint32_t tbuf_size, max_entries, num_entries, i; 906 907 if (!fb_info) 908 return 0; 909 910 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 911 if (!tbuf_base) 912 return 0; 913 914 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 915 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 916 sizeof(struct dmub_debugfs_trace_entry); 917 918 num_entries = 919 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 920 921 num_entries = min(num_entries, max_entries); 922 923 entries = (struct dmub_debugfs_trace_entry 924 *)(tbuf_base + 925 sizeof(struct dmub_debugfs_trace_header)); 926 927 for (i = 0; i < num_entries; ++i) { 928 struct dmub_debugfs_trace_entry *entry = &entries[i]; 929 930 seq_printf(m, 931 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 932 entry->trace_code, entry->tick_count, entry->param0, 933 entry->param1); 934 } 935 936 return 0; 937 } 938 939 /* 940 * Returns the DMCUB firmware state contents. 941 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 942 */ 943 static int dmub_fw_state_show(struct seq_file *m, void *data) 944 { 945 struct amdgpu_device *adev = m->private; 946 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 947 uint8_t *state_base; 948 uint32_t state_size; 949 950 if (!fb_info) 951 return 0; 952 953 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 954 if (!state_base) 955 return 0; 956 957 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 958 959 return seq_write(m, state_base, state_size); 960 } 961 962 /* psr_capability_show() - show eDP panel PSR capability 963 * 964 * The read function: sink_psr_capability_show 965 * Shows if sink has PSR capability or not. 966 * If yes - the PSR version is appended 967 * 968 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 969 * 970 * Expected output: 971 * "Sink support: no\n" - if panel doesn't support PSR 972 * "Sink support: yes [0x01]\n" - if panel supports PSR1 973 * "Driver support: no\n" - if driver doesn't support PSR 974 * "Driver support: yes [0x01]\n" - if driver supports PSR1 975 */ 976 static int psr_capability_show(struct seq_file *m, void *data) 977 { 978 struct drm_connector *connector = m->private; 979 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 980 struct dc_link *link = aconnector->dc_link; 981 982 if (!link) 983 return -ENODEV; 984 985 if (link->type == dc_connection_none) 986 return -ENODEV; 987 988 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 989 return -ENODEV; 990 991 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 992 if (link->dpcd_caps.psr_info.psr_version) 993 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 994 seq_puts(m, "\n"); 995 996 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 997 if (link->psr_settings.psr_version) 998 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 999 seq_puts(m, "\n"); 1000 1001 return 0; 1002 } 1003 1004 /* 1005 * Returns the current bpc for the crtc. 1006 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 1007 */ 1008 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 1009 { 1010 struct drm_crtc *crtc = m->private; 1011 struct drm_device *dev = crtc->dev; 1012 struct dm_crtc_state *dm_crtc_state = NULL; 1013 int res = -ENODEV; 1014 unsigned int bpc; 1015 1016 mutex_lock(&dev->mode_config.mutex); 1017 drm_modeset_lock(&crtc->mutex, NULL); 1018 if (crtc->state == NULL) 1019 goto unlock; 1020 1021 dm_crtc_state = to_dm_crtc_state(crtc->state); 1022 if (dm_crtc_state->stream == NULL) 1023 goto unlock; 1024 1025 switch (dm_crtc_state->stream->timing.display_color_depth) { 1026 case COLOR_DEPTH_666: 1027 bpc = 6; 1028 break; 1029 case COLOR_DEPTH_888: 1030 bpc = 8; 1031 break; 1032 case COLOR_DEPTH_101010: 1033 bpc = 10; 1034 break; 1035 case COLOR_DEPTH_121212: 1036 bpc = 12; 1037 break; 1038 case COLOR_DEPTH_161616: 1039 bpc = 16; 1040 break; 1041 default: 1042 goto unlock; 1043 } 1044 1045 seq_printf(m, "Current: %u\n", bpc); 1046 res = 0; 1047 1048 unlock: 1049 drm_modeset_unlock(&crtc->mutex); 1050 mutex_unlock(&dev->mode_config.mutex); 1051 1052 return res; 1053 } 1054 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 1055 1056 /* 1057 * Returns the current colorspace for the crtc. 1058 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 1059 */ 1060 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 1061 { 1062 struct drm_crtc *crtc = m->private; 1063 struct drm_device *dev = crtc->dev; 1064 struct dm_crtc_state *dm_crtc_state = NULL; 1065 int res = -ENODEV; 1066 1067 mutex_lock(&dev->mode_config.mutex); 1068 drm_modeset_lock(&crtc->mutex, NULL); 1069 if (crtc->state == NULL) 1070 goto unlock; 1071 1072 dm_crtc_state = to_dm_crtc_state(crtc->state); 1073 if (dm_crtc_state->stream == NULL) 1074 goto unlock; 1075 1076 switch (dm_crtc_state->stream->output_color_space) { 1077 case COLOR_SPACE_SRGB: 1078 seq_puts(m, "sRGB"); 1079 break; 1080 case COLOR_SPACE_YCBCR601: 1081 case COLOR_SPACE_YCBCR601_LIMITED: 1082 seq_puts(m, "BT601_YCC"); 1083 break; 1084 case COLOR_SPACE_YCBCR709: 1085 case COLOR_SPACE_YCBCR709_LIMITED: 1086 seq_puts(m, "BT709_YCC"); 1087 break; 1088 case COLOR_SPACE_ADOBERGB: 1089 seq_puts(m, "opRGB"); 1090 break; 1091 case COLOR_SPACE_2020_RGB_FULLRANGE: 1092 seq_puts(m, "BT2020_RGB"); 1093 break; 1094 case COLOR_SPACE_2020_YCBCR: 1095 seq_puts(m, "BT2020_YCC"); 1096 break; 1097 default: 1098 goto unlock; 1099 } 1100 res = 0; 1101 1102 unlock: 1103 drm_modeset_unlock(&crtc->mutex); 1104 mutex_unlock(&dev->mode_config.mutex); 1105 1106 return res; 1107 } 1108 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 1109 1110 1111 /* 1112 * Example usage: 1113 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 1114 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1115 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 1116 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1117 */ 1118 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 1119 size_t size, loff_t *pos) 1120 { 1121 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1122 char *wr_buf = NULL; 1123 uint32_t wr_buf_size = 42; 1124 int max_param_num = 1; 1125 long param; 1126 uint8_t param_nums = 0; 1127 1128 if (size == 0) 1129 return -EINVAL; 1130 1131 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1132 1133 if (!wr_buf) { 1134 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1135 return -ENOSPC; 1136 } 1137 1138 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1139 ¶m, buf, 1140 max_param_num, 1141 ¶m_nums)) { 1142 kfree(wr_buf); 1143 return -EINVAL; 1144 } 1145 1146 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1147 1148 kfree(wr_buf); 1149 return 0; 1150 } 1151 1152 /* 1153 * Returns the HDCP capability of the Display (1.4 for now). 1154 * 1155 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1156 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1157 * 1158 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1159 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1160 */ 1161 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1162 { 1163 struct drm_connector *connector = m->private; 1164 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1165 bool hdcp_cap, hdcp2_cap; 1166 1167 if (connector->status != connector_status_connected) 1168 return -ENODEV; 1169 1170 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1171 1172 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1173 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1174 1175 1176 if (hdcp_cap) 1177 seq_printf(m, "%s ", "HDCP1.4"); 1178 if (hdcp2_cap) 1179 seq_printf(m, "%s ", "HDCP2.2"); 1180 1181 if (!hdcp_cap && !hdcp2_cap) 1182 seq_printf(m, "%s ", "None"); 1183 1184 seq_puts(m, "\n"); 1185 1186 return 0; 1187 } 1188 1189 /* 1190 * Returns whether the connected display is internal and not hotpluggable. 1191 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1192 */ 1193 static int internal_display_show(struct seq_file *m, void *data) 1194 { 1195 struct drm_connector *connector = m->private; 1196 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1197 struct dc_link *link = aconnector->dc_link; 1198 1199 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1200 1201 return 0; 1202 } 1203 1204 /* 1205 * Returns the number of segments used if ODM Combine mode is enabled. 1206 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments 1207 */ 1208 static int odm_combine_segments_show(struct seq_file *m, void *unused) 1209 { 1210 struct drm_connector *connector = m->private; 1211 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1212 struct dc_link *link = aconnector->dc_link; 1213 struct pipe_ctx *pipe_ctx = NULL; 1214 int i, segments = 0; 1215 1216 for (i = 0; i < MAX_PIPES; i++) { 1217 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 1218 if (pipe_ctx->stream && 1219 pipe_ctx->stream->link == link) 1220 break; 1221 } 1222 1223 if (connector->status != connector_status_connected) 1224 return -ENODEV; 1225 1226 if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1227 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1228 1229 seq_printf(m, "%d\n", segments); 1230 return 0; 1231 } 1232 1233 /* function description 1234 * 1235 * generic SDP message access for testing 1236 * 1237 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1238 * 1239 * SDP header 1240 * Hb0 : Secondary-Data Packet ID 1241 * Hb1 : Secondary-Data Packet type 1242 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1243 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1244 * 1245 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1246 */ 1247 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1248 size_t size, loff_t *pos) 1249 { 1250 int r; 1251 uint8_t data[36]; 1252 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1253 struct dm_crtc_state *acrtc_state; 1254 uint32_t write_size = 36; 1255 1256 if (connector->base.status != connector_status_connected) 1257 return -ENODEV; 1258 1259 if (size == 0) 1260 return 0; 1261 1262 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1263 1264 r = copy_from_user(data, buf, write_size); 1265 1266 write_size -= r; 1267 1268 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1269 1270 return write_size; 1271 } 1272 1273 /* function: Read link's DSC & FEC capabilities 1274 * 1275 * 1276 * Access it with the following command (you need to specify 1277 * connector like DP-1): 1278 * 1279 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1280 * 1281 */ 1282 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1283 { 1284 struct drm_connector *connector = m->private; 1285 struct drm_modeset_acquire_ctx ctx; 1286 struct drm_device *dev = connector->dev; 1287 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1288 int ret = 0; 1289 bool try_again = false; 1290 bool is_fec_supported = false; 1291 bool is_dsc_supported = false; 1292 struct dpcd_caps dpcd_caps; 1293 1294 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1295 do { 1296 try_again = false; 1297 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1298 if (ret) { 1299 if (ret == -EDEADLK) { 1300 ret = drm_modeset_backoff(&ctx); 1301 if (!ret) { 1302 try_again = true; 1303 continue; 1304 } 1305 } 1306 break; 1307 } 1308 if (connector->status != connector_status_connected) { 1309 ret = -ENODEV; 1310 break; 1311 } 1312 dpcd_caps = aconnector->dc_link->dpcd_caps; 1313 if (aconnector->mst_output_port) { 1314 /* aconnector sets dsc_aux during get_modes call 1315 * if MST connector has it means it can either 1316 * enable DSC on the sink device or on MST branch 1317 * its connected to. 1318 */ 1319 if (aconnector->dsc_aux) { 1320 is_fec_supported = true; 1321 is_dsc_supported = true; 1322 } 1323 } else { 1324 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1325 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1326 } 1327 } while (try_again); 1328 1329 drm_modeset_drop_locks(&ctx); 1330 drm_modeset_acquire_fini(&ctx); 1331 1332 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1333 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1334 1335 return ret; 1336 } 1337 1338 /* function: Trigger virtual HPD redetection on connector 1339 * 1340 * This function will perform link rediscovery, link disable 1341 * and enable, and dm connector state update. 1342 * 1343 * Retrigger HPD on an existing connector by echoing 1 into 1344 * its respectful "trigger_hotplug" debugfs entry: 1345 * 1346 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1347 * 1348 * This function can perform HPD unplug: 1349 * 1350 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1351 * 1352 */ 1353 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1354 size_t size, loff_t *pos) 1355 { 1356 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1357 struct drm_connector *connector = &aconnector->base; 1358 struct dc_link *link = NULL; 1359 struct drm_device *dev = connector->dev; 1360 struct amdgpu_device *adev = drm_to_adev(dev); 1361 enum dc_connection_type new_connection_type = dc_connection_none; 1362 char *wr_buf = NULL; 1363 uint32_t wr_buf_size = 42; 1364 int max_param_num = 1; 1365 long param[1] = {0}; 1366 uint8_t param_nums = 0; 1367 bool ret = false; 1368 1369 if (!aconnector || !aconnector->dc_link) 1370 return -EINVAL; 1371 1372 if (size == 0) 1373 return -EINVAL; 1374 1375 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1376 1377 if (!wr_buf) { 1378 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1379 return -ENOSPC; 1380 } 1381 1382 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1383 (long *)param, buf, 1384 max_param_num, 1385 ¶m_nums)) { 1386 kfree(wr_buf); 1387 return -EINVAL; 1388 } 1389 1390 kfree(wr_buf); 1391 1392 if (param_nums <= 0) { 1393 DRM_DEBUG_DRIVER("user data not be read\n"); 1394 return -EINVAL; 1395 } 1396 1397 mutex_lock(&aconnector->hpd_lock); 1398 1399 /* Don't support for mst end device*/ 1400 if (aconnector->mst_root) { 1401 mutex_unlock(&aconnector->hpd_lock); 1402 return -EINVAL; 1403 } 1404 1405 if (param[0] == 1) { 1406 1407 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1408 new_connection_type != dc_connection_none) 1409 goto unlock; 1410 1411 mutex_lock(&adev->dm.dc_lock); 1412 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1413 mutex_unlock(&adev->dm.dc_lock); 1414 1415 if (!ret) 1416 goto unlock; 1417 1418 amdgpu_dm_update_connector_after_detect(aconnector); 1419 1420 drm_modeset_lock_all(dev); 1421 dm_restore_drm_connector_state(dev, connector); 1422 drm_modeset_unlock_all(dev); 1423 1424 drm_kms_helper_connector_hotplug_event(connector); 1425 } else if (param[0] == 0) { 1426 if (!aconnector->dc_link) 1427 goto unlock; 1428 1429 link = aconnector->dc_link; 1430 1431 if (link->local_sink) { 1432 dc_sink_release(link->local_sink); 1433 link->local_sink = NULL; 1434 } 1435 1436 link->dpcd_sink_count = 0; 1437 link->type = dc_connection_none; 1438 link->dongle_max_pix_clk = 0; 1439 1440 amdgpu_dm_update_connector_after_detect(aconnector); 1441 1442 /* If the aconnector is the root node in mst topology */ 1443 if (aconnector->mst_mgr.mst_state == true) 1444 dc_link_reset_cur_dp_mst_topology(link); 1445 1446 drm_modeset_lock_all(dev); 1447 dm_restore_drm_connector_state(dev, connector); 1448 drm_modeset_unlock_all(dev); 1449 1450 drm_kms_helper_connector_hotplug_event(connector); 1451 } 1452 1453 unlock: 1454 mutex_unlock(&aconnector->hpd_lock); 1455 1456 return size; 1457 } 1458 1459 /* function: read DSC status on the connector 1460 * 1461 * The read function: dp_dsc_clock_en_read 1462 * returns current status of DSC clock on the connector. 1463 * The return is a boolean flag: 1 or 0. 1464 * 1465 * Access it with the following command (you need to specify 1466 * connector like DP-1): 1467 * 1468 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1469 * 1470 * Expected output: 1471 * 1 - means that DSC is currently enabled 1472 * 0 - means that DSC is disabled 1473 */ 1474 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1475 size_t size, loff_t *pos) 1476 { 1477 char *rd_buf = NULL; 1478 char *rd_buf_ptr = NULL; 1479 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1480 struct display_stream_compressor *dsc; 1481 struct dcn_dsc_state dsc_state = {0}; 1482 const uint32_t rd_buf_size = 10; 1483 struct pipe_ctx *pipe_ctx; 1484 ssize_t result = 0; 1485 int i, r, str_len = 30; 1486 1487 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1488 1489 if (!rd_buf) 1490 return -ENOMEM; 1491 1492 rd_buf_ptr = rd_buf; 1493 1494 for (i = 0; i < MAX_PIPES; i++) { 1495 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1496 if (pipe_ctx->stream && 1497 pipe_ctx->stream->link == aconnector->dc_link) 1498 break; 1499 } 1500 1501 dsc = pipe_ctx->stream_res.dsc; 1502 if (dsc) 1503 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1504 1505 snprintf(rd_buf_ptr, str_len, 1506 "%d\n", 1507 dsc_state.dsc_clock_en); 1508 rd_buf_ptr += str_len; 1509 1510 while (size) { 1511 if (*pos >= rd_buf_size) 1512 break; 1513 1514 r = put_user(*(rd_buf + result), buf); 1515 if (r) { 1516 kfree(rd_buf); 1517 return r; /* r = -EFAULT */ 1518 } 1519 1520 buf += 1; 1521 size -= 1; 1522 *pos += 1; 1523 result += 1; 1524 } 1525 1526 kfree(rd_buf); 1527 return result; 1528 } 1529 1530 /* function: write force DSC on the connector 1531 * 1532 * The write function: dp_dsc_clock_en_write 1533 * enables to force DSC on the connector. 1534 * User can write to either force enable or force disable DSC 1535 * on the next modeset or set it to driver default 1536 * 1537 * Accepted inputs: 1538 * 0 - default DSC enablement policy 1539 * 1 - force enable DSC on the connector 1540 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1541 * 1542 * Writing DSC settings is done with the following command: 1543 * - To force enable DSC (you need to specify 1544 * connector like DP-1): 1545 * 1546 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1547 * 1548 * - To return to default state set the flag to zero and 1549 * let driver deal with DSC automatically 1550 * (you need to specify connector like DP-1): 1551 * 1552 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1553 * 1554 */ 1555 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1556 size_t size, loff_t *pos) 1557 { 1558 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1559 struct drm_connector *connector = &aconnector->base; 1560 struct drm_device *dev = connector->dev; 1561 struct drm_crtc *crtc = NULL; 1562 struct dm_crtc_state *dm_crtc_state = NULL; 1563 struct pipe_ctx *pipe_ctx; 1564 int i; 1565 char *wr_buf = NULL; 1566 uint32_t wr_buf_size = 42; 1567 int max_param_num = 1; 1568 long param[1] = {0}; 1569 uint8_t param_nums = 0; 1570 1571 if (size == 0) 1572 return -EINVAL; 1573 1574 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1575 1576 if (!wr_buf) { 1577 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1578 return -ENOSPC; 1579 } 1580 1581 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1582 (long *)param, buf, 1583 max_param_num, 1584 ¶m_nums)) { 1585 kfree(wr_buf); 1586 return -EINVAL; 1587 } 1588 1589 if (param_nums <= 0) { 1590 DRM_DEBUG_DRIVER("user data not be read\n"); 1591 kfree(wr_buf); 1592 return -EINVAL; 1593 } 1594 1595 for (i = 0; i < MAX_PIPES; i++) { 1596 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1597 if (pipe_ctx->stream && 1598 pipe_ctx->stream->link == aconnector->dc_link) 1599 break; 1600 } 1601 1602 if (!pipe_ctx->stream) 1603 goto done; 1604 1605 // Get CRTC state 1606 mutex_lock(&dev->mode_config.mutex); 1607 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1608 1609 if (connector->state == NULL) 1610 goto unlock; 1611 1612 crtc = connector->state->crtc; 1613 if (crtc == NULL) 1614 goto unlock; 1615 1616 drm_modeset_lock(&crtc->mutex, NULL); 1617 if (crtc->state == NULL) 1618 goto unlock; 1619 1620 dm_crtc_state = to_dm_crtc_state(crtc->state); 1621 if (dm_crtc_state->stream == NULL) 1622 goto unlock; 1623 1624 if (param[0] == 1) 1625 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1626 else if (param[0] == 2) 1627 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1628 else 1629 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1630 1631 dm_crtc_state->dsc_force_changed = true; 1632 1633 unlock: 1634 if (crtc) 1635 drm_modeset_unlock(&crtc->mutex); 1636 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1637 mutex_unlock(&dev->mode_config.mutex); 1638 1639 done: 1640 kfree(wr_buf); 1641 return size; 1642 } 1643 1644 /* function: read DSC slice width parameter on the connector 1645 * 1646 * The read function: dp_dsc_slice_width_read 1647 * returns dsc slice width used in the current configuration 1648 * The return is an integer: 0 or other positive number 1649 * 1650 * Access the status with the following command: 1651 * 1652 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1653 * 1654 * 0 - means that DSC is disabled 1655 * 1656 * Any other number more than zero represents the 1657 * slice width currently used by DSC in pixels 1658 * 1659 */ 1660 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1661 size_t size, loff_t *pos) 1662 { 1663 char *rd_buf = NULL; 1664 char *rd_buf_ptr = NULL; 1665 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1666 struct display_stream_compressor *dsc; 1667 struct dcn_dsc_state dsc_state = {0}; 1668 const uint32_t rd_buf_size = 100; 1669 struct pipe_ctx *pipe_ctx; 1670 ssize_t result = 0; 1671 int i, r, str_len = 30; 1672 1673 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1674 1675 if (!rd_buf) 1676 return -ENOMEM; 1677 1678 rd_buf_ptr = rd_buf; 1679 1680 for (i = 0; i < MAX_PIPES; i++) { 1681 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1682 if (pipe_ctx->stream && 1683 pipe_ctx->stream->link == aconnector->dc_link) 1684 break; 1685 } 1686 1687 dsc = pipe_ctx->stream_res.dsc; 1688 if (dsc) 1689 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1690 1691 snprintf(rd_buf_ptr, str_len, 1692 "%d\n", 1693 dsc_state.dsc_slice_width); 1694 rd_buf_ptr += str_len; 1695 1696 while (size) { 1697 if (*pos >= rd_buf_size) 1698 break; 1699 1700 r = put_user(*(rd_buf + result), buf); 1701 if (r) { 1702 kfree(rd_buf); 1703 return r; /* r = -EFAULT */ 1704 } 1705 1706 buf += 1; 1707 size -= 1; 1708 *pos += 1; 1709 result += 1; 1710 } 1711 1712 kfree(rd_buf); 1713 return result; 1714 } 1715 1716 /* function: write DSC slice width parameter 1717 * 1718 * The write function: dp_dsc_slice_width_write 1719 * overwrites automatically generated DSC configuration 1720 * of slice width. 1721 * 1722 * The user has to write the slice width divisible by the 1723 * picture width. 1724 * 1725 * Also the user has to write width in hexidecimal 1726 * rather than in decimal. 1727 * 1728 * Writing DSC settings is done with the following command: 1729 * - To force overwrite slice width: (example sets to 1920 pixels) 1730 * 1731 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1732 * 1733 * - To stop overwriting and let driver find the optimal size, 1734 * set the width to zero: 1735 * 1736 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1737 * 1738 */ 1739 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1740 size_t size, loff_t *pos) 1741 { 1742 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1743 struct pipe_ctx *pipe_ctx; 1744 struct drm_connector *connector = &aconnector->base; 1745 struct drm_device *dev = connector->dev; 1746 struct drm_crtc *crtc = NULL; 1747 struct dm_crtc_state *dm_crtc_state = NULL; 1748 int i; 1749 char *wr_buf = NULL; 1750 uint32_t wr_buf_size = 42; 1751 int max_param_num = 1; 1752 long param[1] = {0}; 1753 uint8_t param_nums = 0; 1754 1755 if (size == 0) 1756 return -EINVAL; 1757 1758 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1759 1760 if (!wr_buf) { 1761 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1762 return -ENOSPC; 1763 } 1764 1765 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1766 (long *)param, buf, 1767 max_param_num, 1768 ¶m_nums)) { 1769 kfree(wr_buf); 1770 return -EINVAL; 1771 } 1772 1773 if (param_nums <= 0) { 1774 DRM_DEBUG_DRIVER("user data not be read\n"); 1775 kfree(wr_buf); 1776 return -EINVAL; 1777 } 1778 1779 for (i = 0; i < MAX_PIPES; i++) { 1780 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1781 if (pipe_ctx->stream && 1782 pipe_ctx->stream->link == aconnector->dc_link) 1783 break; 1784 } 1785 1786 if (!pipe_ctx->stream) 1787 goto done; 1788 1789 // Safely get CRTC state 1790 mutex_lock(&dev->mode_config.mutex); 1791 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1792 1793 if (connector->state == NULL) 1794 goto unlock; 1795 1796 crtc = connector->state->crtc; 1797 if (crtc == NULL) 1798 goto unlock; 1799 1800 drm_modeset_lock(&crtc->mutex, NULL); 1801 if (crtc->state == NULL) 1802 goto unlock; 1803 1804 dm_crtc_state = to_dm_crtc_state(crtc->state); 1805 if (dm_crtc_state->stream == NULL) 1806 goto unlock; 1807 1808 if (param[0] > 0) 1809 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1810 pipe_ctx->stream->timing.h_addressable, 1811 param[0]); 1812 else 1813 aconnector->dsc_settings.dsc_num_slices_h = 0; 1814 1815 dm_crtc_state->dsc_force_changed = true; 1816 1817 unlock: 1818 if (crtc) 1819 drm_modeset_unlock(&crtc->mutex); 1820 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1821 mutex_unlock(&dev->mode_config.mutex); 1822 1823 done: 1824 kfree(wr_buf); 1825 return size; 1826 } 1827 1828 /* function: read DSC slice height parameter on the connector 1829 * 1830 * The read function: dp_dsc_slice_height_read 1831 * returns dsc slice height used in the current configuration 1832 * The return is an integer: 0 or other positive number 1833 * 1834 * Access the status with the following command: 1835 * 1836 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1837 * 1838 * 0 - means that DSC is disabled 1839 * 1840 * Any other number more than zero represents the 1841 * slice height currently used by DSC in pixels 1842 * 1843 */ 1844 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1845 size_t size, loff_t *pos) 1846 { 1847 char *rd_buf = NULL; 1848 char *rd_buf_ptr = NULL; 1849 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1850 struct display_stream_compressor *dsc; 1851 struct dcn_dsc_state dsc_state = {0}; 1852 const uint32_t rd_buf_size = 100; 1853 struct pipe_ctx *pipe_ctx; 1854 ssize_t result = 0; 1855 int i, r, str_len = 30; 1856 1857 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1858 1859 if (!rd_buf) 1860 return -ENOMEM; 1861 1862 rd_buf_ptr = rd_buf; 1863 1864 for (i = 0; i < MAX_PIPES; i++) { 1865 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1866 if (pipe_ctx->stream && 1867 pipe_ctx->stream->link == aconnector->dc_link) 1868 break; 1869 } 1870 1871 dsc = pipe_ctx->stream_res.dsc; 1872 if (dsc) 1873 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1874 1875 snprintf(rd_buf_ptr, str_len, 1876 "%d\n", 1877 dsc_state.dsc_slice_height); 1878 rd_buf_ptr += str_len; 1879 1880 while (size) { 1881 if (*pos >= rd_buf_size) 1882 break; 1883 1884 r = put_user(*(rd_buf + result), buf); 1885 if (r) { 1886 kfree(rd_buf); 1887 return r; /* r = -EFAULT */ 1888 } 1889 1890 buf += 1; 1891 size -= 1; 1892 *pos += 1; 1893 result += 1; 1894 } 1895 1896 kfree(rd_buf); 1897 return result; 1898 } 1899 1900 /* function: write DSC slice height parameter 1901 * 1902 * The write function: dp_dsc_slice_height_write 1903 * overwrites automatically generated DSC configuration 1904 * of slice height. 1905 * 1906 * The user has to write the slice height divisible by the 1907 * picture height. 1908 * 1909 * Also the user has to write height in hexidecimal 1910 * rather than in decimal. 1911 * 1912 * Writing DSC settings is done with the following command: 1913 * - To force overwrite slice height (example sets to 128 pixels): 1914 * 1915 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1916 * 1917 * - To stop overwriting and let driver find the optimal size, 1918 * set the height to zero: 1919 * 1920 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1921 * 1922 */ 1923 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1924 size_t size, loff_t *pos) 1925 { 1926 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1927 struct drm_connector *connector = &aconnector->base; 1928 struct drm_device *dev = connector->dev; 1929 struct drm_crtc *crtc = NULL; 1930 struct dm_crtc_state *dm_crtc_state = NULL; 1931 struct pipe_ctx *pipe_ctx; 1932 int i; 1933 char *wr_buf = NULL; 1934 uint32_t wr_buf_size = 42; 1935 int max_param_num = 1; 1936 uint8_t param_nums = 0; 1937 long param[1] = {0}; 1938 1939 if (size == 0) 1940 return -EINVAL; 1941 1942 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1943 1944 if (!wr_buf) { 1945 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1946 return -ENOSPC; 1947 } 1948 1949 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1950 (long *)param, buf, 1951 max_param_num, 1952 ¶m_nums)) { 1953 kfree(wr_buf); 1954 return -EINVAL; 1955 } 1956 1957 if (param_nums <= 0) { 1958 DRM_DEBUG_DRIVER("user data not be read\n"); 1959 kfree(wr_buf); 1960 return -EINVAL; 1961 } 1962 1963 for (i = 0; i < MAX_PIPES; i++) { 1964 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1965 if (pipe_ctx->stream && 1966 pipe_ctx->stream->link == aconnector->dc_link) 1967 break; 1968 } 1969 1970 if (!pipe_ctx->stream) 1971 goto done; 1972 1973 // Get CRTC state 1974 mutex_lock(&dev->mode_config.mutex); 1975 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1976 1977 if (connector->state == NULL) 1978 goto unlock; 1979 1980 crtc = connector->state->crtc; 1981 if (crtc == NULL) 1982 goto unlock; 1983 1984 drm_modeset_lock(&crtc->mutex, NULL); 1985 if (crtc->state == NULL) 1986 goto unlock; 1987 1988 dm_crtc_state = to_dm_crtc_state(crtc->state); 1989 if (dm_crtc_state->stream == NULL) 1990 goto unlock; 1991 1992 if (param[0] > 0) 1993 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1994 pipe_ctx->stream->timing.v_addressable, 1995 param[0]); 1996 else 1997 aconnector->dsc_settings.dsc_num_slices_v = 0; 1998 1999 dm_crtc_state->dsc_force_changed = true; 2000 2001 unlock: 2002 if (crtc) 2003 drm_modeset_unlock(&crtc->mutex); 2004 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2005 mutex_unlock(&dev->mode_config.mutex); 2006 2007 done: 2008 kfree(wr_buf); 2009 return size; 2010 } 2011 2012 /* function: read DSC target rate on the connector in bits per pixel 2013 * 2014 * The read function: dp_dsc_bits_per_pixel_read 2015 * returns target rate of compression in bits per pixel 2016 * The return is an integer: 0 or other positive integer 2017 * 2018 * Access it with the following command: 2019 * 2020 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2021 * 2022 * 0 - means that DSC is disabled 2023 */ 2024 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 2025 size_t size, loff_t *pos) 2026 { 2027 char *rd_buf = NULL; 2028 char *rd_buf_ptr = NULL; 2029 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2030 struct display_stream_compressor *dsc; 2031 struct dcn_dsc_state dsc_state = {0}; 2032 const uint32_t rd_buf_size = 100; 2033 struct pipe_ctx *pipe_ctx; 2034 ssize_t result = 0; 2035 int i, r, str_len = 30; 2036 2037 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2038 2039 if (!rd_buf) 2040 return -ENOMEM; 2041 2042 rd_buf_ptr = rd_buf; 2043 2044 for (i = 0; i < MAX_PIPES; i++) { 2045 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2046 if (pipe_ctx->stream && 2047 pipe_ctx->stream->link == aconnector->dc_link) 2048 break; 2049 } 2050 2051 dsc = pipe_ctx->stream_res.dsc; 2052 if (dsc) 2053 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2054 2055 snprintf(rd_buf_ptr, str_len, 2056 "%d\n", 2057 dsc_state.dsc_bits_per_pixel); 2058 rd_buf_ptr += str_len; 2059 2060 while (size) { 2061 if (*pos >= rd_buf_size) 2062 break; 2063 2064 r = put_user(*(rd_buf + result), buf); 2065 if (r) { 2066 kfree(rd_buf); 2067 return r; /* r = -EFAULT */ 2068 } 2069 2070 buf += 1; 2071 size -= 1; 2072 *pos += 1; 2073 result += 1; 2074 } 2075 2076 kfree(rd_buf); 2077 return result; 2078 } 2079 2080 /* function: write DSC target rate in bits per pixel 2081 * 2082 * The write function: dp_dsc_bits_per_pixel_write 2083 * overwrites automatically generated DSC configuration 2084 * of DSC target bit rate. 2085 * 2086 * Also the user has to write bpp in hexidecimal 2087 * rather than in decimal. 2088 * 2089 * Writing DSC settings is done with the following command: 2090 * - To force overwrite rate (example sets to 256 bpp x 1/16): 2091 * 2092 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2093 * 2094 * - To stop overwriting and let driver find the optimal rate, 2095 * set the rate to zero: 2096 * 2097 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2098 * 2099 */ 2100 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2101 size_t size, loff_t *pos) 2102 { 2103 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2104 struct drm_connector *connector = &aconnector->base; 2105 struct drm_device *dev = connector->dev; 2106 struct drm_crtc *crtc = NULL; 2107 struct dm_crtc_state *dm_crtc_state = NULL; 2108 struct pipe_ctx *pipe_ctx; 2109 int i; 2110 char *wr_buf = NULL; 2111 uint32_t wr_buf_size = 42; 2112 int max_param_num = 1; 2113 uint8_t param_nums = 0; 2114 long param[1] = {0}; 2115 2116 if (size == 0) 2117 return -EINVAL; 2118 2119 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2120 2121 if (!wr_buf) { 2122 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2123 return -ENOSPC; 2124 } 2125 2126 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2127 (long *)param, buf, 2128 max_param_num, 2129 ¶m_nums)) { 2130 kfree(wr_buf); 2131 return -EINVAL; 2132 } 2133 2134 if (param_nums <= 0) { 2135 DRM_DEBUG_DRIVER("user data not be read\n"); 2136 kfree(wr_buf); 2137 return -EINVAL; 2138 } 2139 2140 for (i = 0; i < MAX_PIPES; i++) { 2141 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2142 if (pipe_ctx->stream && 2143 pipe_ctx->stream->link == aconnector->dc_link) 2144 break; 2145 } 2146 2147 if (!pipe_ctx->stream) 2148 goto done; 2149 2150 // Get CRTC state 2151 mutex_lock(&dev->mode_config.mutex); 2152 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2153 2154 if (connector->state == NULL) 2155 goto unlock; 2156 2157 crtc = connector->state->crtc; 2158 if (crtc == NULL) 2159 goto unlock; 2160 2161 drm_modeset_lock(&crtc->mutex, NULL); 2162 if (crtc->state == NULL) 2163 goto unlock; 2164 2165 dm_crtc_state = to_dm_crtc_state(crtc->state); 2166 if (dm_crtc_state->stream == NULL) 2167 goto unlock; 2168 2169 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2170 2171 dm_crtc_state->dsc_force_changed = true; 2172 2173 unlock: 2174 if (crtc) 2175 drm_modeset_unlock(&crtc->mutex); 2176 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2177 mutex_unlock(&dev->mode_config.mutex); 2178 2179 done: 2180 kfree(wr_buf); 2181 return size; 2182 } 2183 2184 /* function: read DSC picture width parameter on the connector 2185 * 2186 * The read function: dp_dsc_pic_width_read 2187 * returns dsc picture width used in the current configuration 2188 * It is the same as h_addressable of the current 2189 * display's timing 2190 * The return is an integer: 0 or other positive integer 2191 * If 0 then DSC is disabled. 2192 * 2193 * Access it with the following command: 2194 * 2195 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2196 * 2197 * 0 - means that DSC is disabled 2198 */ 2199 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2200 size_t size, loff_t *pos) 2201 { 2202 char *rd_buf = NULL; 2203 char *rd_buf_ptr = NULL; 2204 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2205 struct display_stream_compressor *dsc; 2206 struct dcn_dsc_state dsc_state = {0}; 2207 const uint32_t rd_buf_size = 100; 2208 struct pipe_ctx *pipe_ctx; 2209 ssize_t result = 0; 2210 int i, r, str_len = 30; 2211 2212 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2213 2214 if (!rd_buf) 2215 return -ENOMEM; 2216 2217 rd_buf_ptr = rd_buf; 2218 2219 for (i = 0; i < MAX_PIPES; i++) { 2220 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2221 if (pipe_ctx->stream && 2222 pipe_ctx->stream->link == aconnector->dc_link) 2223 break; 2224 } 2225 2226 dsc = pipe_ctx->stream_res.dsc; 2227 if (dsc) 2228 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2229 2230 snprintf(rd_buf_ptr, str_len, 2231 "%d\n", 2232 dsc_state.dsc_pic_width); 2233 rd_buf_ptr += str_len; 2234 2235 while (size) { 2236 if (*pos >= rd_buf_size) 2237 break; 2238 2239 r = put_user(*(rd_buf + result), buf); 2240 if (r) { 2241 kfree(rd_buf); 2242 return r; /* r = -EFAULT */ 2243 } 2244 2245 buf += 1; 2246 size -= 1; 2247 *pos += 1; 2248 result += 1; 2249 } 2250 2251 kfree(rd_buf); 2252 return result; 2253 } 2254 2255 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2256 size_t size, loff_t *pos) 2257 { 2258 char *rd_buf = NULL; 2259 char *rd_buf_ptr = NULL; 2260 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2261 struct display_stream_compressor *dsc; 2262 struct dcn_dsc_state dsc_state = {0}; 2263 const uint32_t rd_buf_size = 100; 2264 struct pipe_ctx *pipe_ctx; 2265 ssize_t result = 0; 2266 int i, r, str_len = 30; 2267 2268 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2269 2270 if (!rd_buf) 2271 return -ENOMEM; 2272 2273 rd_buf_ptr = rd_buf; 2274 2275 for (i = 0; i < MAX_PIPES; i++) { 2276 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2277 if (pipe_ctx->stream && 2278 pipe_ctx->stream->link == aconnector->dc_link) 2279 break; 2280 } 2281 2282 dsc = pipe_ctx->stream_res.dsc; 2283 if (dsc) 2284 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2285 2286 snprintf(rd_buf_ptr, str_len, 2287 "%d\n", 2288 dsc_state.dsc_pic_height); 2289 rd_buf_ptr += str_len; 2290 2291 while (size) { 2292 if (*pos >= rd_buf_size) 2293 break; 2294 2295 r = put_user(*(rd_buf + result), buf); 2296 if (r) { 2297 kfree(rd_buf); 2298 return r; /* r = -EFAULT */ 2299 } 2300 2301 buf += 1; 2302 size -= 1; 2303 *pos += 1; 2304 result += 1; 2305 } 2306 2307 kfree(rd_buf); 2308 return result; 2309 } 2310 2311 /* function: read DSC chunk size parameter on the connector 2312 * 2313 * The read function: dp_dsc_chunk_size_read 2314 * returns dsc chunk size set in the current configuration 2315 * The value is calculated automatically by DSC code 2316 * and depends on slice parameters and bpp target rate 2317 * The return is an integer: 0 or other positive integer 2318 * If 0 then DSC is disabled. 2319 * 2320 * Access it with the following command: 2321 * 2322 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2323 * 2324 * 0 - means that DSC is disabled 2325 */ 2326 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2327 size_t size, loff_t *pos) 2328 { 2329 char *rd_buf = NULL; 2330 char *rd_buf_ptr = NULL; 2331 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2332 struct display_stream_compressor *dsc; 2333 struct dcn_dsc_state dsc_state = {0}; 2334 const uint32_t rd_buf_size = 100; 2335 struct pipe_ctx *pipe_ctx; 2336 ssize_t result = 0; 2337 int i, r, str_len = 30; 2338 2339 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2340 2341 if (!rd_buf) 2342 return -ENOMEM; 2343 2344 rd_buf_ptr = rd_buf; 2345 2346 for (i = 0; i < MAX_PIPES; i++) { 2347 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2348 if (pipe_ctx->stream && 2349 pipe_ctx->stream->link == aconnector->dc_link) 2350 break; 2351 } 2352 2353 dsc = pipe_ctx->stream_res.dsc; 2354 if (dsc) 2355 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2356 2357 snprintf(rd_buf_ptr, str_len, 2358 "%d\n", 2359 dsc_state.dsc_chunk_size); 2360 rd_buf_ptr += str_len; 2361 2362 while (size) { 2363 if (*pos >= rd_buf_size) 2364 break; 2365 2366 r = put_user(*(rd_buf + result), buf); 2367 if (r) { 2368 kfree(rd_buf); 2369 return r; /* r = -EFAULT */ 2370 } 2371 2372 buf += 1; 2373 size -= 1; 2374 *pos += 1; 2375 result += 1; 2376 } 2377 2378 kfree(rd_buf); 2379 return result; 2380 } 2381 2382 /* function: read DSC slice bpg offset on the connector 2383 * 2384 * The read function: dp_dsc_slice_bpg_offset_read 2385 * returns dsc bpg slice offset set in the current configuration 2386 * The value is calculated automatically by DSC code 2387 * and depends on slice parameters and bpp target rate 2388 * The return is an integer: 0 or other positive integer 2389 * If 0 then DSC is disabled. 2390 * 2391 * Access it with the following command: 2392 * 2393 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2394 * 2395 * 0 - means that DSC is disabled 2396 */ 2397 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2398 size_t size, loff_t *pos) 2399 { 2400 char *rd_buf = NULL; 2401 char *rd_buf_ptr = NULL; 2402 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2403 struct display_stream_compressor *dsc; 2404 struct dcn_dsc_state dsc_state = {0}; 2405 const uint32_t rd_buf_size = 100; 2406 struct pipe_ctx *pipe_ctx; 2407 ssize_t result = 0; 2408 int i, r, str_len = 30; 2409 2410 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2411 2412 if (!rd_buf) 2413 return -ENOMEM; 2414 2415 rd_buf_ptr = rd_buf; 2416 2417 for (i = 0; i < MAX_PIPES; i++) { 2418 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2419 if (pipe_ctx->stream && 2420 pipe_ctx->stream->link == aconnector->dc_link) 2421 break; 2422 } 2423 2424 dsc = pipe_ctx->stream_res.dsc; 2425 if (dsc) 2426 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2427 2428 snprintf(rd_buf_ptr, str_len, 2429 "%d\n", 2430 dsc_state.dsc_slice_bpg_offset); 2431 rd_buf_ptr += str_len; 2432 2433 while (size) { 2434 if (*pos >= rd_buf_size) 2435 break; 2436 2437 r = put_user(*(rd_buf + result), buf); 2438 if (r) { 2439 kfree(rd_buf); 2440 return r; /* r = -EFAULT */ 2441 } 2442 2443 buf += 1; 2444 size -= 1; 2445 *pos += 1; 2446 result += 1; 2447 } 2448 2449 kfree(rd_buf); 2450 return result; 2451 } 2452 2453 2454 /* 2455 * function description: Read max_requested_bpc property from the connector 2456 * 2457 * Access it with the following command: 2458 * 2459 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2460 * 2461 */ 2462 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2463 size_t size, loff_t *pos) 2464 { 2465 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2466 struct drm_connector *connector = &aconnector->base; 2467 struct drm_device *dev = connector->dev; 2468 struct dm_connector_state *state; 2469 ssize_t result = 0; 2470 char *rd_buf = NULL; 2471 char *rd_buf_ptr = NULL; 2472 const uint32_t rd_buf_size = 10; 2473 int r; 2474 2475 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2476 2477 if (!rd_buf) 2478 return -ENOMEM; 2479 2480 mutex_lock(&dev->mode_config.mutex); 2481 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2482 2483 if (connector->state == NULL) 2484 goto unlock; 2485 2486 state = to_dm_connector_state(connector->state); 2487 2488 rd_buf_ptr = rd_buf; 2489 snprintf(rd_buf_ptr, rd_buf_size, 2490 "%u\n", 2491 state->base.max_requested_bpc); 2492 2493 while (size) { 2494 if (*pos >= rd_buf_size) 2495 break; 2496 2497 r = put_user(*(rd_buf + result), buf); 2498 if (r) { 2499 result = r; /* r = -EFAULT */ 2500 goto unlock; 2501 } 2502 buf += 1; 2503 size -= 1; 2504 *pos += 1; 2505 result += 1; 2506 } 2507 unlock: 2508 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2509 mutex_unlock(&dev->mode_config.mutex); 2510 kfree(rd_buf); 2511 return result; 2512 } 2513 2514 2515 /* 2516 * function description: Set max_requested_bpc property on the connector 2517 * 2518 * This function will not force the input BPC on connector, it will only 2519 * change the max value. This is equivalent to setting max_bpc through 2520 * xrandr. 2521 * 2522 * The BPC value written must be >= 6 and <= 16. Values outside of this 2523 * range will result in errors. 2524 * 2525 * BPC values: 2526 * 0x6 - 6 BPC 2527 * 0x8 - 8 BPC 2528 * 0xa - 10 BPC 2529 * 0xc - 12 BPC 2530 * 0x10 - 16 BPC 2531 * 2532 * Write the max_bpc in the following way: 2533 * 2534 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2535 * 2536 */ 2537 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2538 size_t size, loff_t *pos) 2539 { 2540 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2541 struct drm_connector *connector = &aconnector->base; 2542 struct dm_connector_state *state; 2543 struct drm_device *dev = connector->dev; 2544 char *wr_buf = NULL; 2545 uint32_t wr_buf_size = 42; 2546 int max_param_num = 1; 2547 long param[1] = {0}; 2548 uint8_t param_nums = 0; 2549 2550 if (size == 0) 2551 return -EINVAL; 2552 2553 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2554 2555 if (!wr_buf) { 2556 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2557 return -ENOSPC; 2558 } 2559 2560 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2561 (long *)param, buf, 2562 max_param_num, 2563 ¶m_nums)) { 2564 kfree(wr_buf); 2565 return -EINVAL; 2566 } 2567 2568 if (param_nums <= 0) { 2569 DRM_DEBUG_DRIVER("user data not be read\n"); 2570 kfree(wr_buf); 2571 return -EINVAL; 2572 } 2573 2574 if (param[0] < 6 || param[0] > 16) { 2575 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2576 kfree(wr_buf); 2577 return -EINVAL; 2578 } 2579 2580 mutex_lock(&dev->mode_config.mutex); 2581 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2582 2583 if (connector->state == NULL) 2584 goto unlock; 2585 2586 state = to_dm_connector_state(connector->state); 2587 state->base.max_requested_bpc = param[0]; 2588 unlock: 2589 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2590 mutex_unlock(&dev->mode_config.mutex); 2591 2592 kfree(wr_buf); 2593 return size; 2594 } 2595 2596 /* 2597 * Backlight at this moment. Read only. 2598 * As written to display, taking ABM and backlight lut into account. 2599 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2600 * 2601 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2602 */ 2603 static int current_backlight_show(struct seq_file *m, void *unused) 2604 { 2605 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2606 struct dc_link *link = aconnector->dc_link; 2607 unsigned int backlight; 2608 2609 backlight = dc_link_get_backlight_level(link); 2610 seq_printf(m, "0x%x\n", backlight); 2611 2612 return 0; 2613 } 2614 2615 /* 2616 * Backlight value that is being approached. Read only. 2617 * As written to display, taking ABM and backlight lut into account. 2618 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2619 * 2620 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2621 */ 2622 static int target_backlight_show(struct seq_file *m, void *unused) 2623 { 2624 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2625 struct dc_link *link = aconnector->dc_link; 2626 unsigned int backlight; 2627 2628 backlight = dc_link_get_target_backlight_pwm(link); 2629 seq_printf(m, "0x%x\n", backlight); 2630 2631 return 0; 2632 } 2633 2634 /* 2635 * function description: Determine if the connector is mst connector 2636 * 2637 * This function helps to determine whether a connector is a mst connector. 2638 * - "root" stands for the root connector of the topology 2639 * - "branch" stands for branch device of the topology 2640 * - "end" stands for leaf node connector of the topology 2641 * - "no" stands for the connector is not a device of a mst topology 2642 * Access it with the following command: 2643 * 2644 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2645 * 2646 */ 2647 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2648 { 2649 struct drm_connector *connector = m->private; 2650 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2651 struct drm_dp_mst_topology_mgr *mgr = NULL; 2652 struct drm_dp_mst_port *port = NULL; 2653 char *role = NULL; 2654 2655 mutex_lock(&aconnector->hpd_lock); 2656 2657 if (aconnector->mst_mgr.mst_state) { 2658 role = "root"; 2659 } else if (aconnector->mst_root && 2660 aconnector->mst_root->mst_mgr.mst_state) { 2661 2662 role = "end"; 2663 2664 mgr = &aconnector->mst_root->mst_mgr; 2665 port = aconnector->mst_output_port; 2666 2667 drm_modeset_lock(&mgr->base.lock, NULL); 2668 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2669 port->mcs) 2670 role = "branch"; 2671 drm_modeset_unlock(&mgr->base.lock); 2672 2673 } else { 2674 role = "no"; 2675 } 2676 2677 seq_printf(m, "%s\n", role); 2678 2679 mutex_unlock(&aconnector->hpd_lock); 2680 2681 return 0; 2682 } 2683 2684 /* 2685 * function description: Read out the mst progress status 2686 * 2687 * This function helps to determine the mst progress status of 2688 * a mst connector. 2689 * 2690 * Access it with the following command: 2691 * 2692 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2693 * 2694 */ 2695 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2696 { 2697 struct drm_connector *connector = m->private; 2698 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2699 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2700 int i; 2701 2702 mutex_lock(&aconnector->hpd_lock); 2703 mutex_lock(&adev->dm.dc_lock); 2704 2705 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2706 seq_puts(m, "disabled\n"); 2707 } else { 2708 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2709 seq_printf(m, "%s:%s\n", 2710 mst_progress_status[i], 2711 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2712 } 2713 2714 mutex_unlock(&adev->dm.dc_lock); 2715 mutex_unlock(&aconnector->hpd_lock); 2716 2717 return 0; 2718 } 2719 2720 /* 2721 * Reports whether the connected display is a USB4 DPIA tunneled display 2722 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2723 */ 2724 static int is_dpia_link_show(struct seq_file *m, void *data) 2725 { 2726 struct drm_connector *connector = m->private; 2727 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2728 struct dc_link *link = aconnector->dc_link; 2729 2730 if (connector->status != connector_status_connected) 2731 return -ENODEV; 2732 2733 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2734 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2735 2736 return 0; 2737 } 2738 2739 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2740 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2741 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2742 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2743 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2744 DEFINE_SHOW_ATTRIBUTE(internal_display); 2745 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); 2746 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2747 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2748 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2749 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2750 2751 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2752 .owner = THIS_MODULE, 2753 .read = dp_dsc_clock_en_read, 2754 .write = dp_dsc_clock_en_write, 2755 .llseek = default_llseek 2756 }; 2757 2758 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2759 .owner = THIS_MODULE, 2760 .read = dp_dsc_slice_width_read, 2761 .write = dp_dsc_slice_width_write, 2762 .llseek = default_llseek 2763 }; 2764 2765 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2766 .owner = THIS_MODULE, 2767 .read = dp_dsc_slice_height_read, 2768 .write = dp_dsc_slice_height_write, 2769 .llseek = default_llseek 2770 }; 2771 2772 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2773 .owner = THIS_MODULE, 2774 .read = dp_dsc_bits_per_pixel_read, 2775 .write = dp_dsc_bits_per_pixel_write, 2776 .llseek = default_llseek 2777 }; 2778 2779 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2780 .owner = THIS_MODULE, 2781 .read = dp_dsc_pic_width_read, 2782 .llseek = default_llseek 2783 }; 2784 2785 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2786 .owner = THIS_MODULE, 2787 .read = dp_dsc_pic_height_read, 2788 .llseek = default_llseek 2789 }; 2790 2791 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2792 .owner = THIS_MODULE, 2793 .read = dp_dsc_chunk_size_read, 2794 .llseek = default_llseek 2795 }; 2796 2797 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2798 .owner = THIS_MODULE, 2799 .read = dp_dsc_slice_bpg_offset_read, 2800 .llseek = default_llseek 2801 }; 2802 2803 static const struct file_operations trigger_hotplug_debugfs_fops = { 2804 .owner = THIS_MODULE, 2805 .write = trigger_hotplug, 2806 .llseek = default_llseek 2807 }; 2808 2809 static const struct file_operations dp_link_settings_debugfs_fops = { 2810 .owner = THIS_MODULE, 2811 .read = dp_link_settings_read, 2812 .write = dp_link_settings_write, 2813 .llseek = default_llseek 2814 }; 2815 2816 static const struct file_operations dp_phy_settings_debugfs_fop = { 2817 .owner = THIS_MODULE, 2818 .read = dp_phy_settings_read, 2819 .write = dp_phy_settings_write, 2820 .llseek = default_llseek 2821 }; 2822 2823 static const struct file_operations dp_phy_test_pattern_fops = { 2824 .owner = THIS_MODULE, 2825 .write = dp_phy_test_pattern_debugfs_write, 2826 .llseek = default_llseek 2827 }; 2828 2829 static const struct file_operations sdp_message_fops = { 2830 .owner = THIS_MODULE, 2831 .write = dp_sdp_message_debugfs_write, 2832 .llseek = default_llseek 2833 }; 2834 2835 static const struct file_operations dp_max_bpc_debugfs_fops = { 2836 .owner = THIS_MODULE, 2837 .read = dp_max_bpc_read, 2838 .write = dp_max_bpc_write, 2839 .llseek = default_llseek 2840 }; 2841 2842 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2843 .owner = THIS_MODULE, 2844 .write = dp_dsc_passthrough_set, 2845 .llseek = default_llseek 2846 }; 2847 2848 static const struct file_operations dp_mst_link_settings_debugfs_fops = { 2849 .owner = THIS_MODULE, 2850 .write = dp_mst_link_setting, 2851 .llseek = default_llseek 2852 }; 2853 2854 static const struct { 2855 char *name; 2856 const struct file_operations *fops; 2857 } dp_debugfs_entries[] = { 2858 {"link_settings", &dp_link_settings_debugfs_fops}, 2859 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2860 {"lttpr_status", &dp_lttpr_status_fops}, 2861 {"test_pattern", &dp_phy_test_pattern_fops}, 2862 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2863 {"sdp_message", &sdp_message_fops}, 2864 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2865 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2866 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2867 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2868 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2869 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2870 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2871 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2872 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2873 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2874 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2875 {"is_mst_connector", &dp_is_mst_connector_fops}, 2876 {"mst_progress_status", &dp_mst_progress_status_fops}, 2877 {"is_dpia_link", &is_dpia_link_fops}, 2878 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} 2879 }; 2880 2881 static const struct { 2882 char *name; 2883 const struct file_operations *fops; 2884 } hdmi_debugfs_entries[] = { 2885 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2886 }; 2887 2888 /* 2889 * Force YUV420 output if available from the given mode 2890 */ 2891 static int force_yuv420_output_set(void *data, u64 val) 2892 { 2893 struct amdgpu_dm_connector *connector = data; 2894 2895 connector->force_yuv420_output = (bool)val; 2896 2897 return 0; 2898 } 2899 2900 /* 2901 * Check if YUV420 is forced when available from the given mode 2902 */ 2903 static int force_yuv420_output_get(void *data, u64 *val) 2904 { 2905 struct amdgpu_dm_connector *connector = data; 2906 2907 *val = connector->force_yuv420_output; 2908 2909 return 0; 2910 } 2911 2912 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2913 force_yuv420_output_set, "%llu\n"); 2914 2915 /* 2916 * Read PSR state 2917 */ 2918 static int psr_get(void *data, u64 *val) 2919 { 2920 struct amdgpu_dm_connector *connector = data; 2921 struct dc_link *link = connector->dc_link; 2922 enum dc_psr_state state = PSR_STATE0; 2923 2924 dc_link_get_psr_state(link, &state); 2925 2926 *val = state; 2927 2928 return 0; 2929 } 2930 2931 /* 2932 * Read PSR state residency 2933 */ 2934 static int psr_read_residency(void *data, u64 *val) 2935 { 2936 struct amdgpu_dm_connector *connector = data; 2937 struct dc_link *link = connector->dc_link; 2938 u32 residency; 2939 2940 link->dc->link_srv->edp_get_psr_residency(link, &residency); 2941 2942 *val = (u64)residency; 2943 2944 return 0; 2945 } 2946 2947 /* read allow_edp_hotplug_detection */ 2948 static int allow_edp_hotplug_detection_get(void *data, u64 *val) 2949 { 2950 struct amdgpu_dm_connector *aconnector = data; 2951 struct drm_connector *connector = &aconnector->base; 2952 struct drm_device *dev = connector->dev; 2953 struct amdgpu_device *adev = drm_to_adev(dev); 2954 2955 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 2956 2957 return 0; 2958 } 2959 2960 /* set allow_edp_hotplug_detection */ 2961 static int allow_edp_hotplug_detection_set(void *data, u64 val) 2962 { 2963 struct amdgpu_dm_connector *aconnector = data; 2964 struct drm_connector *connector = &aconnector->base; 2965 struct drm_device *dev = connector->dev; 2966 struct amdgpu_device *adev = drm_to_adev(dev); 2967 2968 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 2969 2970 return 0; 2971 } 2972 2973 /* 2974 * Set dmcub trace event IRQ enable or disable. 2975 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2976 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2977 */ 2978 static int dmcub_trace_event_state_set(void *data, u64 val) 2979 { 2980 struct amdgpu_device *adev = data; 2981 2982 if (val == 1 || val == 0) { 2983 dc_dmub_trace_event_control(adev->dm.dc, val); 2984 adev->dm.dmcub_trace_event_en = (bool)val; 2985 } else 2986 return 0; 2987 2988 return 0; 2989 } 2990 2991 /* 2992 * The interface doesn't need get function, so it will return the 2993 * value of zero 2994 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2995 */ 2996 static int dmcub_trace_event_state_get(void *data, u64 *val) 2997 { 2998 struct amdgpu_device *adev = data; 2999 3000 *val = adev->dm.dmcub_trace_event_en; 3001 return 0; 3002 } 3003 3004 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 3005 dmcub_trace_event_state_set, "%llu\n"); 3006 3007 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 3008 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 3009 "%llu\n"); 3010 3011 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 3012 allow_edp_hotplug_detection_get, 3013 allow_edp_hotplug_detection_set, "%llu\n"); 3014 3015 DEFINE_SHOW_ATTRIBUTE(current_backlight); 3016 DEFINE_SHOW_ATTRIBUTE(target_backlight); 3017 3018 static const struct { 3019 char *name; 3020 const struct file_operations *fops; 3021 } connector_debugfs_entries[] = { 3022 {"force_yuv420_output", &force_yuv420_output_fops}, 3023 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 3024 {"internal_display", &internal_display_fops}, 3025 {"odm_combine_segments", &odm_combine_segments_fops} 3026 }; 3027 3028 /* 3029 * Returns supported customized link rates by this eDP panel. 3030 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3031 */ 3032 static int edp_ilr_show(struct seq_file *m, void *unused) 3033 { 3034 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 3035 struct dc_link *link = aconnector->dc_link; 3036 uint8_t supported_link_rates[16]; 3037 uint32_t link_rate_in_khz; 3038 uint32_t entry = 0; 3039 uint8_t dpcd_rev; 3040 3041 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 3042 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3043 supported_link_rates, sizeof(supported_link_rates)); 3044 3045 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3046 3047 if (dpcd_rev >= DP_DPCD_REV_13 && 3048 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 3049 3050 for (entry = 0; entry < 16; entry += 2) { 3051 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 3052 supported_link_rates[entry]) * 200; 3053 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 3054 } 3055 } else { 3056 seq_puts(m, "ILR is not supported by this eDP panel.\n"); 3057 } 3058 3059 return 0; 3060 } 3061 3062 /* 3063 * Set supported customized link rate to eDP panel. 3064 * 3065 * echo <lane_count> <link_rate option> > ilr_setting 3066 * 3067 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 3068 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3069 * to set 4 lanes and 2.16 GHz 3070 */ 3071 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 3072 size_t size, loff_t *pos) 3073 { 3074 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 3075 struct dc_link *link = connector->dc_link; 3076 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3077 struct dc *dc = (struct dc *)link->dc; 3078 struct dc_link_settings prefer_link_settings; 3079 char *wr_buf = NULL; 3080 const uint32_t wr_buf_size = 40; 3081 /* 0: lane_count; 1: link_rate */ 3082 int max_param_num = 2; 3083 uint8_t param_nums = 0; 3084 long param[2]; 3085 bool valid_input = true; 3086 3087 if (size == 0) 3088 return -EINVAL; 3089 3090 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 3091 if (!wr_buf) 3092 return -ENOMEM; 3093 3094 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 3095 (long *)param, buf, 3096 max_param_num, 3097 ¶m_nums)) { 3098 kfree(wr_buf); 3099 return -EINVAL; 3100 } 3101 3102 if (param_nums <= 0) { 3103 kfree(wr_buf); 3104 return -EINVAL; 3105 } 3106 3107 switch (param[0]) { 3108 case LANE_COUNT_ONE: 3109 case LANE_COUNT_TWO: 3110 case LANE_COUNT_FOUR: 3111 break; 3112 default: 3113 valid_input = false; 3114 break; 3115 } 3116 3117 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 3118 valid_input = false; 3119 3120 if (!valid_input) { 3121 kfree(wr_buf); 3122 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 3123 prefer_link_settings.use_link_rate_set = false; 3124 mutex_lock(&adev->dm.dc_lock); 3125 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 3126 mutex_unlock(&adev->dm.dc_lock); 3127 return size; 3128 } 3129 3130 /* save user force lane_count, link_rate to preferred settings 3131 * spread spectrum will not be changed 3132 */ 3133 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3134 prefer_link_settings.lane_count = param[0]; 3135 prefer_link_settings.use_link_rate_set = true; 3136 prefer_link_settings.link_rate_set = param[1]; 3137 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3138 3139 mutex_lock(&adev->dm.dc_lock); 3140 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3141 NULL, link, false); 3142 mutex_unlock(&adev->dm.dc_lock); 3143 3144 kfree(wr_buf); 3145 return size; 3146 } 3147 3148 static int edp_ilr_open(struct inode *inode, struct file *file) 3149 { 3150 return single_open(file, edp_ilr_show, inode->i_private); 3151 } 3152 3153 static const struct file_operations edp_ilr_debugfs_fops = { 3154 .owner = THIS_MODULE, 3155 .open = edp_ilr_open, 3156 .read = seq_read, 3157 .llseek = seq_lseek, 3158 .release = single_release, 3159 .write = edp_ilr_write 3160 }; 3161 3162 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3163 { 3164 int i; 3165 struct dentry *dir = connector->base.debugfs_entry; 3166 3167 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3168 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3169 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3170 debugfs_create_file(dp_debugfs_entries[i].name, 3171 0644, dir, connector, 3172 dp_debugfs_entries[i].fops); 3173 } 3174 } 3175 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3176 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3177 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3178 debugfs_create_file_unsafe("psr_residency", 0444, dir, 3179 connector, &psr_residency_fops); 3180 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3181 ¤t_backlight_fops); 3182 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3183 &target_backlight_fops); 3184 debugfs_create_file("ilr_setting", 0644, dir, connector, 3185 &edp_ilr_debugfs_fops); 3186 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3187 &allow_edp_hotplug_detection_fops); 3188 } 3189 3190 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3191 debugfs_create_file(connector_debugfs_entries[i].name, 3192 0644, dir, connector, 3193 connector_debugfs_entries[i].fops); 3194 } 3195 3196 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3197 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3198 debugfs_create_file(hdmi_debugfs_entries[i].name, 3199 0644, dir, connector, 3200 hdmi_debugfs_entries[i].fops); 3201 } 3202 } 3203 } 3204 3205 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3206 /* 3207 * Set crc window coordinate x start 3208 */ 3209 static int crc_win_x_start_set(void *data, u64 val) 3210 { 3211 struct drm_crtc *crtc = data; 3212 struct drm_device *drm_dev = crtc->dev; 3213 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3214 3215 spin_lock_irq(&drm_dev->event_lock); 3216 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3217 acrtc->dm_irq_params.window_param.update_win = false; 3218 spin_unlock_irq(&drm_dev->event_lock); 3219 3220 return 0; 3221 } 3222 3223 /* 3224 * Get crc window coordinate x start 3225 */ 3226 static int crc_win_x_start_get(void *data, u64 *val) 3227 { 3228 struct drm_crtc *crtc = data; 3229 struct drm_device *drm_dev = crtc->dev; 3230 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3231 3232 spin_lock_irq(&drm_dev->event_lock); 3233 *val = acrtc->dm_irq_params.window_param.x_start; 3234 spin_unlock_irq(&drm_dev->event_lock); 3235 3236 return 0; 3237 } 3238 3239 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3240 crc_win_x_start_set, "%llu\n"); 3241 3242 3243 /* 3244 * Set crc window coordinate y start 3245 */ 3246 static int crc_win_y_start_set(void *data, u64 val) 3247 { 3248 struct drm_crtc *crtc = data; 3249 struct drm_device *drm_dev = crtc->dev; 3250 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3251 3252 spin_lock_irq(&drm_dev->event_lock); 3253 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3254 acrtc->dm_irq_params.window_param.update_win = false; 3255 spin_unlock_irq(&drm_dev->event_lock); 3256 3257 return 0; 3258 } 3259 3260 /* 3261 * Get crc window coordinate y start 3262 */ 3263 static int crc_win_y_start_get(void *data, u64 *val) 3264 { 3265 struct drm_crtc *crtc = data; 3266 struct drm_device *drm_dev = crtc->dev; 3267 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3268 3269 spin_lock_irq(&drm_dev->event_lock); 3270 *val = acrtc->dm_irq_params.window_param.y_start; 3271 spin_unlock_irq(&drm_dev->event_lock); 3272 3273 return 0; 3274 } 3275 3276 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3277 crc_win_y_start_set, "%llu\n"); 3278 3279 /* 3280 * Set crc window coordinate x end 3281 */ 3282 static int crc_win_x_end_set(void *data, u64 val) 3283 { 3284 struct drm_crtc *crtc = data; 3285 struct drm_device *drm_dev = crtc->dev; 3286 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3287 3288 spin_lock_irq(&drm_dev->event_lock); 3289 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3290 acrtc->dm_irq_params.window_param.update_win = false; 3291 spin_unlock_irq(&drm_dev->event_lock); 3292 3293 return 0; 3294 } 3295 3296 /* 3297 * Get crc window coordinate x end 3298 */ 3299 static int crc_win_x_end_get(void *data, u64 *val) 3300 { 3301 struct drm_crtc *crtc = data; 3302 struct drm_device *drm_dev = crtc->dev; 3303 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3304 3305 spin_lock_irq(&drm_dev->event_lock); 3306 *val = acrtc->dm_irq_params.window_param.x_end; 3307 spin_unlock_irq(&drm_dev->event_lock); 3308 3309 return 0; 3310 } 3311 3312 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3313 crc_win_x_end_set, "%llu\n"); 3314 3315 /* 3316 * Set crc window coordinate y end 3317 */ 3318 static int crc_win_y_end_set(void *data, u64 val) 3319 { 3320 struct drm_crtc *crtc = data; 3321 struct drm_device *drm_dev = crtc->dev; 3322 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3323 3324 spin_lock_irq(&drm_dev->event_lock); 3325 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3326 acrtc->dm_irq_params.window_param.update_win = false; 3327 spin_unlock_irq(&drm_dev->event_lock); 3328 3329 return 0; 3330 } 3331 3332 /* 3333 * Get crc window coordinate y end 3334 */ 3335 static int crc_win_y_end_get(void *data, u64 *val) 3336 { 3337 struct drm_crtc *crtc = data; 3338 struct drm_device *drm_dev = crtc->dev; 3339 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3340 3341 spin_lock_irq(&drm_dev->event_lock); 3342 *val = acrtc->dm_irq_params.window_param.y_end; 3343 spin_unlock_irq(&drm_dev->event_lock); 3344 3345 return 0; 3346 } 3347 3348 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3349 crc_win_y_end_set, "%llu\n"); 3350 /* 3351 * Trigger to commit crc window 3352 */ 3353 static int crc_win_update_set(void *data, u64 val) 3354 { 3355 struct drm_crtc *crtc = data; 3356 struct amdgpu_crtc *acrtc; 3357 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3358 3359 if (val) { 3360 acrtc = to_amdgpu_crtc(crtc); 3361 mutex_lock(&adev->dm.dc_lock); 3362 /* PSR may write to OTG CRC window control register, 3363 * so close it before starting secure_display. 3364 */ 3365 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3366 3367 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3368 3369 acrtc->dm_irq_params.window_param.activated = true; 3370 acrtc->dm_irq_params.window_param.update_win = true; 3371 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3372 3373 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3374 mutex_unlock(&adev->dm.dc_lock); 3375 } 3376 3377 return 0; 3378 } 3379 3380 /* 3381 * Get crc window update flag 3382 */ 3383 static int crc_win_update_get(void *data, u64 *val) 3384 { 3385 *val = 0; 3386 return 0; 3387 } 3388 3389 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3390 crc_win_update_set, "%llu\n"); 3391 #endif 3392 void crtc_debugfs_init(struct drm_crtc *crtc) 3393 { 3394 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3395 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3396 3397 if (!dir) 3398 return; 3399 3400 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3401 &crc_win_x_start_fops); 3402 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3403 &crc_win_y_start_fops); 3404 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3405 &crc_win_x_end_fops); 3406 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3407 &crc_win_y_end_fops); 3408 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3409 &crc_win_update_fops); 3410 dput(dir); 3411 #endif 3412 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3413 crtc, &amdgpu_current_bpc_fops); 3414 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 3415 crtc, &amdgpu_current_colorspace_fops); 3416 } 3417 3418 /* 3419 * Writes DTN log state to the user supplied buffer. 3420 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3421 */ 3422 static ssize_t dtn_log_read( 3423 struct file *f, 3424 char __user *buf, 3425 size_t size, 3426 loff_t *pos) 3427 { 3428 struct amdgpu_device *adev = file_inode(f)->i_private; 3429 struct dc *dc = adev->dm.dc; 3430 struct dc_log_buffer_ctx log_ctx = { 0 }; 3431 ssize_t result = 0; 3432 3433 if (!buf || !size) 3434 return -EINVAL; 3435 3436 if (!dc->hwss.log_hw_state) 3437 return 0; 3438 3439 dc->hwss.log_hw_state(dc, &log_ctx); 3440 3441 if (*pos < log_ctx.pos) { 3442 size_t to_copy = log_ctx.pos - *pos; 3443 3444 to_copy = min(to_copy, size); 3445 3446 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3447 *pos += to_copy; 3448 result = to_copy; 3449 } 3450 } 3451 3452 kfree(log_ctx.buf); 3453 3454 return result; 3455 } 3456 3457 /* 3458 * Writes DTN log state to dmesg when triggered via a write. 3459 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3460 */ 3461 static ssize_t dtn_log_write( 3462 struct file *f, 3463 const char __user *buf, 3464 size_t size, 3465 loff_t *pos) 3466 { 3467 struct amdgpu_device *adev = file_inode(f)->i_private; 3468 struct dc *dc = adev->dm.dc; 3469 3470 /* Write triggers log output via dmesg. */ 3471 if (size == 0) 3472 return 0; 3473 3474 if (dc->hwss.log_hw_state) 3475 dc->hwss.log_hw_state(dc, NULL); 3476 3477 return size; 3478 } 3479 3480 static int mst_topo_show(struct seq_file *m, void *unused) 3481 { 3482 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3483 struct drm_device *dev = adev_to_drm(adev); 3484 struct drm_connector *connector; 3485 struct drm_connector_list_iter conn_iter; 3486 struct amdgpu_dm_connector *aconnector; 3487 3488 drm_connector_list_iter_begin(dev, &conn_iter); 3489 drm_for_each_connector_iter(connector, &conn_iter) { 3490 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3491 continue; 3492 3493 aconnector = to_amdgpu_dm_connector(connector); 3494 3495 /* Ensure we're only dumping the topology of a root mst node */ 3496 if (!aconnector->mst_mgr.mst_state) 3497 continue; 3498 3499 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3500 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3501 } 3502 drm_connector_list_iter_end(&conn_iter); 3503 3504 return 0; 3505 } 3506 3507 /* 3508 * Sets trigger hpd for MST topologies. 3509 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3510 * All topologies will be disconnected if val of 0 is set . 3511 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3512 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3513 */ 3514 static int trigger_hpd_mst_set(void *data, u64 val) 3515 { 3516 struct amdgpu_device *adev = data; 3517 struct drm_device *dev = adev_to_drm(adev); 3518 struct drm_connector_list_iter iter; 3519 struct amdgpu_dm_connector *aconnector; 3520 struct drm_connector *connector; 3521 struct dc_link *link = NULL; 3522 3523 if (val == 1) { 3524 drm_connector_list_iter_begin(dev, &iter); 3525 drm_for_each_connector_iter(connector, &iter) { 3526 aconnector = to_amdgpu_dm_connector(connector); 3527 if (aconnector->dc_link->type == dc_connection_mst_branch && 3528 aconnector->mst_mgr.aux) { 3529 mutex_lock(&adev->dm.dc_lock); 3530 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3531 mutex_unlock(&adev->dm.dc_lock); 3532 3533 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3534 } 3535 } 3536 } else if (val == 0) { 3537 drm_connector_list_iter_begin(dev, &iter); 3538 drm_for_each_connector_iter(connector, &iter) { 3539 aconnector = to_amdgpu_dm_connector(connector); 3540 if (!aconnector->dc_link) 3541 continue; 3542 3543 if (!aconnector->mst_root) 3544 continue; 3545 3546 link = aconnector->dc_link; 3547 dc_link_dp_receiver_power_ctrl(link, false); 3548 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3549 link->mst_stream_alloc_table.stream_count = 0; 3550 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3551 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3552 } 3553 } else { 3554 return 0; 3555 } 3556 drm_kms_helper_hotplug_event(dev); 3557 3558 return 0; 3559 } 3560 3561 /* 3562 * The interface doesn't need get function, so it will return the 3563 * value of zero 3564 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3565 */ 3566 static int trigger_hpd_mst_get(void *data, u64 *val) 3567 { 3568 *val = 0; 3569 return 0; 3570 } 3571 3572 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3573 trigger_hpd_mst_set, "%llu\n"); 3574 3575 3576 /* 3577 * Sets the force_timing_sync debug option from the given string. 3578 * All connected displays will be force synchronized immediately. 3579 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3580 */ 3581 static int force_timing_sync_set(void *data, u64 val) 3582 { 3583 struct amdgpu_device *adev = data; 3584 3585 adev->dm.force_timing_sync = (bool)val; 3586 3587 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3588 3589 return 0; 3590 } 3591 3592 /* 3593 * Gets the force_timing_sync debug option value into the given buffer. 3594 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3595 */ 3596 static int force_timing_sync_get(void *data, u64 *val) 3597 { 3598 struct amdgpu_device *adev = data; 3599 3600 *val = adev->dm.force_timing_sync; 3601 3602 return 0; 3603 } 3604 3605 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3606 force_timing_sync_set, "%llu\n"); 3607 3608 3609 /* 3610 * Disables all HPD and HPD RX interrupt handling in the 3611 * driver when set to 1. Default is 0. 3612 */ 3613 static int disable_hpd_set(void *data, u64 val) 3614 { 3615 struct amdgpu_device *adev = data; 3616 3617 adev->dm.disable_hpd_irq = (bool)val; 3618 3619 return 0; 3620 } 3621 3622 3623 /* 3624 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3625 * 0 otherwise. 3626 */ 3627 static int disable_hpd_get(void *data, u64 *val) 3628 { 3629 struct amdgpu_device *adev = data; 3630 3631 *val = adev->dm.disable_hpd_irq; 3632 3633 return 0; 3634 } 3635 3636 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3637 disable_hpd_set, "%llu\n"); 3638 3639 /* 3640 * Prints hardware capabilities. These are used for IGT testing. 3641 */ 3642 static int capabilities_show(struct seq_file *m, void *unused) 3643 { 3644 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3645 struct dc_caps caps = adev->dm.dc->caps; 3646 bool mall_supported = caps.mall_size_total; 3647 3648 seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no"); 3649 3650 return 0; 3651 } 3652 3653 DEFINE_SHOW_ATTRIBUTE(capabilities); 3654 3655 /* 3656 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3657 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3658 */ 3659 static int dp_force_sst_set(void *data, u64 val) 3660 { 3661 struct amdgpu_device *adev = data; 3662 3663 adev->dm.dc->debug.set_mst_en_for_sst = val; 3664 3665 return 0; 3666 } 3667 3668 static int dp_force_sst_get(void *data, u64 *val) 3669 { 3670 struct amdgpu_device *adev = data; 3671 3672 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3673 3674 return 0; 3675 } 3676 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3677 dp_force_sst_set, "%llu\n"); 3678 3679 /* 3680 * Force DP2 sequence without VESA certified cable. 3681 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3682 */ 3683 static int dp_ignore_cable_id_set(void *data, u64 val) 3684 { 3685 struct amdgpu_device *adev = data; 3686 3687 adev->dm.dc->debug.ignore_cable_id = val; 3688 3689 return 0; 3690 } 3691 3692 static int dp_ignore_cable_id_get(void *data, u64 *val) 3693 { 3694 struct amdgpu_device *adev = data; 3695 3696 *val = adev->dm.dc->debug.ignore_cable_id; 3697 3698 return 0; 3699 } 3700 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3701 dp_ignore_cable_id_set, "%llu\n"); 3702 3703 /* 3704 * Sets the DC visual confirm debug option from the given string. 3705 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3706 */ 3707 static int visual_confirm_set(void *data, u64 val) 3708 { 3709 struct amdgpu_device *adev = data; 3710 3711 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3712 3713 return 0; 3714 } 3715 3716 /* 3717 * Reads the DC visual confirm debug option value into the given buffer. 3718 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3719 */ 3720 static int visual_confirm_get(void *data, u64 *val) 3721 { 3722 struct amdgpu_device *adev = data; 3723 3724 *val = adev->dm.dc->debug.visual_confirm; 3725 3726 return 0; 3727 } 3728 3729 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3730 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3731 visual_confirm_set, "%llu\n"); 3732 3733 3734 /* 3735 * Sets the DC skip_detection_link_training debug option from the given string. 3736 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3737 */ 3738 static int skip_detection_link_training_set(void *data, u64 val) 3739 { 3740 struct amdgpu_device *adev = data; 3741 3742 if (val == 0) 3743 adev->dm.dc->debug.skip_detection_link_training = false; 3744 else 3745 adev->dm.dc->debug.skip_detection_link_training = true; 3746 3747 return 0; 3748 } 3749 3750 /* 3751 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3752 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3753 */ 3754 static int skip_detection_link_training_get(void *data, u64 *val) 3755 { 3756 struct amdgpu_device *adev = data; 3757 3758 *val = adev->dm.dc->debug.skip_detection_link_training; 3759 3760 return 0; 3761 } 3762 3763 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3764 skip_detection_link_training_get, 3765 skip_detection_link_training_set, "%llu\n"); 3766 3767 /* 3768 * Dumps the DCC_EN bit for each pipe. 3769 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3770 */ 3771 static ssize_t dcc_en_bits_read( 3772 struct file *f, 3773 char __user *buf, 3774 size_t size, 3775 loff_t *pos) 3776 { 3777 struct amdgpu_device *adev = file_inode(f)->i_private; 3778 struct dc *dc = adev->dm.dc; 3779 char *rd_buf = NULL; 3780 const uint32_t rd_buf_size = 32; 3781 uint32_t result = 0; 3782 int offset = 0; 3783 int num_pipes = dc->res_pool->pipe_count; 3784 int *dcc_en_bits; 3785 int i, r; 3786 3787 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3788 if (!dcc_en_bits) 3789 return -ENOMEM; 3790 3791 if (!dc->hwss.get_dcc_en_bits) { 3792 kfree(dcc_en_bits); 3793 return 0; 3794 } 3795 3796 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3797 3798 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3799 if (!rd_buf) { 3800 kfree(dcc_en_bits); 3801 return -ENOMEM; 3802 } 3803 3804 for (i = 0; i < num_pipes; i++) 3805 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3806 "%d ", dcc_en_bits[i]); 3807 rd_buf[strlen(rd_buf)] = '\n'; 3808 3809 kfree(dcc_en_bits); 3810 3811 while (size) { 3812 if (*pos >= rd_buf_size) 3813 break; 3814 r = put_user(*(rd_buf + result), buf); 3815 if (r) { 3816 kfree(rd_buf); 3817 return r; /* r = -EFAULT */ 3818 } 3819 buf += 1; 3820 size -= 1; 3821 *pos += 1; 3822 result += 1; 3823 } 3824 3825 kfree(rd_buf); 3826 return result; 3827 } 3828 3829 void dtn_debugfs_init(struct amdgpu_device *adev) 3830 { 3831 static const struct file_operations dtn_log_fops = { 3832 .owner = THIS_MODULE, 3833 .read = dtn_log_read, 3834 .write = dtn_log_write, 3835 .llseek = default_llseek 3836 }; 3837 static const struct file_operations dcc_en_bits_fops = { 3838 .owner = THIS_MODULE, 3839 .read = dcc_en_bits_read, 3840 .llseek = default_llseek 3841 }; 3842 3843 struct drm_minor *minor = adev_to_drm(adev)->primary; 3844 struct dentry *root = minor->debugfs_root; 3845 3846 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3847 adev, &mst_topo_fops); 3848 debugfs_create_file("amdgpu_dm_capabilities", 0444, root, 3849 adev, &capabilities_fops); 3850 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3851 &dtn_log_fops); 3852 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3853 &dp_set_mst_en_for_sst_ops); 3854 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3855 &dp_ignore_cable_id_ops); 3856 3857 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3858 &visual_confirm_fops); 3859 3860 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3861 &skip_detection_link_training_fops); 3862 3863 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3864 adev, &dmub_tracebuffer_fops); 3865 3866 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3867 adev, &dmub_fw_state_fops); 3868 3869 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3870 adev, &force_timing_sync_ops); 3871 3872 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3873 adev, &dmcub_trace_event_state_fops); 3874 3875 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3876 adev, &trigger_hpd_mst_ops); 3877 3878 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3879 &dcc_en_bits_fops); 3880 3881 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3882 &disable_hpd_ops); 3883 3884 } 3885