1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "link_hwss.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "link/protocols/link_dp_capability.h" 40 41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42 #include "amdgpu_dm_psr.h" 43 #endif 44 45 struct dmub_debugfs_trace_header { 46 uint32_t entry_count; 47 uint32_t reserved[3]; 48 }; 49 50 struct dmub_debugfs_trace_entry { 51 uint32_t trace_code; 52 uint32_t tick_count; 53 uint32_t param0; 54 uint32_t param1; 55 }; 56 57 static const char *const mst_progress_status[] = { 58 "probe", 59 "remote_edid", 60 "allocate_new_payload", 61 "clear_allocated_payload", 62 }; 63 64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 65 * 66 * Function takes in attributes passed to debugfs write entry 67 * and writes into param array. 68 * The user passes max_param_num to identify maximum number of 69 * parameters that could be parsed. 70 * 71 */ 72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 73 long *param, const char __user *buf, 74 int max_param_num, 75 uint8_t *param_nums) 76 { 77 char *wr_buf_ptr = NULL; 78 uint32_t wr_buf_count = 0; 79 int r; 80 char *sub_str = NULL; 81 const char delimiter[3] = {' ', '\n', '\0'}; 82 uint8_t param_index = 0; 83 84 *param_nums = 0; 85 86 wr_buf_ptr = wr_buf; 87 88 /* r is bytes not be copied */ 89 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 90 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 91 return -EFAULT; 92 } 93 94 /* check number of parameters. isspace could not differ space and \n */ 95 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 96 /* skip space*/ 97 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 98 wr_buf_ptr++; 99 wr_buf_count++; 100 } 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 105 /* skip non-space*/ 106 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 107 wr_buf_ptr++; 108 wr_buf_count++; 109 } 110 111 (*param_nums)++; 112 113 if (wr_buf_count == wr_buf_size) 114 break; 115 } 116 117 if (*param_nums > max_param_num) 118 *param_nums = max_param_num; 119 120 wr_buf_ptr = wr_buf; /* reset buf pointer */ 121 wr_buf_count = 0; /* number of char already checked */ 122 123 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 124 wr_buf_ptr++; 125 wr_buf_count++; 126 } 127 128 while (param_index < *param_nums) { 129 /* after strsep, wr_buf_ptr will be moved to after space */ 130 sub_str = strsep(&wr_buf_ptr, delimiter); 131 132 r = kstrtol(sub_str, 16, &(param[param_index])); 133 134 if (r) 135 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 136 137 param_index++; 138 } 139 140 return 0; 141 } 142 143 /* function description 144 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 145 * 146 * valid lane count value: 1, 2, 4 147 * valid link rate value: 148 * 06h = 1.62Gbps per lane 149 * 0Ah = 2.7Gbps per lane 150 * 0Ch = 3.24Gbps per lane 151 * 14h = 5.4Gbps per lane 152 * 1Eh = 8.1Gbps per lane 153 * 154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * --- to get dp configuration 157 * 158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 159 * 160 * It will list current, verified, reported, preferred dp configuration. 161 * current -- for current video mode 162 * verified --- maximum configuration which pass link training 163 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 164 * preferred --- user force settings 165 * 166 * --- set (or force) dp configuration 167 * 168 * echo <lane_count> <link_rate> > link_settings 169 * 170 * for example, to force to 2 lane, 2.7GHz, 171 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 172 * 173 * spread_spectrum could not be changed dynamically. 174 * 175 * in case invalid lane count, link rate are force, no hw programming will be 176 * done. please check link settings after force operation to see if HW get 177 * programming. 178 * 179 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 180 * 181 * check current and preferred settings. 182 * 183 */ 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 185 size_t size, loff_t *pos) 186 { 187 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 188 struct dc_link *link = connector->dc_link; 189 char *rd_buf = NULL; 190 char *rd_buf_ptr = NULL; 191 const uint32_t rd_buf_size = 100; 192 uint32_t result = 0; 193 uint8_t str_len = 0; 194 int r; 195 196 if (*pos & 3 || size & 3) 197 return -EINVAL; 198 199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 200 if (!rd_buf) 201 return 0; 202 203 rd_buf_ptr = rd_buf; 204 205 str_len = strlen("Current: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 207 link->cur_link_settings.lane_count, 208 link->cur_link_settings.link_rate, 209 link->cur_link_settings.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Verified: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 214 link->verified_link_cap.lane_count, 215 link->verified_link_cap.link_rate, 216 link->verified_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Reported: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 221 link->reported_link_cap.lane_count, 222 link->reported_link_cap.link_rate, 223 link->reported_link_cap.link_spread); 224 rd_buf_ptr += str_len; 225 226 str_len = strlen("Preferred: %d 0x%x %d "); 227 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 228 link->preferred_link_setting.lane_count, 229 link->preferred_link_setting.link_rate, 230 link->preferred_link_setting.link_spread); 231 232 while (size) { 233 if (*pos >= rd_buf_size) 234 break; 235 236 r = put_user(*(rd_buf + result), buf); 237 if (r) { 238 kfree(rd_buf); 239 return r; /* r = -EFAULT */ 240 } 241 242 buf += 1; 243 size -= 1; 244 *pos += 1; 245 result += 1; 246 } 247 248 kfree(rd_buf); 249 return result; 250 } 251 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 253 size_t size, loff_t *pos) 254 { 255 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 256 struct dc_link *link = connector->dc_link; 257 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 258 struct dc *dc = (struct dc *)link->dc; 259 struct dc_link_settings prefer_link_settings; 260 char *wr_buf = NULL; 261 const uint32_t wr_buf_size = 40; 262 /* 0: lane_count; 1: link_rate */ 263 int max_param_num = 2; 264 uint8_t param_nums = 0; 265 long param[2]; 266 bool valid_input = true; 267 268 if (size == 0) 269 return -EINVAL; 270 271 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 272 if (!wr_buf) 273 return -ENOSPC; 274 275 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 276 (long *)param, buf, 277 max_param_num, 278 ¶m_nums)) { 279 kfree(wr_buf); 280 return -EINVAL; 281 } 282 283 if (param_nums <= 0) { 284 kfree(wr_buf); 285 DRM_DEBUG_DRIVER("user data not be read\n"); 286 return -EINVAL; 287 } 288 289 switch (param[0]) { 290 case LANE_COUNT_ONE: 291 case LANE_COUNT_TWO: 292 case LANE_COUNT_FOUR: 293 break; 294 default: 295 valid_input = false; 296 break; 297 } 298 299 switch (param[1]) { 300 case LINK_RATE_LOW: 301 case LINK_RATE_HIGH: 302 case LINK_RATE_RBR2: 303 case LINK_RATE_HIGH2: 304 case LINK_RATE_HIGH3: 305 case LINK_RATE_UHBR10: 306 case LINK_RATE_UHBR13_5: 307 case LINK_RATE_UHBR20: 308 break; 309 default: 310 valid_input = false; 311 break; 312 } 313 314 if (!valid_input) { 315 kfree(wr_buf); 316 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 317 mutex_lock(&adev->dm.dc_lock); 318 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 319 mutex_unlock(&adev->dm.dc_lock); 320 return size; 321 } 322 323 /* save user force lane_count, link_rate to preferred settings 324 * spread spectrum will not be changed 325 */ 326 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 327 prefer_link_settings.use_link_rate_set = false; 328 prefer_link_settings.lane_count = param[0]; 329 prefer_link_settings.link_rate = param[1]; 330 331 mutex_lock(&adev->dm.dc_lock); 332 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 333 mutex_unlock(&adev->dm.dc_lock); 334 335 kfree(wr_buf); 336 return size; 337 } 338 339 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 340 * post-cursor2 (defined by VESA DP specification) 341 * 342 * valid values 343 * voltage swing: 0,1,2,3 344 * pre-emphasis : 0,1,2,3 345 * post cursor2 : 0,1,2,3 346 * 347 * 348 * how to use this debugfs 349 * 350 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 351 * 352 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 353 * 354 * To figure out which DP-x is the display for DP to be check, 355 * cd DP-x 356 * ls -ll 357 * There should be debugfs file, like link_settings, phy_settings. 358 * cat link_settings 359 * from lane_count, link_rate to figure which DP-x is for display to be worked 360 * on 361 * 362 * To get current DP PHY settings, 363 * cat phy_settings 364 * 365 * To change DP PHY settings, 366 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 367 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 368 * 0, 369 * echo 2 3 0 > phy_settings 370 * 371 * To check if change be applied, get current phy settings by 372 * cat phy_settings 373 * 374 * In case invalid values are set by user, like 375 * echo 1 4 0 > phy_settings 376 * 377 * HW will NOT be programmed by these settings. 378 * cat phy_settings will show the previous valid settings. 379 */ 380 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 381 size_t size, loff_t *pos) 382 { 383 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 384 struct dc_link *link = connector->dc_link; 385 char *rd_buf = NULL; 386 const uint32_t rd_buf_size = 20; 387 uint32_t result = 0; 388 int r; 389 390 if (*pos & 3 || size & 3) 391 return -EINVAL; 392 393 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 394 if (!rd_buf) 395 return -EINVAL; 396 397 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 398 link->cur_lane_setting[0].VOLTAGE_SWING, 399 link->cur_lane_setting[0].PRE_EMPHASIS, 400 link->cur_lane_setting[0].POST_CURSOR2); 401 402 while (size) { 403 if (*pos >= rd_buf_size) 404 break; 405 406 r = put_user((*(rd_buf + result)), buf); 407 if (r) { 408 kfree(rd_buf); 409 return r; /* r = -EFAULT */ 410 } 411 412 buf += 1; 413 size -= 1; 414 *pos += 1; 415 result += 1; 416 } 417 418 kfree(rd_buf); 419 return result; 420 } 421 422 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 423 { 424 struct drm_connector *connector = m->private; 425 struct amdgpu_dm_connector *aconnector = 426 to_amdgpu_dm_connector(connector); 427 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 428 429 if (connector->status != connector_status_connected) 430 return -ENODEV; 431 432 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 433 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 434 caps.phy_repeater_cnt); 435 436 seq_puts(m, "phy repeater mode: "); 437 438 switch (caps.mode) { 439 case DP_PHY_REPEATER_MODE_TRANSPARENT: 440 seq_puts(m, "transparent"); 441 break; 442 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 443 seq_puts(m, "non-transparent"); 444 break; 445 case 0x00: 446 seq_puts(m, "non lttpr"); 447 break; 448 default: 449 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 450 break; 451 } 452 453 seq_puts(m, "\n"); 454 return 0; 455 } 456 457 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 458 size_t size, loff_t *pos) 459 { 460 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 461 struct dc_link *link = connector->dc_link; 462 struct dc *dc = (struct dc *)link->dc; 463 char *wr_buf = NULL; 464 uint32_t wr_buf_size = 40; 465 long param[3]; 466 bool use_prefer_link_setting; 467 struct link_training_settings link_lane_settings; 468 int max_param_num = 3; 469 uint8_t param_nums = 0; 470 int r = 0; 471 472 473 if (size == 0) 474 return -EINVAL; 475 476 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 477 if (!wr_buf) 478 return -ENOSPC; 479 480 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 481 (long *)param, buf, 482 max_param_num, 483 ¶m_nums)) { 484 kfree(wr_buf); 485 return -EINVAL; 486 } 487 488 if (param_nums <= 0) { 489 kfree(wr_buf); 490 DRM_DEBUG_DRIVER("user data not be read\n"); 491 return -EINVAL; 492 } 493 494 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 495 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 496 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 497 kfree(wr_buf); 498 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 499 return size; 500 } 501 502 /* get link settings: lane count, link rate */ 503 use_prefer_link_setting = 504 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 505 (link->test_pattern_enabled)); 506 507 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 508 509 if (use_prefer_link_setting) { 510 link_lane_settings.link_settings.lane_count = 511 link->preferred_link_setting.lane_count; 512 link_lane_settings.link_settings.link_rate = 513 link->preferred_link_setting.link_rate; 514 link_lane_settings.link_settings.link_spread = 515 link->preferred_link_setting.link_spread; 516 } else { 517 link_lane_settings.link_settings.lane_count = 518 link->cur_link_settings.lane_count; 519 link_lane_settings.link_settings.link_rate = 520 link->cur_link_settings.link_rate; 521 link_lane_settings.link_settings.link_spread = 522 link->cur_link_settings.link_spread; 523 } 524 525 /* apply phy settings from user */ 526 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 527 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 528 (enum dc_voltage_swing) (param[0]); 529 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 530 (enum dc_pre_emphasis) (param[1]); 531 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 532 (enum dc_post_cursor2) (param[2]); 533 } 534 535 /* program ASIC registers and DPCD registers */ 536 dc_link_set_drive_settings(dc, &link_lane_settings, link); 537 538 kfree(wr_buf); 539 return size; 540 } 541 542 /* function description 543 * 544 * set PHY layer or Link layer test pattern 545 * PHY test pattern is used for PHY SI check. 546 * Link layer test will not affect PHY SI. 547 * 548 * Reset Test Pattern: 549 * 0 = DP_TEST_PATTERN_VIDEO_MODE 550 * 551 * PHY test pattern supported: 552 * 1 = DP_TEST_PATTERN_D102 553 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 554 * 3 = DP_TEST_PATTERN_PRBS7 555 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 556 * 5 = DP_TEST_PATTERN_CP2520_1 557 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 558 * 7 = DP_TEST_PATTERN_CP2520_3 559 * 560 * DP PHY Link Training Patterns 561 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 562 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 563 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 564 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 565 * 566 * DP Link Layer Test pattern 567 * c = DP_TEST_PATTERN_COLOR_SQUARES 568 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 569 * e = DP_TEST_PATTERN_VERTICAL_BARS 570 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 571 * 10= DP_TEST_PATTERN_COLOR_RAMP 572 * 573 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 574 * 575 * --- set test pattern 576 * echo <test pattern #> > test_pattern 577 * 578 * If test pattern # is not supported, NO HW programming will be done. 579 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 580 * for the user pattern. input 10 bytes data are separated by space 581 * 582 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 583 * 584 * --- reset test pattern 585 * echo 0 > test_pattern 586 * 587 * --- HPD detection is disabled when set PHY test pattern 588 * 589 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 590 * is disable. User could unplug DP display from DP connected and plug scope to 591 * check test pattern PHY SI. 592 * If there is need unplug scope and plug DP display back, do steps below: 593 * echo 0 > phy_test_pattern 594 * unplug scope 595 * plug DP display. 596 * 597 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 598 * driver could detect "unplug scope" and "plug DP display" 599 */ 600 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 601 size_t size, loff_t *pos) 602 { 603 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 604 struct dc_link *link = connector->dc_link; 605 char *wr_buf = NULL; 606 uint32_t wr_buf_size = 100; 607 long param[11] = {0x0}; 608 int max_param_num = 11; 609 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 610 bool disable_hpd = false; 611 bool valid_test_pattern = false; 612 uint8_t param_nums = 0; 613 /* init with default 80bit custom pattern */ 614 uint8_t custom_pattern[10] = { 615 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 616 0x1f, 0x7c, 0xf0, 0xc1, 0x07 617 }; 618 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 619 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 620 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 621 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 622 struct link_training_settings link_training_settings; 623 int i; 624 625 if (size == 0) 626 return -EINVAL; 627 628 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 629 if (!wr_buf) 630 return -ENOSPC; 631 632 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 633 (long *)param, buf, 634 max_param_num, 635 ¶m_nums)) { 636 kfree(wr_buf); 637 return -EINVAL; 638 } 639 640 if (param_nums <= 0) { 641 kfree(wr_buf); 642 DRM_DEBUG_DRIVER("user data not be read\n"); 643 return -EINVAL; 644 } 645 646 647 test_pattern = param[0]; 648 649 switch (test_pattern) { 650 case DP_TEST_PATTERN_VIDEO_MODE: 651 case DP_TEST_PATTERN_COLOR_SQUARES: 652 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 653 case DP_TEST_PATTERN_VERTICAL_BARS: 654 case DP_TEST_PATTERN_HORIZONTAL_BARS: 655 case DP_TEST_PATTERN_COLOR_RAMP: 656 valid_test_pattern = true; 657 break; 658 659 case DP_TEST_PATTERN_D102: 660 case DP_TEST_PATTERN_SYMBOL_ERROR: 661 case DP_TEST_PATTERN_PRBS7: 662 case DP_TEST_PATTERN_80BIT_CUSTOM: 663 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 664 case DP_TEST_PATTERN_TRAINING_PATTERN4: 665 disable_hpd = true; 666 valid_test_pattern = true; 667 break; 668 669 default: 670 valid_test_pattern = false; 671 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 672 break; 673 } 674 675 if (!valid_test_pattern) { 676 kfree(wr_buf); 677 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 678 return size; 679 } 680 681 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 682 for (i = 0; i < 10; i++) { 683 if ((uint8_t) param[i + 1] != 0x0) 684 break; 685 } 686 687 if (i < 10) { 688 /* not use default value */ 689 for (i = 0; i < 10; i++) 690 custom_pattern[i] = (uint8_t) param[i + 1]; 691 } 692 } 693 694 /* Usage: set DP physical test pattern using debugfs with normal DP 695 * panel. Then plug out DP panel and connect a scope to measure 696 * For normal video mode and test pattern generated from CRCT, 697 * they are visibile to user. So do not disable HPD. 698 * Video Mode is also set to clear the test pattern, so enable HPD 699 * because it might have been disabled after a test pattern was set. 700 * AUX depends on HPD * sequence dependent, do not move! 701 */ 702 if (!disable_hpd) 703 dc_link_enable_hpd(link); 704 705 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 706 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 707 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 708 709 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 710 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 711 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 712 713 link_training_settings.link_settings = cur_link_settings; 714 715 716 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 717 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 718 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 719 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 720 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 721 link_training_settings.link_settings = prefer_link_settings; 722 } 723 724 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 725 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 726 727 dc_link_dp_set_test_pattern( 728 link, 729 test_pattern, 730 DP_TEST_PATTERN_COLOR_SPACE_RGB, 731 &link_training_settings, 732 custom_pattern, 733 10); 734 735 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 736 * Then plug out DP panel and connect a scope to measure DP PHY signal. 737 * Need disable interrupt to avoid SW driver disable DP output. This is 738 * done after the test pattern is set. 739 */ 740 if (valid_test_pattern && disable_hpd) 741 dc_link_disable_hpd(link); 742 743 kfree(wr_buf); 744 745 return size; 746 } 747 748 /* 749 * Returns the DMCUB tracebuffer contents. 750 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 751 */ 752 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 753 { 754 struct amdgpu_device *adev = m->private; 755 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 756 struct dmub_debugfs_trace_entry *entries; 757 uint8_t *tbuf_base; 758 uint32_t tbuf_size, max_entries, num_entries, i; 759 760 if (!fb_info) 761 return 0; 762 763 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 764 if (!tbuf_base) 765 return 0; 766 767 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 768 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 769 sizeof(struct dmub_debugfs_trace_entry); 770 771 num_entries = 772 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 773 774 num_entries = min(num_entries, max_entries); 775 776 entries = (struct dmub_debugfs_trace_entry 777 *)(tbuf_base + 778 sizeof(struct dmub_debugfs_trace_header)); 779 780 for (i = 0; i < num_entries; ++i) { 781 struct dmub_debugfs_trace_entry *entry = &entries[i]; 782 783 seq_printf(m, 784 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 785 entry->trace_code, entry->tick_count, entry->param0, 786 entry->param1); 787 } 788 789 return 0; 790 } 791 792 /* 793 * Returns the DMCUB firmware state contents. 794 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 795 */ 796 static int dmub_fw_state_show(struct seq_file *m, void *data) 797 { 798 struct amdgpu_device *adev = m->private; 799 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 800 uint8_t *state_base; 801 uint32_t state_size; 802 803 if (!fb_info) 804 return 0; 805 806 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 807 if (!state_base) 808 return 0; 809 810 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 811 812 return seq_write(m, state_base, state_size); 813 } 814 815 /* psr_capability_show() - show eDP panel PSR capability 816 * 817 * The read function: sink_psr_capability_show 818 * Shows if sink has PSR capability or not. 819 * If yes - the PSR version is appended 820 * 821 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 822 * 823 * Expected output: 824 * "Sink support: no\n" - if panel doesn't support PSR 825 * "Sink support: yes [0x01]\n" - if panel supports PSR1 826 * "Driver support: no\n" - if driver doesn't support PSR 827 * "Driver support: yes [0x01]\n" - if driver supports PSR1 828 */ 829 static int psr_capability_show(struct seq_file *m, void *data) 830 { 831 struct drm_connector *connector = m->private; 832 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 833 struct dc_link *link = aconnector->dc_link; 834 835 if (!link) 836 return -ENODEV; 837 838 if (link->type == dc_connection_none) 839 return -ENODEV; 840 841 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 842 return -ENODEV; 843 844 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 845 if (link->dpcd_caps.psr_info.psr_version) 846 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 847 seq_puts(m, "\n"); 848 849 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 850 if (link->psr_settings.psr_version) 851 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 852 seq_puts(m, "\n"); 853 854 return 0; 855 } 856 857 /* 858 * Returns the current bpc for the crtc. 859 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 860 */ 861 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 862 { 863 struct drm_crtc *crtc = m->private; 864 struct drm_device *dev = crtc->dev; 865 struct dm_crtc_state *dm_crtc_state = NULL; 866 int res = -ENODEV; 867 unsigned int bpc; 868 869 mutex_lock(&dev->mode_config.mutex); 870 drm_modeset_lock(&crtc->mutex, NULL); 871 if (crtc->state == NULL) 872 goto unlock; 873 874 dm_crtc_state = to_dm_crtc_state(crtc->state); 875 if (dm_crtc_state->stream == NULL) 876 goto unlock; 877 878 switch (dm_crtc_state->stream->timing.display_color_depth) { 879 case COLOR_DEPTH_666: 880 bpc = 6; 881 break; 882 case COLOR_DEPTH_888: 883 bpc = 8; 884 break; 885 case COLOR_DEPTH_101010: 886 bpc = 10; 887 break; 888 case COLOR_DEPTH_121212: 889 bpc = 12; 890 break; 891 case COLOR_DEPTH_161616: 892 bpc = 16; 893 break; 894 default: 895 goto unlock; 896 } 897 898 seq_printf(m, "Current: %u\n", bpc); 899 res = 0; 900 901 unlock: 902 drm_modeset_unlock(&crtc->mutex); 903 mutex_unlock(&dev->mode_config.mutex); 904 905 return res; 906 } 907 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 908 909 /* 910 * Returns the current colorspace for the crtc. 911 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 912 */ 913 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 914 { 915 struct drm_crtc *crtc = m->private; 916 struct drm_device *dev = crtc->dev; 917 struct dm_crtc_state *dm_crtc_state = NULL; 918 int res = -ENODEV; 919 920 mutex_lock(&dev->mode_config.mutex); 921 drm_modeset_lock(&crtc->mutex, NULL); 922 if (crtc->state == NULL) 923 goto unlock; 924 925 dm_crtc_state = to_dm_crtc_state(crtc->state); 926 if (dm_crtc_state->stream == NULL) 927 goto unlock; 928 929 switch (dm_crtc_state->stream->output_color_space) { 930 case COLOR_SPACE_SRGB: 931 seq_printf(m, "sRGB"); 932 break; 933 case COLOR_SPACE_YCBCR601: 934 case COLOR_SPACE_YCBCR601_LIMITED: 935 seq_printf(m, "BT601_YCC"); 936 break; 937 case COLOR_SPACE_YCBCR709: 938 case COLOR_SPACE_YCBCR709_LIMITED: 939 seq_printf(m, "BT709_YCC"); 940 break; 941 case COLOR_SPACE_ADOBERGB: 942 seq_printf(m, "opRGB"); 943 break; 944 case COLOR_SPACE_2020_RGB_FULLRANGE: 945 seq_printf(m, "BT2020_RGB"); 946 break; 947 case COLOR_SPACE_2020_YCBCR: 948 seq_printf(m, "BT2020_YCC"); 949 break; 950 default: 951 goto unlock; 952 } 953 res = 0; 954 955 unlock: 956 drm_modeset_unlock(&crtc->mutex); 957 mutex_unlock(&dev->mode_config.mutex); 958 959 return res; 960 } 961 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 962 963 964 /* 965 * Example usage: 966 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 967 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 968 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 969 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 970 */ 971 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 972 size_t size, loff_t *pos) 973 { 974 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 975 char *wr_buf = NULL; 976 uint32_t wr_buf_size = 42; 977 int max_param_num = 1; 978 long param; 979 uint8_t param_nums = 0; 980 981 if (size == 0) 982 return -EINVAL; 983 984 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 985 986 if (!wr_buf) { 987 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 988 return -ENOSPC; 989 } 990 991 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 992 ¶m, buf, 993 max_param_num, 994 ¶m_nums)) { 995 kfree(wr_buf); 996 return -EINVAL; 997 } 998 999 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1000 1001 kfree(wr_buf); 1002 return 0; 1003 } 1004 1005 /* 1006 * Returns the HDCP capability of the Display (1.4 for now). 1007 * 1008 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1009 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1010 * 1011 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1012 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1013 */ 1014 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1015 { 1016 struct drm_connector *connector = m->private; 1017 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1018 bool hdcp_cap, hdcp2_cap; 1019 1020 if (connector->status != connector_status_connected) 1021 return -ENODEV; 1022 1023 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1024 1025 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1026 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1027 1028 1029 if (hdcp_cap) 1030 seq_printf(m, "%s ", "HDCP1.4"); 1031 if (hdcp2_cap) 1032 seq_printf(m, "%s ", "HDCP2.2"); 1033 1034 if (!hdcp_cap && !hdcp2_cap) 1035 seq_printf(m, "%s ", "None"); 1036 1037 seq_puts(m, "\n"); 1038 1039 return 0; 1040 } 1041 1042 /* 1043 * Returns whether the connected display is internal and not hotpluggable. 1044 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1045 */ 1046 static int internal_display_show(struct seq_file *m, void *data) 1047 { 1048 struct drm_connector *connector = m->private; 1049 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1050 struct dc_link *link = aconnector->dc_link; 1051 1052 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1053 1054 return 0; 1055 } 1056 1057 /* function description 1058 * 1059 * generic SDP message access for testing 1060 * 1061 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1062 * 1063 * SDP header 1064 * Hb0 : Secondary-Data Packet ID 1065 * Hb1 : Secondary-Data Packet type 1066 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1067 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1068 * 1069 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1070 */ 1071 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1072 size_t size, loff_t *pos) 1073 { 1074 int r; 1075 uint8_t data[36]; 1076 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1077 struct dm_crtc_state *acrtc_state; 1078 uint32_t write_size = 36; 1079 1080 if (connector->base.status != connector_status_connected) 1081 return -ENODEV; 1082 1083 if (size == 0) 1084 return 0; 1085 1086 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1087 1088 r = copy_from_user(data, buf, write_size); 1089 1090 write_size -= r; 1091 1092 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1093 1094 return write_size; 1095 } 1096 1097 /* function: Read link's DSC & FEC capabilities 1098 * 1099 * 1100 * Access it with the following command (you need to specify 1101 * connector like DP-1): 1102 * 1103 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1104 * 1105 */ 1106 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1107 { 1108 struct drm_connector *connector = m->private; 1109 struct drm_modeset_acquire_ctx ctx; 1110 struct drm_device *dev = connector->dev; 1111 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1112 int ret = 0; 1113 bool try_again = false; 1114 bool is_fec_supported = false; 1115 bool is_dsc_supported = false; 1116 struct dpcd_caps dpcd_caps; 1117 1118 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1119 do { 1120 try_again = false; 1121 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1122 if (ret) { 1123 if (ret == -EDEADLK) { 1124 ret = drm_modeset_backoff(&ctx); 1125 if (!ret) { 1126 try_again = true; 1127 continue; 1128 } 1129 } 1130 break; 1131 } 1132 if (connector->status != connector_status_connected) { 1133 ret = -ENODEV; 1134 break; 1135 } 1136 dpcd_caps = aconnector->dc_link->dpcd_caps; 1137 if (aconnector->mst_output_port) { 1138 /* aconnector sets dsc_aux during get_modes call 1139 * if MST connector has it means it can either 1140 * enable DSC on the sink device or on MST branch 1141 * its connected to. 1142 */ 1143 if (aconnector->dsc_aux) { 1144 is_fec_supported = true; 1145 is_dsc_supported = true; 1146 } 1147 } else { 1148 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1149 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1150 } 1151 } while (try_again); 1152 1153 drm_modeset_drop_locks(&ctx); 1154 drm_modeset_acquire_fini(&ctx); 1155 1156 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1157 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1158 1159 return ret; 1160 } 1161 1162 /* function: Trigger virtual HPD redetection on connector 1163 * 1164 * This function will perform link rediscovery, link disable 1165 * and enable, and dm connector state update. 1166 * 1167 * Retrigger HPD on an existing connector by echoing 1 into 1168 * its respectful "trigger_hotplug" debugfs entry: 1169 * 1170 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1171 * 1172 * This function can perform HPD unplug: 1173 * 1174 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1175 * 1176 */ 1177 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1178 size_t size, loff_t *pos) 1179 { 1180 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1181 struct drm_connector *connector = &aconnector->base; 1182 struct dc_link *link = NULL; 1183 struct drm_device *dev = connector->dev; 1184 struct amdgpu_device *adev = drm_to_adev(dev); 1185 enum dc_connection_type new_connection_type = dc_connection_none; 1186 char *wr_buf = NULL; 1187 uint32_t wr_buf_size = 42; 1188 int max_param_num = 1; 1189 long param[1] = {0}; 1190 uint8_t param_nums = 0; 1191 bool ret = false; 1192 1193 if (!aconnector || !aconnector->dc_link) 1194 return -EINVAL; 1195 1196 if (size == 0) 1197 return -EINVAL; 1198 1199 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1200 1201 if (!wr_buf) { 1202 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1203 return -ENOSPC; 1204 } 1205 1206 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1207 (long *)param, buf, 1208 max_param_num, 1209 ¶m_nums)) { 1210 kfree(wr_buf); 1211 return -EINVAL; 1212 } 1213 1214 kfree(wr_buf); 1215 1216 if (param_nums <= 0) { 1217 DRM_DEBUG_DRIVER("user data not be read\n"); 1218 return -EINVAL; 1219 } 1220 1221 mutex_lock(&aconnector->hpd_lock); 1222 1223 /* Don't support for mst end device*/ 1224 if (aconnector->mst_root) { 1225 mutex_unlock(&aconnector->hpd_lock); 1226 return -EINVAL; 1227 } 1228 1229 if (param[0] == 1) { 1230 1231 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1232 new_connection_type != dc_connection_none) 1233 goto unlock; 1234 1235 mutex_lock(&adev->dm.dc_lock); 1236 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1237 mutex_unlock(&adev->dm.dc_lock); 1238 1239 if (!ret) 1240 goto unlock; 1241 1242 amdgpu_dm_update_connector_after_detect(aconnector); 1243 1244 drm_modeset_lock_all(dev); 1245 dm_restore_drm_connector_state(dev, connector); 1246 drm_modeset_unlock_all(dev); 1247 1248 drm_kms_helper_connector_hotplug_event(connector); 1249 } else if (param[0] == 0) { 1250 if (!aconnector->dc_link) 1251 goto unlock; 1252 1253 link = aconnector->dc_link; 1254 1255 if (link->local_sink) { 1256 dc_sink_release(link->local_sink); 1257 link->local_sink = NULL; 1258 } 1259 1260 link->dpcd_sink_count = 0; 1261 link->type = dc_connection_none; 1262 link->dongle_max_pix_clk = 0; 1263 1264 amdgpu_dm_update_connector_after_detect(aconnector); 1265 1266 /* If the aconnector is the root node in mst topology */ 1267 if (aconnector->mst_mgr.mst_state == true) 1268 dc_link_reset_cur_dp_mst_topology(link); 1269 1270 drm_modeset_lock_all(dev); 1271 dm_restore_drm_connector_state(dev, connector); 1272 drm_modeset_unlock_all(dev); 1273 1274 drm_kms_helper_connector_hotplug_event(connector); 1275 } 1276 1277 unlock: 1278 mutex_unlock(&aconnector->hpd_lock); 1279 1280 return size; 1281 } 1282 1283 /* function: read DSC status on the connector 1284 * 1285 * The read function: dp_dsc_clock_en_read 1286 * returns current status of DSC clock on the connector. 1287 * The return is a boolean flag: 1 or 0. 1288 * 1289 * Access it with the following command (you need to specify 1290 * connector like DP-1): 1291 * 1292 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1293 * 1294 * Expected output: 1295 * 1 - means that DSC is currently enabled 1296 * 0 - means that DSC is disabled 1297 */ 1298 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1299 size_t size, loff_t *pos) 1300 { 1301 char *rd_buf = NULL; 1302 char *rd_buf_ptr = NULL; 1303 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1304 struct display_stream_compressor *dsc; 1305 struct dcn_dsc_state dsc_state = {0}; 1306 const uint32_t rd_buf_size = 10; 1307 struct pipe_ctx *pipe_ctx; 1308 ssize_t result = 0; 1309 int i, r, str_len = 30; 1310 1311 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1312 1313 if (!rd_buf) 1314 return -ENOMEM; 1315 1316 rd_buf_ptr = rd_buf; 1317 1318 for (i = 0; i < MAX_PIPES; i++) { 1319 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1320 if (pipe_ctx->stream && 1321 pipe_ctx->stream->link == aconnector->dc_link) 1322 break; 1323 } 1324 1325 dsc = pipe_ctx->stream_res.dsc; 1326 if (dsc) 1327 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1328 1329 snprintf(rd_buf_ptr, str_len, 1330 "%d\n", 1331 dsc_state.dsc_clock_en); 1332 rd_buf_ptr += str_len; 1333 1334 while (size) { 1335 if (*pos >= rd_buf_size) 1336 break; 1337 1338 r = put_user(*(rd_buf + result), buf); 1339 if (r) { 1340 kfree(rd_buf); 1341 return r; /* r = -EFAULT */ 1342 } 1343 1344 buf += 1; 1345 size -= 1; 1346 *pos += 1; 1347 result += 1; 1348 } 1349 1350 kfree(rd_buf); 1351 return result; 1352 } 1353 1354 /* function: write force DSC on the connector 1355 * 1356 * The write function: dp_dsc_clock_en_write 1357 * enables to force DSC on the connector. 1358 * User can write to either force enable or force disable DSC 1359 * on the next modeset or set it to driver default 1360 * 1361 * Accepted inputs: 1362 * 0 - default DSC enablement policy 1363 * 1 - force enable DSC on the connector 1364 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1365 * 1366 * Writing DSC settings is done with the following command: 1367 * - To force enable DSC (you need to specify 1368 * connector like DP-1): 1369 * 1370 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1371 * 1372 * - To return to default state set the flag to zero and 1373 * let driver deal with DSC automatically 1374 * (you need to specify connector like DP-1): 1375 * 1376 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1377 * 1378 */ 1379 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1380 size_t size, loff_t *pos) 1381 { 1382 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1383 struct drm_connector *connector = &aconnector->base; 1384 struct drm_device *dev = connector->dev; 1385 struct drm_crtc *crtc = NULL; 1386 struct dm_crtc_state *dm_crtc_state = NULL; 1387 struct pipe_ctx *pipe_ctx; 1388 int i; 1389 char *wr_buf = NULL; 1390 uint32_t wr_buf_size = 42; 1391 int max_param_num = 1; 1392 long param[1] = {0}; 1393 uint8_t param_nums = 0; 1394 1395 if (size == 0) 1396 return -EINVAL; 1397 1398 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1399 1400 if (!wr_buf) { 1401 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1402 return -ENOSPC; 1403 } 1404 1405 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1406 (long *)param, buf, 1407 max_param_num, 1408 ¶m_nums)) { 1409 kfree(wr_buf); 1410 return -EINVAL; 1411 } 1412 1413 if (param_nums <= 0) { 1414 DRM_DEBUG_DRIVER("user data not be read\n"); 1415 kfree(wr_buf); 1416 return -EINVAL; 1417 } 1418 1419 for (i = 0; i < MAX_PIPES; i++) { 1420 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1421 if (pipe_ctx->stream && 1422 pipe_ctx->stream->link == aconnector->dc_link) 1423 break; 1424 } 1425 1426 if (!pipe_ctx->stream) 1427 goto done; 1428 1429 // Get CRTC state 1430 mutex_lock(&dev->mode_config.mutex); 1431 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1432 1433 if (connector->state == NULL) 1434 goto unlock; 1435 1436 crtc = connector->state->crtc; 1437 if (crtc == NULL) 1438 goto unlock; 1439 1440 drm_modeset_lock(&crtc->mutex, NULL); 1441 if (crtc->state == NULL) 1442 goto unlock; 1443 1444 dm_crtc_state = to_dm_crtc_state(crtc->state); 1445 if (dm_crtc_state->stream == NULL) 1446 goto unlock; 1447 1448 if (param[0] == 1) 1449 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1450 else if (param[0] == 2) 1451 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1452 else 1453 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1454 1455 dm_crtc_state->dsc_force_changed = true; 1456 1457 unlock: 1458 if (crtc) 1459 drm_modeset_unlock(&crtc->mutex); 1460 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1461 mutex_unlock(&dev->mode_config.mutex); 1462 1463 done: 1464 kfree(wr_buf); 1465 return size; 1466 } 1467 1468 /* function: read DSC slice width parameter on the connector 1469 * 1470 * The read function: dp_dsc_slice_width_read 1471 * returns dsc slice width used in the current configuration 1472 * The return is an integer: 0 or other positive number 1473 * 1474 * Access the status with the following command: 1475 * 1476 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1477 * 1478 * 0 - means that DSC is disabled 1479 * 1480 * Any other number more than zero represents the 1481 * slice width currently used by DSC in pixels 1482 * 1483 */ 1484 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1485 size_t size, loff_t *pos) 1486 { 1487 char *rd_buf = NULL; 1488 char *rd_buf_ptr = NULL; 1489 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1490 struct display_stream_compressor *dsc; 1491 struct dcn_dsc_state dsc_state = {0}; 1492 const uint32_t rd_buf_size = 100; 1493 struct pipe_ctx *pipe_ctx; 1494 ssize_t result = 0; 1495 int i, r, str_len = 30; 1496 1497 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1498 1499 if (!rd_buf) 1500 return -ENOMEM; 1501 1502 rd_buf_ptr = rd_buf; 1503 1504 for (i = 0; i < MAX_PIPES; i++) { 1505 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1506 if (pipe_ctx->stream && 1507 pipe_ctx->stream->link == aconnector->dc_link) 1508 break; 1509 } 1510 1511 dsc = pipe_ctx->stream_res.dsc; 1512 if (dsc) 1513 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1514 1515 snprintf(rd_buf_ptr, str_len, 1516 "%d\n", 1517 dsc_state.dsc_slice_width); 1518 rd_buf_ptr += str_len; 1519 1520 while (size) { 1521 if (*pos >= rd_buf_size) 1522 break; 1523 1524 r = put_user(*(rd_buf + result), buf); 1525 if (r) { 1526 kfree(rd_buf); 1527 return r; /* r = -EFAULT */ 1528 } 1529 1530 buf += 1; 1531 size -= 1; 1532 *pos += 1; 1533 result += 1; 1534 } 1535 1536 kfree(rd_buf); 1537 return result; 1538 } 1539 1540 /* function: write DSC slice width parameter 1541 * 1542 * The write function: dp_dsc_slice_width_write 1543 * overwrites automatically generated DSC configuration 1544 * of slice width. 1545 * 1546 * The user has to write the slice width divisible by the 1547 * picture width. 1548 * 1549 * Also the user has to write width in hexidecimal 1550 * rather than in decimal. 1551 * 1552 * Writing DSC settings is done with the following command: 1553 * - To force overwrite slice width: (example sets to 1920 pixels) 1554 * 1555 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1556 * 1557 * - To stop overwriting and let driver find the optimal size, 1558 * set the width to zero: 1559 * 1560 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1561 * 1562 */ 1563 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1564 size_t size, loff_t *pos) 1565 { 1566 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1567 struct pipe_ctx *pipe_ctx; 1568 struct drm_connector *connector = &aconnector->base; 1569 struct drm_device *dev = connector->dev; 1570 struct drm_crtc *crtc = NULL; 1571 struct dm_crtc_state *dm_crtc_state = NULL; 1572 int i; 1573 char *wr_buf = NULL; 1574 uint32_t wr_buf_size = 42; 1575 int max_param_num = 1; 1576 long param[1] = {0}; 1577 uint8_t param_nums = 0; 1578 1579 if (size == 0) 1580 return -EINVAL; 1581 1582 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1583 1584 if (!wr_buf) { 1585 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1586 return -ENOSPC; 1587 } 1588 1589 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1590 (long *)param, buf, 1591 max_param_num, 1592 ¶m_nums)) { 1593 kfree(wr_buf); 1594 return -EINVAL; 1595 } 1596 1597 if (param_nums <= 0) { 1598 DRM_DEBUG_DRIVER("user data not be read\n"); 1599 kfree(wr_buf); 1600 return -EINVAL; 1601 } 1602 1603 for (i = 0; i < MAX_PIPES; i++) { 1604 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1605 if (pipe_ctx->stream && 1606 pipe_ctx->stream->link == aconnector->dc_link) 1607 break; 1608 } 1609 1610 if (!pipe_ctx->stream) 1611 goto done; 1612 1613 // Safely get CRTC state 1614 mutex_lock(&dev->mode_config.mutex); 1615 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1616 1617 if (connector->state == NULL) 1618 goto unlock; 1619 1620 crtc = connector->state->crtc; 1621 if (crtc == NULL) 1622 goto unlock; 1623 1624 drm_modeset_lock(&crtc->mutex, NULL); 1625 if (crtc->state == NULL) 1626 goto unlock; 1627 1628 dm_crtc_state = to_dm_crtc_state(crtc->state); 1629 if (dm_crtc_state->stream == NULL) 1630 goto unlock; 1631 1632 if (param[0] > 0) 1633 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1634 pipe_ctx->stream->timing.h_addressable, 1635 param[0]); 1636 else 1637 aconnector->dsc_settings.dsc_num_slices_h = 0; 1638 1639 dm_crtc_state->dsc_force_changed = true; 1640 1641 unlock: 1642 if (crtc) 1643 drm_modeset_unlock(&crtc->mutex); 1644 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1645 mutex_unlock(&dev->mode_config.mutex); 1646 1647 done: 1648 kfree(wr_buf); 1649 return size; 1650 } 1651 1652 /* function: read DSC slice height parameter on the connector 1653 * 1654 * The read function: dp_dsc_slice_height_read 1655 * returns dsc slice height used in the current configuration 1656 * The return is an integer: 0 or other positive number 1657 * 1658 * Access the status with the following command: 1659 * 1660 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1661 * 1662 * 0 - means that DSC is disabled 1663 * 1664 * Any other number more than zero represents the 1665 * slice height currently used by DSC in pixels 1666 * 1667 */ 1668 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1669 size_t size, loff_t *pos) 1670 { 1671 char *rd_buf = NULL; 1672 char *rd_buf_ptr = NULL; 1673 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1674 struct display_stream_compressor *dsc; 1675 struct dcn_dsc_state dsc_state = {0}; 1676 const uint32_t rd_buf_size = 100; 1677 struct pipe_ctx *pipe_ctx; 1678 ssize_t result = 0; 1679 int i, r, str_len = 30; 1680 1681 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1682 1683 if (!rd_buf) 1684 return -ENOMEM; 1685 1686 rd_buf_ptr = rd_buf; 1687 1688 for (i = 0; i < MAX_PIPES; i++) { 1689 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1690 if (pipe_ctx->stream && 1691 pipe_ctx->stream->link == aconnector->dc_link) 1692 break; 1693 } 1694 1695 dsc = pipe_ctx->stream_res.dsc; 1696 if (dsc) 1697 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1698 1699 snprintf(rd_buf_ptr, str_len, 1700 "%d\n", 1701 dsc_state.dsc_slice_height); 1702 rd_buf_ptr += str_len; 1703 1704 while (size) { 1705 if (*pos >= rd_buf_size) 1706 break; 1707 1708 r = put_user(*(rd_buf + result), buf); 1709 if (r) { 1710 kfree(rd_buf); 1711 return r; /* r = -EFAULT */ 1712 } 1713 1714 buf += 1; 1715 size -= 1; 1716 *pos += 1; 1717 result += 1; 1718 } 1719 1720 kfree(rd_buf); 1721 return result; 1722 } 1723 1724 /* function: write DSC slice height parameter 1725 * 1726 * The write function: dp_dsc_slice_height_write 1727 * overwrites automatically generated DSC configuration 1728 * of slice height. 1729 * 1730 * The user has to write the slice height divisible by the 1731 * picture height. 1732 * 1733 * Also the user has to write height in hexidecimal 1734 * rather than in decimal. 1735 * 1736 * Writing DSC settings is done with the following command: 1737 * - To force overwrite slice height (example sets to 128 pixels): 1738 * 1739 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1740 * 1741 * - To stop overwriting and let driver find the optimal size, 1742 * set the height to zero: 1743 * 1744 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1745 * 1746 */ 1747 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1748 size_t size, loff_t *pos) 1749 { 1750 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1751 struct drm_connector *connector = &aconnector->base; 1752 struct drm_device *dev = connector->dev; 1753 struct drm_crtc *crtc = NULL; 1754 struct dm_crtc_state *dm_crtc_state = NULL; 1755 struct pipe_ctx *pipe_ctx; 1756 int i; 1757 char *wr_buf = NULL; 1758 uint32_t wr_buf_size = 42; 1759 int max_param_num = 1; 1760 uint8_t param_nums = 0; 1761 long param[1] = {0}; 1762 1763 if (size == 0) 1764 return -EINVAL; 1765 1766 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1767 1768 if (!wr_buf) { 1769 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1770 return -ENOSPC; 1771 } 1772 1773 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1774 (long *)param, buf, 1775 max_param_num, 1776 ¶m_nums)) { 1777 kfree(wr_buf); 1778 return -EINVAL; 1779 } 1780 1781 if (param_nums <= 0) { 1782 DRM_DEBUG_DRIVER("user data not be read\n"); 1783 kfree(wr_buf); 1784 return -EINVAL; 1785 } 1786 1787 for (i = 0; i < MAX_PIPES; i++) { 1788 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1789 if (pipe_ctx->stream && 1790 pipe_ctx->stream->link == aconnector->dc_link) 1791 break; 1792 } 1793 1794 if (!pipe_ctx->stream) 1795 goto done; 1796 1797 // Get CRTC state 1798 mutex_lock(&dev->mode_config.mutex); 1799 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1800 1801 if (connector->state == NULL) 1802 goto unlock; 1803 1804 crtc = connector->state->crtc; 1805 if (crtc == NULL) 1806 goto unlock; 1807 1808 drm_modeset_lock(&crtc->mutex, NULL); 1809 if (crtc->state == NULL) 1810 goto unlock; 1811 1812 dm_crtc_state = to_dm_crtc_state(crtc->state); 1813 if (dm_crtc_state->stream == NULL) 1814 goto unlock; 1815 1816 if (param[0] > 0) 1817 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1818 pipe_ctx->stream->timing.v_addressable, 1819 param[0]); 1820 else 1821 aconnector->dsc_settings.dsc_num_slices_v = 0; 1822 1823 dm_crtc_state->dsc_force_changed = true; 1824 1825 unlock: 1826 if (crtc) 1827 drm_modeset_unlock(&crtc->mutex); 1828 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1829 mutex_unlock(&dev->mode_config.mutex); 1830 1831 done: 1832 kfree(wr_buf); 1833 return size; 1834 } 1835 1836 /* function: read DSC target rate on the connector in bits per pixel 1837 * 1838 * The read function: dp_dsc_bits_per_pixel_read 1839 * returns target rate of compression in bits per pixel 1840 * The return is an integer: 0 or other positive integer 1841 * 1842 * Access it with the following command: 1843 * 1844 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1845 * 1846 * 0 - means that DSC is disabled 1847 */ 1848 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1849 size_t size, loff_t *pos) 1850 { 1851 char *rd_buf = NULL; 1852 char *rd_buf_ptr = NULL; 1853 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1854 struct display_stream_compressor *dsc; 1855 struct dcn_dsc_state dsc_state = {0}; 1856 const uint32_t rd_buf_size = 100; 1857 struct pipe_ctx *pipe_ctx; 1858 ssize_t result = 0; 1859 int i, r, str_len = 30; 1860 1861 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1862 1863 if (!rd_buf) 1864 return -ENOMEM; 1865 1866 rd_buf_ptr = rd_buf; 1867 1868 for (i = 0; i < MAX_PIPES; i++) { 1869 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1870 if (pipe_ctx->stream && 1871 pipe_ctx->stream->link == aconnector->dc_link) 1872 break; 1873 } 1874 1875 dsc = pipe_ctx->stream_res.dsc; 1876 if (dsc) 1877 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1878 1879 snprintf(rd_buf_ptr, str_len, 1880 "%d\n", 1881 dsc_state.dsc_bits_per_pixel); 1882 rd_buf_ptr += str_len; 1883 1884 while (size) { 1885 if (*pos >= rd_buf_size) 1886 break; 1887 1888 r = put_user(*(rd_buf + result), buf); 1889 if (r) { 1890 kfree(rd_buf); 1891 return r; /* r = -EFAULT */ 1892 } 1893 1894 buf += 1; 1895 size -= 1; 1896 *pos += 1; 1897 result += 1; 1898 } 1899 1900 kfree(rd_buf); 1901 return result; 1902 } 1903 1904 /* function: write DSC target rate in bits per pixel 1905 * 1906 * The write function: dp_dsc_bits_per_pixel_write 1907 * overwrites automatically generated DSC configuration 1908 * of DSC target bit rate. 1909 * 1910 * Also the user has to write bpp in hexidecimal 1911 * rather than in decimal. 1912 * 1913 * Writing DSC settings is done with the following command: 1914 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1915 * 1916 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1917 * 1918 * - To stop overwriting and let driver find the optimal rate, 1919 * set the rate to zero: 1920 * 1921 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1922 * 1923 */ 1924 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1925 size_t size, loff_t *pos) 1926 { 1927 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1928 struct drm_connector *connector = &aconnector->base; 1929 struct drm_device *dev = connector->dev; 1930 struct drm_crtc *crtc = NULL; 1931 struct dm_crtc_state *dm_crtc_state = NULL; 1932 struct pipe_ctx *pipe_ctx; 1933 int i; 1934 char *wr_buf = NULL; 1935 uint32_t wr_buf_size = 42; 1936 int max_param_num = 1; 1937 uint8_t param_nums = 0; 1938 long param[1] = {0}; 1939 1940 if (size == 0) 1941 return -EINVAL; 1942 1943 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1944 1945 if (!wr_buf) { 1946 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1947 return -ENOSPC; 1948 } 1949 1950 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1951 (long *)param, buf, 1952 max_param_num, 1953 ¶m_nums)) { 1954 kfree(wr_buf); 1955 return -EINVAL; 1956 } 1957 1958 if (param_nums <= 0) { 1959 DRM_DEBUG_DRIVER("user data not be read\n"); 1960 kfree(wr_buf); 1961 return -EINVAL; 1962 } 1963 1964 for (i = 0; i < MAX_PIPES; i++) { 1965 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1966 if (pipe_ctx->stream && 1967 pipe_ctx->stream->link == aconnector->dc_link) 1968 break; 1969 } 1970 1971 if (!pipe_ctx->stream) 1972 goto done; 1973 1974 // Get CRTC state 1975 mutex_lock(&dev->mode_config.mutex); 1976 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1977 1978 if (connector->state == NULL) 1979 goto unlock; 1980 1981 crtc = connector->state->crtc; 1982 if (crtc == NULL) 1983 goto unlock; 1984 1985 drm_modeset_lock(&crtc->mutex, NULL); 1986 if (crtc->state == NULL) 1987 goto unlock; 1988 1989 dm_crtc_state = to_dm_crtc_state(crtc->state); 1990 if (dm_crtc_state->stream == NULL) 1991 goto unlock; 1992 1993 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 1994 1995 dm_crtc_state->dsc_force_changed = true; 1996 1997 unlock: 1998 if (crtc) 1999 drm_modeset_unlock(&crtc->mutex); 2000 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2001 mutex_unlock(&dev->mode_config.mutex); 2002 2003 done: 2004 kfree(wr_buf); 2005 return size; 2006 } 2007 2008 /* function: read DSC picture width parameter on the connector 2009 * 2010 * The read function: dp_dsc_pic_width_read 2011 * returns dsc picture width used in the current configuration 2012 * It is the same as h_addressable of the current 2013 * display's timing 2014 * The return is an integer: 0 or other positive integer 2015 * If 0 then DSC is disabled. 2016 * 2017 * Access it with the following command: 2018 * 2019 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2020 * 2021 * 0 - means that DSC is disabled 2022 */ 2023 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2024 size_t size, loff_t *pos) 2025 { 2026 char *rd_buf = NULL; 2027 char *rd_buf_ptr = NULL; 2028 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2029 struct display_stream_compressor *dsc; 2030 struct dcn_dsc_state dsc_state = {0}; 2031 const uint32_t rd_buf_size = 100; 2032 struct pipe_ctx *pipe_ctx; 2033 ssize_t result = 0; 2034 int i, r, str_len = 30; 2035 2036 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2037 2038 if (!rd_buf) 2039 return -ENOMEM; 2040 2041 rd_buf_ptr = rd_buf; 2042 2043 for (i = 0; i < MAX_PIPES; i++) { 2044 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2045 if (pipe_ctx->stream && 2046 pipe_ctx->stream->link == aconnector->dc_link) 2047 break; 2048 } 2049 2050 dsc = pipe_ctx->stream_res.dsc; 2051 if (dsc) 2052 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2053 2054 snprintf(rd_buf_ptr, str_len, 2055 "%d\n", 2056 dsc_state.dsc_pic_width); 2057 rd_buf_ptr += str_len; 2058 2059 while (size) { 2060 if (*pos >= rd_buf_size) 2061 break; 2062 2063 r = put_user(*(rd_buf + result), buf); 2064 if (r) { 2065 kfree(rd_buf); 2066 return r; /* r = -EFAULT */ 2067 } 2068 2069 buf += 1; 2070 size -= 1; 2071 *pos += 1; 2072 result += 1; 2073 } 2074 2075 kfree(rd_buf); 2076 return result; 2077 } 2078 2079 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2080 size_t size, loff_t *pos) 2081 { 2082 char *rd_buf = NULL; 2083 char *rd_buf_ptr = NULL; 2084 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2085 struct display_stream_compressor *dsc; 2086 struct dcn_dsc_state dsc_state = {0}; 2087 const uint32_t rd_buf_size = 100; 2088 struct pipe_ctx *pipe_ctx; 2089 ssize_t result = 0; 2090 int i, r, str_len = 30; 2091 2092 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2093 2094 if (!rd_buf) 2095 return -ENOMEM; 2096 2097 rd_buf_ptr = rd_buf; 2098 2099 for (i = 0; i < MAX_PIPES; i++) { 2100 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2101 if (pipe_ctx->stream && 2102 pipe_ctx->stream->link == aconnector->dc_link) 2103 break; 2104 } 2105 2106 dsc = pipe_ctx->stream_res.dsc; 2107 if (dsc) 2108 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2109 2110 snprintf(rd_buf_ptr, str_len, 2111 "%d\n", 2112 dsc_state.dsc_pic_height); 2113 rd_buf_ptr += str_len; 2114 2115 while (size) { 2116 if (*pos >= rd_buf_size) 2117 break; 2118 2119 r = put_user(*(rd_buf + result), buf); 2120 if (r) { 2121 kfree(rd_buf); 2122 return r; /* r = -EFAULT */ 2123 } 2124 2125 buf += 1; 2126 size -= 1; 2127 *pos += 1; 2128 result += 1; 2129 } 2130 2131 kfree(rd_buf); 2132 return result; 2133 } 2134 2135 /* function: read DSC chunk size parameter on the connector 2136 * 2137 * The read function: dp_dsc_chunk_size_read 2138 * returns dsc chunk size set in the current configuration 2139 * The value is calculated automatically by DSC code 2140 * and depends on slice parameters and bpp target rate 2141 * The return is an integer: 0 or other positive integer 2142 * If 0 then DSC is disabled. 2143 * 2144 * Access it with the following command: 2145 * 2146 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2147 * 2148 * 0 - means that DSC is disabled 2149 */ 2150 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2151 size_t size, loff_t *pos) 2152 { 2153 char *rd_buf = NULL; 2154 char *rd_buf_ptr = NULL; 2155 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2156 struct display_stream_compressor *dsc; 2157 struct dcn_dsc_state dsc_state = {0}; 2158 const uint32_t rd_buf_size = 100; 2159 struct pipe_ctx *pipe_ctx; 2160 ssize_t result = 0; 2161 int i, r, str_len = 30; 2162 2163 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2164 2165 if (!rd_buf) 2166 return -ENOMEM; 2167 2168 rd_buf_ptr = rd_buf; 2169 2170 for (i = 0; i < MAX_PIPES; i++) { 2171 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2172 if (pipe_ctx->stream && 2173 pipe_ctx->stream->link == aconnector->dc_link) 2174 break; 2175 } 2176 2177 dsc = pipe_ctx->stream_res.dsc; 2178 if (dsc) 2179 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2180 2181 snprintf(rd_buf_ptr, str_len, 2182 "%d\n", 2183 dsc_state.dsc_chunk_size); 2184 rd_buf_ptr += str_len; 2185 2186 while (size) { 2187 if (*pos >= rd_buf_size) 2188 break; 2189 2190 r = put_user(*(rd_buf + result), buf); 2191 if (r) { 2192 kfree(rd_buf); 2193 return r; /* r = -EFAULT */ 2194 } 2195 2196 buf += 1; 2197 size -= 1; 2198 *pos += 1; 2199 result += 1; 2200 } 2201 2202 kfree(rd_buf); 2203 return result; 2204 } 2205 2206 /* function: read DSC slice bpg offset on the connector 2207 * 2208 * The read function: dp_dsc_slice_bpg_offset_read 2209 * returns dsc bpg slice offset set in the current configuration 2210 * The value is calculated automatically by DSC code 2211 * and depends on slice parameters and bpp target rate 2212 * The return is an integer: 0 or other positive integer 2213 * If 0 then DSC is disabled. 2214 * 2215 * Access it with the following command: 2216 * 2217 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2218 * 2219 * 0 - means that DSC is disabled 2220 */ 2221 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2222 size_t size, loff_t *pos) 2223 { 2224 char *rd_buf = NULL; 2225 char *rd_buf_ptr = NULL; 2226 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2227 struct display_stream_compressor *dsc; 2228 struct dcn_dsc_state dsc_state = {0}; 2229 const uint32_t rd_buf_size = 100; 2230 struct pipe_ctx *pipe_ctx; 2231 ssize_t result = 0; 2232 int i, r, str_len = 30; 2233 2234 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2235 2236 if (!rd_buf) 2237 return -ENOMEM; 2238 2239 rd_buf_ptr = rd_buf; 2240 2241 for (i = 0; i < MAX_PIPES; i++) { 2242 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2243 if (pipe_ctx->stream && 2244 pipe_ctx->stream->link == aconnector->dc_link) 2245 break; 2246 } 2247 2248 dsc = pipe_ctx->stream_res.dsc; 2249 if (dsc) 2250 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2251 2252 snprintf(rd_buf_ptr, str_len, 2253 "%d\n", 2254 dsc_state.dsc_slice_bpg_offset); 2255 rd_buf_ptr += str_len; 2256 2257 while (size) { 2258 if (*pos >= rd_buf_size) 2259 break; 2260 2261 r = put_user(*(rd_buf + result), buf); 2262 if (r) { 2263 kfree(rd_buf); 2264 return r; /* r = -EFAULT */ 2265 } 2266 2267 buf += 1; 2268 size -= 1; 2269 *pos += 1; 2270 result += 1; 2271 } 2272 2273 kfree(rd_buf); 2274 return result; 2275 } 2276 2277 2278 /* 2279 * function description: Read max_requested_bpc property from the connector 2280 * 2281 * Access it with the following command: 2282 * 2283 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2284 * 2285 */ 2286 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2287 size_t size, loff_t *pos) 2288 { 2289 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2290 struct drm_connector *connector = &aconnector->base; 2291 struct drm_device *dev = connector->dev; 2292 struct dm_connector_state *state; 2293 ssize_t result = 0; 2294 char *rd_buf = NULL; 2295 char *rd_buf_ptr = NULL; 2296 const uint32_t rd_buf_size = 10; 2297 int r; 2298 2299 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2300 2301 if (!rd_buf) 2302 return -ENOMEM; 2303 2304 mutex_lock(&dev->mode_config.mutex); 2305 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2306 2307 if (connector->state == NULL) 2308 goto unlock; 2309 2310 state = to_dm_connector_state(connector->state); 2311 2312 rd_buf_ptr = rd_buf; 2313 snprintf(rd_buf_ptr, rd_buf_size, 2314 "%u\n", 2315 state->base.max_requested_bpc); 2316 2317 while (size) { 2318 if (*pos >= rd_buf_size) 2319 break; 2320 2321 r = put_user(*(rd_buf + result), buf); 2322 if (r) { 2323 result = r; /* r = -EFAULT */ 2324 goto unlock; 2325 } 2326 buf += 1; 2327 size -= 1; 2328 *pos += 1; 2329 result += 1; 2330 } 2331 unlock: 2332 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2333 mutex_unlock(&dev->mode_config.mutex); 2334 kfree(rd_buf); 2335 return result; 2336 } 2337 2338 2339 /* 2340 * function description: Set max_requested_bpc property on the connector 2341 * 2342 * This function will not force the input BPC on connector, it will only 2343 * change the max value. This is equivalent to setting max_bpc through 2344 * xrandr. 2345 * 2346 * The BPC value written must be >= 6 and <= 16. Values outside of this 2347 * range will result in errors. 2348 * 2349 * BPC values: 2350 * 0x6 - 6 BPC 2351 * 0x8 - 8 BPC 2352 * 0xa - 10 BPC 2353 * 0xc - 12 BPC 2354 * 0x10 - 16 BPC 2355 * 2356 * Write the max_bpc in the following way: 2357 * 2358 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2359 * 2360 */ 2361 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2362 size_t size, loff_t *pos) 2363 { 2364 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2365 struct drm_connector *connector = &aconnector->base; 2366 struct dm_connector_state *state; 2367 struct drm_device *dev = connector->dev; 2368 char *wr_buf = NULL; 2369 uint32_t wr_buf_size = 42; 2370 int max_param_num = 1; 2371 long param[1] = {0}; 2372 uint8_t param_nums = 0; 2373 2374 if (size == 0) 2375 return -EINVAL; 2376 2377 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2378 2379 if (!wr_buf) { 2380 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2381 return -ENOSPC; 2382 } 2383 2384 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2385 (long *)param, buf, 2386 max_param_num, 2387 ¶m_nums)) { 2388 kfree(wr_buf); 2389 return -EINVAL; 2390 } 2391 2392 if (param_nums <= 0) { 2393 DRM_DEBUG_DRIVER("user data not be read\n"); 2394 kfree(wr_buf); 2395 return -EINVAL; 2396 } 2397 2398 if (param[0] < 6 || param[0] > 16) { 2399 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2400 kfree(wr_buf); 2401 return -EINVAL; 2402 } 2403 2404 mutex_lock(&dev->mode_config.mutex); 2405 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2406 2407 if (connector->state == NULL) 2408 goto unlock; 2409 2410 state = to_dm_connector_state(connector->state); 2411 state->base.max_requested_bpc = param[0]; 2412 unlock: 2413 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2414 mutex_unlock(&dev->mode_config.mutex); 2415 2416 kfree(wr_buf); 2417 return size; 2418 } 2419 2420 /* 2421 * Backlight at this moment. Read only. 2422 * As written to display, taking ABM and backlight lut into account. 2423 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2424 * 2425 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2426 */ 2427 static int current_backlight_show(struct seq_file *m, void *unused) 2428 { 2429 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2430 struct dc_link *link = aconnector->dc_link; 2431 unsigned int backlight; 2432 2433 backlight = dc_link_get_backlight_level(link); 2434 seq_printf(m, "0x%x\n", backlight); 2435 2436 return 0; 2437 } 2438 2439 /* 2440 * Backlight value that is being approached. Read only. 2441 * As written to display, taking ABM and backlight lut into account. 2442 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2443 * 2444 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2445 */ 2446 static int target_backlight_show(struct seq_file *m, void *unused) 2447 { 2448 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2449 struct dc_link *link = aconnector->dc_link; 2450 unsigned int backlight; 2451 2452 backlight = dc_link_get_target_backlight_pwm(link); 2453 seq_printf(m, "0x%x\n", backlight); 2454 2455 return 0; 2456 } 2457 2458 /* 2459 * function description: Determine if the connector is mst connector 2460 * 2461 * This function helps to determine whether a connector is a mst connector. 2462 * - "root" stands for the root connector of the topology 2463 * - "branch" stands for branch device of the topology 2464 * - "end" stands for leaf node connector of the topology 2465 * - "no" stands for the connector is not a device of a mst topology 2466 * Access it with the following command: 2467 * 2468 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2469 * 2470 */ 2471 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2472 { 2473 struct drm_connector *connector = m->private; 2474 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2475 struct drm_dp_mst_topology_mgr *mgr = NULL; 2476 struct drm_dp_mst_port *port = NULL; 2477 char *role = NULL; 2478 2479 mutex_lock(&aconnector->hpd_lock); 2480 2481 if (aconnector->mst_mgr.mst_state) { 2482 role = "root"; 2483 } else if (aconnector->mst_root && 2484 aconnector->mst_root->mst_mgr.mst_state) { 2485 2486 role = "end"; 2487 2488 mgr = &aconnector->mst_root->mst_mgr; 2489 port = aconnector->mst_output_port; 2490 2491 drm_modeset_lock(&mgr->base.lock, NULL); 2492 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2493 port->mcs) 2494 role = "branch"; 2495 drm_modeset_unlock(&mgr->base.lock); 2496 2497 } else { 2498 role = "no"; 2499 } 2500 2501 seq_printf(m, "%s\n", role); 2502 2503 mutex_unlock(&aconnector->hpd_lock); 2504 2505 return 0; 2506 } 2507 2508 /* 2509 * function description: Read out the mst progress status 2510 * 2511 * This function helps to determine the mst progress status of 2512 * a mst connector. 2513 * 2514 * Access it with the following command: 2515 * 2516 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2517 * 2518 */ 2519 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2520 { 2521 struct drm_connector *connector = m->private; 2522 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2523 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2524 int i; 2525 2526 mutex_lock(&aconnector->hpd_lock); 2527 mutex_lock(&adev->dm.dc_lock); 2528 2529 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2530 seq_puts(m, "disabled\n"); 2531 } else { 2532 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2533 seq_printf(m, "%s:%s\n", 2534 mst_progress_status[i], 2535 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2536 } 2537 2538 mutex_unlock(&adev->dm.dc_lock); 2539 mutex_unlock(&aconnector->hpd_lock); 2540 2541 return 0; 2542 } 2543 2544 /* 2545 * Reports whether the connected display is a USB4 DPIA tunneled display 2546 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2547 */ 2548 static int is_dpia_link_show(struct seq_file *m, void *data) 2549 { 2550 struct drm_connector *connector = m->private; 2551 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2552 struct dc_link *link = aconnector->dc_link; 2553 2554 if (connector->status != connector_status_connected) 2555 return -ENODEV; 2556 2557 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2558 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2559 2560 return 0; 2561 } 2562 2563 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2564 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2565 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2566 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2567 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2568 DEFINE_SHOW_ATTRIBUTE(internal_display); 2569 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2570 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2571 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2572 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2573 2574 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2575 .owner = THIS_MODULE, 2576 .read = dp_dsc_clock_en_read, 2577 .write = dp_dsc_clock_en_write, 2578 .llseek = default_llseek 2579 }; 2580 2581 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2582 .owner = THIS_MODULE, 2583 .read = dp_dsc_slice_width_read, 2584 .write = dp_dsc_slice_width_write, 2585 .llseek = default_llseek 2586 }; 2587 2588 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2589 .owner = THIS_MODULE, 2590 .read = dp_dsc_slice_height_read, 2591 .write = dp_dsc_slice_height_write, 2592 .llseek = default_llseek 2593 }; 2594 2595 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2596 .owner = THIS_MODULE, 2597 .read = dp_dsc_bits_per_pixel_read, 2598 .write = dp_dsc_bits_per_pixel_write, 2599 .llseek = default_llseek 2600 }; 2601 2602 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2603 .owner = THIS_MODULE, 2604 .read = dp_dsc_pic_width_read, 2605 .llseek = default_llseek 2606 }; 2607 2608 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2609 .owner = THIS_MODULE, 2610 .read = dp_dsc_pic_height_read, 2611 .llseek = default_llseek 2612 }; 2613 2614 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2615 .owner = THIS_MODULE, 2616 .read = dp_dsc_chunk_size_read, 2617 .llseek = default_llseek 2618 }; 2619 2620 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2621 .owner = THIS_MODULE, 2622 .read = dp_dsc_slice_bpg_offset_read, 2623 .llseek = default_llseek 2624 }; 2625 2626 static const struct file_operations trigger_hotplug_debugfs_fops = { 2627 .owner = THIS_MODULE, 2628 .write = trigger_hotplug, 2629 .llseek = default_llseek 2630 }; 2631 2632 static const struct file_operations dp_link_settings_debugfs_fops = { 2633 .owner = THIS_MODULE, 2634 .read = dp_link_settings_read, 2635 .write = dp_link_settings_write, 2636 .llseek = default_llseek 2637 }; 2638 2639 static const struct file_operations dp_phy_settings_debugfs_fop = { 2640 .owner = THIS_MODULE, 2641 .read = dp_phy_settings_read, 2642 .write = dp_phy_settings_write, 2643 .llseek = default_llseek 2644 }; 2645 2646 static const struct file_operations dp_phy_test_pattern_fops = { 2647 .owner = THIS_MODULE, 2648 .write = dp_phy_test_pattern_debugfs_write, 2649 .llseek = default_llseek 2650 }; 2651 2652 static const struct file_operations sdp_message_fops = { 2653 .owner = THIS_MODULE, 2654 .write = dp_sdp_message_debugfs_write, 2655 .llseek = default_llseek 2656 }; 2657 2658 static const struct file_operations dp_max_bpc_debugfs_fops = { 2659 .owner = THIS_MODULE, 2660 .read = dp_max_bpc_read, 2661 .write = dp_max_bpc_write, 2662 .llseek = default_llseek 2663 }; 2664 2665 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2666 .owner = THIS_MODULE, 2667 .write = dp_dsc_passthrough_set, 2668 .llseek = default_llseek 2669 }; 2670 2671 static const struct { 2672 char *name; 2673 const struct file_operations *fops; 2674 } dp_debugfs_entries[] = { 2675 {"link_settings", &dp_link_settings_debugfs_fops}, 2676 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2677 {"lttpr_status", &dp_lttpr_status_fops}, 2678 {"test_pattern", &dp_phy_test_pattern_fops}, 2679 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2680 {"sdp_message", &sdp_message_fops}, 2681 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2682 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2683 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2684 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2685 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2686 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2687 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2688 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2689 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2690 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2691 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2692 {"is_mst_connector", &dp_is_mst_connector_fops}, 2693 {"mst_progress_status", &dp_mst_progress_status_fops}, 2694 {"is_dpia_link", &is_dpia_link_fops} 2695 }; 2696 2697 static const struct { 2698 char *name; 2699 const struct file_operations *fops; 2700 } hdmi_debugfs_entries[] = { 2701 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2702 }; 2703 2704 /* 2705 * Force YUV420 output if available from the given mode 2706 */ 2707 static int force_yuv420_output_set(void *data, u64 val) 2708 { 2709 struct amdgpu_dm_connector *connector = data; 2710 2711 connector->force_yuv420_output = (bool)val; 2712 2713 return 0; 2714 } 2715 2716 /* 2717 * Check if YUV420 is forced when available from the given mode 2718 */ 2719 static int force_yuv420_output_get(void *data, u64 *val) 2720 { 2721 struct amdgpu_dm_connector *connector = data; 2722 2723 *val = connector->force_yuv420_output; 2724 2725 return 0; 2726 } 2727 2728 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2729 force_yuv420_output_set, "%llu\n"); 2730 2731 /* 2732 * Read PSR state 2733 */ 2734 static int psr_get(void *data, u64 *val) 2735 { 2736 struct amdgpu_dm_connector *connector = data; 2737 struct dc_link *link = connector->dc_link; 2738 enum dc_psr_state state = PSR_STATE0; 2739 2740 dc_link_get_psr_state(link, &state); 2741 2742 *val = state; 2743 2744 return 0; 2745 } 2746 2747 /* 2748 * Read PSR state residency 2749 */ 2750 static int psr_read_residency(void *data, u64 *val) 2751 { 2752 struct amdgpu_dm_connector *connector = data; 2753 struct dc_link *link = connector->dc_link; 2754 u32 residency; 2755 2756 link->dc->link_srv->edp_get_psr_residency(link, &residency); 2757 2758 *val = (u64)residency; 2759 2760 return 0; 2761 } 2762 2763 /* read allow_edp_hotplug_detection */ 2764 static int allow_edp_hotplug_detection_get(void *data, u64 *val) 2765 { 2766 struct amdgpu_dm_connector *aconnector = data; 2767 struct drm_connector *connector = &aconnector->base; 2768 struct drm_device *dev = connector->dev; 2769 struct amdgpu_device *adev = drm_to_adev(dev); 2770 2771 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 2772 2773 return 0; 2774 } 2775 2776 /* set allow_edp_hotplug_detection */ 2777 static int allow_edp_hotplug_detection_set(void *data, u64 val) 2778 { 2779 struct amdgpu_dm_connector *aconnector = data; 2780 struct drm_connector *connector = &aconnector->base; 2781 struct drm_device *dev = connector->dev; 2782 struct amdgpu_device *adev = drm_to_adev(dev); 2783 2784 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 2785 2786 return 0; 2787 } 2788 2789 /* 2790 * Set dmcub trace event IRQ enable or disable. 2791 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2792 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2793 */ 2794 static int dmcub_trace_event_state_set(void *data, u64 val) 2795 { 2796 struct amdgpu_device *adev = data; 2797 2798 if (val == 1 || val == 0) { 2799 dc_dmub_trace_event_control(adev->dm.dc, val); 2800 adev->dm.dmcub_trace_event_en = (bool)val; 2801 } else 2802 return 0; 2803 2804 return 0; 2805 } 2806 2807 /* 2808 * The interface doesn't need get function, so it will return the 2809 * value of zero 2810 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2811 */ 2812 static int dmcub_trace_event_state_get(void *data, u64 *val) 2813 { 2814 struct amdgpu_device *adev = data; 2815 2816 *val = adev->dm.dmcub_trace_event_en; 2817 return 0; 2818 } 2819 2820 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2821 dmcub_trace_event_state_set, "%llu\n"); 2822 2823 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2824 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 2825 "%llu\n"); 2826 2827 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 2828 allow_edp_hotplug_detection_get, 2829 allow_edp_hotplug_detection_set, "%llu\n"); 2830 2831 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2832 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2833 2834 static const struct { 2835 char *name; 2836 const struct file_operations *fops; 2837 } connector_debugfs_entries[] = { 2838 {"force_yuv420_output", &force_yuv420_output_fops}, 2839 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2840 {"internal_display", &internal_display_fops} 2841 }; 2842 2843 /* 2844 * Returns supported customized link rates by this eDP panel. 2845 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2846 */ 2847 static int edp_ilr_show(struct seq_file *m, void *unused) 2848 { 2849 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2850 struct dc_link *link = aconnector->dc_link; 2851 uint8_t supported_link_rates[16]; 2852 uint32_t link_rate_in_khz; 2853 uint32_t entry = 0; 2854 uint8_t dpcd_rev; 2855 2856 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2857 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2858 supported_link_rates, sizeof(supported_link_rates)); 2859 2860 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2861 2862 if (dpcd_rev >= DP_DPCD_REV_13 && 2863 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2864 2865 for (entry = 0; entry < 16; entry += 2) { 2866 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2867 supported_link_rates[entry]) * 200; 2868 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2869 } 2870 } else { 2871 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2872 } 2873 2874 return 0; 2875 } 2876 2877 /* 2878 * Set supported customized link rate to eDP panel. 2879 * 2880 * echo <lane_count> <link_rate option> > ilr_setting 2881 * 2882 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2883 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2884 * to set 4 lanes and 2.16 GHz 2885 */ 2886 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2887 size_t size, loff_t *pos) 2888 { 2889 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2890 struct dc_link *link = connector->dc_link; 2891 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2892 struct dc *dc = (struct dc *)link->dc; 2893 struct dc_link_settings prefer_link_settings; 2894 char *wr_buf = NULL; 2895 const uint32_t wr_buf_size = 40; 2896 /* 0: lane_count; 1: link_rate */ 2897 int max_param_num = 2; 2898 uint8_t param_nums = 0; 2899 long param[2]; 2900 bool valid_input = true; 2901 2902 if (size == 0) 2903 return -EINVAL; 2904 2905 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2906 if (!wr_buf) 2907 return -ENOMEM; 2908 2909 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2910 (long *)param, buf, 2911 max_param_num, 2912 ¶m_nums)) { 2913 kfree(wr_buf); 2914 return -EINVAL; 2915 } 2916 2917 if (param_nums <= 0) { 2918 kfree(wr_buf); 2919 return -EINVAL; 2920 } 2921 2922 switch (param[0]) { 2923 case LANE_COUNT_ONE: 2924 case LANE_COUNT_TWO: 2925 case LANE_COUNT_FOUR: 2926 break; 2927 default: 2928 valid_input = false; 2929 break; 2930 } 2931 2932 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2933 valid_input = false; 2934 2935 if (!valid_input) { 2936 kfree(wr_buf); 2937 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2938 prefer_link_settings.use_link_rate_set = false; 2939 mutex_lock(&adev->dm.dc_lock); 2940 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2941 mutex_unlock(&adev->dm.dc_lock); 2942 return size; 2943 } 2944 2945 /* save user force lane_count, link_rate to preferred settings 2946 * spread spectrum will not be changed 2947 */ 2948 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2949 prefer_link_settings.lane_count = param[0]; 2950 prefer_link_settings.use_link_rate_set = true; 2951 prefer_link_settings.link_rate_set = param[1]; 2952 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2953 2954 mutex_lock(&adev->dm.dc_lock); 2955 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2956 NULL, link, false); 2957 mutex_unlock(&adev->dm.dc_lock); 2958 2959 kfree(wr_buf); 2960 return size; 2961 } 2962 2963 static int edp_ilr_open(struct inode *inode, struct file *file) 2964 { 2965 return single_open(file, edp_ilr_show, inode->i_private); 2966 } 2967 2968 static const struct file_operations edp_ilr_debugfs_fops = { 2969 .owner = THIS_MODULE, 2970 .open = edp_ilr_open, 2971 .read = seq_read, 2972 .llseek = seq_lseek, 2973 .release = single_release, 2974 .write = edp_ilr_write 2975 }; 2976 2977 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2978 { 2979 int i; 2980 struct dentry *dir = connector->base.debugfs_entry; 2981 2982 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2983 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2984 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2985 debugfs_create_file(dp_debugfs_entries[i].name, 2986 0644, dir, connector, 2987 dp_debugfs_entries[i].fops); 2988 } 2989 } 2990 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2991 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 2992 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2993 debugfs_create_file_unsafe("psr_residency", 0444, dir, 2994 connector, &psr_residency_fops); 2995 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2996 ¤t_backlight_fops); 2997 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2998 &target_backlight_fops); 2999 debugfs_create_file("ilr_setting", 0644, dir, connector, 3000 &edp_ilr_debugfs_fops); 3001 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3002 &allow_edp_hotplug_detection_fops); 3003 } 3004 3005 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3006 debugfs_create_file(connector_debugfs_entries[i].name, 3007 0644, dir, connector, 3008 connector_debugfs_entries[i].fops); 3009 } 3010 3011 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3012 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3013 debugfs_create_file(hdmi_debugfs_entries[i].name, 3014 0644, dir, connector, 3015 hdmi_debugfs_entries[i].fops); 3016 } 3017 } 3018 } 3019 3020 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3021 /* 3022 * Set crc window coordinate x start 3023 */ 3024 static int crc_win_x_start_set(void *data, u64 val) 3025 { 3026 struct drm_crtc *crtc = data; 3027 struct drm_device *drm_dev = crtc->dev; 3028 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3029 3030 spin_lock_irq(&drm_dev->event_lock); 3031 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3032 acrtc->dm_irq_params.window_param.update_win = false; 3033 spin_unlock_irq(&drm_dev->event_lock); 3034 3035 return 0; 3036 } 3037 3038 /* 3039 * Get crc window coordinate x start 3040 */ 3041 static int crc_win_x_start_get(void *data, u64 *val) 3042 { 3043 struct drm_crtc *crtc = data; 3044 struct drm_device *drm_dev = crtc->dev; 3045 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3046 3047 spin_lock_irq(&drm_dev->event_lock); 3048 *val = acrtc->dm_irq_params.window_param.x_start; 3049 spin_unlock_irq(&drm_dev->event_lock); 3050 3051 return 0; 3052 } 3053 3054 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3055 crc_win_x_start_set, "%llu\n"); 3056 3057 3058 /* 3059 * Set crc window coordinate y start 3060 */ 3061 static int crc_win_y_start_set(void *data, u64 val) 3062 { 3063 struct drm_crtc *crtc = data; 3064 struct drm_device *drm_dev = crtc->dev; 3065 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3066 3067 spin_lock_irq(&drm_dev->event_lock); 3068 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3069 acrtc->dm_irq_params.window_param.update_win = false; 3070 spin_unlock_irq(&drm_dev->event_lock); 3071 3072 return 0; 3073 } 3074 3075 /* 3076 * Get crc window coordinate y start 3077 */ 3078 static int crc_win_y_start_get(void *data, u64 *val) 3079 { 3080 struct drm_crtc *crtc = data; 3081 struct drm_device *drm_dev = crtc->dev; 3082 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3083 3084 spin_lock_irq(&drm_dev->event_lock); 3085 *val = acrtc->dm_irq_params.window_param.y_start; 3086 spin_unlock_irq(&drm_dev->event_lock); 3087 3088 return 0; 3089 } 3090 3091 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3092 crc_win_y_start_set, "%llu\n"); 3093 3094 /* 3095 * Set crc window coordinate x end 3096 */ 3097 static int crc_win_x_end_set(void *data, u64 val) 3098 { 3099 struct drm_crtc *crtc = data; 3100 struct drm_device *drm_dev = crtc->dev; 3101 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3102 3103 spin_lock_irq(&drm_dev->event_lock); 3104 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3105 acrtc->dm_irq_params.window_param.update_win = false; 3106 spin_unlock_irq(&drm_dev->event_lock); 3107 3108 return 0; 3109 } 3110 3111 /* 3112 * Get crc window coordinate x end 3113 */ 3114 static int crc_win_x_end_get(void *data, u64 *val) 3115 { 3116 struct drm_crtc *crtc = data; 3117 struct drm_device *drm_dev = crtc->dev; 3118 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3119 3120 spin_lock_irq(&drm_dev->event_lock); 3121 *val = acrtc->dm_irq_params.window_param.x_end; 3122 spin_unlock_irq(&drm_dev->event_lock); 3123 3124 return 0; 3125 } 3126 3127 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3128 crc_win_x_end_set, "%llu\n"); 3129 3130 /* 3131 * Set crc window coordinate y end 3132 */ 3133 static int crc_win_y_end_set(void *data, u64 val) 3134 { 3135 struct drm_crtc *crtc = data; 3136 struct drm_device *drm_dev = crtc->dev; 3137 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3138 3139 spin_lock_irq(&drm_dev->event_lock); 3140 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3141 acrtc->dm_irq_params.window_param.update_win = false; 3142 spin_unlock_irq(&drm_dev->event_lock); 3143 3144 return 0; 3145 } 3146 3147 /* 3148 * Get crc window coordinate y end 3149 */ 3150 static int crc_win_y_end_get(void *data, u64 *val) 3151 { 3152 struct drm_crtc *crtc = data; 3153 struct drm_device *drm_dev = crtc->dev; 3154 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3155 3156 spin_lock_irq(&drm_dev->event_lock); 3157 *val = acrtc->dm_irq_params.window_param.y_end; 3158 spin_unlock_irq(&drm_dev->event_lock); 3159 3160 return 0; 3161 } 3162 3163 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3164 crc_win_y_end_set, "%llu\n"); 3165 /* 3166 * Trigger to commit crc window 3167 */ 3168 static int crc_win_update_set(void *data, u64 val) 3169 { 3170 struct drm_crtc *crtc = data; 3171 struct amdgpu_crtc *acrtc; 3172 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3173 3174 if (val) { 3175 acrtc = to_amdgpu_crtc(crtc); 3176 mutex_lock(&adev->dm.dc_lock); 3177 /* PSR may write to OTG CRC window control register, 3178 * so close it before starting secure_display. 3179 */ 3180 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3181 3182 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3183 3184 acrtc->dm_irq_params.window_param.activated = true; 3185 acrtc->dm_irq_params.window_param.update_win = true; 3186 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3187 3188 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3189 mutex_unlock(&adev->dm.dc_lock); 3190 } 3191 3192 return 0; 3193 } 3194 3195 /* 3196 * Get crc window update flag 3197 */ 3198 static int crc_win_update_get(void *data, u64 *val) 3199 { 3200 *val = 0; 3201 return 0; 3202 } 3203 3204 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3205 crc_win_update_set, "%llu\n"); 3206 #endif 3207 void crtc_debugfs_init(struct drm_crtc *crtc) 3208 { 3209 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3210 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3211 3212 if (!dir) 3213 return; 3214 3215 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3216 &crc_win_x_start_fops); 3217 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3218 &crc_win_y_start_fops); 3219 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3220 &crc_win_x_end_fops); 3221 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3222 &crc_win_y_end_fops); 3223 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3224 &crc_win_update_fops); 3225 dput(dir); 3226 #endif 3227 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3228 crtc, &amdgpu_current_bpc_fops); 3229 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 3230 crtc, &amdgpu_current_colorspace_fops); 3231 } 3232 3233 /* 3234 * Writes DTN log state to the user supplied buffer. 3235 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3236 */ 3237 static ssize_t dtn_log_read( 3238 struct file *f, 3239 char __user *buf, 3240 size_t size, 3241 loff_t *pos) 3242 { 3243 struct amdgpu_device *adev = file_inode(f)->i_private; 3244 struct dc *dc = adev->dm.dc; 3245 struct dc_log_buffer_ctx log_ctx = { 0 }; 3246 ssize_t result = 0; 3247 3248 if (!buf || !size) 3249 return -EINVAL; 3250 3251 if (!dc->hwss.log_hw_state) 3252 return 0; 3253 3254 dc->hwss.log_hw_state(dc, &log_ctx); 3255 3256 if (*pos < log_ctx.pos) { 3257 size_t to_copy = log_ctx.pos - *pos; 3258 3259 to_copy = min(to_copy, size); 3260 3261 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3262 *pos += to_copy; 3263 result = to_copy; 3264 } 3265 } 3266 3267 kfree(log_ctx.buf); 3268 3269 return result; 3270 } 3271 3272 /* 3273 * Writes DTN log state to dmesg when triggered via a write. 3274 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3275 */ 3276 static ssize_t dtn_log_write( 3277 struct file *f, 3278 const char __user *buf, 3279 size_t size, 3280 loff_t *pos) 3281 { 3282 struct amdgpu_device *adev = file_inode(f)->i_private; 3283 struct dc *dc = adev->dm.dc; 3284 3285 /* Write triggers log output via dmesg. */ 3286 if (size == 0) 3287 return 0; 3288 3289 if (dc->hwss.log_hw_state) 3290 dc->hwss.log_hw_state(dc, NULL); 3291 3292 return size; 3293 } 3294 3295 static int mst_topo_show(struct seq_file *m, void *unused) 3296 { 3297 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3298 struct drm_device *dev = adev_to_drm(adev); 3299 struct drm_connector *connector; 3300 struct drm_connector_list_iter conn_iter; 3301 struct amdgpu_dm_connector *aconnector; 3302 3303 drm_connector_list_iter_begin(dev, &conn_iter); 3304 drm_for_each_connector_iter(connector, &conn_iter) { 3305 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3306 continue; 3307 3308 aconnector = to_amdgpu_dm_connector(connector); 3309 3310 /* Ensure we're only dumping the topology of a root mst node */ 3311 if (!aconnector->mst_mgr.mst_state) 3312 continue; 3313 3314 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3315 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3316 } 3317 drm_connector_list_iter_end(&conn_iter); 3318 3319 return 0; 3320 } 3321 3322 /* 3323 * Sets trigger hpd for MST topologies. 3324 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3325 * All topologies will be disconnected if val of 0 is set . 3326 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3327 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3328 */ 3329 static int trigger_hpd_mst_set(void *data, u64 val) 3330 { 3331 struct amdgpu_device *adev = data; 3332 struct drm_device *dev = adev_to_drm(adev); 3333 struct drm_connector_list_iter iter; 3334 struct amdgpu_dm_connector *aconnector; 3335 struct drm_connector *connector; 3336 struct dc_link *link = NULL; 3337 3338 if (val == 1) { 3339 drm_connector_list_iter_begin(dev, &iter); 3340 drm_for_each_connector_iter(connector, &iter) { 3341 aconnector = to_amdgpu_dm_connector(connector); 3342 if (aconnector->dc_link->type == dc_connection_mst_branch && 3343 aconnector->mst_mgr.aux) { 3344 mutex_lock(&adev->dm.dc_lock); 3345 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3346 mutex_unlock(&adev->dm.dc_lock); 3347 3348 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3349 } 3350 } 3351 } else if (val == 0) { 3352 drm_connector_list_iter_begin(dev, &iter); 3353 drm_for_each_connector_iter(connector, &iter) { 3354 aconnector = to_amdgpu_dm_connector(connector); 3355 if (!aconnector->dc_link) 3356 continue; 3357 3358 if (!aconnector->mst_root) 3359 continue; 3360 3361 link = aconnector->dc_link; 3362 dc_link_dp_receiver_power_ctrl(link, false); 3363 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3364 link->mst_stream_alloc_table.stream_count = 0; 3365 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3366 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3367 } 3368 } else { 3369 return 0; 3370 } 3371 drm_kms_helper_hotplug_event(dev); 3372 3373 return 0; 3374 } 3375 3376 /* 3377 * The interface doesn't need get function, so it will return the 3378 * value of zero 3379 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3380 */ 3381 static int trigger_hpd_mst_get(void *data, u64 *val) 3382 { 3383 *val = 0; 3384 return 0; 3385 } 3386 3387 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3388 trigger_hpd_mst_set, "%llu\n"); 3389 3390 3391 /* 3392 * Sets the force_timing_sync debug option from the given string. 3393 * All connected displays will be force synchronized immediately. 3394 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3395 */ 3396 static int force_timing_sync_set(void *data, u64 val) 3397 { 3398 struct amdgpu_device *adev = data; 3399 3400 adev->dm.force_timing_sync = (bool)val; 3401 3402 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3403 3404 return 0; 3405 } 3406 3407 /* 3408 * Gets the force_timing_sync debug option value into the given buffer. 3409 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3410 */ 3411 static int force_timing_sync_get(void *data, u64 *val) 3412 { 3413 struct amdgpu_device *adev = data; 3414 3415 *val = adev->dm.force_timing_sync; 3416 3417 return 0; 3418 } 3419 3420 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3421 force_timing_sync_set, "%llu\n"); 3422 3423 3424 /* 3425 * Disables all HPD and HPD RX interrupt handling in the 3426 * driver when set to 1. Default is 0. 3427 */ 3428 static int disable_hpd_set(void *data, u64 val) 3429 { 3430 struct amdgpu_device *adev = data; 3431 3432 adev->dm.disable_hpd_irq = (bool)val; 3433 3434 return 0; 3435 } 3436 3437 3438 /* 3439 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3440 * 0 otherwise. 3441 */ 3442 static int disable_hpd_get(void *data, u64 *val) 3443 { 3444 struct amdgpu_device *adev = data; 3445 3446 *val = adev->dm.disable_hpd_irq; 3447 3448 return 0; 3449 } 3450 3451 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3452 disable_hpd_set, "%llu\n"); 3453 3454 /* 3455 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3456 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3457 */ 3458 static int dp_force_sst_set(void *data, u64 val) 3459 { 3460 struct amdgpu_device *adev = data; 3461 3462 adev->dm.dc->debug.set_mst_en_for_sst = val; 3463 3464 return 0; 3465 } 3466 3467 static int dp_force_sst_get(void *data, u64 *val) 3468 { 3469 struct amdgpu_device *adev = data; 3470 3471 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3472 3473 return 0; 3474 } 3475 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3476 dp_force_sst_set, "%llu\n"); 3477 3478 /* 3479 * Force DP2 sequence without VESA certified cable. 3480 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3481 */ 3482 static int dp_ignore_cable_id_set(void *data, u64 val) 3483 { 3484 struct amdgpu_device *adev = data; 3485 3486 adev->dm.dc->debug.ignore_cable_id = val; 3487 3488 return 0; 3489 } 3490 3491 static int dp_ignore_cable_id_get(void *data, u64 *val) 3492 { 3493 struct amdgpu_device *adev = data; 3494 3495 *val = adev->dm.dc->debug.ignore_cable_id; 3496 3497 return 0; 3498 } 3499 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3500 dp_ignore_cable_id_set, "%llu\n"); 3501 3502 /* 3503 * Sets the DC visual confirm debug option from the given string. 3504 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3505 */ 3506 static int visual_confirm_set(void *data, u64 val) 3507 { 3508 struct amdgpu_device *adev = data; 3509 3510 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3511 3512 return 0; 3513 } 3514 3515 /* 3516 * Reads the DC visual confirm debug option value into the given buffer. 3517 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3518 */ 3519 static int visual_confirm_get(void *data, u64 *val) 3520 { 3521 struct amdgpu_device *adev = data; 3522 3523 *val = adev->dm.dc->debug.visual_confirm; 3524 3525 return 0; 3526 } 3527 3528 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3529 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3530 visual_confirm_set, "%llu\n"); 3531 3532 3533 /* 3534 * Sets the DC skip_detection_link_training debug option from the given string. 3535 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3536 */ 3537 static int skip_detection_link_training_set(void *data, u64 val) 3538 { 3539 struct amdgpu_device *adev = data; 3540 3541 if (val == 0) 3542 adev->dm.dc->debug.skip_detection_link_training = false; 3543 else 3544 adev->dm.dc->debug.skip_detection_link_training = true; 3545 3546 return 0; 3547 } 3548 3549 /* 3550 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3551 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3552 */ 3553 static int skip_detection_link_training_get(void *data, u64 *val) 3554 { 3555 struct amdgpu_device *adev = data; 3556 3557 *val = adev->dm.dc->debug.skip_detection_link_training; 3558 3559 return 0; 3560 } 3561 3562 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3563 skip_detection_link_training_get, 3564 skip_detection_link_training_set, "%llu\n"); 3565 3566 /* 3567 * Dumps the DCC_EN bit for each pipe. 3568 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3569 */ 3570 static ssize_t dcc_en_bits_read( 3571 struct file *f, 3572 char __user *buf, 3573 size_t size, 3574 loff_t *pos) 3575 { 3576 struct amdgpu_device *adev = file_inode(f)->i_private; 3577 struct dc *dc = adev->dm.dc; 3578 char *rd_buf = NULL; 3579 const uint32_t rd_buf_size = 32; 3580 uint32_t result = 0; 3581 int offset = 0; 3582 int num_pipes = dc->res_pool->pipe_count; 3583 int *dcc_en_bits; 3584 int i, r; 3585 3586 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3587 if (!dcc_en_bits) 3588 return -ENOMEM; 3589 3590 if (!dc->hwss.get_dcc_en_bits) { 3591 kfree(dcc_en_bits); 3592 return 0; 3593 } 3594 3595 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3596 3597 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3598 if (!rd_buf) { 3599 kfree(dcc_en_bits); 3600 return -ENOMEM; 3601 } 3602 3603 for (i = 0; i < num_pipes; i++) 3604 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3605 "%d ", dcc_en_bits[i]); 3606 rd_buf[strlen(rd_buf)] = '\n'; 3607 3608 kfree(dcc_en_bits); 3609 3610 while (size) { 3611 if (*pos >= rd_buf_size) 3612 break; 3613 r = put_user(*(rd_buf + result), buf); 3614 if (r) { 3615 kfree(rd_buf); 3616 return r; /* r = -EFAULT */ 3617 } 3618 buf += 1; 3619 size -= 1; 3620 *pos += 1; 3621 result += 1; 3622 } 3623 3624 kfree(rd_buf); 3625 return result; 3626 } 3627 3628 void dtn_debugfs_init(struct amdgpu_device *adev) 3629 { 3630 static const struct file_operations dtn_log_fops = { 3631 .owner = THIS_MODULE, 3632 .read = dtn_log_read, 3633 .write = dtn_log_write, 3634 .llseek = default_llseek 3635 }; 3636 static const struct file_operations dcc_en_bits_fops = { 3637 .owner = THIS_MODULE, 3638 .read = dcc_en_bits_read, 3639 .llseek = default_llseek 3640 }; 3641 3642 struct drm_minor *minor = adev_to_drm(adev)->primary; 3643 struct dentry *root = minor->debugfs_root; 3644 3645 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3646 adev, &mst_topo_fops); 3647 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3648 &dtn_log_fops); 3649 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3650 &dp_set_mst_en_for_sst_ops); 3651 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3652 &dp_ignore_cable_id_ops); 3653 3654 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3655 &visual_confirm_fops); 3656 3657 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3658 &skip_detection_link_training_fops); 3659 3660 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3661 adev, &dmub_tracebuffer_fops); 3662 3663 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3664 adev, &dmub_fw_state_fops); 3665 3666 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3667 adev, &force_timing_sync_ops); 3668 3669 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3670 adev, &dmcub_trace_event_state_fops); 3671 3672 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3673 adev, &trigger_hpd_mst_ops); 3674 3675 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3676 &dcc_en_bits_fops); 3677 3678 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3679 &disable_hpd_ops); 3680 3681 } 3682