1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_replay.h" 33 #include "amdgpu_dm_crtc.h" 34 #include "amdgpu_dm_plane.h" 35 #include "amdgpu_dm_trace.h" 36 #include "amdgpu_dm_debugfs.h" 37 38 #define HPD_DETECTION_PERIOD_uS 5000000 39 #define HPD_DETECTION_TIME_uS 1000 40 41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 42 { 43 struct drm_crtc *crtc = &acrtc->base; 44 struct drm_device *dev = crtc->dev; 45 unsigned long flags; 46 47 drm_crtc_handle_vblank(crtc); 48 49 spin_lock_irqsave(&dev->event_lock, flags); 50 51 /* Send completion event for cursor-only commits */ 52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 53 drm_crtc_send_vblank_event(crtc, acrtc->event); 54 drm_crtc_vblank_put(crtc); 55 acrtc->event = NULL; 56 } 57 58 spin_unlock_irqrestore(&dev->event_lock, flags); 59 } 60 61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 62 struct dc_stream_state *new_stream, 63 struct dc_stream_state *old_stream) 64 { 65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 66 } 67 68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 69 70 { 71 return acrtc->dm_irq_params.freesync_config.state == 72 VRR_STATE_ACTIVE_VARIABLE || 73 acrtc->dm_irq_params.freesync_config.state == 74 VRR_STATE_ACTIVE_FIXED; 75 } 76 77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 78 { 79 enum dc_irq_source irq_source; 80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 81 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 82 int rc; 83 84 if (acrtc->otg_inst == -1) 85 return 0; 86 87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 88 89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 90 91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 92 acrtc->crtc_id, enable ? "en" : "dis", rc); 93 return rc; 94 } 95 96 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 97 { 98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 100 } 101 102 /** 103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. 104 * 105 * @vblank_work: is a pointer to a struct vblank_control_work object. 106 * @vblank_enabled: indicates whether the DRM vblank counter is currently 107 * enabled (true) or disabled (false). 108 * @allow_sr_entry: represents whether entry into the self-refresh mode is 109 * allowed (true) or not allowed (false). 110 * 111 * The DRM vblank counter enable/disable action is used as the trigger to enable 112 * or disable various panel self-refresh features: 113 * 114 * Panel Replay and PSR SU 115 * - Enable when: 116 * - vblank counter is disabled 117 * - entry is allowed: usermode demonstrates an adequate number of fast 118 * commits) 119 * - CRC capture window isn't active 120 * - Keep enabled even when vblank counter gets enabled 121 * 122 * PSR1 123 * - Enable condition same as above 124 * - Disable when vblank counter is enabled 125 */ 126 static void amdgpu_dm_crtc_set_panel_sr_feature( 127 struct vblank_control_work *vblank_work, 128 bool vblank_enabled, bool allow_sr_entry) 129 { 130 struct dc_link *link = vblank_work->stream->link; 131 bool is_sr_active = (link->replay_settings.replay_allow_active || 132 link->psr_settings.psr_allow_active); 133 bool is_crc_window_active = false; 134 135 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 136 is_crc_window_active = 137 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); 138 #endif 139 140 if (link->replay_settings.replay_feature_enabled && 141 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 142 amdgpu_dm_replay_enable(vblank_work->stream, true); 143 } else if (vblank_enabled) { 144 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) 145 amdgpu_dm_psr_disable(vblank_work->stream); 146 } else if (link->psr_settings.psr_feature_enabled && 147 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 148 149 struct amdgpu_dm_connector *aconn = 150 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context; 151 152 if (!aconn->disallow_edp_enter_psr) { 153 struct amdgpu_display_manager *dm = vblank_work->dm; 154 155 amdgpu_dm_psr_enable(vblank_work->stream); 156 if (dm->idle_workqueue && 157 dm->dc->idle_optimizations_allowed && 158 dm->idle_workqueue->enable && 159 !dm->idle_workqueue->running) 160 schedule_work(&dm->idle_workqueue->work); 161 } 162 } 163 } 164 165 bool amdgpu_dm_is_headless(struct amdgpu_device *adev) 166 { 167 struct drm_connector *connector; 168 struct drm_connector_list_iter iter; 169 struct drm_device *dev; 170 bool is_headless = true; 171 172 if (adev == NULL) 173 return true; 174 175 dev = adev->dm.ddev; 176 177 drm_connector_list_iter_begin(dev, &iter); 178 drm_for_each_connector_iter(connector, &iter) { 179 180 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 181 continue; 182 183 if (connector->status == connector_status_connected) { 184 is_headless = false; 185 break; 186 } 187 } 188 drm_connector_list_iter_end(&iter); 189 return is_headless; 190 } 191 192 static void amdgpu_dm_idle_worker(struct work_struct *work) 193 { 194 struct idle_workqueue *idle_work; 195 196 idle_work = container_of(work, struct idle_workqueue, work); 197 idle_work->dm->idle_workqueue->running = true; 198 199 while (idle_work->enable) { 200 fsleep(HPD_DETECTION_PERIOD_uS); 201 mutex_lock(&idle_work->dm->dc_lock); 202 if (!idle_work->dm->dc->idle_optimizations_allowed) { 203 mutex_unlock(&idle_work->dm->dc_lock); 204 break; 205 } 206 dc_allow_idle_optimizations(idle_work->dm->dc, false); 207 208 mutex_unlock(&idle_work->dm->dc_lock); 209 fsleep(HPD_DETECTION_TIME_uS); 210 mutex_lock(&idle_work->dm->dc_lock); 211 212 if (!amdgpu_dm_is_headless(idle_work->dm->adev) && 213 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) { 214 mutex_unlock(&idle_work->dm->dc_lock); 215 break; 216 } 217 218 if (idle_work->enable) 219 dc_allow_idle_optimizations(idle_work->dm->dc, true); 220 mutex_unlock(&idle_work->dm->dc_lock); 221 } 222 idle_work->dm->idle_workqueue->running = false; 223 } 224 225 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev) 226 { 227 struct idle_workqueue *idle_work; 228 229 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL); 230 if (ZERO_OR_NULL_PTR(idle_work)) 231 return NULL; 232 233 idle_work->dm = &adev->dm; 234 idle_work->enable = false; 235 idle_work->running = false; 236 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker); 237 238 return idle_work; 239 } 240 241 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 242 { 243 struct vblank_control_work *vblank_work = 244 container_of(work, struct vblank_control_work, work); 245 struct amdgpu_display_manager *dm = vblank_work->dm; 246 247 mutex_lock(&dm->dc_lock); 248 249 if (vblank_work->enable) 250 dm->active_vblank_irq_count++; 251 else if (dm->active_vblank_irq_count) 252 dm->active_vblank_irq_count--; 253 254 if (dm->active_vblank_irq_count > 0) { 255 DRM_DEBUG_KMS("Allow idle optimizations (MALL): false\n"); 256 dc_allow_idle_optimizations(dm->dc, false); 257 } 258 259 /* 260 * Control PSR based on vblank requirements from OS 261 * 262 * If panel supports PSR SU, there's no need to disable PSR when OS is 263 * submitting fast atomic commits (we infer this by whether the OS 264 * requests vblank events). Fast atomic commits will simply trigger a 265 * full-frame-update (FFU); a specific case of selective-update (SU) 266 * where the SU region is the full hactive*vactive region. See 267 * fill_dc_dirty_rects(). 268 */ 269 if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) { 270 amdgpu_dm_crtc_set_panel_sr_feature( 271 vblank_work, vblank_work->enable, 272 vblank_work->acrtc->dm_irq_params.allow_sr_entry); 273 } 274 275 if (dm->active_vblank_irq_count == 0) { 276 DRM_DEBUG_KMS("Allow idle optimizations (MALL): true\n"); 277 dc_allow_idle_optimizations(dm->dc, true); 278 } 279 280 mutex_unlock(&dm->dc_lock); 281 282 dc_stream_release(vblank_work->stream); 283 284 kfree(vblank_work); 285 } 286 287 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 288 { 289 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 290 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 291 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 292 struct amdgpu_display_manager *dm = &adev->dm; 293 struct vblank_control_work *work; 294 int irq_type; 295 int rc = 0; 296 297 if (acrtc->otg_inst == -1) 298 goto skip; 299 300 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 301 302 if (enable) { 303 /* vblank irq on -> Only need vupdate irq in vrr mode */ 304 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 305 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 306 } else { 307 /* vblank irq off -> vupdate irq off */ 308 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 309 } 310 311 if (rc) 312 return rc; 313 314 /* crtc vblank or vstartup interrupt */ 315 if (enable) { 316 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type); 317 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc); 318 } else { 319 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type); 320 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc); 321 } 322 323 if (rc) 324 return rc; 325 326 /* 327 * hubp surface flip interrupt 328 * 329 * We have no guarantee that the frontend index maps to the same 330 * backend index - some even map to more than one. 331 * 332 * TODO: Use a different interrupt or check DC itself for the mapping. 333 */ 334 if (enable) { 335 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type); 336 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc); 337 } else { 338 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type); 339 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc); 340 } 341 342 if (rc) 343 return rc; 344 345 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 346 /* crtc vline0 interrupt, only available on DCN+ */ 347 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { 348 if (enable) { 349 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type); 350 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc); 351 } else { 352 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type); 353 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc); 354 } 355 356 if (rc) 357 return rc; 358 } 359 #endif 360 skip: 361 if (amdgpu_in_reset(adev)) 362 return 0; 363 364 if (dm->vblank_control_workqueue) { 365 work = kzalloc(sizeof(*work), GFP_ATOMIC); 366 if (!work) 367 return -ENOMEM; 368 369 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 370 work->dm = dm; 371 work->acrtc = acrtc; 372 work->enable = enable; 373 374 if (acrtc_state->stream) { 375 dc_stream_retain(acrtc_state->stream); 376 work->stream = acrtc_state->stream; 377 } 378 379 queue_work(dm->vblank_control_workqueue, &work->work); 380 } 381 382 return 0; 383 } 384 385 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 386 { 387 return amdgpu_dm_crtc_set_vblank(crtc, true); 388 } 389 390 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 391 { 392 amdgpu_dm_crtc_set_vblank(crtc, false); 393 } 394 395 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 396 struct drm_crtc_state *state) 397 { 398 struct dm_crtc_state *cur = to_dm_crtc_state(state); 399 400 /* TODO Destroy dc_stream objects are stream object is flattened */ 401 if (cur->stream) 402 dc_stream_release(cur->stream); 403 404 405 __drm_atomic_helper_crtc_destroy_state(state); 406 407 408 kfree(state); 409 } 410 411 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 412 { 413 struct dm_crtc_state *state, *cur; 414 415 cur = to_dm_crtc_state(crtc->state); 416 417 if (WARN_ON(!crtc->state)) 418 return NULL; 419 420 state = kzalloc(sizeof(*state), GFP_KERNEL); 421 if (!state) 422 return NULL; 423 424 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 425 426 if (cur->stream) { 427 state->stream = cur->stream; 428 dc_stream_retain(state->stream); 429 } 430 431 state->active_planes = cur->active_planes; 432 state->vrr_infopacket = cur->vrr_infopacket; 433 state->abm_level = cur->abm_level; 434 state->vrr_supported = cur->vrr_supported; 435 state->freesync_config = cur->freesync_config; 436 state->cm_has_degamma = cur->cm_has_degamma; 437 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 438 state->regamma_tf = cur->regamma_tf; 439 state->crc_skip_count = cur->crc_skip_count; 440 state->mpo_requested = cur->mpo_requested; 441 state->cursor_mode = cur->cursor_mode; 442 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 443 444 return &state->base; 445 } 446 447 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 448 { 449 drm_crtc_cleanup(crtc); 450 kfree(crtc); 451 } 452 453 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 454 { 455 struct dm_crtc_state *state; 456 457 if (crtc->state) 458 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 459 460 state = kzalloc(sizeof(*state), GFP_KERNEL); 461 if (WARN_ON(!state)) 462 return; 463 464 __drm_atomic_helper_crtc_reset(crtc, &state->base); 465 } 466 467 #ifdef CONFIG_DEBUG_FS 468 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 469 { 470 crtc_debugfs_init(crtc); 471 472 return 0; 473 } 474 #endif 475 476 #ifdef AMD_PRIVATE_COLOR 477 /** 478 * dm_crtc_additional_color_mgmt - enable additional color properties 479 * @crtc: DRM CRTC 480 * 481 * This function lets the driver enable post-blending CRTC regamma transfer 482 * function property in addition to DRM CRTC gamma LUT. Default value means 483 * linear transfer function, which is the default CRTC gamma LUT behaviour 484 * without this property. 485 */ 486 static void 487 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 488 { 489 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 490 491 if (adev->dm.dc->caps.color.mpc.ogam_ram) 492 drm_object_attach_property(&crtc->base, 493 adev->mode_info.regamma_tf_property, 494 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 495 } 496 497 static int 498 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 499 struct drm_crtc_state *state, 500 struct drm_property *property, 501 uint64_t val) 502 { 503 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 504 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 505 506 if (property == adev->mode_info.regamma_tf_property) { 507 if (acrtc_state->regamma_tf != val) { 508 acrtc_state->regamma_tf = val; 509 acrtc_state->base.color_mgmt_changed |= 1; 510 } 511 } else { 512 drm_dbg_atomic(crtc->dev, 513 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 514 crtc->base.id, crtc->name, 515 property->base.id, property->name); 516 return -EINVAL; 517 } 518 519 return 0; 520 } 521 522 static int 523 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 524 const struct drm_crtc_state *state, 525 struct drm_property *property, 526 uint64_t *val) 527 { 528 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 529 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 530 531 if (property == adev->mode_info.regamma_tf_property) 532 *val = acrtc_state->regamma_tf; 533 else 534 return -EINVAL; 535 536 return 0; 537 } 538 #endif 539 540 /* Implemented only the options currently available for the driver */ 541 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 542 .reset = amdgpu_dm_crtc_reset_state, 543 .destroy = amdgpu_dm_crtc_destroy, 544 .set_config = drm_atomic_helper_set_config, 545 .page_flip = drm_atomic_helper_page_flip, 546 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 547 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 548 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 549 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 550 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 551 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 552 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 553 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 554 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 555 #if defined(CONFIG_DEBUG_FS) 556 .late_register = amdgpu_dm_crtc_late_register, 557 #endif 558 #ifdef AMD_PRIVATE_COLOR 559 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 560 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 561 #endif 562 }; 563 564 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 565 { 566 } 567 568 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 569 { 570 struct drm_atomic_state *state = new_crtc_state->state; 571 struct drm_plane *plane; 572 int num_active = 0; 573 574 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 575 struct drm_plane_state *new_plane_state; 576 577 /* Cursor planes are "fake". */ 578 if (plane->type == DRM_PLANE_TYPE_CURSOR) 579 continue; 580 581 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 582 583 if (!new_plane_state) { 584 /* 585 * The plane is enable on the CRTC and hasn't changed 586 * state. This means that it previously passed 587 * validation and is therefore enabled. 588 */ 589 num_active += 1; 590 continue; 591 } 592 593 /* We need a framebuffer to be considered enabled. */ 594 num_active += (new_plane_state->fb != NULL); 595 } 596 597 return num_active; 598 } 599 600 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 601 struct drm_crtc_state *new_crtc_state) 602 { 603 struct dm_crtc_state *dm_new_crtc_state = 604 to_dm_crtc_state(new_crtc_state); 605 606 dm_new_crtc_state->active_planes = 0; 607 608 if (!dm_new_crtc_state->stream) 609 return; 610 611 dm_new_crtc_state->active_planes = 612 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 613 } 614 615 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 616 const struct drm_display_mode *mode, 617 struct drm_display_mode *adjusted_mode) 618 { 619 return true; 620 } 621 622 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 623 struct drm_atomic_state *state) 624 { 625 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 626 crtc); 627 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 628 struct dc *dc = adev->dm.dc; 629 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 630 int ret = -EINVAL; 631 632 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 633 634 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 635 636 if (WARN_ON(unlikely(!dm_crtc_state->stream && 637 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 638 return ret; 639 } 640 641 /* 642 * We require the primary plane to be enabled whenever the CRTC is, otherwise 643 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 644 * planes are disabled, which is not supported by the hardware. And there is legacy 645 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 646 */ 647 if (crtc_state->enable && 648 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 649 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 650 return -EINVAL; 651 } 652 653 /* 654 * Only allow async flips for fast updates that don't change the FB 655 * pitch, the DCC state, rotation, etc. 656 */ 657 if (crtc_state->async_flip && 658 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 659 drm_dbg_atomic(crtc->dev, 660 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 661 crtc->base.id, crtc->name); 662 return -EINVAL; 663 } 664 665 /* In some use cases, like reset, no stream is attached */ 666 if (!dm_crtc_state->stream) 667 return 0; 668 669 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 670 return 0; 671 672 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 673 return ret; 674 } 675 676 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 677 .disable = amdgpu_dm_crtc_helper_disable, 678 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 679 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 680 .get_scanout_position = amdgpu_crtc_get_scanout_position, 681 }; 682 683 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 684 struct drm_plane *plane, 685 uint32_t crtc_index) 686 { 687 struct amdgpu_crtc *acrtc = NULL; 688 struct drm_plane *cursor_plane; 689 bool is_dcn; 690 int res = -ENOMEM; 691 692 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 693 if (!cursor_plane) 694 goto fail; 695 696 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 697 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 698 699 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 700 if (!acrtc) 701 goto fail; 702 703 res = drm_crtc_init_with_planes( 704 dm->ddev, 705 &acrtc->base, 706 plane, 707 cursor_plane, 708 &amdgpu_dm_crtc_funcs, NULL); 709 710 if (res) 711 goto fail; 712 713 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 714 715 /* Create (reset) the plane state */ 716 if (acrtc->base.funcs->reset) 717 acrtc->base.funcs->reset(&acrtc->base); 718 719 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 720 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 721 722 acrtc->crtc_id = crtc_index; 723 acrtc->base.enabled = false; 724 acrtc->otg_inst = -1; 725 726 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 727 728 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 729 * support programmable degamma anywhere. 730 */ 731 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 732 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 733 true, MAX_COLOR_LUT_ENTRIES); 734 735 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 736 737 #ifdef AMD_PRIVATE_COLOR 738 dm_crtc_additional_color_mgmt(&acrtc->base); 739 #endif 740 return 0; 741 742 fail: 743 kfree(acrtc); 744 kfree(cursor_plane); 745 return res; 746 } 747 748