1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_replay.h" 33 #include "amdgpu_dm_crtc.h" 34 #include "amdgpu_dm_plane.h" 35 #include "amdgpu_dm_trace.h" 36 #include "amdgpu_dm_debugfs.h" 37 38 #define HPD_DETECTION_PERIOD_uS 2000000 39 #define HPD_DETECTION_TIME_uS 100000 40 41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 42 { 43 struct drm_crtc *crtc = &acrtc->base; 44 struct drm_device *dev = crtc->dev; 45 unsigned long flags; 46 47 drm_crtc_handle_vblank(crtc); 48 49 spin_lock_irqsave(&dev->event_lock, flags); 50 51 /* Send completion event for cursor-only commits */ 52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 53 drm_crtc_send_vblank_event(crtc, acrtc->event); 54 drm_crtc_vblank_put(crtc); 55 acrtc->event = NULL; 56 } 57 58 spin_unlock_irqrestore(&dev->event_lock, flags); 59 } 60 61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 62 struct dc_stream_state *new_stream, 63 struct dc_stream_state *old_stream) 64 { 65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 66 } 67 68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 69 70 { 71 return acrtc->dm_irq_params.freesync_config.state == 72 VRR_STATE_ACTIVE_VARIABLE || 73 acrtc->dm_irq_params.freesync_config.state == 74 VRR_STATE_ACTIVE_FIXED; 75 } 76 77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 78 { 79 enum dc_irq_source irq_source; 80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 81 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 82 int rc; 83 84 if (acrtc->otg_inst == -1) 85 return 0; 86 87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 88 89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 90 91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 92 acrtc->crtc_id, enable ? "en" : "dis", rc); 93 return rc; 94 } 95 96 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 97 { 98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 100 } 101 102 /** 103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. 104 * 105 * @vblank_work: is a pointer to a struct vblank_control_work object. 106 * @vblank_enabled: indicates whether the DRM vblank counter is currently 107 * enabled (true) or disabled (false). 108 * @allow_sr_entry: represents whether entry into the self-refresh mode is 109 * allowed (true) or not allowed (false). 110 * 111 * The DRM vblank counter enable/disable action is used as the trigger to enable 112 * or disable various panel self-refresh features: 113 * 114 * Panel Replay and PSR SU 115 * - Enable when: 116 * - vblank counter is disabled 117 * - entry is allowed: usermode demonstrates an adequate number of fast 118 * commits) 119 * - CRC capture window isn't active 120 * - Keep enabled even when vblank counter gets enabled 121 * 122 * PSR1 123 * - Enable condition same as above 124 * - Disable when vblank counter is enabled 125 */ 126 static void amdgpu_dm_crtc_set_panel_sr_feature( 127 struct vblank_control_work *vblank_work, 128 bool vblank_enabled, bool allow_sr_entry) 129 { 130 struct dc_link *link = vblank_work->stream->link; 131 bool is_sr_active = (link->replay_settings.replay_allow_active || 132 link->psr_settings.psr_allow_active); 133 bool is_crc_window_active = false; 134 135 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 136 is_crc_window_active = 137 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); 138 #endif 139 140 if (link->replay_settings.replay_feature_enabled && 141 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 142 amdgpu_dm_replay_enable(vblank_work->stream, true); 143 } else if (vblank_enabled) { 144 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) 145 amdgpu_dm_psr_disable(vblank_work->stream); 146 } else if (link->psr_settings.psr_feature_enabled && 147 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 148 149 struct amdgpu_dm_connector *aconn = 150 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context; 151 152 if (!aconn->disallow_edp_enter_psr) { 153 struct amdgpu_display_manager *dm = vblank_work->dm; 154 155 amdgpu_dm_psr_enable(vblank_work->stream); 156 if (dm->idle_workqueue && 157 (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) && 158 dm->dc->idle_optimizations_allowed && 159 dm->idle_workqueue->enable && 160 !dm->idle_workqueue->running) 161 schedule_work(&dm->idle_workqueue->work); 162 } 163 } 164 } 165 166 bool amdgpu_dm_is_headless(struct amdgpu_device *adev) 167 { 168 struct drm_connector *connector; 169 struct drm_connector_list_iter iter; 170 struct drm_device *dev; 171 bool is_headless = true; 172 173 if (adev == NULL) 174 return true; 175 176 dev = adev->dm.ddev; 177 178 drm_connector_list_iter_begin(dev, &iter); 179 drm_for_each_connector_iter(connector, &iter) { 180 181 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 182 continue; 183 184 if (connector->status == connector_status_connected) { 185 is_headless = false; 186 break; 187 } 188 } 189 drm_connector_list_iter_end(&iter); 190 return is_headless; 191 } 192 193 static void amdgpu_dm_idle_worker(struct work_struct *work) 194 { 195 struct idle_workqueue *idle_work; 196 197 idle_work = container_of(work, struct idle_workqueue, work); 198 idle_work->dm->idle_workqueue->running = true; 199 200 while (idle_work->enable) { 201 fsleep(HPD_DETECTION_PERIOD_uS); 202 mutex_lock(&idle_work->dm->dc_lock); 203 if (!idle_work->dm->dc->idle_optimizations_allowed) { 204 mutex_unlock(&idle_work->dm->dc_lock); 205 break; 206 } 207 dc_allow_idle_optimizations(idle_work->dm->dc, false); 208 209 mutex_unlock(&idle_work->dm->dc_lock); 210 fsleep(HPD_DETECTION_TIME_uS); 211 mutex_lock(&idle_work->dm->dc_lock); 212 213 if (!amdgpu_dm_is_headless(idle_work->dm->adev) && 214 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) { 215 mutex_unlock(&idle_work->dm->dc_lock); 216 break; 217 } 218 219 if (idle_work->enable) 220 dc_allow_idle_optimizations(idle_work->dm->dc, true); 221 mutex_unlock(&idle_work->dm->dc_lock); 222 } 223 idle_work->dm->idle_workqueue->running = false; 224 } 225 226 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev) 227 { 228 struct idle_workqueue *idle_work; 229 230 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL); 231 if (ZERO_OR_NULL_PTR(idle_work)) 232 return NULL; 233 234 idle_work->dm = &adev->dm; 235 idle_work->enable = false; 236 idle_work->running = false; 237 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker); 238 239 return idle_work; 240 } 241 242 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 243 { 244 struct vblank_control_work *vblank_work = 245 container_of(work, struct vblank_control_work, work); 246 struct amdgpu_display_manager *dm = vblank_work->dm; 247 248 mutex_lock(&dm->dc_lock); 249 250 if (vblank_work->enable) 251 dm->active_vblank_irq_count++; 252 else if (dm->active_vblank_irq_count) 253 dm->active_vblank_irq_count--; 254 255 if (dm->active_vblank_irq_count > 0) 256 dc_allow_idle_optimizations(dm->dc, false); 257 258 /* 259 * Control PSR based on vblank requirements from OS 260 * 261 * If panel supports PSR SU, there's no need to disable PSR when OS is 262 * submitting fast atomic commits (we infer this by whether the OS 263 * requests vblank events). Fast atomic commits will simply trigger a 264 * full-frame-update (FFU); a specific case of selective-update (SU) 265 * where the SU region is the full hactive*vactive region. See 266 * fill_dc_dirty_rects(). 267 */ 268 if (vblank_work->stream && vblank_work->stream->link) { 269 amdgpu_dm_crtc_set_panel_sr_feature( 270 vblank_work, vblank_work->enable, 271 vblank_work->acrtc->dm_irq_params.allow_psr_entry || 272 vblank_work->stream->link->replay_settings.replay_feature_enabled); 273 } 274 275 if (dm->active_vblank_irq_count == 0) 276 dc_allow_idle_optimizations(dm->dc, true); 277 278 mutex_unlock(&dm->dc_lock); 279 280 dc_stream_release(vblank_work->stream); 281 282 kfree(vblank_work); 283 } 284 285 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 286 { 287 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 288 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 289 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 290 struct amdgpu_display_manager *dm = &adev->dm; 291 struct vblank_control_work *work; 292 int irq_type; 293 int rc = 0; 294 295 if (acrtc->otg_inst == -1) 296 goto skip; 297 298 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 299 300 if (enable) { 301 /* vblank irq on -> Only need vupdate irq in vrr mode */ 302 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 303 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 304 } else { 305 /* vblank irq off -> vupdate irq off */ 306 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 307 } 308 309 if (rc) 310 return rc; 311 312 /* crtc vblank or vstartup interrupt */ 313 if (enable) { 314 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type); 315 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc); 316 } else { 317 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type); 318 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc); 319 } 320 321 if (rc) 322 return rc; 323 324 /* 325 * hubp surface flip interrupt 326 * 327 * We have no guarantee that the frontend index maps to the same 328 * backend index - some even map to more than one. 329 * 330 * TODO: Use a different interrupt or check DC itself for the mapping. 331 */ 332 if (enable) { 333 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type); 334 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc); 335 } else { 336 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type); 337 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc); 338 } 339 340 if (rc) 341 return rc; 342 343 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 344 /* crtc vline0 interrupt, only available on DCN+ */ 345 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { 346 if (enable) { 347 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type); 348 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc); 349 } else { 350 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type); 351 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc); 352 } 353 354 if (rc) 355 return rc; 356 } 357 #endif 358 skip: 359 if (amdgpu_in_reset(adev)) 360 return 0; 361 362 if (dm->vblank_control_workqueue) { 363 work = kzalloc(sizeof(*work), GFP_ATOMIC); 364 if (!work) 365 return -ENOMEM; 366 367 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 368 work->dm = dm; 369 work->acrtc = acrtc; 370 work->enable = enable; 371 372 if (acrtc_state->stream) { 373 dc_stream_retain(acrtc_state->stream); 374 work->stream = acrtc_state->stream; 375 } 376 377 queue_work(dm->vblank_control_workqueue, &work->work); 378 } 379 380 return 0; 381 } 382 383 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 384 { 385 return amdgpu_dm_crtc_set_vblank(crtc, true); 386 } 387 388 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 389 { 390 amdgpu_dm_crtc_set_vblank(crtc, false); 391 } 392 393 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 394 struct drm_crtc_state *state) 395 { 396 struct dm_crtc_state *cur = to_dm_crtc_state(state); 397 398 /* TODO Destroy dc_stream objects are stream object is flattened */ 399 if (cur->stream) 400 dc_stream_release(cur->stream); 401 402 403 __drm_atomic_helper_crtc_destroy_state(state); 404 405 406 kfree(state); 407 } 408 409 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 410 { 411 struct dm_crtc_state *state, *cur; 412 413 cur = to_dm_crtc_state(crtc->state); 414 415 if (WARN_ON(!crtc->state)) 416 return NULL; 417 418 state = kzalloc(sizeof(*state), GFP_KERNEL); 419 if (!state) 420 return NULL; 421 422 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 423 424 if (cur->stream) { 425 state->stream = cur->stream; 426 dc_stream_retain(state->stream); 427 } 428 429 state->active_planes = cur->active_planes; 430 state->vrr_infopacket = cur->vrr_infopacket; 431 state->abm_level = cur->abm_level; 432 state->vrr_supported = cur->vrr_supported; 433 state->freesync_config = cur->freesync_config; 434 state->cm_has_degamma = cur->cm_has_degamma; 435 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 436 state->regamma_tf = cur->regamma_tf; 437 state->crc_skip_count = cur->crc_skip_count; 438 state->mpo_requested = cur->mpo_requested; 439 state->cursor_mode = cur->cursor_mode; 440 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 441 442 return &state->base; 443 } 444 445 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 446 { 447 drm_crtc_cleanup(crtc); 448 kfree(crtc); 449 } 450 451 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 452 { 453 struct dm_crtc_state *state; 454 455 if (crtc->state) 456 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 457 458 state = kzalloc(sizeof(*state), GFP_KERNEL); 459 if (WARN_ON(!state)) 460 return; 461 462 __drm_atomic_helper_crtc_reset(crtc, &state->base); 463 } 464 465 #ifdef CONFIG_DEBUG_FS 466 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 467 { 468 crtc_debugfs_init(crtc); 469 470 return 0; 471 } 472 #endif 473 474 #ifdef AMD_PRIVATE_COLOR 475 /** 476 * dm_crtc_additional_color_mgmt - enable additional color properties 477 * @crtc: DRM CRTC 478 * 479 * This function lets the driver enable post-blending CRTC regamma transfer 480 * function property in addition to DRM CRTC gamma LUT. Default value means 481 * linear transfer function, which is the default CRTC gamma LUT behaviour 482 * without this property. 483 */ 484 static void 485 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 486 { 487 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 488 489 if (adev->dm.dc->caps.color.mpc.ogam_ram) 490 drm_object_attach_property(&crtc->base, 491 adev->mode_info.regamma_tf_property, 492 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 493 } 494 495 static int 496 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 497 struct drm_crtc_state *state, 498 struct drm_property *property, 499 uint64_t val) 500 { 501 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 502 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 503 504 if (property == adev->mode_info.regamma_tf_property) { 505 if (acrtc_state->regamma_tf != val) { 506 acrtc_state->regamma_tf = val; 507 acrtc_state->base.color_mgmt_changed |= 1; 508 } 509 } else { 510 drm_dbg_atomic(crtc->dev, 511 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 512 crtc->base.id, crtc->name, 513 property->base.id, property->name); 514 return -EINVAL; 515 } 516 517 return 0; 518 } 519 520 static int 521 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 522 const struct drm_crtc_state *state, 523 struct drm_property *property, 524 uint64_t *val) 525 { 526 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 527 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 528 529 if (property == adev->mode_info.regamma_tf_property) 530 *val = acrtc_state->regamma_tf; 531 else 532 return -EINVAL; 533 534 return 0; 535 } 536 #endif 537 538 /* Implemented only the options currently available for the driver */ 539 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 540 .reset = amdgpu_dm_crtc_reset_state, 541 .destroy = amdgpu_dm_crtc_destroy, 542 .set_config = drm_atomic_helper_set_config, 543 .page_flip = drm_atomic_helper_page_flip, 544 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 545 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 546 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 547 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 548 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 549 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 550 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 551 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 552 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 553 #if defined(CONFIG_DEBUG_FS) 554 .late_register = amdgpu_dm_crtc_late_register, 555 #endif 556 #ifdef AMD_PRIVATE_COLOR 557 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 558 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 559 #endif 560 }; 561 562 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 563 { 564 } 565 566 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 567 { 568 struct drm_atomic_state *state = new_crtc_state->state; 569 struct drm_plane *plane; 570 int num_active = 0; 571 572 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 573 struct drm_plane_state *new_plane_state; 574 575 /* Cursor planes are "fake". */ 576 if (plane->type == DRM_PLANE_TYPE_CURSOR) 577 continue; 578 579 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 580 581 if (!new_plane_state) { 582 /* 583 * The plane is enable on the CRTC and hasn't changed 584 * state. This means that it previously passed 585 * validation and is therefore enabled. 586 */ 587 num_active += 1; 588 continue; 589 } 590 591 /* We need a framebuffer to be considered enabled. */ 592 num_active += (new_plane_state->fb != NULL); 593 } 594 595 return num_active; 596 } 597 598 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 599 struct drm_crtc_state *new_crtc_state) 600 { 601 struct dm_crtc_state *dm_new_crtc_state = 602 to_dm_crtc_state(new_crtc_state); 603 604 dm_new_crtc_state->active_planes = 0; 605 606 if (!dm_new_crtc_state->stream) 607 return; 608 609 dm_new_crtc_state->active_planes = 610 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 611 } 612 613 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 614 const struct drm_display_mode *mode, 615 struct drm_display_mode *adjusted_mode) 616 { 617 return true; 618 } 619 620 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 621 struct drm_atomic_state *state) 622 { 623 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 624 crtc); 625 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 626 struct dc *dc = adev->dm.dc; 627 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 628 int ret = -EINVAL; 629 630 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 631 632 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 633 634 if (WARN_ON(unlikely(!dm_crtc_state->stream && 635 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 636 return ret; 637 } 638 639 /* 640 * We require the primary plane to be enabled whenever the CRTC is, otherwise 641 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 642 * planes are disabled, which is not supported by the hardware. And there is legacy 643 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 644 */ 645 if (crtc_state->enable && 646 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 647 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 648 return -EINVAL; 649 } 650 651 /* 652 * Only allow async flips for fast updates that don't change the FB 653 * pitch, the DCC state, rotation, etc. 654 */ 655 if (crtc_state->async_flip && 656 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 657 drm_dbg_atomic(crtc->dev, 658 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 659 crtc->base.id, crtc->name); 660 return -EINVAL; 661 } 662 663 /* In some use cases, like reset, no stream is attached */ 664 if (!dm_crtc_state->stream) 665 return 0; 666 667 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 668 return 0; 669 670 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 671 return ret; 672 } 673 674 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 675 .disable = amdgpu_dm_crtc_helper_disable, 676 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 677 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 678 .get_scanout_position = amdgpu_crtc_get_scanout_position, 679 }; 680 681 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 682 struct drm_plane *plane, 683 uint32_t crtc_index) 684 { 685 struct amdgpu_crtc *acrtc = NULL; 686 struct drm_plane *cursor_plane; 687 bool is_dcn; 688 int res = -ENOMEM; 689 690 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 691 if (!cursor_plane) 692 goto fail; 693 694 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 695 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 696 697 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 698 if (!acrtc) 699 goto fail; 700 701 res = drm_crtc_init_with_planes( 702 dm->ddev, 703 &acrtc->base, 704 plane, 705 cursor_plane, 706 &amdgpu_dm_crtc_funcs, NULL); 707 708 if (res) 709 goto fail; 710 711 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 712 713 /* Create (reset) the plane state */ 714 if (acrtc->base.funcs->reset) 715 acrtc->base.funcs->reset(&acrtc->base); 716 717 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 718 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 719 720 acrtc->crtc_id = crtc_index; 721 acrtc->base.enabled = false; 722 acrtc->otg_inst = -1; 723 724 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 725 726 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 727 * support programmable degamma anywhere. 728 */ 729 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 730 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 731 true, MAX_COLOR_LUT_ENTRIES); 732 733 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 734 735 #ifdef AMD_PRIVATE_COLOR 736 dm_crtc_additional_color_mgmt(&acrtc->base); 737 #endif 738 return 0; 739 740 fail: 741 kfree(acrtc); 742 kfree(cursor_plane); 743 return res; 744 } 745 746