1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28 
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_crtc.h"
33 #include "amdgpu_dm_plane.h"
34 #include "amdgpu_dm_trace.h"
35 #include "amdgpu_dm_debugfs.h"
36 
37 void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
38 {
39 	struct drm_crtc *crtc = &acrtc->base;
40 	struct drm_device *dev = crtc->dev;
41 	unsigned long flags;
42 
43 	drm_crtc_handle_vblank(crtc);
44 
45 	spin_lock_irqsave(&dev->event_lock, flags);
46 
47 	/* Send completion event for cursor-only commits */
48 	if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
49 		drm_crtc_send_vblank_event(crtc, acrtc->event);
50 		drm_crtc_vblank_put(crtc);
51 		acrtc->event = NULL;
52 	}
53 
54 	spin_unlock_irqrestore(&dev->event_lock, flags);
55 }
56 
57 bool modeset_required(struct drm_crtc_state *crtc_state,
58 			     struct dc_stream_state *new_stream,
59 			     struct dc_stream_state *old_stream)
60 {
61 	return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
62 }
63 
64 bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
65 
66 {
67 	return acrtc->dm_irq_params.freesync_config.state ==
68 		       VRR_STATE_ACTIVE_VARIABLE ||
69 	       acrtc->dm_irq_params.freesync_config.state ==
70 		       VRR_STATE_ACTIVE_FIXED;
71 }
72 
73 int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
74 {
75 	enum dc_irq_source irq_source;
76 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
77 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
78 	int rc;
79 
80 	if (acrtc->otg_inst == -1)
81 		return 0;
82 
83 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
84 
85 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
86 
87 	DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
88 		      acrtc->crtc_id, enable ? "en" : "dis", rc);
89 	return rc;
90 }
91 
92 bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
93 {
94 	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
95 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
96 }
97 
98 static void vblank_control_worker(struct work_struct *work)
99 {
100 	struct vblank_control_work *vblank_work =
101 		container_of(work, struct vblank_control_work, work);
102 	struct amdgpu_display_manager *dm = vblank_work->dm;
103 
104 	mutex_lock(&dm->dc_lock);
105 
106 	if (vblank_work->enable)
107 		dm->active_vblank_irq_count++;
108 	else if (dm->active_vblank_irq_count)
109 		dm->active_vblank_irq_count--;
110 
111 	dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
112 
113 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
114 
115 	/*
116 	 * Control PSR based on vblank requirements from OS
117 	 *
118 	 * If panel supports PSR SU, there's no need to disable PSR when OS is
119 	 * submitting fast atomic commits (we infer this by whether the OS
120 	 * requests vblank events). Fast atomic commits will simply trigger a
121 	 * full-frame-update (FFU); a specific case of selective-update (SU)
122 	 * where the SU region is the full hactive*vactive region. See
123 	 * fill_dc_dirty_rects().
124 	 */
125 	if (vblank_work->stream && vblank_work->stream->link) {
126 		if (vblank_work->enable) {
127 			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
128 			    vblank_work->stream->link->psr_settings.psr_allow_active)
129 				amdgpu_dm_psr_disable(vblank_work->stream);
130 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
131 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
133 			   !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
134 #endif
135 			   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
136 			amdgpu_dm_psr_enable(vblank_work->stream);
137 		}
138 	}
139 
140 	mutex_unlock(&dm->dc_lock);
141 
142 	dc_stream_release(vblank_work->stream);
143 
144 	kfree(vblank_work);
145 }
146 
147 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
148 {
149 	enum dc_irq_source irq_source;
150 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
151 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
152 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
153 	struct amdgpu_display_manager *dm = &adev->dm;
154 	struct vblank_control_work *work;
155 	int rc = 0;
156 
157 	if (acrtc->otg_inst == -1)
158 		goto skip;
159 
160 	if (enable) {
161 		/* vblank irq on -> Only need vupdate irq in vrr mode */
162 		if (amdgpu_dm_vrr_active(acrtc_state))
163 			rc = dm_set_vupdate_irq(crtc, true);
164 	} else {
165 		/* vblank irq off -> vupdate irq off */
166 		rc = dm_set_vupdate_irq(crtc, false);
167 	}
168 
169 	if (rc)
170 		return rc;
171 
172 	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
173 
174 	if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
175 		return -EBUSY;
176 
177 skip:
178 	if (amdgpu_in_reset(adev))
179 		return 0;
180 
181 	if (dm->vblank_control_workqueue) {
182 		work = kzalloc(sizeof(*work), GFP_ATOMIC);
183 		if (!work)
184 			return -ENOMEM;
185 
186 		INIT_WORK(&work->work, vblank_control_worker);
187 		work->dm = dm;
188 		work->acrtc = acrtc;
189 		work->enable = enable;
190 
191 		if (acrtc_state->stream) {
192 			dc_stream_retain(acrtc_state->stream);
193 			work->stream = acrtc_state->stream;
194 		}
195 
196 		queue_work(dm->vblank_control_workqueue, &work->work);
197 	}
198 
199 	return 0;
200 }
201 
202 int dm_enable_vblank(struct drm_crtc *crtc)
203 {
204 	return dm_set_vblank(crtc, true);
205 }
206 
207 void dm_disable_vblank(struct drm_crtc *crtc)
208 {
209 	dm_set_vblank(crtc, false);
210 }
211 
212 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
213 				  struct drm_crtc_state *state)
214 {
215 	struct dm_crtc_state *cur = to_dm_crtc_state(state);
216 
217 	/* TODO Destroy dc_stream objects are stream object is flattened */
218 	if (cur->stream)
219 		dc_stream_release(cur->stream);
220 
221 
222 	__drm_atomic_helper_crtc_destroy_state(state);
223 
224 
225 	kfree(state);
226 }
227 
228 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
229 {
230 	struct dm_crtc_state *state, *cur;
231 
232 	cur = to_dm_crtc_state(crtc->state);
233 
234 	if (WARN_ON(!crtc->state))
235 		return NULL;
236 
237 	state = kzalloc(sizeof(*state), GFP_KERNEL);
238 	if (!state)
239 		return NULL;
240 
241 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
242 
243 	if (cur->stream) {
244 		state->stream = cur->stream;
245 		dc_stream_retain(state->stream);
246 	}
247 
248 	state->active_planes = cur->active_planes;
249 	state->vrr_infopacket = cur->vrr_infopacket;
250 	state->abm_level = cur->abm_level;
251 	state->vrr_supported = cur->vrr_supported;
252 	state->freesync_config = cur->freesync_config;
253 	state->cm_has_degamma = cur->cm_has_degamma;
254 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
255 	state->crc_skip_count = cur->crc_skip_count;
256 	state->mpo_requested = cur->mpo_requested;
257 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
258 
259 	return &state->base;
260 }
261 
262 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
263 {
264 	drm_crtc_cleanup(crtc);
265 	kfree(crtc);
266 }
267 
268 static void dm_crtc_reset_state(struct drm_crtc *crtc)
269 {
270 	struct dm_crtc_state *state;
271 
272 	if (crtc->state)
273 		dm_crtc_destroy_state(crtc, crtc->state);
274 
275 	state = kzalloc(sizeof(*state), GFP_KERNEL);
276 	if (WARN_ON(!state))
277 		return;
278 
279 	__drm_atomic_helper_crtc_reset(crtc, &state->base);
280 }
281 
282 #ifdef CONFIG_DEBUG_FS
283 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
284 {
285 	crtc_debugfs_init(crtc);
286 
287 	return 0;
288 }
289 #endif
290 
291 /* Implemented only the options currently available for the driver */
292 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
293 	.reset = dm_crtc_reset_state,
294 	.destroy = amdgpu_dm_crtc_destroy,
295 	.set_config = drm_atomic_helper_set_config,
296 	.page_flip = drm_atomic_helper_page_flip,
297 	.atomic_duplicate_state = dm_crtc_duplicate_state,
298 	.atomic_destroy_state = dm_crtc_destroy_state,
299 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
300 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
301 	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
302 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
303 	.enable_vblank = dm_enable_vblank,
304 	.disable_vblank = dm_disable_vblank,
305 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
306 #if defined(CONFIG_DEBUG_FS)
307 	.late_register = amdgpu_dm_crtc_late_register,
308 #endif
309 };
310 
311 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
312 {
313 }
314 
315 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
316 {
317 	struct drm_atomic_state *state = new_crtc_state->state;
318 	struct drm_plane *plane;
319 	int num_active = 0;
320 
321 	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
322 		struct drm_plane_state *new_plane_state;
323 
324 		/* Cursor planes are "fake". */
325 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
326 			continue;
327 
328 		new_plane_state = drm_atomic_get_new_plane_state(state, plane);
329 
330 		if (!new_plane_state) {
331 			/*
332 			 * The plane is enable on the CRTC and hasn't changed
333 			 * state. This means that it previously passed
334 			 * validation and is therefore enabled.
335 			 */
336 			num_active += 1;
337 			continue;
338 		}
339 
340 		/* We need a framebuffer to be considered enabled. */
341 		num_active += (new_plane_state->fb != NULL);
342 	}
343 
344 	return num_active;
345 }
346 
347 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
348 					 struct drm_crtc_state *new_crtc_state)
349 {
350 	struct dm_crtc_state *dm_new_crtc_state =
351 		to_dm_crtc_state(new_crtc_state);
352 
353 	dm_new_crtc_state->active_planes = 0;
354 
355 	if (!dm_new_crtc_state->stream)
356 		return;
357 
358 	dm_new_crtc_state->active_planes =
359 		count_crtc_active_planes(new_crtc_state);
360 }
361 
362 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
363 				      const struct drm_display_mode *mode,
364 				      struct drm_display_mode *adjusted_mode)
365 {
366 	return true;
367 }
368 
369 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
370 				      struct drm_atomic_state *state)
371 {
372 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
373 										crtc);
374 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
375 	struct dc *dc = adev->dm.dc;
376 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
377 	int ret = -EINVAL;
378 
379 	trace_amdgpu_dm_crtc_atomic_check(crtc_state);
380 
381 	dm_update_crtc_active_planes(crtc, crtc_state);
382 
383 	if (WARN_ON(unlikely(!dm_crtc_state->stream &&
384 			modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
385 		return ret;
386 	}
387 
388 	/*
389 	 * We require the primary plane to be enabled whenever the CRTC is, otherwise
390 	 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
391 	 * planes are disabled, which is not supported by the hardware. And there is legacy
392 	 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
393 	 */
394 	if (crtc_state->enable &&
395 		!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
396 		DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
397 		return -EINVAL;
398 	}
399 
400 	/* In some use cases, like reset, no stream is attached */
401 	if (!dm_crtc_state->stream)
402 		return 0;
403 
404 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
405 		return 0;
406 
407 	DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
408 	return ret;
409 }
410 
411 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
412 	.disable = dm_crtc_helper_disable,
413 	.atomic_check = dm_crtc_helper_atomic_check,
414 	.mode_fixup = dm_crtc_helper_mode_fixup,
415 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
416 };
417 
418 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
419 			       struct drm_plane *plane,
420 			       uint32_t crtc_index)
421 {
422 	struct amdgpu_crtc *acrtc = NULL;
423 	struct drm_plane *cursor_plane;
424 	bool is_dcn;
425 	int res = -ENOMEM;
426 
427 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
428 	if (!cursor_plane)
429 		goto fail;
430 
431 	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
432 	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
433 
434 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
435 	if (!acrtc)
436 		goto fail;
437 
438 	res = drm_crtc_init_with_planes(
439 			dm->ddev,
440 			&acrtc->base,
441 			plane,
442 			cursor_plane,
443 			&amdgpu_dm_crtc_funcs, NULL);
444 
445 	if (res)
446 		goto fail;
447 
448 	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
449 
450 	/* Create (reset) the plane state */
451 	if (acrtc->base.funcs->reset)
452 		acrtc->base.funcs->reset(&acrtc->base);
453 
454 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
455 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
456 
457 	acrtc->crtc_id = crtc_index;
458 	acrtc->base.enabled = false;
459 	acrtc->otg_inst = -1;
460 
461 	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
462 
463 	/* Don't enable DRM CRTC degamma property for DCE since it doesn't
464 	 * support programmable degamma anywhere.
465 	 */
466 	is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
467 	drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
468 				   true, MAX_COLOR_LUT_ENTRIES);
469 
470 	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
471 
472 	return 0;
473 
474 fail:
475 	kfree(acrtc);
476 	kfree(cursor_plane);
477 	return res;
478 }
479 
480