1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28 
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_crtc.h"
33 #include "amdgpu_dm_plane.h"
34 #include "amdgpu_dm_trace.h"
35 #include "amdgpu_dm_debugfs.h"
36 
37 void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
38 {
39 	struct drm_crtc *crtc = &acrtc->base;
40 	struct drm_device *dev = crtc->dev;
41 	unsigned long flags;
42 
43 	drm_crtc_handle_vblank(crtc);
44 
45 	spin_lock_irqsave(&dev->event_lock, flags);
46 
47 	/* Send completion event for cursor-only commits */
48 	if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
49 		drm_crtc_send_vblank_event(crtc, acrtc->event);
50 		drm_crtc_vblank_put(crtc);
51 		acrtc->event = NULL;
52 	}
53 
54 	spin_unlock_irqrestore(&dev->event_lock, flags);
55 }
56 
57 bool modeset_required(struct drm_crtc_state *crtc_state,
58 			     struct dc_stream_state *new_stream,
59 			     struct dc_stream_state *old_stream)
60 {
61 	return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
62 }
63 
64 bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
65 
66 {
67 	return acrtc->dm_irq_params.freesync_config.state ==
68 		       VRR_STATE_ACTIVE_VARIABLE ||
69 	       acrtc->dm_irq_params.freesync_config.state ==
70 		       VRR_STATE_ACTIVE_FIXED;
71 }
72 
73 int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
74 {
75 	enum dc_irq_source irq_source;
76 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
77 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
78 	int rc;
79 
80 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
81 
82 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
83 
84 	DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
85 		      acrtc->crtc_id, enable ? "en" : "dis", rc);
86 	return rc;
87 }
88 
89 bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
90 {
91 	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
92 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
93 }
94 
95 static void vblank_control_worker(struct work_struct *work)
96 {
97 	struct vblank_control_work *vblank_work =
98 		container_of(work, struct vblank_control_work, work);
99 	struct amdgpu_display_manager *dm = vblank_work->dm;
100 
101 	mutex_lock(&dm->dc_lock);
102 
103 	if (vblank_work->enable)
104 		dm->active_vblank_irq_count++;
105 	else if (dm->active_vblank_irq_count)
106 		dm->active_vblank_irq_count--;
107 
108 	dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
109 
110 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
111 
112 	/*
113 	 * Control PSR based on vblank requirements from OS
114 	 *
115 	 * If panel supports PSR SU, there's no need to disable PSR when OS is
116 	 * submitting fast atomic commits (we infer this by whether the OS
117 	 * requests vblank events). Fast atomic commits will simply trigger a
118 	 * full-frame-update (FFU); a specific case of selective-update (SU)
119 	 * where the SU region is the full hactive*vactive region. See
120 	 * fill_dc_dirty_rects().
121 	 */
122 	if (vblank_work->stream && vblank_work->stream->link) {
123 		if (vblank_work->enable) {
124 			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
125 			    vblank_work->stream->link->psr_settings.psr_allow_active)
126 				amdgpu_dm_psr_disable(vblank_work->stream);
127 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
128 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
129 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
130 			   !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
131 #endif
132 			   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
133 			amdgpu_dm_psr_enable(vblank_work->stream);
134 		}
135 	}
136 
137 	mutex_unlock(&dm->dc_lock);
138 
139 	dc_stream_release(vblank_work->stream);
140 
141 	kfree(vblank_work);
142 }
143 
144 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
145 {
146 	enum dc_irq_source irq_source;
147 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
148 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
149 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
150 	struct amdgpu_display_manager *dm = &adev->dm;
151 	struct vblank_control_work *work;
152 	int rc = 0;
153 
154 	if (enable) {
155 		/* vblank irq on -> Only need vupdate irq in vrr mode */
156 		if (amdgpu_dm_vrr_active(acrtc_state))
157 			rc = dm_set_vupdate_irq(crtc, true);
158 	} else {
159 		/* vblank irq off -> vupdate irq off */
160 		rc = dm_set_vupdate_irq(crtc, false);
161 	}
162 
163 	if (rc)
164 		return rc;
165 
166 	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
167 
168 	if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
169 		return -EBUSY;
170 
171 	if (amdgpu_in_reset(adev))
172 		return 0;
173 
174 	if (dm->vblank_control_workqueue) {
175 		work = kzalloc(sizeof(*work), GFP_ATOMIC);
176 		if (!work)
177 			return -ENOMEM;
178 
179 		INIT_WORK(&work->work, vblank_control_worker);
180 		work->dm = dm;
181 		work->acrtc = acrtc;
182 		work->enable = enable;
183 
184 		if (acrtc_state->stream) {
185 			dc_stream_retain(acrtc_state->stream);
186 			work->stream = acrtc_state->stream;
187 		}
188 
189 		queue_work(dm->vblank_control_workqueue, &work->work);
190 	}
191 
192 	return 0;
193 }
194 
195 int dm_enable_vblank(struct drm_crtc *crtc)
196 {
197 	return dm_set_vblank(crtc, true);
198 }
199 
200 void dm_disable_vblank(struct drm_crtc *crtc)
201 {
202 	dm_set_vblank(crtc, false);
203 }
204 
205 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
206 				  struct drm_crtc_state *state)
207 {
208 	struct dm_crtc_state *cur = to_dm_crtc_state(state);
209 
210 	/* TODO Destroy dc_stream objects are stream object is flattened */
211 	if (cur->stream)
212 		dc_stream_release(cur->stream);
213 
214 
215 	__drm_atomic_helper_crtc_destroy_state(state);
216 
217 
218 	kfree(state);
219 }
220 
221 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
222 {
223 	struct dm_crtc_state *state, *cur;
224 
225 	cur = to_dm_crtc_state(crtc->state);
226 
227 	if (WARN_ON(!crtc->state))
228 		return NULL;
229 
230 	state = kzalloc(sizeof(*state), GFP_KERNEL);
231 	if (!state)
232 		return NULL;
233 
234 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
235 
236 	if (cur->stream) {
237 		state->stream = cur->stream;
238 		dc_stream_retain(state->stream);
239 	}
240 
241 	state->active_planes = cur->active_planes;
242 	state->vrr_infopacket = cur->vrr_infopacket;
243 	state->abm_level = cur->abm_level;
244 	state->vrr_supported = cur->vrr_supported;
245 	state->freesync_config = cur->freesync_config;
246 	state->cm_has_degamma = cur->cm_has_degamma;
247 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
248 	state->crc_skip_count = cur->crc_skip_count;
249 	state->mpo_requested = cur->mpo_requested;
250 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
251 
252 	return &state->base;
253 }
254 
255 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
256 {
257 	drm_crtc_cleanup(crtc);
258 	kfree(crtc);
259 }
260 
261 static void dm_crtc_reset_state(struct drm_crtc *crtc)
262 {
263 	struct dm_crtc_state *state;
264 
265 	if (crtc->state)
266 		dm_crtc_destroy_state(crtc, crtc->state);
267 
268 	state = kzalloc(sizeof(*state), GFP_KERNEL);
269 	if (WARN_ON(!state))
270 		return;
271 
272 	__drm_atomic_helper_crtc_reset(crtc, &state->base);
273 }
274 
275 #ifdef CONFIG_DEBUG_FS
276 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
277 {
278 	crtc_debugfs_init(crtc);
279 
280 	return 0;
281 }
282 #endif
283 
284 /* Implemented only the options currently available for the driver */
285 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
286 	.reset = dm_crtc_reset_state,
287 	.destroy = amdgpu_dm_crtc_destroy,
288 	.set_config = drm_atomic_helper_set_config,
289 	.page_flip = drm_atomic_helper_page_flip,
290 	.atomic_duplicate_state = dm_crtc_duplicate_state,
291 	.atomic_destroy_state = dm_crtc_destroy_state,
292 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
293 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
294 	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
295 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
296 	.enable_vblank = dm_enable_vblank,
297 	.disable_vblank = dm_disable_vblank,
298 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
299 #if defined(CONFIG_DEBUG_FS)
300 	.late_register = amdgpu_dm_crtc_late_register,
301 #endif
302 };
303 
304 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
305 {
306 }
307 
308 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
309 {
310 	struct drm_atomic_state *state = new_crtc_state->state;
311 	struct drm_plane *plane;
312 	int num_active = 0;
313 
314 	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
315 		struct drm_plane_state *new_plane_state;
316 
317 		/* Cursor planes are "fake". */
318 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
319 			continue;
320 
321 		new_plane_state = drm_atomic_get_new_plane_state(state, plane);
322 
323 		if (!new_plane_state) {
324 			/*
325 			 * The plane is enable on the CRTC and hasn't changed
326 			 * state. This means that it previously passed
327 			 * validation and is therefore enabled.
328 			 */
329 			num_active += 1;
330 			continue;
331 		}
332 
333 		/* We need a framebuffer to be considered enabled. */
334 		num_active += (new_plane_state->fb != NULL);
335 	}
336 
337 	return num_active;
338 }
339 
340 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
341 					 struct drm_crtc_state *new_crtc_state)
342 {
343 	struct dm_crtc_state *dm_new_crtc_state =
344 		to_dm_crtc_state(new_crtc_state);
345 
346 	dm_new_crtc_state->active_planes = 0;
347 
348 	if (!dm_new_crtc_state->stream)
349 		return;
350 
351 	dm_new_crtc_state->active_planes =
352 		count_crtc_active_planes(new_crtc_state);
353 }
354 
355 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
356 				      const struct drm_display_mode *mode,
357 				      struct drm_display_mode *adjusted_mode)
358 {
359 	return true;
360 }
361 
362 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
363 				      struct drm_atomic_state *state)
364 {
365 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
366 										crtc);
367 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
368 	struct dc *dc = adev->dm.dc;
369 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
370 	int ret = -EINVAL;
371 
372 	trace_amdgpu_dm_crtc_atomic_check(crtc_state);
373 
374 	dm_update_crtc_active_planes(crtc, crtc_state);
375 
376 	if (WARN_ON(unlikely(!dm_crtc_state->stream &&
377 			modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
378 		return ret;
379 	}
380 
381 	/*
382 	 * We require the primary plane to be enabled whenever the CRTC is, otherwise
383 	 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
384 	 * planes are disabled, which is not supported by the hardware. And there is legacy
385 	 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
386 	 */
387 	if (crtc_state->enable &&
388 		!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
389 		DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
390 		return -EINVAL;
391 	}
392 
393 	/* In some use cases, like reset, no stream is attached */
394 	if (!dm_crtc_state->stream)
395 		return 0;
396 
397 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
398 		return 0;
399 
400 	DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
401 	return ret;
402 }
403 
404 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
405 	.disable = dm_crtc_helper_disable,
406 	.atomic_check = dm_crtc_helper_atomic_check,
407 	.mode_fixup = dm_crtc_helper_mode_fixup,
408 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
409 };
410 
411 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
412 			       struct drm_plane *plane,
413 			       uint32_t crtc_index)
414 {
415 	struct amdgpu_crtc *acrtc = NULL;
416 	struct drm_plane *cursor_plane;
417 	bool is_dcn;
418 	int res = -ENOMEM;
419 
420 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
421 	if (!cursor_plane)
422 		goto fail;
423 
424 	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
425 	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
426 
427 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
428 	if (!acrtc)
429 		goto fail;
430 
431 	res = drm_crtc_init_with_planes(
432 			dm->ddev,
433 			&acrtc->base,
434 			plane,
435 			cursor_plane,
436 			&amdgpu_dm_crtc_funcs, NULL);
437 
438 	if (res)
439 		goto fail;
440 
441 	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
442 
443 	/* Create (reset) the plane state */
444 	if (acrtc->base.funcs->reset)
445 		acrtc->base.funcs->reset(&acrtc->base);
446 
447 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
448 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
449 
450 	acrtc->crtc_id = crtc_index;
451 	acrtc->base.enabled = false;
452 	acrtc->otg_inst = -1;
453 
454 	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
455 
456 	/* Don't enable DRM CRTC degamma property for DCE since it doesn't
457 	 * support programmable degamma anywhere.
458 	 */
459 	is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
460 	drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
461 				   true, MAX_COLOR_LUT_ENTRIES);
462 
463 	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
464 
465 	return 0;
466 
467 fail:
468 	kfree(acrtc);
469 	kfree(cursor_plane);
470 	return res;
471 }
472 
473