1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_replay.h" 33 #include "amdgpu_dm_crtc.h" 34 #include "amdgpu_dm_plane.h" 35 #include "amdgpu_dm_trace.h" 36 #include "amdgpu_dm_debugfs.h" 37 38 #define HPD_DETECTION_PERIOD_uS 5000000 39 #define HPD_DETECTION_TIME_uS 1000 40 41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 42 { 43 struct drm_crtc *crtc = &acrtc->base; 44 struct drm_device *dev = crtc->dev; 45 unsigned long flags; 46 47 drm_crtc_handle_vblank(crtc); 48 49 spin_lock_irqsave(&dev->event_lock, flags); 50 51 /* Send completion event for cursor-only commits */ 52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 53 drm_crtc_send_vblank_event(crtc, acrtc->event); 54 drm_crtc_vblank_put(crtc); 55 acrtc->event = NULL; 56 } 57 58 spin_unlock_irqrestore(&dev->event_lock, flags); 59 } 60 61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 62 struct dc_stream_state *new_stream, 63 struct dc_stream_state *old_stream) 64 { 65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 66 } 67 68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 69 70 { 71 return acrtc->dm_irq_params.freesync_config.state == 72 VRR_STATE_ACTIVE_VARIABLE || 73 acrtc->dm_irq_params.freesync_config.state == 74 VRR_STATE_ACTIVE_FIXED; 75 } 76 77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 78 { 79 enum dc_irq_source irq_source; 80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 81 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 82 int rc; 83 84 if (acrtc->otg_inst == -1) 85 return 0; 86 87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 88 89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 90 91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 92 acrtc->crtc_id, enable ? "en" : "dis", rc); 93 return rc; 94 } 95 96 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 97 { 98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 100 } 101 102 /** 103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. 104 * 105 * @vblank_work: is a pointer to a struct vblank_control_work object. 106 * @vblank_enabled: indicates whether the DRM vblank counter is currently 107 * enabled (true) or disabled (false). 108 * @allow_sr_entry: represents whether entry into the self-refresh mode is 109 * allowed (true) or not allowed (false). 110 * 111 * The DRM vblank counter enable/disable action is used as the trigger to enable 112 * or disable various panel self-refresh features: 113 * 114 * Panel Replay and PSR SU 115 * - Enable when: 116 * - vblank counter is disabled 117 * - entry is allowed: usermode demonstrates an adequate number of fast 118 * commits) 119 * - CRC capture window isn't active 120 * - Keep enabled even when vblank counter gets enabled 121 * 122 * PSR1 123 * - Enable condition same as above 124 * - Disable when vblank counter is enabled 125 */ 126 static void amdgpu_dm_crtc_set_panel_sr_feature( 127 struct vblank_control_work *vblank_work, 128 bool vblank_enabled, bool allow_sr_entry) 129 { 130 struct dc_link *link = vblank_work->stream->link; 131 bool is_sr_active = (link->replay_settings.replay_allow_active || 132 link->psr_settings.psr_allow_active); 133 bool is_crc_window_active = false; 134 135 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 136 is_crc_window_active = 137 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); 138 #endif 139 140 if (link->replay_settings.replay_feature_enabled && 141 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 142 amdgpu_dm_replay_enable(vblank_work->stream, true); 143 } else if (vblank_enabled) { 144 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) 145 amdgpu_dm_psr_disable(vblank_work->stream); 146 } else if (link->psr_settings.psr_feature_enabled && 147 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 148 149 struct amdgpu_dm_connector *aconn = 150 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context; 151 152 if (!aconn->disallow_edp_enter_psr) { 153 struct amdgpu_display_manager *dm = vblank_work->dm; 154 155 amdgpu_dm_psr_enable(vblank_work->stream); 156 if (dm->idle_workqueue && 157 dm->dc->idle_optimizations_allowed && 158 dm->idle_workqueue->enable && 159 !dm->idle_workqueue->running) 160 schedule_work(&dm->idle_workqueue->work); 161 } 162 } 163 } 164 165 static void amdgpu_dm_idle_worker(struct work_struct *work) 166 { 167 struct idle_workqueue *idle_work; 168 169 idle_work = container_of(work, struct idle_workqueue, work); 170 idle_work->dm->idle_workqueue->running = true; 171 fsleep(HPD_DETECTION_PERIOD_uS); 172 mutex_lock(&idle_work->dm->dc_lock); 173 while (idle_work->enable) { 174 if (!idle_work->dm->dc->idle_optimizations_allowed) 175 break; 176 177 dc_allow_idle_optimizations(idle_work->dm->dc, false); 178 179 mutex_unlock(&idle_work->dm->dc_lock); 180 fsleep(HPD_DETECTION_TIME_uS); 181 mutex_lock(&idle_work->dm->dc_lock); 182 183 if (!amdgpu_dm_psr_is_active_allowed(idle_work->dm)) 184 break; 185 186 dc_allow_idle_optimizations(idle_work->dm->dc, true); 187 mutex_unlock(&idle_work->dm->dc_lock); 188 fsleep(HPD_DETECTION_PERIOD_uS); 189 mutex_lock(&idle_work->dm->dc_lock); 190 } 191 mutex_unlock(&idle_work->dm->dc_lock); 192 idle_work->dm->idle_workqueue->running = false; 193 } 194 195 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev) 196 { 197 struct idle_workqueue *idle_work; 198 199 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL); 200 if (ZERO_OR_NULL_PTR(idle_work)) 201 return NULL; 202 203 idle_work->dm = &adev->dm; 204 idle_work->enable = false; 205 idle_work->running = false; 206 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker); 207 208 return idle_work; 209 } 210 211 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 212 { 213 struct vblank_control_work *vblank_work = 214 container_of(work, struct vblank_control_work, work); 215 struct amdgpu_display_manager *dm = vblank_work->dm; 216 217 mutex_lock(&dm->dc_lock); 218 219 if (vblank_work->enable) 220 dm->active_vblank_irq_count++; 221 else if (dm->active_vblank_irq_count) 222 dm->active_vblank_irq_count--; 223 224 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 225 226 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 227 228 /* 229 * Control PSR based on vblank requirements from OS 230 * 231 * If panel supports PSR SU, there's no need to disable PSR when OS is 232 * submitting fast atomic commits (we infer this by whether the OS 233 * requests vblank events). Fast atomic commits will simply trigger a 234 * full-frame-update (FFU); a specific case of selective-update (SU) 235 * where the SU region is the full hactive*vactive region. See 236 * fill_dc_dirty_rects(). 237 */ 238 if (vblank_work->stream && vblank_work->stream->link) { 239 amdgpu_dm_crtc_set_panel_sr_feature( 240 vblank_work, vblank_work->enable, 241 vblank_work->acrtc->dm_irq_params.allow_psr_entry || 242 vblank_work->stream->link->replay_settings.replay_feature_enabled); 243 } 244 245 mutex_unlock(&dm->dc_lock); 246 247 dc_stream_release(vblank_work->stream); 248 249 kfree(vblank_work); 250 } 251 252 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 253 { 254 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 255 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 256 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 257 struct amdgpu_display_manager *dm = &adev->dm; 258 struct vblank_control_work *work; 259 int rc = 0; 260 261 if (acrtc->otg_inst == -1) 262 goto skip; 263 264 if (enable) { 265 /* vblank irq on -> Only need vupdate irq in vrr mode */ 266 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 267 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 268 } else { 269 /* vblank irq off -> vupdate irq off */ 270 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 271 } 272 273 if (rc) 274 return rc; 275 276 rc = (enable) 277 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id) 278 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id); 279 280 if (rc) 281 return rc; 282 283 skip: 284 if (amdgpu_in_reset(adev)) 285 return 0; 286 287 if (dm->vblank_control_workqueue) { 288 work = kzalloc(sizeof(*work), GFP_ATOMIC); 289 if (!work) 290 return -ENOMEM; 291 292 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 293 work->dm = dm; 294 work->acrtc = acrtc; 295 work->enable = enable; 296 297 if (acrtc_state->stream) { 298 dc_stream_retain(acrtc_state->stream); 299 work->stream = acrtc_state->stream; 300 } 301 302 queue_work(dm->vblank_control_workqueue, &work->work); 303 } 304 305 return 0; 306 } 307 308 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 309 { 310 return amdgpu_dm_crtc_set_vblank(crtc, true); 311 } 312 313 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 314 { 315 amdgpu_dm_crtc_set_vblank(crtc, false); 316 } 317 318 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 319 struct drm_crtc_state *state) 320 { 321 struct dm_crtc_state *cur = to_dm_crtc_state(state); 322 323 /* TODO Destroy dc_stream objects are stream object is flattened */ 324 if (cur->stream) 325 dc_stream_release(cur->stream); 326 327 328 __drm_atomic_helper_crtc_destroy_state(state); 329 330 331 kfree(state); 332 } 333 334 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 335 { 336 struct dm_crtc_state *state, *cur; 337 338 cur = to_dm_crtc_state(crtc->state); 339 340 if (WARN_ON(!crtc->state)) 341 return NULL; 342 343 state = kzalloc(sizeof(*state), GFP_KERNEL); 344 if (!state) 345 return NULL; 346 347 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 348 349 if (cur->stream) { 350 state->stream = cur->stream; 351 dc_stream_retain(state->stream); 352 } 353 354 state->active_planes = cur->active_planes; 355 state->vrr_infopacket = cur->vrr_infopacket; 356 state->abm_level = cur->abm_level; 357 state->vrr_supported = cur->vrr_supported; 358 state->freesync_config = cur->freesync_config; 359 state->cm_has_degamma = cur->cm_has_degamma; 360 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 361 state->regamma_tf = cur->regamma_tf; 362 state->crc_skip_count = cur->crc_skip_count; 363 state->mpo_requested = cur->mpo_requested; 364 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 365 366 return &state->base; 367 } 368 369 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 370 { 371 drm_crtc_cleanup(crtc); 372 kfree(crtc); 373 } 374 375 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 376 { 377 struct dm_crtc_state *state; 378 379 if (crtc->state) 380 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 381 382 state = kzalloc(sizeof(*state), GFP_KERNEL); 383 if (WARN_ON(!state)) 384 return; 385 386 __drm_atomic_helper_crtc_reset(crtc, &state->base); 387 } 388 389 #ifdef CONFIG_DEBUG_FS 390 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 391 { 392 crtc_debugfs_init(crtc); 393 394 return 0; 395 } 396 #endif 397 398 #ifdef AMD_PRIVATE_COLOR 399 /** 400 * dm_crtc_additional_color_mgmt - enable additional color properties 401 * @crtc: DRM CRTC 402 * 403 * This function lets the driver enable post-blending CRTC regamma transfer 404 * function property in addition to DRM CRTC gamma LUT. Default value means 405 * linear transfer function, which is the default CRTC gamma LUT behaviour 406 * without this property. 407 */ 408 static void 409 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 410 { 411 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 412 413 if (adev->dm.dc->caps.color.mpc.ogam_ram) 414 drm_object_attach_property(&crtc->base, 415 adev->mode_info.regamma_tf_property, 416 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 417 } 418 419 static int 420 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 421 struct drm_crtc_state *state, 422 struct drm_property *property, 423 uint64_t val) 424 { 425 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 426 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 427 428 if (property == adev->mode_info.regamma_tf_property) { 429 if (acrtc_state->regamma_tf != val) { 430 acrtc_state->regamma_tf = val; 431 acrtc_state->base.color_mgmt_changed |= 1; 432 } 433 } else { 434 drm_dbg_atomic(crtc->dev, 435 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 436 crtc->base.id, crtc->name, 437 property->base.id, property->name); 438 return -EINVAL; 439 } 440 441 return 0; 442 } 443 444 static int 445 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 446 const struct drm_crtc_state *state, 447 struct drm_property *property, 448 uint64_t *val) 449 { 450 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 451 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 452 453 if (property == adev->mode_info.regamma_tf_property) 454 *val = acrtc_state->regamma_tf; 455 else 456 return -EINVAL; 457 458 return 0; 459 } 460 #endif 461 462 /* Implemented only the options currently available for the driver */ 463 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 464 .reset = amdgpu_dm_crtc_reset_state, 465 .destroy = amdgpu_dm_crtc_destroy, 466 .set_config = drm_atomic_helper_set_config, 467 .page_flip = drm_atomic_helper_page_flip, 468 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 469 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 470 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 471 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 472 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 473 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 474 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 475 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 476 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 477 #if defined(CONFIG_DEBUG_FS) 478 .late_register = amdgpu_dm_crtc_late_register, 479 #endif 480 #ifdef AMD_PRIVATE_COLOR 481 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 482 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 483 #endif 484 }; 485 486 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 487 { 488 } 489 490 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 491 { 492 struct drm_atomic_state *state = new_crtc_state->state; 493 struct drm_plane *plane; 494 int num_active = 0; 495 496 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 497 struct drm_plane_state *new_plane_state; 498 499 /* Cursor planes are "fake". */ 500 if (plane->type == DRM_PLANE_TYPE_CURSOR) 501 continue; 502 503 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 504 505 if (!new_plane_state) { 506 /* 507 * The plane is enable on the CRTC and hasn't changed 508 * state. This means that it previously passed 509 * validation and is therefore enabled. 510 */ 511 num_active += 1; 512 continue; 513 } 514 515 /* We need a framebuffer to be considered enabled. */ 516 num_active += (new_plane_state->fb != NULL); 517 } 518 519 return num_active; 520 } 521 522 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 523 struct drm_crtc_state *new_crtc_state) 524 { 525 struct dm_crtc_state *dm_new_crtc_state = 526 to_dm_crtc_state(new_crtc_state); 527 528 dm_new_crtc_state->active_planes = 0; 529 530 if (!dm_new_crtc_state->stream) 531 return; 532 533 dm_new_crtc_state->active_planes = 534 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 535 } 536 537 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 538 const struct drm_display_mode *mode, 539 struct drm_display_mode *adjusted_mode) 540 { 541 return true; 542 } 543 544 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 545 struct drm_atomic_state *state) 546 { 547 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 548 crtc); 549 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 550 struct dc *dc = adev->dm.dc; 551 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 552 int ret = -EINVAL; 553 554 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 555 556 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 557 558 if (WARN_ON(unlikely(!dm_crtc_state->stream && 559 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 560 return ret; 561 } 562 563 /* 564 * We require the primary plane to be enabled whenever the CRTC is, otherwise 565 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 566 * planes are disabled, which is not supported by the hardware. And there is legacy 567 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 568 */ 569 if (crtc_state->enable && 570 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 571 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 572 return -EINVAL; 573 } 574 575 /* 576 * Only allow async flips for fast updates that don't change the FB 577 * pitch, the DCC state, rotation, etc. 578 */ 579 if (crtc_state->async_flip && 580 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 581 drm_dbg_atomic(crtc->dev, 582 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 583 crtc->base.id, crtc->name); 584 return -EINVAL; 585 } 586 587 /* In some use cases, like reset, no stream is attached */ 588 if (!dm_crtc_state->stream) 589 return 0; 590 591 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 592 return 0; 593 594 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 595 return ret; 596 } 597 598 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 599 .disable = amdgpu_dm_crtc_helper_disable, 600 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 601 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 602 .get_scanout_position = amdgpu_crtc_get_scanout_position, 603 }; 604 605 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 606 struct drm_plane *plane, 607 uint32_t crtc_index) 608 { 609 struct amdgpu_crtc *acrtc = NULL; 610 struct drm_plane *cursor_plane; 611 bool is_dcn; 612 int res = -ENOMEM; 613 614 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 615 if (!cursor_plane) 616 goto fail; 617 618 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 619 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 620 621 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 622 if (!acrtc) 623 goto fail; 624 625 res = drm_crtc_init_with_planes( 626 dm->ddev, 627 &acrtc->base, 628 plane, 629 cursor_plane, 630 &amdgpu_dm_crtc_funcs, NULL); 631 632 if (res) 633 goto fail; 634 635 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 636 637 /* Create (reset) the plane state */ 638 if (acrtc->base.funcs->reset) 639 acrtc->base.funcs->reset(&acrtc->base); 640 641 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 642 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 643 644 acrtc->crtc_id = crtc_index; 645 acrtc->base.enabled = false; 646 acrtc->otg_inst = -1; 647 648 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 649 650 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 651 * support programmable degamma anywhere. 652 */ 653 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 654 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 655 true, MAX_COLOR_LUT_ENTRIES); 656 657 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 658 659 #ifdef AMD_PRIVATE_COLOR 660 dm_crtc_additional_color_mgmt(&acrtc->base); 661 #endif 662 return 0; 663 664 fail: 665 kfree(acrtc); 666 kfree(cursor_plane); 667 return res; 668 } 669 670