1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_replay.h" 33 #include "amdgpu_dm_crtc.h" 34 #include "amdgpu_dm_plane.h" 35 #include "amdgpu_dm_trace.h" 36 #include "amdgpu_dm_debugfs.h" 37 38 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 39 { 40 struct drm_crtc *crtc = &acrtc->base; 41 struct drm_device *dev = crtc->dev; 42 unsigned long flags; 43 44 drm_crtc_handle_vblank(crtc); 45 46 spin_lock_irqsave(&dev->event_lock, flags); 47 48 /* Send completion event for cursor-only commits */ 49 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 50 drm_crtc_send_vblank_event(crtc, acrtc->event); 51 drm_crtc_vblank_put(crtc); 52 acrtc->event = NULL; 53 } 54 55 spin_unlock_irqrestore(&dev->event_lock, flags); 56 } 57 58 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 59 struct dc_stream_state *new_stream, 60 struct dc_stream_state *old_stream) 61 { 62 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 63 } 64 65 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 66 67 { 68 return acrtc->dm_irq_params.freesync_config.state == 69 VRR_STATE_ACTIVE_VARIABLE || 70 acrtc->dm_irq_params.freesync_config.state == 71 VRR_STATE_ACTIVE_FIXED; 72 } 73 74 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 75 { 76 enum dc_irq_source irq_source; 77 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 78 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 79 int rc; 80 81 if (acrtc->otg_inst == -1) 82 return 0; 83 84 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 85 86 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 87 88 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 89 acrtc->crtc_id, enable ? "en" : "dis", rc); 90 return rc; 91 } 92 93 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 94 { 95 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 96 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 97 } 98 99 /** 100 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. 101 * 102 * @vblank_work: is a pointer to a struct vblank_control_work object. 103 * @vblank_enabled: indicates whether the DRM vblank counter is currently 104 * enabled (true) or disabled (false). 105 * @allow_sr_entry: represents whether entry into the self-refresh mode is 106 * allowed (true) or not allowed (false). 107 * 108 * The DRM vblank counter enable/disable action is used as the trigger to enable 109 * or disable various panel self-refresh features: 110 * 111 * Panel Replay and PSR SU 112 * - Enable when: 113 * - vblank counter is disabled 114 * - entry is allowed: usermode demonstrates an adequate number of fast 115 * commits) 116 * - CRC capture window isn't active 117 * - Keep enabled even when vblank counter gets enabled 118 * 119 * PSR1 120 * - Enable condition same as above 121 * - Disable when vblank counter is enabled 122 */ 123 static void amdgpu_dm_crtc_set_panel_sr_feature( 124 struct vblank_control_work *vblank_work, 125 bool vblank_enabled, bool allow_sr_entry) 126 { 127 struct dc_link *link = vblank_work->stream->link; 128 bool is_sr_active = (link->replay_settings.replay_allow_active || 129 link->psr_settings.psr_allow_active); 130 bool is_crc_window_active = false; 131 132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 133 is_crc_window_active = 134 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base); 135 #endif 136 137 if (link->replay_settings.replay_feature_enabled && 138 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 139 amdgpu_dm_replay_enable(vblank_work->stream, true); 140 } else if (vblank_enabled) { 141 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) 142 amdgpu_dm_psr_disable(vblank_work->stream); 143 } else if (link->psr_settings.psr_feature_enabled && 144 allow_sr_entry && !is_sr_active && !is_crc_window_active) { 145 amdgpu_dm_psr_enable(vblank_work->stream); 146 } 147 } 148 149 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 150 { 151 struct vblank_control_work *vblank_work = 152 container_of(work, struct vblank_control_work, work); 153 struct amdgpu_display_manager *dm = vblank_work->dm; 154 155 mutex_lock(&dm->dc_lock); 156 157 if (vblank_work->enable) 158 dm->active_vblank_irq_count++; 159 else if (dm->active_vblank_irq_count) 160 dm->active_vblank_irq_count--; 161 162 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 163 164 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 165 166 /* 167 * Control PSR based on vblank requirements from OS 168 * 169 * If panel supports PSR SU, there's no need to disable PSR when OS is 170 * submitting fast atomic commits (we infer this by whether the OS 171 * requests vblank events). Fast atomic commits will simply trigger a 172 * full-frame-update (FFU); a specific case of selective-update (SU) 173 * where the SU region is the full hactive*vactive region. See 174 * fill_dc_dirty_rects(). 175 */ 176 if (vblank_work->stream && vblank_work->stream->link) { 177 amdgpu_dm_crtc_set_panel_sr_feature( 178 vblank_work, vblank_work->enable, 179 vblank_work->acrtc->dm_irq_params.allow_psr_entry || 180 vblank_work->stream->link->replay_settings.replay_feature_enabled); 181 } 182 183 mutex_unlock(&dm->dc_lock); 184 185 dc_stream_release(vblank_work->stream); 186 187 kfree(vblank_work); 188 } 189 190 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 191 { 192 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 193 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 194 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 195 struct amdgpu_display_manager *dm = &adev->dm; 196 struct vblank_control_work *work; 197 int rc = 0; 198 199 if (acrtc->otg_inst == -1) 200 goto skip; 201 202 if (enable) { 203 /* vblank irq on -> Only need vupdate irq in vrr mode */ 204 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 205 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 206 } else { 207 /* vblank irq off -> vupdate irq off */ 208 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 209 } 210 211 if (rc) 212 return rc; 213 214 rc = (enable) 215 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id) 216 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id); 217 218 if (rc) 219 return rc; 220 221 skip: 222 if (amdgpu_in_reset(adev)) 223 return 0; 224 225 if (dm->vblank_control_workqueue) { 226 work = kzalloc(sizeof(*work), GFP_ATOMIC); 227 if (!work) 228 return -ENOMEM; 229 230 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 231 work->dm = dm; 232 work->acrtc = acrtc; 233 work->enable = enable; 234 235 if (acrtc_state->stream) { 236 dc_stream_retain(acrtc_state->stream); 237 work->stream = acrtc_state->stream; 238 } 239 240 queue_work(dm->vblank_control_workqueue, &work->work); 241 } 242 243 return 0; 244 } 245 246 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 247 { 248 return amdgpu_dm_crtc_set_vblank(crtc, true); 249 } 250 251 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 252 { 253 amdgpu_dm_crtc_set_vblank(crtc, false); 254 } 255 256 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 257 struct drm_crtc_state *state) 258 { 259 struct dm_crtc_state *cur = to_dm_crtc_state(state); 260 261 /* TODO Destroy dc_stream objects are stream object is flattened */ 262 if (cur->stream) 263 dc_stream_release(cur->stream); 264 265 266 __drm_atomic_helper_crtc_destroy_state(state); 267 268 269 kfree(state); 270 } 271 272 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 273 { 274 struct dm_crtc_state *state, *cur; 275 276 cur = to_dm_crtc_state(crtc->state); 277 278 if (WARN_ON(!crtc->state)) 279 return NULL; 280 281 state = kzalloc(sizeof(*state), GFP_KERNEL); 282 if (!state) 283 return NULL; 284 285 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 286 287 if (cur->stream) { 288 state->stream = cur->stream; 289 dc_stream_retain(state->stream); 290 } 291 292 state->active_planes = cur->active_planes; 293 state->vrr_infopacket = cur->vrr_infopacket; 294 state->abm_level = cur->abm_level; 295 state->vrr_supported = cur->vrr_supported; 296 state->freesync_config = cur->freesync_config; 297 state->cm_has_degamma = cur->cm_has_degamma; 298 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 299 state->regamma_tf = cur->regamma_tf; 300 state->crc_skip_count = cur->crc_skip_count; 301 state->mpo_requested = cur->mpo_requested; 302 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 303 304 return &state->base; 305 } 306 307 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 308 { 309 drm_crtc_cleanup(crtc); 310 kfree(crtc); 311 } 312 313 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 314 { 315 struct dm_crtc_state *state; 316 317 if (crtc->state) 318 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 319 320 state = kzalloc(sizeof(*state), GFP_KERNEL); 321 if (WARN_ON(!state)) 322 return; 323 324 __drm_atomic_helper_crtc_reset(crtc, &state->base); 325 } 326 327 #ifdef CONFIG_DEBUG_FS 328 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 329 { 330 crtc_debugfs_init(crtc); 331 332 return 0; 333 } 334 #endif 335 336 #ifdef AMD_PRIVATE_COLOR 337 /** 338 * dm_crtc_additional_color_mgmt - enable additional color properties 339 * @crtc: DRM CRTC 340 * 341 * This function lets the driver enable post-blending CRTC regamma transfer 342 * function property in addition to DRM CRTC gamma LUT. Default value means 343 * linear transfer function, which is the default CRTC gamma LUT behaviour 344 * without this property. 345 */ 346 static void 347 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 348 { 349 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 350 351 if (adev->dm.dc->caps.color.mpc.ogam_ram) 352 drm_object_attach_property(&crtc->base, 353 adev->mode_info.regamma_tf_property, 354 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 355 } 356 357 static int 358 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 359 struct drm_crtc_state *state, 360 struct drm_property *property, 361 uint64_t val) 362 { 363 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 364 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 365 366 if (property == adev->mode_info.regamma_tf_property) { 367 if (acrtc_state->regamma_tf != val) { 368 acrtc_state->regamma_tf = val; 369 acrtc_state->base.color_mgmt_changed |= 1; 370 } 371 } else { 372 drm_dbg_atomic(crtc->dev, 373 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 374 crtc->base.id, crtc->name, 375 property->base.id, property->name); 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static int 383 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 384 const struct drm_crtc_state *state, 385 struct drm_property *property, 386 uint64_t *val) 387 { 388 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 389 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 390 391 if (property == adev->mode_info.regamma_tf_property) 392 *val = acrtc_state->regamma_tf; 393 else 394 return -EINVAL; 395 396 return 0; 397 } 398 #endif 399 400 /* Implemented only the options currently available for the driver */ 401 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 402 .reset = amdgpu_dm_crtc_reset_state, 403 .destroy = amdgpu_dm_crtc_destroy, 404 .set_config = drm_atomic_helper_set_config, 405 .page_flip = drm_atomic_helper_page_flip, 406 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 407 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 408 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 409 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 410 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 411 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 412 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 413 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 414 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 415 #if defined(CONFIG_DEBUG_FS) 416 .late_register = amdgpu_dm_crtc_late_register, 417 #endif 418 #ifdef AMD_PRIVATE_COLOR 419 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 420 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 421 #endif 422 }; 423 424 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 425 { 426 } 427 428 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 429 { 430 struct drm_atomic_state *state = new_crtc_state->state; 431 struct drm_plane *plane; 432 int num_active = 0; 433 434 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 435 struct drm_plane_state *new_plane_state; 436 437 /* Cursor planes are "fake". */ 438 if (plane->type == DRM_PLANE_TYPE_CURSOR) 439 continue; 440 441 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 442 443 if (!new_plane_state) { 444 /* 445 * The plane is enable on the CRTC and hasn't changed 446 * state. This means that it previously passed 447 * validation and is therefore enabled. 448 */ 449 num_active += 1; 450 continue; 451 } 452 453 /* We need a framebuffer to be considered enabled. */ 454 num_active += (new_plane_state->fb != NULL); 455 } 456 457 return num_active; 458 } 459 460 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 461 struct drm_crtc_state *new_crtc_state) 462 { 463 struct dm_crtc_state *dm_new_crtc_state = 464 to_dm_crtc_state(new_crtc_state); 465 466 dm_new_crtc_state->active_planes = 0; 467 468 if (!dm_new_crtc_state->stream) 469 return; 470 471 dm_new_crtc_state->active_planes = 472 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 473 } 474 475 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 476 const struct drm_display_mode *mode, 477 struct drm_display_mode *adjusted_mode) 478 { 479 return true; 480 } 481 482 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 483 struct drm_atomic_state *state) 484 { 485 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 486 crtc); 487 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 488 struct dc *dc = adev->dm.dc; 489 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 490 int ret = -EINVAL; 491 492 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 493 494 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 495 496 if (WARN_ON(unlikely(!dm_crtc_state->stream && 497 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 498 return ret; 499 } 500 501 /* 502 * We require the primary plane to be enabled whenever the CRTC is, otherwise 503 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 504 * planes are disabled, which is not supported by the hardware. And there is legacy 505 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 506 */ 507 if (crtc_state->enable && 508 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 509 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 510 return -EINVAL; 511 } 512 513 /* 514 * Only allow async flips for fast updates that don't change the FB 515 * pitch, the DCC state, rotation, etc. 516 */ 517 if (crtc_state->async_flip && 518 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 519 drm_dbg_atomic(crtc->dev, 520 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 521 crtc->base.id, crtc->name); 522 return -EINVAL; 523 } 524 525 /* In some use cases, like reset, no stream is attached */ 526 if (!dm_crtc_state->stream) 527 return 0; 528 529 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 530 return 0; 531 532 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 533 return ret; 534 } 535 536 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 537 .disable = amdgpu_dm_crtc_helper_disable, 538 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 539 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 540 .get_scanout_position = amdgpu_crtc_get_scanout_position, 541 }; 542 543 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 544 struct drm_plane *plane, 545 uint32_t crtc_index) 546 { 547 struct amdgpu_crtc *acrtc = NULL; 548 struct drm_plane *cursor_plane; 549 bool is_dcn; 550 int res = -ENOMEM; 551 552 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 553 if (!cursor_plane) 554 goto fail; 555 556 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 557 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 558 559 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 560 if (!acrtc) 561 goto fail; 562 563 res = drm_crtc_init_with_planes( 564 dm->ddev, 565 &acrtc->base, 566 plane, 567 cursor_plane, 568 &amdgpu_dm_crtc_funcs, NULL); 569 570 if (res) 571 goto fail; 572 573 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 574 575 /* Create (reset) the plane state */ 576 if (acrtc->base.funcs->reset) 577 acrtc->base.funcs->reset(&acrtc->base); 578 579 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 580 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 581 582 acrtc->crtc_id = crtc_index; 583 acrtc->base.enabled = false; 584 acrtc->otg_inst = -1; 585 586 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 587 588 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 589 * support programmable degamma anywhere. 590 */ 591 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 592 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 593 true, MAX_COLOR_LUT_ENTRIES); 594 595 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 596 597 #ifdef AMD_PRIVATE_COLOR 598 dm_crtc_additional_color_mgmt(&acrtc->base); 599 #endif 600 return 0; 601 602 fail: 603 kfree(acrtc); 604 kfree(cursor_plane); 605 return res; 606 } 607 608