1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28 
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_crtc.h"
33 #include "amdgpu_dm_plane.h"
34 #include "amdgpu_dm_trace.h"
35 #include "amdgpu_dm_debugfs.h"
36 
37 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
38 {
39 	struct drm_crtc *crtc = &acrtc->base;
40 	struct drm_device *dev = crtc->dev;
41 	unsigned long flags;
42 
43 	drm_crtc_handle_vblank(crtc);
44 
45 	spin_lock_irqsave(&dev->event_lock, flags);
46 
47 	/* Send completion event for cursor-only commits */
48 	if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
49 		drm_crtc_send_vblank_event(crtc, acrtc->event);
50 		drm_crtc_vblank_put(crtc);
51 		acrtc->event = NULL;
52 	}
53 
54 	spin_unlock_irqrestore(&dev->event_lock, flags);
55 }
56 
57 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
58 			     struct dc_stream_state *new_stream,
59 			     struct dc_stream_state *old_stream)
60 {
61 	return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
62 }
63 
64 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
65 
66 {
67 	return acrtc->dm_irq_params.freesync_config.state ==
68 		       VRR_STATE_ACTIVE_VARIABLE ||
69 	       acrtc->dm_irq_params.freesync_config.state ==
70 		       VRR_STATE_ACTIVE_FIXED;
71 }
72 
73 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
74 {
75 	enum dc_irq_source irq_source;
76 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
77 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
78 	int rc;
79 
80 	if (acrtc->otg_inst == -1)
81 		return 0;
82 
83 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
84 
85 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
86 
87 	DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
88 		      acrtc->crtc_id, enable ? "en" : "dis", rc);
89 	return rc;
90 }
91 
92 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
93 {
94 	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
95 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
96 }
97 
98 static void vblank_control_worker(struct work_struct *work)
99 {
100 	struct vblank_control_work *vblank_work =
101 		container_of(work, struct vblank_control_work, work);
102 	struct amdgpu_display_manager *dm = vblank_work->dm;
103 
104 	mutex_lock(&dm->dc_lock);
105 
106 	if (vblank_work->enable)
107 		dm->active_vblank_irq_count++;
108 	else if (dm->active_vblank_irq_count)
109 		dm->active_vblank_irq_count--;
110 
111 	dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
112 
113 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
114 
115 	/*
116 	 * Control PSR based on vblank requirements from OS
117 	 *
118 	 * If panel supports PSR SU, there's no need to disable PSR when OS is
119 	 * submitting fast atomic commits (we infer this by whether the OS
120 	 * requests vblank events). Fast atomic commits will simply trigger a
121 	 * full-frame-update (FFU); a specific case of selective-update (SU)
122 	 * where the SU region is the full hactive*vactive region. See
123 	 * fill_dc_dirty_rects().
124 	 */
125 	if (vblank_work->stream && vblank_work->stream->link) {
126 		if (vblank_work->enable) {
127 			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
128 			    vblank_work->stream->link->psr_settings.psr_allow_active)
129 				amdgpu_dm_psr_disable(vblank_work->stream);
130 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
131 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
133 			   !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
134 #endif
135 			   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
136 			amdgpu_dm_psr_enable(vblank_work->stream);
137 		}
138 	}
139 
140 	mutex_unlock(&dm->dc_lock);
141 
142 	dc_stream_release(vblank_work->stream);
143 
144 	kfree(vblank_work);
145 }
146 
147 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
148 {
149 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
150 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
151 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
152 	struct amdgpu_display_manager *dm = &adev->dm;
153 	struct vblank_control_work *work;
154 	int rc = 0;
155 
156 	if (acrtc->otg_inst == -1)
157 		goto skip;
158 
159 	if (enable) {
160 		/* vblank irq on -> Only need vupdate irq in vrr mode */
161 		if (amdgpu_dm_crtc_vrr_active(acrtc_state))
162 			rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
163 	} else {
164 		/* vblank irq off -> vupdate irq off */
165 		rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
166 	}
167 
168 	if (rc)
169 		return rc;
170 
171 	rc = (enable)
172 		? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
173 		: amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
174 
175 	if (rc)
176 		return rc;
177 
178 skip:
179 	if (amdgpu_in_reset(adev))
180 		return 0;
181 
182 	if (dm->vblank_control_workqueue) {
183 		work = kzalloc(sizeof(*work), GFP_ATOMIC);
184 		if (!work)
185 			return -ENOMEM;
186 
187 		INIT_WORK(&work->work, vblank_control_worker);
188 		work->dm = dm;
189 		work->acrtc = acrtc;
190 		work->enable = enable;
191 
192 		if (acrtc_state->stream) {
193 			dc_stream_retain(acrtc_state->stream);
194 			work->stream = acrtc_state->stream;
195 		}
196 
197 		queue_work(dm->vblank_control_workqueue, &work->work);
198 	}
199 
200 	return 0;
201 }
202 
203 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
204 {
205 	return dm_set_vblank(crtc, true);
206 }
207 
208 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
209 {
210 	dm_set_vblank(crtc, false);
211 }
212 
213 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
214 				  struct drm_crtc_state *state)
215 {
216 	struct dm_crtc_state *cur = to_dm_crtc_state(state);
217 
218 	/* TODO Destroy dc_stream objects are stream object is flattened */
219 	if (cur->stream)
220 		dc_stream_release(cur->stream);
221 
222 
223 	__drm_atomic_helper_crtc_destroy_state(state);
224 
225 
226 	kfree(state);
227 }
228 
229 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
230 {
231 	struct dm_crtc_state *state, *cur;
232 
233 	cur = to_dm_crtc_state(crtc->state);
234 
235 	if (WARN_ON(!crtc->state))
236 		return NULL;
237 
238 	state = kzalloc(sizeof(*state), GFP_KERNEL);
239 	if (!state)
240 		return NULL;
241 
242 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
243 
244 	if (cur->stream) {
245 		state->stream = cur->stream;
246 		dc_stream_retain(state->stream);
247 	}
248 
249 	state->active_planes = cur->active_planes;
250 	state->vrr_infopacket = cur->vrr_infopacket;
251 	state->abm_level = cur->abm_level;
252 	state->vrr_supported = cur->vrr_supported;
253 	state->freesync_config = cur->freesync_config;
254 	state->cm_has_degamma = cur->cm_has_degamma;
255 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
256 	state->crc_skip_count = cur->crc_skip_count;
257 	state->mpo_requested = cur->mpo_requested;
258 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
259 
260 	return &state->base;
261 }
262 
263 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
264 {
265 	drm_crtc_cleanup(crtc);
266 	kfree(crtc);
267 }
268 
269 static void dm_crtc_reset_state(struct drm_crtc *crtc)
270 {
271 	struct dm_crtc_state *state;
272 
273 	if (crtc->state)
274 		dm_crtc_destroy_state(crtc, crtc->state);
275 
276 	state = kzalloc(sizeof(*state), GFP_KERNEL);
277 	if (WARN_ON(!state))
278 		return;
279 
280 	__drm_atomic_helper_crtc_reset(crtc, &state->base);
281 }
282 
283 #ifdef CONFIG_DEBUG_FS
284 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
285 {
286 	crtc_debugfs_init(crtc);
287 
288 	return 0;
289 }
290 #endif
291 
292 /* Implemented only the options currently available for the driver */
293 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
294 	.reset = dm_crtc_reset_state,
295 	.destroy = amdgpu_dm_crtc_destroy,
296 	.set_config = drm_atomic_helper_set_config,
297 	.page_flip = drm_atomic_helper_page_flip,
298 	.atomic_duplicate_state = dm_crtc_duplicate_state,
299 	.atomic_destroy_state = dm_crtc_destroy_state,
300 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
301 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
302 	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
303 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
304 	.enable_vblank = amdgpu_dm_crtc_enable_vblank,
305 	.disable_vblank = amdgpu_dm_crtc_disable_vblank,
306 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
307 #if defined(CONFIG_DEBUG_FS)
308 	.late_register = amdgpu_dm_crtc_late_register,
309 #endif
310 };
311 
312 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
313 {
314 }
315 
316 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
317 {
318 	struct drm_atomic_state *state = new_crtc_state->state;
319 	struct drm_plane *plane;
320 	int num_active = 0;
321 
322 	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
323 		struct drm_plane_state *new_plane_state;
324 
325 		/* Cursor planes are "fake". */
326 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
327 			continue;
328 
329 		new_plane_state = drm_atomic_get_new_plane_state(state, plane);
330 
331 		if (!new_plane_state) {
332 			/*
333 			 * The plane is enable on the CRTC and hasn't changed
334 			 * state. This means that it previously passed
335 			 * validation and is therefore enabled.
336 			 */
337 			num_active += 1;
338 			continue;
339 		}
340 
341 		/* We need a framebuffer to be considered enabled. */
342 		num_active += (new_plane_state->fb != NULL);
343 	}
344 
345 	return num_active;
346 }
347 
348 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
349 					 struct drm_crtc_state *new_crtc_state)
350 {
351 	struct dm_crtc_state *dm_new_crtc_state =
352 		to_dm_crtc_state(new_crtc_state);
353 
354 	dm_new_crtc_state->active_planes = 0;
355 
356 	if (!dm_new_crtc_state->stream)
357 		return;
358 
359 	dm_new_crtc_state->active_planes =
360 		count_crtc_active_planes(new_crtc_state);
361 }
362 
363 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
364 				      const struct drm_display_mode *mode,
365 				      struct drm_display_mode *adjusted_mode)
366 {
367 	return true;
368 }
369 
370 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
371 				      struct drm_atomic_state *state)
372 {
373 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
374 										crtc);
375 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
376 	struct dc *dc = adev->dm.dc;
377 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
378 	int ret = -EINVAL;
379 
380 	trace_amdgpu_dm_crtc_atomic_check(crtc_state);
381 
382 	dm_update_crtc_active_planes(crtc, crtc_state);
383 
384 	if (WARN_ON(unlikely(!dm_crtc_state->stream &&
385 			amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
386 		return ret;
387 	}
388 
389 	/*
390 	 * We require the primary plane to be enabled whenever the CRTC is, otherwise
391 	 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
392 	 * planes are disabled, which is not supported by the hardware. And there is legacy
393 	 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
394 	 */
395 	if (crtc_state->enable &&
396 		!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
397 		DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
398 		return -EINVAL;
399 	}
400 
401 	/* In some use cases, like reset, no stream is attached */
402 	if (!dm_crtc_state->stream)
403 		return 0;
404 
405 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
406 		return 0;
407 
408 	DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
409 	return ret;
410 }
411 
412 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
413 	.disable = dm_crtc_helper_disable,
414 	.atomic_check = dm_crtc_helper_atomic_check,
415 	.mode_fixup = dm_crtc_helper_mode_fixup,
416 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
417 };
418 
419 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
420 			       struct drm_plane *plane,
421 			       uint32_t crtc_index)
422 {
423 	struct amdgpu_crtc *acrtc = NULL;
424 	struct drm_plane *cursor_plane;
425 	bool is_dcn;
426 	int res = -ENOMEM;
427 
428 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
429 	if (!cursor_plane)
430 		goto fail;
431 
432 	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
433 	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
434 
435 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
436 	if (!acrtc)
437 		goto fail;
438 
439 	res = drm_crtc_init_with_planes(
440 			dm->ddev,
441 			&acrtc->base,
442 			plane,
443 			cursor_plane,
444 			&amdgpu_dm_crtc_funcs, NULL);
445 
446 	if (res)
447 		goto fail;
448 
449 	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
450 
451 	/* Create (reset) the plane state */
452 	if (acrtc->base.funcs->reset)
453 		acrtc->base.funcs->reset(&acrtc->base);
454 
455 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
456 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
457 
458 	acrtc->crtc_id = crtc_index;
459 	acrtc->base.enabled = false;
460 	acrtc->otg_inst = -1;
461 
462 	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
463 
464 	/* Don't enable DRM CRTC degamma property for DCE since it doesn't
465 	 * support programmable degamma anywhere.
466 	 */
467 	is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
468 	drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
469 				   true, MAX_COLOR_LUT_ENTRIES);
470 
471 	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
472 
473 	return 0;
474 
475 fail:
476 	kfree(acrtc);
477 	kfree(cursor_plane);
478 	return res;
479 }
480 
481