1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_crtc.h" 33 #include "amdgpu_dm_plane.h" 34 #include "amdgpu_dm_trace.h" 35 #include "amdgpu_dm_debugfs.h" 36 37 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 38 { 39 struct drm_crtc *crtc = &acrtc->base; 40 struct drm_device *dev = crtc->dev; 41 unsigned long flags; 42 43 drm_crtc_handle_vblank(crtc); 44 45 spin_lock_irqsave(&dev->event_lock, flags); 46 47 /* Send completion event for cursor-only commits */ 48 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 49 drm_crtc_send_vblank_event(crtc, acrtc->event); 50 drm_crtc_vblank_put(crtc); 51 acrtc->event = NULL; 52 } 53 54 spin_unlock_irqrestore(&dev->event_lock, flags); 55 } 56 57 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, 58 struct dc_stream_state *new_stream, 59 struct dc_stream_state *old_stream) 60 { 61 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 62 } 63 64 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) 65 66 { 67 return acrtc->dm_irq_params.freesync_config.state == 68 VRR_STATE_ACTIVE_VARIABLE || 69 acrtc->dm_irq_params.freesync_config.state == 70 VRR_STATE_ACTIVE_FIXED; 71 } 72 73 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 74 { 75 enum dc_irq_source irq_source; 76 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 77 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 78 int rc; 79 80 if (acrtc->otg_inst == -1) 81 return 0; 82 83 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 84 85 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 86 87 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 88 acrtc->crtc_id, enable ? "en" : "dis", rc); 89 return rc; 90 } 91 92 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state) 93 { 94 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 95 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 96 } 97 98 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) 99 { 100 struct vblank_control_work *vblank_work = 101 container_of(work, struct vblank_control_work, work); 102 struct amdgpu_display_manager *dm = vblank_work->dm; 103 104 mutex_lock(&dm->dc_lock); 105 106 if (vblank_work->enable) 107 dm->active_vblank_irq_count++; 108 else if (dm->active_vblank_irq_count) 109 dm->active_vblank_irq_count--; 110 111 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 112 113 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 114 115 /* 116 * Control PSR based on vblank requirements from OS 117 * 118 * If panel supports PSR SU, there's no need to disable PSR when OS is 119 * submitting fast atomic commits (we infer this by whether the OS 120 * requests vblank events). Fast atomic commits will simply trigger a 121 * full-frame-update (FFU); a specific case of selective-update (SU) 122 * where the SU region is the full hactive*vactive region. See 123 * fill_dc_dirty_rects(). 124 */ 125 if (vblank_work->stream && vblank_work->stream->link) { 126 if (vblank_work->enable) { 127 if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && 128 vblank_work->stream->link->psr_settings.psr_allow_active) 129 amdgpu_dm_psr_disable(vblank_work->stream); 130 } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && 131 !vblank_work->stream->link->psr_settings.psr_allow_active && 132 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 133 !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) && 134 #endif 135 vblank_work->acrtc->dm_irq_params.allow_psr_entry) { 136 amdgpu_dm_psr_enable(vblank_work->stream); 137 } 138 } 139 140 mutex_unlock(&dm->dc_lock); 141 142 dc_stream_release(vblank_work->stream); 143 144 kfree(vblank_work); 145 } 146 147 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 148 { 149 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 150 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 151 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 152 struct amdgpu_display_manager *dm = &adev->dm; 153 struct vblank_control_work *work; 154 int rc = 0; 155 156 if (acrtc->otg_inst == -1) 157 goto skip; 158 159 if (enable) { 160 /* vblank irq on -> Only need vupdate irq in vrr mode */ 161 if (amdgpu_dm_crtc_vrr_active(acrtc_state)) 162 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); 163 } else { 164 /* vblank irq off -> vupdate irq off */ 165 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); 166 } 167 168 if (rc) 169 return rc; 170 171 rc = (enable) 172 ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id) 173 : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id); 174 175 if (rc) 176 return rc; 177 178 skip: 179 if (amdgpu_in_reset(adev)) 180 return 0; 181 182 if (dm->vblank_control_workqueue) { 183 work = kzalloc(sizeof(*work), GFP_ATOMIC); 184 if (!work) 185 return -ENOMEM; 186 187 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); 188 work->dm = dm; 189 work->acrtc = acrtc; 190 work->enable = enable; 191 192 if (acrtc_state->stream) { 193 dc_stream_retain(acrtc_state->stream); 194 work->stream = acrtc_state->stream; 195 } 196 197 queue_work(dm->vblank_control_workqueue, &work->work); 198 } 199 200 return 0; 201 } 202 203 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) 204 { 205 return amdgpu_dm_crtc_set_vblank(crtc, true); 206 } 207 208 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) 209 { 210 amdgpu_dm_crtc_set_vblank(crtc, false); 211 } 212 213 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, 214 struct drm_crtc_state *state) 215 { 216 struct dm_crtc_state *cur = to_dm_crtc_state(state); 217 218 /* TODO Destroy dc_stream objects are stream object is flattened */ 219 if (cur->stream) 220 dc_stream_release(cur->stream); 221 222 223 __drm_atomic_helper_crtc_destroy_state(state); 224 225 226 kfree(state); 227 } 228 229 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) 230 { 231 struct dm_crtc_state *state, *cur; 232 233 cur = to_dm_crtc_state(crtc->state); 234 235 if (WARN_ON(!crtc->state)) 236 return NULL; 237 238 state = kzalloc(sizeof(*state), GFP_KERNEL); 239 if (!state) 240 return NULL; 241 242 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 243 244 if (cur->stream) { 245 state->stream = cur->stream; 246 dc_stream_retain(state->stream); 247 } 248 249 state->active_planes = cur->active_planes; 250 state->vrr_infopacket = cur->vrr_infopacket; 251 state->abm_level = cur->abm_level; 252 state->vrr_supported = cur->vrr_supported; 253 state->freesync_config = cur->freesync_config; 254 state->cm_has_degamma = cur->cm_has_degamma; 255 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 256 state->regamma_tf = cur->regamma_tf; 257 state->crc_skip_count = cur->crc_skip_count; 258 state->mpo_requested = cur->mpo_requested; 259 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 260 261 return &state->base; 262 } 263 264 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 265 { 266 drm_crtc_cleanup(crtc); 267 kfree(crtc); 268 } 269 270 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) 271 { 272 struct dm_crtc_state *state; 273 274 if (crtc->state) 275 amdgpu_dm_crtc_destroy_state(crtc, crtc->state); 276 277 state = kzalloc(sizeof(*state), GFP_KERNEL); 278 if (WARN_ON(!state)) 279 return; 280 281 __drm_atomic_helper_crtc_reset(crtc, &state->base); 282 } 283 284 #ifdef CONFIG_DEBUG_FS 285 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 286 { 287 crtc_debugfs_init(crtc); 288 289 return 0; 290 } 291 #endif 292 293 #ifdef AMD_PRIVATE_COLOR 294 /** 295 * dm_crtc_additional_color_mgmt - enable additional color properties 296 * @crtc: DRM CRTC 297 * 298 * This function lets the driver enable post-blending CRTC regamma transfer 299 * function property in addition to DRM CRTC gamma LUT. Default value means 300 * linear transfer function, which is the default CRTC gamma LUT behaviour 301 * without this property. 302 */ 303 static void 304 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) 305 { 306 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 307 308 if (adev->dm.dc->caps.color.mpc.ogam_ram) 309 drm_object_attach_property(&crtc->base, 310 adev->mode_info.regamma_tf_property, 311 AMDGPU_TRANSFER_FUNCTION_DEFAULT); 312 } 313 314 static int 315 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, 316 struct drm_crtc_state *state, 317 struct drm_property *property, 318 uint64_t val) 319 { 320 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 321 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 322 323 if (property == adev->mode_info.regamma_tf_property) { 324 if (acrtc_state->regamma_tf != val) { 325 acrtc_state->regamma_tf = val; 326 acrtc_state->base.color_mgmt_changed |= 1; 327 } 328 } else { 329 drm_dbg_atomic(crtc->dev, 330 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", 331 crtc->base.id, crtc->name, 332 property->base.id, property->name); 333 return -EINVAL; 334 } 335 336 return 0; 337 } 338 339 static int 340 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, 341 const struct drm_crtc_state *state, 342 struct drm_property *property, 343 uint64_t *val) 344 { 345 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 346 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state); 347 348 if (property == adev->mode_info.regamma_tf_property) 349 *val = acrtc_state->regamma_tf; 350 else 351 return -EINVAL; 352 353 return 0; 354 } 355 #endif 356 357 /* Implemented only the options currently available for the driver */ 358 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 359 .reset = amdgpu_dm_crtc_reset_state, 360 .destroy = amdgpu_dm_crtc_destroy, 361 .set_config = drm_atomic_helper_set_config, 362 .page_flip = drm_atomic_helper_page_flip, 363 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, 364 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, 365 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 366 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 367 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 368 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 369 .enable_vblank = amdgpu_dm_crtc_enable_vblank, 370 .disable_vblank = amdgpu_dm_crtc_disable_vblank, 371 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 372 #if defined(CONFIG_DEBUG_FS) 373 .late_register = amdgpu_dm_crtc_late_register, 374 #endif 375 #ifdef AMD_PRIVATE_COLOR 376 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, 377 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, 378 #endif 379 }; 380 381 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) 382 { 383 } 384 385 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 386 { 387 struct drm_atomic_state *state = new_crtc_state->state; 388 struct drm_plane *plane; 389 int num_active = 0; 390 391 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 392 struct drm_plane_state *new_plane_state; 393 394 /* Cursor planes are "fake". */ 395 if (plane->type == DRM_PLANE_TYPE_CURSOR) 396 continue; 397 398 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 399 400 if (!new_plane_state) { 401 /* 402 * The plane is enable on the CRTC and hasn't changed 403 * state. This means that it previously passed 404 * validation and is therefore enabled. 405 */ 406 num_active += 1; 407 continue; 408 } 409 410 /* We need a framebuffer to be considered enabled. */ 411 num_active += (new_plane_state->fb != NULL); 412 } 413 414 return num_active; 415 } 416 417 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, 418 struct drm_crtc_state *new_crtc_state) 419 { 420 struct dm_crtc_state *dm_new_crtc_state = 421 to_dm_crtc_state(new_crtc_state); 422 423 dm_new_crtc_state->active_planes = 0; 424 425 if (!dm_new_crtc_state->stream) 426 return; 427 428 dm_new_crtc_state->active_planes = 429 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state); 430 } 431 432 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 433 const struct drm_display_mode *mode, 434 struct drm_display_mode *adjusted_mode) 435 { 436 return true; 437 } 438 439 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 440 struct drm_atomic_state *state) 441 { 442 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 443 crtc); 444 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 445 struct dc *dc = adev->dm.dc; 446 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 447 int ret = -EINVAL; 448 449 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 450 451 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state); 452 453 if (WARN_ON(unlikely(!dm_crtc_state->stream && 454 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 455 return ret; 456 } 457 458 /* 459 * We require the primary plane to be enabled whenever the CRTC is, otherwise 460 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 461 * planes are disabled, which is not supported by the hardware. And there is legacy 462 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 463 */ 464 if (crtc_state->enable && 465 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 466 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 467 return -EINVAL; 468 } 469 470 /* 471 * Only allow async flips for fast updates that don't change the FB 472 * pitch, the DCC state, rotation, etc. 473 */ 474 if (crtc_state->async_flip && 475 dm_crtc_state->update_type != UPDATE_TYPE_FAST) { 476 drm_dbg_atomic(crtc->dev, 477 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 478 crtc->base.id, crtc->name); 479 return -EINVAL; 480 } 481 482 /* In some use cases, like reset, no stream is attached */ 483 if (!dm_crtc_state->stream) 484 return 0; 485 486 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 487 return 0; 488 489 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 490 return ret; 491 } 492 493 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 494 .disable = amdgpu_dm_crtc_helper_disable, 495 .atomic_check = amdgpu_dm_crtc_helper_atomic_check, 496 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, 497 .get_scanout_position = amdgpu_crtc_get_scanout_position, 498 }; 499 500 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 501 struct drm_plane *plane, 502 uint32_t crtc_index) 503 { 504 struct amdgpu_crtc *acrtc = NULL; 505 struct drm_plane *cursor_plane; 506 bool is_dcn; 507 int res = -ENOMEM; 508 509 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 510 if (!cursor_plane) 511 goto fail; 512 513 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 514 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 515 516 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 517 if (!acrtc) 518 goto fail; 519 520 res = drm_crtc_init_with_planes( 521 dm->ddev, 522 &acrtc->base, 523 plane, 524 cursor_plane, 525 &amdgpu_dm_crtc_funcs, NULL); 526 527 if (res) 528 goto fail; 529 530 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 531 532 /* Create (reset) the plane state */ 533 if (acrtc->base.funcs->reset) 534 acrtc->base.funcs->reset(&acrtc->base); 535 536 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 537 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 538 539 acrtc->crtc_id = crtc_index; 540 acrtc->base.enabled = false; 541 acrtc->otg_inst = -1; 542 543 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 544 545 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 546 * support programmable degamma anywhere. 547 */ 548 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 549 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 550 true, MAX_COLOR_LUT_ENTRIES); 551 552 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 553 554 #ifdef AMD_PRIVATE_COLOR 555 dm_crtc_additional_color_mgmt(&acrtc->base); 556 #endif 557 return 0; 558 559 fail: 560 kfree(acrtc); 561 kfree(cursor_plane); 562 return res; 563 } 564 565